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2024
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Invention
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Modulation of source voltage in nand-flash array read.
Modulation of the source voltage in a NAN... |
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Invention
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Smart prologue for nonvolatile memory program operation.
For a nonvolatile (NV) storage media su... |
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Invention
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Improved diagnostic ring oscillator circuit for dc and transient characterization.
A ring oscill... |
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Invention
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Calibrate system with calculated receive eye for volume testing based on receive eye measurement ... |
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Invention
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Flash memory chip that modulates its program step voltage as a function of chip temperature.
A m... |
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2023
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Invention
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Diagnostic ring oscillator circuit for dc and transient characterization.
Methods and apparatus ... |
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Invention
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Simultaneous statistical multi-subblock verify for nand memories.
Program verify can be performe... |
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Invention
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Efficient bitline stabilization for program inhibit in nand arrays.
A storage device charges bit... |
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Invention
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Deck reset read.
A storage device includes a storage array having multiple decks of NAND cells i... |
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Invention
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Ald vs pvd igzo channel and alox channel passivation in a 3d nand vertical wordline driver.
ALD ... |
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Invention
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Fast and efficient verify recovery and array discharge for 3d nand memory arrays.
Methods and ap... |
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Invention
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Early read operation for storage devices with independent planes and plane groups. A storage devi... |
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Invention
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Method and apparatus to reduce memory in a nand flash device to store page related information. T... |
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Invention
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Vertical wordline driver structures and methods. Vertical wordline driver structures and methods.... |
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Invention
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Method and apparatus to reduce time to program single level cell blocks in a non-volatile memory.... |
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Invention
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Floating gate nand cell – methods and approaches for fabrication.
Methods and approaches for fab... |
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Invention
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Large grain and halogen-free silicon cell channel for 3d nand string.
An example of an apparatus... |
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Invention
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Prevention of floating gate 3d-nand cell residual by using hybrid plug process in super-deck stru... |
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Invention
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Integrated word line contact structures in three-dimensional (3d) memory array.
A memory array i... |
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Invention
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Techniques for preventing read disturb in nand memory. In one example, reads in a NAND memory dev... |
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Invention
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Enhanced io interface for plc program and program-suspend-resume operations.
Methods and apparat... |
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Invention
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Method for pillar bending improvement by cut tiers pattern implementation.
Methods and apparatus... |
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Invention
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Apparatus and method to improve read window budget in a three dimensional nand memory.
The gap w... |
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Invention
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Low-cost mask punch flow.
Methods and apparatus for low-cost punch through flows. Pillar recesse... |
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Invention
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Engineered dielectric profile for high aspect-ratio 3d nand structures.
Methods and apparatus of... |
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Invention
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Method and apparatus to reduce power consumption of page buffer circuitry in a non-volatile memor... |
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Invention
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Early read operation for storage devices with independent planes and plane groups.
A storage de... |
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Invention
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Express status operation for storage devices with independent planes and plane groups.
A storag... |
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Invention
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Vertical wordline driver structures and methods.
Vertical wordline driver structures and methods... |
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Invention
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Zero voltage program state detection.
For NAND devices having a zero voltage program state as a ... |
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Invention
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Method and apparatus to reduce memory in a nand flash device to store page related information.
... |
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Invention
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Method and apparatus to select a plane in a nand flash die to store a read-only reserved block. M... |
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Invention
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Dynamic program caching. Dynamic program caching reduces latency of a program operation on multi-... |
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2022
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Invention
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Multi-phase clocking scheme for a memory device.
Technology to provide a multi-phase clocking sc... |
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Invention
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Nand aging protection scheme.
Systems, apparatuses, and methods may provide for technology for a... |
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Invention
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Multi-deck nand memory with hybrid deck slc.
An example of a memory device may comprise NAND med... |
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Invention
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Power efficient array discharge for program boosting.
Systems, apparatuses and methods may provi... |
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Invention
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Consolidation of staircase area etch and cmos contact area etch in 3d nand. Systems, apparatuses,... |
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Invention
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Dynamic program caching.
Dynamic program caching reduces latency of a program operation on multi... |
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Invention
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Synchronous independent plane read operation.
An embodiment of an apparatus may include NAND mem... |
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Invention
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Interface for different internal and external memory io paths.
An embodiment of an apparatus may... |
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Invention
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Three-dimensional memory with super-pillar.
An embodiment of a memory device may comprise a supe... |
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Invention
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Method and apparatus to select a plane in a nand flash die to store a read-only reserved block.
... |
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2021
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Invention
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Parallel staircase 3d nand.
Systems, apparatuses, and methods may provide for technology that ar... |
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Invention
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Tier expansion offset.
Systems, apparatuses, and methods may provide for technology for forming ... |
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Invention
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Selective removal of sidewall material for 3d nand integration.
An embodiment of an apparatus ma... |
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Invention
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Pump discharge sequence improvements in external power supply mode for pulse recovery phases in n... |
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Invention
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Chuck with non-flat shaped surface.
An embodiment of an apparatus may include a chuck body, and ... |
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2020
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Invention
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Memory devices with gradient-doped control gate material.
Disclosed herein are memory devices wi... |
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Invention
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Method and apparatus to mitigate word line staircase etch stop layer thickness variations in 3d n... |
