MULTIPLE DIES COUPLED WITH A GLASS CORE SUBSTRATE

Register USPTO Patent
Application Number 17481234
Status Pending
Filing Date 2021-09-21
First Publication Date 2023-03-23
Publication Date 2023-03-23
Owner Intel Corporation (USA)
Inventor
  • Collins, Andrew
  • Pietambaram, Srinivas V.
  • Ganesan, Sanka
  • Ibrahim, Tarek A.
  • Mortensen, Russell

Abstract

Embodiments described herein may be related to apparatuses, processes, and techniques directed to packages that include one or more dies that are coupled with one or more glass layers. These glass layers may be within an interposer or a patch to which the one or more dies are attached. In addition, these glass layers may be used to facilitate pitch translation between the one or more dies proximate to a first side of the glass layer and a substrate proximate to a second side of the glass layer opposite the first side, to which the one or more dies are electrically coupled. Other embodiments may be described and/or claimed.

IPC Classes  ?

  • H01L 23/538 - Arrangements for conducting electric current within the device in operation from one component to another the interconnection structure between a plurality of semiconductor chips being formed on, or in, insulating substrates
  • H01L 25/00 - Assemblies consisting of a plurality of individual semiconductor or other solid state devices
  • H01L 25/065 - Assemblies consisting of a plurality of individual semiconductor or other solid state devices all the devices being of a type provided for in the same subgroup of groups , or in a single subclass of , , e.g. assemblies of rectifier diodes the devices not having separate containers the devices being of a type provided for in group
  • H01L 21/48 - Manufacture or treatment of parts, e.g. containers, prior to assembly of the devices, using processes not provided for in a single one of the groups