MICROELECTRONIC PACKAGE WITH DIELECTRIC LAYER INCLUDING SELF-ASSEMBLED FILLER-DEPLETED REGIONS
Register | USPTO Patent |
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Application Number | 17482092 |
Status | Pending |
Filing Date | 2021-09-22 |
First Publication Date | 2023-03-23 |
Publication Date | 2023-03-23 |
Owner | Intel Corporation (USA) |
Inventor |
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Abstract
Techniques for self-assembly of regions in a dielectric layer with different electrical properties are described herein. In one example, a package includes a substrate, a layer of dielectric material over the substrate, the layer of dielectric material including a filler material. The package includes a plurality of conductive traces in the layer of dielectric material, and a filler-depleted radial region of the dielectric material around each of the plurality of conductive traces. The filler-depleted radial region has a lower volume-percentage of filler than other regions of the layer of dielectric material. In one example, the conductive traces, filler, or both include a coating to cause the filler and traces to have opposing surface chemistry.IPC Classes ?
- H01L 23/498 - Leads on insulating substrates
- H01L 21/48 - Manufacture or treatment of parts, e.g. containers, prior to assembly of the devices, using processes not provided for in a single one of the groups