LANE BASED NORMALIZED HISTORICAL ERROR COUNTER VIEW FOR FAULTY LANE ISOLATION AND DISAMBIGUATION OF TRANSIENT VERSUS PERSISTENT ERRORS
| Register | USPTO Patent |
|---|---|
| Application Number | 17483123 |
| Status | Pending |
| Filing Date | 2021-09-23 |
| First Publication Date | 2023-03-23 |
| Publication Date | 2023-03-23 |
| Owner | Intel Corporation (USA) |
| Inventor |
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Abstract
Methods and apparatus relating to lane based normalized historical error counter view for faulty lane isolation and disambiguation of transient versus persistent errors are described. In an embodiment, a plurality of storage entries store error information to be detected at one or more physical lanes of an interface. Faulty lane detection logic circuitry determines which of the one or more physical lanes is faulty or more likely to be faulty based at least in part on the stored error information for the one or more physical lanes of the interface. The stored error information comprises historical error details for the one or more physical lanes of the interface. Other embodiments are also disclosed and claimed.IPC Classes ?
- G06F 11/07 - Responding to the occurrence of a fault, e.g. fault tolerance
- G06F 13/40 - Bus structure