Register USPTO Patent
Application Number 17483491
Status Pending
Filing Date 2021-09-23
First Publication Date 2023-03-23
Publication Date 2023-03-23
Owner Intel Corporation (USA)
  • Kuo, Chia-Hung S.
  • Gandiga Shivakumar, Deepak
  • Mukker, Anoop
  • Gihon, Arik
  • Greenfield, Zvika
  • Rubinstein, Asaf
  • Aqrabawi, Leo


Some embodiments include apparatuses and electrical models associated with the apparatus. One of the apparatuses includes a power control unit to monitor a power state of the apparatus for entry into a standby mode. The apparatus can include a two-level memory (2LM) hardware accelerator to, responsive to a notification from the power control unit of entry into the standby mode, flush dynamic random access memory (DRAM) content from a first memory part to a second memory part. The apparatus can include processing circuitry to determine memory utilization and move memory from a first memory portion to a second memory portion responsive to memory utilization exceeding a threshold. Other methods systems and apparatuses are described.

IPC Classes  ?

  • G06F 12/0804 - Addressing of a memory level in which the access to the desired data or data block requires associative addressing means, e.g. caches with main memory updating
  • G06F 1/28 - Supervision thereof, e.g. detecting power-supply failure by out of limits supervision
  • G06F 1/3206 - Monitoring of events, devices or parameters that trigger a change in power modality
  • G06F 1/3287 - Power saving characterised by the action undertaken by switching off individual functional units in the computer system