Abstract

The present invention relates to an electronic device (1) comprising a silicon-on-insulator strip (100) laterally defined by insulating trenches (106); a first gate (112) supported by the strip; a second gate (114), or a third gate (116), parallel to the strip (100), supported by the strip and being separated from the first gate (112) a first gap (e1) or a second gap (e2); two first semiconductor regions (110), or two second semiconductor regions (108), doped and arranged along and on either side of the second gate (114) or the third gate (116); at least one fourth gate (122A, 122B), or at least one fifth gate (126A, 126B), arranged facing the first gap (e1) or the second gap (e2); and a region (130) for biasing a substrate under the strip.

IPC Classes  ?

• H01L 29/06 - Semiconductor bodies characterised by the shapes, relative sizes, or dispositions of the semiconductor regions
• H01L 29/423 - Electrodes characterised by their shape, relative sizes or dispositions not carrying the current to be rectified, amplified or switched
• H01L 29/66 - Types of semiconductor device
• H01L 29/76 - Unipolar devices
• B82Y 10/00 - Nanotechnology for information processing, storage or transmission, e.g. quantum computing or single electron logic

Abstract

According to one aspect, the invention relates to a phased array antenna comprising: - a plurality of elementary antennas, - an amplifier circuit (AMPC) for each elementary antenna (ANTE), the amplifier circuit (AMPC) comprising: a power amplifier (PA) configured to amplify at least two useful signals of different frequencies to be transmitted by the elementary antenna, and a third-order intermodulation product control circuit (ICTRL) configured to control a third-order intermodulation product phase generated by the amplifier circuit so as to control an orientation of third-order intermodulation product radiation transmitted by the phased array antenna.

IPC Classes  ?

• H04B 1/04 - Circuits
• H03F 1/32 - Modifications of amplifiers to reduce non-linear distortion

Abstract

The present invention relates to a neutralised amplifier (50) comprising at least one variable-capacitance neutralising capacitor (76, 78), in which the at least one neutralising capacitor (76, 78) is configured to compensate for the phase variations introduced by the amplifier.

IPC Classes  ?

• H03F 1/14 - Modifications of amplifiers to reduce detrimental influences of internal impedances of amplifying elements by use of neutralising means
• H03F 3/26 - Push-pull amplifiers; Phase-splitters therefor
• H03F 3/193 - High-frequency amplifiers, e.g. radio frequency amplifiers with semiconductor devices only with field-effect devices

Abstract

The present description relates to a connector that can be configured mechanically between a wireless radio frequency transmission and a wired radio frequency transmission via a cylindrical radio frequency dielectric waveguide (202), the connector (1) comprising a first housing (102) joined to a printed circuit board (104) provided with a radio frequency antenna (108), and a second housing (200) configured to be joined to the waveguide (202), the second housing (200) being configured to be mounted on the first housing (102) in a removable manner in a wired transmission configuration and being detached from the first housing (102) in a wireless transmission configuration.

IPC Classes  ?

• H01P 3/16 - Dielectric waveguides, i.e. without a longitudinal conductor
• H01Q 13/08 - Radiating ends of two-conductor microwave transmission lines, e.g. of coaxial lines, of microstrip lines
• H01P 5/08 - Coupling devices of the waveguide type for linking lines or devices of different kinds
• H01P 1/208 - Cascaded cavities; Cascaded resonators inside a hollow waveguide structure
• H01P 5/107 - Hollow-waveguide/strip-line transitions
• H01R 13/62 - Means for facilitating engagement or disengagement of coupling parts or for holding them in engagement

Abstract

Disclosed is a method for detecting the phase (Φ1) of an analogue signal (SA1) via a hybrid coupler (CH1) operating in a power combiner mode, the hybrid coupler (CH1) comprising a first input (BE1) intended to receive the analogue signal (SA1), a second input (BE2) intended to receive a reference signal (SREF) having a reference phase (Φ2) and a same frequency (FREF) as the analogue signal (SA1), and two outputs (BS1, BS2), and configured to respectively generate, at these two outputs (BS1, BS2), a first output signal (SS1) and a second output signal (SS2), comprising a measurement of the peak values (A1, A2, A3, A4) of the analogue signal (SA1), of the reference signal (SREF) and of at least one of the first and second output signals (SS1, SS2), a calculation of the phase-shift (Φ1-Φ2) between the phase (Φ1) of the analogue signal and the reference phase (Φ2) as a function of the measured peak values (A1, A2, A3, A4), and determination of the phase (Φ1) of the analogue signal (SA1) as a function of this calculated phase shift (Φ1-Φ2) and of the reference phase (Φ2).

IPC Classes  ?

• G01R 25/02 - Arrangements for measuring phase angle between a voltage and a current or between voltages or currents in circuits having distributed constants
• G01R 25/04 - Arrangements for measuring phase angle between a voltage and a current or between voltages or currents involving adjustment of a phase shifter to produce a predetermined phase difference, e.g. zero difference

Abstract

The method for detecting the phase (PI) of an analog signal (SI3) via a hybrid coupler (CH2) operating in a power combiner mode, the hybrid coupler (CH2) comprising a first input (BE3) intended to receive the analog signal (SI3), a second input (BE4) intended to receive an additional analog signal (SI4) phase shifted by 90° in relation to the analog signal (SI3), a first output (BS3) delivering an output signal (SS1), and a second output (BS4), comprises an injection at the second output (BS4) of a test signal (ST1) having an initial test phase (PTI), an iterative generation of a current test phase (PTC) for the test signal (ST1), from the initial test phase (PTI) until a final test phase (PTF) equal to the initial test phase (PTI) increased by at least a portion of a complete revolution, with, in each iteration, a current peak value measurement (AC1) of the output signal (SS1), and a storing of the current test phase (PTC) and the current peak value (AC1) as a maximum peak value (Amax) or minimum peak value (Amin), if there is respectively no stored maximum peak value (Amax) that is greater or stored minimum peak value (Amin) that is less than the current peak value (AC1), and a determination of the phase (PI) of the analog signal (SI3) using the stored test phase (PTM).

IPC Classes  ?

• H04B 1/04 - Circuits
• H04B 1/18 - Input circuits, e.g. for coupling to an antenna or a transmission line

Abstract

The invention relates to a method for calibrating the centre frequency (FC1) of a hybrid coupler (CH1) operating in power-splitter mode, the hybrid coupler (CH1) comprising two inputs (BE1, BE2), two outputs (BS1, BS2), a capacitive module (MC1) coupled between the inputs (BE1, BE2) and the outputs (BS1, BS2) or on each input (BE1, BE2) and each output (BS1, BS2), the capacitive module (MC1) having an adjustable capacitive value (C1) making it possible to adjust the centre frequency (FC1), which comprises outputting a first reference signal (SREF1) having a first reference frequency (FREF1) on a first input (BE1) of said hybrid coupler (CH1), measuring the peak value (VC1) of a first signal (S1) output at a first output (BS1) of the coupler (CH1) and the peak value (VC2) of a second signal (S2) output at the second output (BS2) of the coupler (CH1), comparing the two peak values (VC1, VC2) and adjusting the capacitive value (C1) of the capacitive module (MC1) until obtaining equal peak values (VC1, VC2) to within a close tolerance.

IPC Classes  ?

• H04B 17/21 - Monitoring; Testing of receivers for correcting measurements
• H01P 5/12 - Coupling devices having more than two ports

Abstract

Integrated optical switch formed in and on a semiconductor substrate, comprising a photoconductive body (PC) comprising a first end (1) configured to receive an electrical input signal and a second end (2) configured to provide an electrical output signal, the photoconductive body (PC) having an electrically conductive state activated by the presence of an optical signal (SO) and an electrically blocked state activated by the absence of the optical signal (SO), wherein the direction from the first end to the second end defines a longitudinal direction (D3), and the photoconductive body has a cross section orthogonal to the longitudinal direction (D3) gradually decreasing in the longitudinal direction (D3) from the first end (1) to the second end (2).

IPC Classes  ?

• H03K 17/78 - Electronic switching or gating, i.e. not by contact-making and -breaking characterised by the use of specified components by the use, as active elements, of opto-electronic devices, i.e. light-emitting and photoelectric devices electrically- or optically-coupled
• G01R 13/34 - Circuits for representing a single waveform by sampling, e.g. for very high frequencies
• H01L 31/08 - SEMICONDUCTOR DEVICES NOT COVERED BY CLASS - Details thereof in which radiation controls flow of current through the device, e.g. photoresistors

Abstract

Method for controlling the matching of an antenna to a transmission path, and corresponding device. The method for controlling the matching of an antenna (3) to a transmission path (2), said transmission path (2) comprising an amplifier stage (4) coupled at input or at output to the antenna (3) and to a resistive load (16), comprises a control phase (PC) comprising a measurement of a first current temperature (Tc1) at the level of the antenna (3) and of a second current temperature (Tc2) at the level of the resistive load (16), a triggering of a matching of the impedance seen at input or at output of the amplifier stage (4) in the presence of a first condition involving at least the first and second current temperatures (Tc1, Tc2) and then a stopping of the matching of the impedance in the presence of a second condition involving at least the second current temperature (Tc2).

IPC Classes  ?

• H04B 1/04 - Circuits

Abstract

The parallel reception system (SYS) comprises a plurality of receiving devices (DIS1-DISN), each comprising an amplifying circuit (CA) in a frequency transformation stage coupled with the antenna and configured to perform a frequency transposition of the signal (Vin) received by said antenna. The analog amplifier circuit (CA) comprises transconductance amplifier units (UAj) in parallel, each comprising a PMOS transistor (PI) and an NMOS transistor (N2) the gates of which are connected to the input node (I) and the drains to the output node (O). A control means (MCOM) is configured to generate a digital control signal, of which each bit (Bj) respectively controls the supply of each amplifier unit (UAj) according to a sinusoidal wave representation at a frequency of interest.

IPC Classes  ?

• H03D 7/12 - Transference of modulation from one carrier to another, e.g. frequency-changing by means of semiconductor devices having more than two electrodes
• H03D 7/14 - Balanced arrangements

Abstract

The coupling device (DC) comprises a 90° hybrid inductive capacitive coupling stage (EC) including two first stage terminals (BE11 and BE12) that are capable of forming two stage inputs or two stage outputs and two second stage terminals (BE21 and BE22) that are capable of respectively forming two stage outputs or two stage inputs. The coupling stage (EC) is advantageously modular, possesses a first axis of stage symmetry (ASE1) and a second axis of stage symmetry (ASE2) that is orthogonal to the first axis of stage symmetry (ASE1), includes neighbouring inductive metal tracks (PM11 and PM12) that overlap in at least one region of crossover (RC) and that form both an inductive circuit (CI1) and a capacitive circuit (CC1), said tracks being coupled to the first stage terminals (BE11, BE12) and to the second stage terminals (BE21, BE22) so that the two first stage terminals (BE11, BE12) are located on one side of the first axis of stage symmetry (ASE1) whereas the two second stage terminals (BE21, B22) are located on the other side of the first axis of stage symmetry (ASE2).

IPC Classes  ?

• H01P 5/18 - Conjugate devices, i.e. devices having at least one port decoupled from one other port consisting of two coupled guides, e.g. directional couplers

Abstract

The invention relates to a driving/assistance method for driving a vehicle (1) on a thoroughfare provided with at least one marking strip (4) for marking said thoroughfare, wherein said method includes burying a plurality of transponders (3) built into said at least one marking strip (4), equipping a vehicle (1) with at least one active communication device (2), performing a series of remote communications between said at least one active communication device (2) and said transponders (3) during the movement of the vehicle (1) on said thoroughfare, and performing a series of distance calculations between said at least one active communication device (2) and the marking strip during said series of remote communications with said consecutive transponders (3).

IPC Classes  ?

• B60W 30/12 - Lane keeping
• G06K 9/00 - Methods or arrangements for reading or recognising printed or written characters or for recognising patterns, e.g. fingerprints
• G06K 7/10 - Methods or arrangements for sensing record carriers by corpuscular radiation
• G01S 13/75 - Systems using reradiation of radio waves, e.g. secondary radar systems; Analogous systems using transponders powered from received waves, e.g. using passive transponders

Abstract

The invention relates to a method for producing at least one pattern in a film resting on a substrate, including the steps of a) making amorphous at least one first block (131) of an upper film of crystalline material resting on a first amorphous supporting film, while the crystalline structure of a second block (132) of the upper film that adjoins and juxtaposes said first block (131) is preserved, b) partially recrystallising the first block (131) by using at least one side surface of the second block (132) that is in contact with the first block as an area for the start of a recrystallisation front, the partial recrystallisation being carried out so as to preserve a region (1311) of amorphous material in the first block, c) selectively etching the amorphous material of the upper film with respect to the crystalline material of the upper film so as to form at least one first pattern in the upper film.

IPC Classes  ?

• H01L 21/308 - Chemical or electrical treatment, e.g. electrolytic etching using masks
• H01L 21/033 - Making masks on semiconductor bodies for further photolithographic processing, not provided for in group or comprising inorganic layers

Abstract

Method for production of a semiconductor wafer suitable for the manufacture of an SOI substrate, comprising the following steps: - production, on the upper face (2) of a semiconductor support (1), of a first layer (4) of polycrystalline semiconductor; then - formation of an interface area (12) on the upper face (7) of said first layer (4), the interface area (12) having a structure distinct from the crystalline structure of said first layer (4); then - production on said interface area (12) of a second layer (14) of polycrystalline semiconductor.

IPC Classes  ?

• H01L 21/02 - Manufacture or treatment of semiconductor devices or of parts thereof
• H01L 21/762 - Dielectric regions
• H01L 21/763 - Polycrystalline semiconductor regions
• H01L 29/04 - Semiconductor bodies characterised by their crystalline structure, e.g. polycrystalline, cubic or particular orientation of crystalline planes

Abstract

The processing means (MT) of the device determine, for each original sample stream (I), an estimated difference (II) between the time constant of a low pass filter representative of the corresponding converter and a reference time constant of a reference low pass filter, and uses this estimated difference (II) and a filtered stream (III) to correct the original stream and deliver a corrected stream of corrected samples (I).

IPC Classes  ?

• H03M 1/06 - Continuously compensating for, or preventing, undesired influence of physical parameters
• H03M 1/12 - Analogue/digital converters

Abstract

An apparatus has a data store configured to store access activity information. The access activity information indicates which one or more of a plurality of different access parameter sets is active. The data store is also configured to store access defining information, which defines, at least for each active access parameter set, a number of channels, location information of said channels, and interleaving information associated with said channels.

IPC Classes  ?

• G06F 12/06 - Addressing a physical block of locations, e.g. base addressing, module addressing, address space extension, memory dedication
• H04W 74/08 - Non-scheduled access, e.g. random access, ALOHA or CSMA [Carrier Sense Multiple Access]
• G06F 13/16 - Handling requests for interconnection or transfer for access to memory bus

Abstract

The invention relates to a device (400) for converting energy, comprising an enclosure (430) containing drops of a liquid (427) and an electret capacitive transducer (417, 419, 421) coupled to that enclosure.

IPC Classes  ?

• H02N 1/08 - Influence generators with conductive charge carrier, i.e. capacitor machines

Abstract

An integrated circuit (4) comprises first and second cells, each comprising first (10, 44) and second (12, 42) FDSOI transistors. According to the invention: -the first and second cells are joined together; -first (20) and second (22) boxes of the first cell and a first box (52) of the second cell have a first type of doping, a second box (50) of the second cell has an opposite type of doping -the circuit comprises a control device (5) for applying a same electrical polarisation to the boxes having the first type of doping; -the transistors of the first cell are configured to have a first threshold voltage level, and the transistors of the second cell are configured to have a second threshold voltage level different from the first level.

IPC Classes  ?

• H01L 27/12 - Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being other than a semiconductor body, e.g. an insulating body

Abstract

The invention concerns a method for producing a capacitor, comprising the forming of a capacitor stack in one portion of a substrate (112), said method comprising: the forming of a cavity (165) along the thickness of the portion of the substrate (112) from an upper face of said substrate (112), the depositing of a plurality of layers contributing to the capacitor stack onto the wall of the cavity (165) and onto the surface of the upper face, and a removal of matter from the layers until the surface of the upper face is reached, characterised in that the formation of the cavity (165) comprises the formation of at least one trench (164) and, associated with each trench (164), of at least one box (163), said at least one trench (164) comprising a trench outlet that opens into the box (163), said box (163) comprising a box outlet that opens at the surface of the upper face, the box outlet being shaped so as to be larger than the trench outlet.

IPC Classes  ?

• H01G 4/33 - Thin- or thick-film capacitors
• H01L 49/02 - Thin-film or thick-film devices
• H01G 4/38 - Multiple capacitors, i.e. structural combinations of fixed capacitors

Abstract

System for converting thermal energy into electrical energy (S1) intended to be disposed between a hot source (SC) and a cold source (SF), comprising means for converting the thermal energy into mechanical energy (6) and a piezoelectric material, the means for converting thermal energy into mechanical energy (6) comprising groups (G1, G2) of at least three bimetallic strips (9, 11, 13) linked mechanically together by their longitudinal ends and suspended above a substrate (12), each bimetallic strip (9, 11, 13) comprising two stable states in which it exhibits in each of the states a curvature, two directly adjacent bimetallic strips (9, 11, 13) exhibiting opposite curvatures for a given temperature, the switching from one stable state of the bimetallic strips (9, 11, 13) to the other causing the deformation of a piezoelectric material.

IPC Classes  ?

• H02N 2/18 - Electric machines in general using piezoelectric effect, electrostriction or magnetostriction producing electrical output from mechanical input, e.g. generators
• H02K 35/00 - Generators with reciprocating, oscillating or vibrating coil system, magnet, armature or other part of the magnetic circuit

Abstract

The invention relates to a housing, including a body (1) comprising a first silicon element (10) and a second porous silicon element (20), at least one first cavity (31) provided in the porous silicon, a first electrically conductive contact area (41), which is electrically coupled to at least a portion (310) of at least one inner wall of said at least one cavity (31), a second electrically conductive contact area (42), which is electrically coupled to a different portion (320) of said second element (20) of the inner walls of said at least one first cavity (31), the two contact areas (41, 42) being electrically insulated from each other.

IPC Classes  ?

• H01M 8/16 - Biochemical fuel cells, i.e. cells in which microorganisms function as catalysts
• H01M 8/10 - Fuel cells with solid electrolytes
• H01G 9/02 - Diaphragms; Separators

Abstract

The invention relates to a device and method for controlling an SRAM memory device, including: one bistable circuit and two switching circuits respectively connecting two access terminals of the bistable circuit to two matching bit sites in a first direction, each switching circuit comprising: a first switch (40G, 40D), a second switch (44G, 44D) in series between one of the bit sites and one of said access terminals, the control terminal of the second switch being connected to a word command line in the first direction; and a third switch (46G, 46D) between the middle point of said series connection and a terminal for applying a reference potential, a control terminal of the third switch being connected to the other one of said access terminals.

IPC Classes  ?

• G11C 11/412 - Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming cells with positive feedback, i.e. cells not needing refreshing or charge regeneration, e.g. bistable multivibrator or Schmitt trigger using field-effect transistors only
• G11C 11/413 - Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing, timing or power reduction

Abstract

The electronic device includes a first (BP) and a second (BN) terminal and electronic means coupled between said two terminals; the electronic means include at least one block (BLC) comprising an MOS transistor (TR) including a parasitic bipolar transistor, the MOS transistor having the drain (D) thereof coupled to the first terminal (BP), the source (S) thereof coupled to the second terminal (BN) and being additionally configured, in the event of a current pulse (IMP) between the two terminals, to operate in a hybrid mode including MOS operation in a subthreshold mode and operation of the parasitic bipolar transistor. The device can comprise two blocks (BLC1, BLC2) connected symmetrically between the two terminals (BP, BN) with a triac (TRC) the trigger of which is connected to the common terminal (BC) of the two blocks.

IPC Classes  ?

• H01L 23/60 - Protection against electrostatic charges or discharges, e.g. Faraday shields
• H01L 27/02 - Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including integrated passive circuit elements with at least one potential-jump barrier or surface barrier

Abstract

The invention concerns a satellite receive unit having an analog to digital converter (302) adapted to sample a satellite signal to generate a data stream; at least one digital channel multiplexer having at least one processing branch (307A, 307B) which includes: a Fourier transform block (307A, 307B); a channel shifter (310A, 310B); and an inverse Fourier transform block (312A, 312B); the satellite receiver comprising a digital to analog converter (316) adapted to convert the output data stream of the processing branch into an analog signal in a transmission band for transmission over a transmission channel to at least one satellite decoder.

IPC Classes  ?

• H04H 40/90 - Arrangements characterised by circuits or components specially adapted for receiving specially adapted for broadcast systems covered by groups specially adapted for satellite broadcast receiving
• H04H 20/63 - Arrangements specially adapted for specific applications, e.g. for traffic information or for mobile receivers for local area broadcast, e.g. instore broadcast to plural spots in a confined site, e.g. MATV [Master Antenna Television]

Abstract

Filtering circuit with coupled resonators comprising : - a substrate (100); an acoustic mirror (101) or a membrane destined to act as a mechanical support of acoustic resonators and to isolate these resonators from the substrate; - a first section (LEFT) comprising an upper resonator (120) and a lower resonator (110) coupled to each other by means of at least one acoustic coupling layer (130), the said upper and lower resonators constituting a first section (Al ); - a second section (RIGHT) comprising an upper resonator (220) and a lower resonator (210) coupled to each other by means of at least one acoustic coupling layer (130), the said upper and lower resonators of the said second section constituting a second section (A2); and metallic vias implementing an inter stage connection between the lower resonator of a section and the upper resonator of the other section.

IPC Classes  ?

• H03H 9/58 - Multiple crystal filters

Abstract

System for generating a pulsed signal of the ultra wideband type, comprising a device for direct digital frequency synthesis (DDS) comprising a phase accumulator (ACCP) able to deliver at a first frequency (Fclk) phases coded on i bits and spaced apart by a phase increment (Δp) differing by a power of two and situated in the vicinity of 2i-1, processing means (MT) able to receive said phases and arranged so as to deliver an amplitude-modulated output signal (SG) whose envelope exhibits a succession of regions respectively delimited by zones of zero amplitude (ZA, ZB), each amplitude-modulated signal part situated in one of said regions forming a pulse of the ultra wideband type (IMP) whose central frequency is equal to said first frequency and whose width depends on the value of the phase increment, and control means (MC) able to regulate the operation of the digital synthesis device so as to selectively deliver one or more pulses of the ultra wideband type.

IPC Classes  ?

• H04B 1/69 - Spread spectrum techniques

Abstract

The present invention relates to a three-dimensional capacitor that includes a stack of vertically adjacent electrodes formed in respective metallization levels of an integrated circuit. The capacitor also comprises at least two additional vertically adjacent electrodes formed on top of said stack, the additional electrodes each including an assembly of at least one bar (B, B’) extending in a first direction. A portion of said bars comprises branches (R) extending in a second direction.

IPC Classes  ?

• H01G 4/005 - Electrodes
• H01G 4/30 - Stacked capacitors
• H01L 21/02 - Manufacture or treatment of semiconductor devices or of parts thereof

Abstract

The invention concerns a switched capacitor amplifier having an amplification unit (102) adapted to amplify a differential signal; a first switched capacitor block (120) including a first plurality of capacitors operable to sample a first differential input signal during a first sampling phase and to drive the amplification unit during a first drive phase; and a second switched capacitor block (122) comprising a second plurality of capacitors operable to sample a second differential input signal during a second sampling phase and to drive the amplification unit during a second drive phase.

IPC Classes  ?

• H03F 3/00 - Amplifiers with only discharge tubes or only semiconductor devices as amplifying elements

Abstract

Integrated circuit, incorporating an electronic device (PA), comprising input means (BE) for receiving a radio frequency digital signal (SCH), output means (BS) able to deliver a radio frequency analogue signal (SARF), and a processing stage coupled between the input means and the output means and comprising several parallel processing pathways (VTi), each processing pathway (VTi) including a voltage switching block (BLCi) whose input is coupled to the input means and a transmission line (LTi) substantially of the quarter wave type at the frequency of the radio frequency analogue signal coupled in series between the output of the voltage switching block and said output means.

IPC Classes  ?

• H03F 1/02 - Modifications of amplifiers to raise the efficiency, e.g. gliding Class A stages, use of an auxiliary oscillation
• H03F 3/60 - Amplifiers in which coupling networks have distributed constants, e.g. with waveguide resonators
• H03H 15/00 - Transversal filters
• H04B 1/00 - TRANSMISSION - Details of transmission systems not characterised by the medium used for transmission
• H04B 1/04 - Circuits

Abstract

Optical element or module designed to be placed in front of an optical sensor of a semiconductor component, through at least one optically useful part of which (5a) the image to be captured is designed to pass, processing method for obtaining such an optical element, in which at least one through passage (25) runs between its front and rear faces and having a refractive index that varies starting from the wall of the said at least one through passage and into the said optically useful part under the effect of ion doping. Image capture apparatus comprising an optical imaging module comprising at least one such element.

IPC Classes  ?

• G02B 3/00 - Simple or compound lenses
• H01L 27/146 - Imager structures

Abstract

The invention relates to a method and a circuit for verifying data transferred between a circuit (21) and a processing unit (11), in which: the data originating from the circuit travels through a first temporary storage element (23) having a size representing an integer multiple of the size of data liable to be presented subsequently on a bus (27) of the processing unit; an address provided by the processing unit (11) destined for the circuit is stored temporarily in a second element (22); and the content of the first element is compared with a current data item (CDATA) originating from the circuit, at least when said data item corresponds to an address of a data item already present in this first element.

IPC Classes  ?

• G06F 21/55 - Detecting local intrusion or implementing counter-measures
• G06F 21/60 - Protecting data

Abstract

Lamb wave resonator (100), comprising at least one piezoelectric layer (102) and a first electrode (106) placed against a first face of the piezoelectric layer and the pattern of which, in a plane parallel to the plane of the first face of the piezoelectric layer, comprises at least two fingers (108) and a contact arm (110), each of the fingers having a first side in contact with said arm and two other sides parallel to each other and spaced apart by a distance W given by the formula, in which: n ∈ N, valateral is the acoustic propagation velocity of the Lamb waves, n is the order of the resonant mode and f is the resonant frequency of the resonator, portions (114) of the piezoelectric layer, which lie in the plane of the first face, between the fingers of the first electrode, being at least partially etched.

IPC Classes  ?

• H03H 9/02 - Networks comprising electromechanical or electro-acoustic elements; Electromechanical resonators - Details

Abstract

The invention relates to a porous silicon wafer serving as a fuel cell holder, that comprises on the upper face a plurality of recesses (5), said upper face being coated with a layer of porous silicon (7) having pores smaller than those of the wafer body.

IPC Classes  ?

• H01M 8/10 - Fuel cells with solid electrolytes
• C25F 3/12 - Etching of semiconducting materials
• H01L 21/00 - Processes or apparatus specially adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof

Abstract

The invention relates to an electromechanical component vibrating at a nanometric or micrometric scale that comprises a vibrating mechanical member (1) interacting with at least one so-called detection electrode (2). The detection electrode (2) is flexible and can vibrate in phase-opposition relative to the vibrating mechanical member (1). The invention can be used in resonators and movement detectors.

IPC Classes  ?

• H03H 9/02 - Networks comprising electromechanical or electro-acoustic elements; Electromechanical resonators - Details
• H03H 3/007 - Apparatus or processes specially adapted for the manufacture of impedance networks, resonating circuits, resonators for the manufacture of electromechanical resonators or networks

Abstract

A collection of K initial symbols is encoded with a code of the parity check type. The K initial symbols belong to a Galois field of order q strictly greater than 2. The code is defined by code characteristics representable by a graph (GRH) comprising N-K first nodes (NC1), each node satisfying a parity check equation defined on the Galois field of order q, N packets of intermediate nodes (NITi) and NI second nodes (NSSi), each intermediate node being connected to a single first node and to several second nodes by way of a linking scheme. The collection of K initial symbols is encoded using said code characteristics and a collection of N encoded symbols is obtained, said symbols being respectively subdivided into NI sub-symbols belonging respectively to mathematical sets whose orders are less than q, according to a subdivision scheme representative of the linking scheme (II).

IPC Classes  ?

• H03M 13/11 - Error detection or forward error correction by redundancy in data representation, i.e. code words containing more digits than the source words using block codes, i.e. a predetermined number of check bits joined to a predetermined number of information bits using multiple parity bits

Abstract

A method for preparing a multilayer substrate, comprising the step of deposing an epitaxial Y-AI2O3 Miller indice (001) layer (22) on a Si Miller indice (001) substrate (20).

IPC Classes  ?

• H01L 21/28 - Manufacture of electrodes on semiconductor bodies using processes or apparatus not provided for in groups
• H01L 29/51 - Insulating materials associated therewith
• H01L 21/314 - Inorganic layers

Abstract

A resistor formed of a lightly-doped P- type region (35) formed in a portion (29) of a lightly-doped N-type semiconductor well (29) extending on a lightly-doped P-type semiconductor substrate (21), the well being laterally delimited by a P-type wall (27) extending down to the substrate, the portion of the well being delimited, vertically, by a heavily-doped N-type area (31) at the limit between the well and the substrate and, horizontally, by a heavily-doped N- type wall (33). A diode (45) is placed between a terminal (37) of the resistor and the heavily-doped N-type wall (33), the cathode of the diode being connected to said terminal.

IPC Classes  ?

• H01L 27/06 - Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body including a plurality of individual components in a non-repetitive configuration
• H01L 29/8605 - Resistors with PN junction

Abstract

The invention relates to an isolated monolithic electrical converter comprising a substrate made of a resistive material (4), the underside of which has two input electrodes (2, 3) spaced apart from each other, constituting the primary, an insulating layer (5) on the top side of the substrate, and, on the insulating layer (5), at least two elements (7, 9) made of respectively p-doped and n-doped semiconductor thermoelectric materials electrically connected in series, the ends of the series connection constituting the secondary of the converter.

IPC Classes  ?

• H01L 27/16 - Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including thermomagnetic components
• H02J 7/00 - Circuit arrangements for charging or depolarising batteries or for supplying loads from batteries
• H04M 1/02 - Constructional features of telephone sets
• H01L 35/30 - SEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR - Details thereof operating with Peltier or Seebeck effect only characterised by the heat-exchanging means at the junction

Abstract

A digital delta-sigma modulator including a signal input for receiving N-bit digital samples, digital filter means connected to the signal input for performing add/subtract and integration operations using redundant arithmetic encoding to give filtered digital samples, and quantization means for performing a non-exact quantization operation to give n-bit output digital samples, where n is less than N. The input of the quantization means is connected within the digital filter means.

IPC Classes  ?

• H03M 7/00 - Conversion of a code where information is represented by a given sequence or number of digits to a code where the same information is represented by a different sequence or number of digits

Abstract

The reconfigurable power amplifier of the present invention includes at least one amplification circuit (E1, E2) and control means (6) of said amplification circuit for adapting the operation thereof depending on an input signal (RF in) applied thereto. The control means include means (4, 5) for modifying the compression point of said amplification circuit and for adapting the gain of the circuit in order to increase the efficient added power of the circuit for the modified compression point.

IPC Classes  ?

• H03F 1/02 - Modifications of amplifiers to raise the efficiency, e.g. gliding Class A stages, use of an auxiliary oscillation
• H03F 1/56 - Modifications of input or output impedances, not otherwise provided for
• H03F 3/19 - High-frequency amplifiers, e.g. radio frequency amplifiers with semiconductor devices only
• H03F 3/68 - Combinations of amplifiers, e.g. multi-channel amplifiers for stereophonics

Abstract

The invention relates to a device for controlling the speed and the rotation direction of an asynchronous motor (1), comprising a first circuit (7) with two bi-directional switches (T'4, T'5) individually controlled and having first conducting terminals connected to a common terminal (6) for applying a direct potential (Vcc) and having second conducting terminals that can be respectively connected to the first ends (12, 14) of windings (15, 16) of the motor stator, and a second circuit (3') with at least two parallel bi-directional switches (T1, T2, T3) individually controlled and having first respective conducting terminals (K i) connected to the common terminal.

IPC Classes  ?

• H02P 1/42 - Arrangements for starting electric motors or dynamo-electric converters for starting dynamo-electric motors or dynamo-electric converters for starting an individual single-phase induction motor
• H02P 25/04 - Single phase motors, e.g. capacitor motors

Abstract

The invention relates to a volume acoustic resonator having an adjustable resonance frequency, comprising a piezoelectric member with two electrodes. It further includes a switching member (12) defining an additional electrode that is selectively superimposed on one of the electrodes for varying the total thickness of said electrode and modifying the resonance frequency of the resonator accordingly.

IPC Classes  ?

• H03H 9/17 - Constructional features of resonators consisting of piezoelectric or electrostrictive material having a single resonator
• B81B 3/00 - Devices comprising flexible or deformable elements, e.g. comprising elastic tongues or membranes

Abstract

The invention relates to a method by which a processor (IC1) executes a program read in a program memory (MEM1), comprising the following steps: detection of a program memory read address jump; prior to a program memory read address jump instruction, prediction of an instruction for the storage of the presence of the address jump instruction; and activation of an error signal (ERR) if an address jump has been detected and if the presence of an address jump instruction has not been stored. The invention can be used to secure integrated circuits.

IPC Classes  ?

• G06F 21/55 - Detecting local intrusion or implementing counter-measures
• G06F 21/77 - Protecting specific internal or peripheral components, in which the protection of a component leads to protection of the entire computer to assure secure computing or processing of information in smart cards

Abstract

The invention relates to an inductive microdevice comprising a rectilinear solenoid winding (13) provided with a plurality of disjointed rectangular turns (14), each one having pre-determined dimensions. At least one of the dimensions of the turns (14) is variable and is determined individually for each turn (14) according to the position of the turn along the winding (13) and pre-determined magnetic characteristics of the winding (13), especially a homogeneous magnetic field and/or an optimum quality factor. Said variable dimension of the turns (14) is selected from the width, length, thickness (EB0B) and height of the turn (ISOL), and the value of the gap (INT) between two adjacent turns (14).

IPC Classes  ?

• H01F 5/00 - Coils

Abstract

The invention relates to an electronic charge retention circuit for time measurement, comprising: at least a first capacitive element (C1), a first electrode (21) of which is connected to a floating node (F); at least a second capacitive element (C2), a first electrode (31) of which is connected to said floating node (F), the first capacitive element having a leakage through its dielectric space (23) and the second capacitive element having a capacitance greater than the first; and at least a first transistor (5) having an isolated control terminal connected to said floating node.

IPC Classes  ?

• G11C 27/02 - Sample-and-hold arrangements

Abstract

The invention relates to a method and a circuit for reading an electronic charge retention element (10) for a temporal measurement, of the type comprising at least one capacitive element (C1, C2) whose dielectric exhibits a leakage and a transistor with insulated control terminal (5) for reading the residual charges, the reading circuit comprising: two parallel branches between two supply terminals, each branch comprising at least one transistor of a first type (P1, P2) and one transistor of a second type (N3, 5), the transistor of the second type of one of the branches consisting of that of the element to be read and the transistor of the second type of the other branch receiving, on its control terminal, a staircase signal (VDAC), the respective drains of the transistors of the first type being connected to the respective inputs of a comparator (135) whose output (OUT) provides an indication of the residual voltage in the charge retention element.

IPC Classes  ?

• G11C 27/00 - Electric analogue stores, e.g. for storing instantaneous values
• G11C 7/10 - Input/output [I/O] data interface arrangements, e.g. I/O data control circuits, I/O data buffers

Abstract

The invention relates to a method of controlling an electronic charge retention circuit for time measurement, comprising at least a first capacitive element (C1), the dielectric of which has a leakage, and at least a second capacitive element (C2), the dielectric of which has a higher capacitance than the first, the two elements having a common electrode defining a floating node (F) that can be connected to an element (5) for measuring its residual charge, in which a charge retention period is programmed or initialized by injecting or extracting charges via the first element.

IPC Classes  ?

• G11C 27/02 - Sample-and-hold arrangements

Abstract

The invention relates to an electronic charge retention circuit for time measurement, implanted in an array of EEPROM memory cells, each comprising a selection transistor in series with a floating-gate transistor, the circuit comprising, on any one row of memory cells: a first subassembly of at least a first cell (C1), the thickness of the dielectric of the tunnel window of the floating-gate transistor of which is less than that of the other cells; a second subassembly of at least a second cell (C2), the drain and source of the floating-gate transistor of which are interconnected; a third subassembly of at least a third cell (7); and a fourth subassembly of at least a fourth cell (6), the tunnel window of which is omitted, the respective floating gates of the transistors of the cells of the four subassemblies being interconnected.

IPC Classes  ?

• G11C 16/04 - Erasable programmable read-only memories electrically programmable using variable threshold transistors, e.g. FAMOS
• G11C 16/26 - Sensing or reading circuits; Data output circuits
• G11C 16/22 - Safety or protection circuits preventing unauthorised or accidental access to memory cells

Abstract

This invention relates to systems, methods and apparatus for driving organic light emitting diodes (OLED) displays, in particular those using multi-line addressing (MLA) techniques. Embodiments of the invention are particularly suitable for use with so-called passive matrix OLED displays. A current drive system for an electroluminescent display, the system comprising: a plurality of current mirrors having a plurality of outputs for driving a plurality of drive electrodes of said display, each said current mirror having a reference signal input; and an automatic selector coupled to said current mirror outputs to automatically select a said output for providing reference signal inputs to said current mirrors.

IPC Classes  ?

• G09G 3/32 - Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED]

Abstract

The invention concerns a device for processing a digital image comprising at least one contour region, including sharpness processing of the contour region. The sharpness processing includes converting data of the level of pixels of the contour zone into initial main data (step 2), ranging between a minimum value, for example 0 and a main value based on the amplitude of the contour, a sharpness sub-processing performed on said initial main data so as to obtain final main data (steps 3 to 10), and converting the final main data into final data of levels (step 11).

IPC Classes  ?

• H04N 5/208 - Circuitry for controlling amplitude response for correcting amplitude versus frequency characteristic for compensating for attenuation of high frequency components, e.g. crispening, aperture distortion correction

Abstract

The invention relates to a binary frequency divider (DIVF2) comprising a counter (CMPT) gated by an input signal (CK1), means (CP1, CP2) for comparing a count value (VAL) with first and second threshold values (B2/2, B2/4) and providing first and second control signals (DET1, DET2) synchronized with a first type of variation edges of the input signal (CK1). According to the invention, the divider comprises means (FFB) for providing at least one third control signal (SDET1, SDET2) offset by half a period from the input signal (CK1) with respect to one of the first or second control signals (DET1, DET2), and control means (ALCT) for generating the output signal (CK2) from control signals chosen on the basis of the value of at least one lowest-order bit (b1, b0) of the division instruction. Application in particular to UHF transponders.

IPC Classes  ?

• H03K 23/66 - Pulse counters comprising counting chains; Frequency dividers comprising counting chains with a base or radix other than a power of two with a variable counting base, e.g. by presetting or by adding or suppressing pulses

Abstract

The invention concerns a method and a system for encoding digital data (DATA) represented by source symbols, with an error correcting code generating parity symbols from, for each parity symbol, a plurality of source symbols and at least one parity symbol of preceding rank, including at least encrypting once (54) at least one first value (P1) into several encrypted values and integrating at least one combination (P1,j) of said encrypted values to compute (55) at least one part (P2... Pn-k) of said parity symbols.

IPC Classes  ?

• H04L 9/00 - Arrangements for secret or secure communications; Network security protocols
• H04L 1/00 - Arrangements for detecting or preventing errors in the information received

Abstract

The invention relates to a fuel cell whose active stack (5, 6, 7) is placed on a thin conductor layer (29) supported by a plate (21) which is provided with gas supply transversal channels (25), wherein said thin layer is projected into the active stack in front of each channel and is transparent to said gas.

IPC Classes  ?

• H01M 8/10 - Fuel cells with solid electrolytes
• H01M 8/04 - Auxiliary arrangements, e.g. for control of pressure or for circulation of fluids

Abstract

The invention concerns a reconfigurable hierarchical computer architecture having N levels, where N is an integer value greater than one, wherein said N levels comprise a first level comprising a first computation block comprising a first data input, a first data output and a plurality of computing nodes interconnected by a first connecting means, each computing node comprising an input port, a functional unit and an output port, the first connecting means capable of connecting each output port to the input port of each other computing node; and a second level comprising a second computation block comprising a second data input, a second data output and a plurality of said first computation blocks interconnected by a second connecting means for selectively connecting said first data output of each of said first computation blocks and said second data input to each of said first data inputs and for selectively connecting each of said first data outputs to said second data output.

IPC Classes  ?

• G06F 15/78 - Architectures of general purpose stored program computers comprising a single central processing unit
• G06F 15/80 - Architectures of general purpose stored program computers comprising an array of processing units with common control, e.g. single instruction multiple data processors

Abstract

The invention relates to a resistive element comprising two vertical resistive parts (R1a, R1b) placed in two holes formed in the upper part of a substrate (1) and a horizontal resistive part (RIc) formed in a buried cavity connecting the bottoms of the holes.

IPC Classes  ?

• H01L 27/08 - Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body including only semiconductor components of a single kind
• H01L 21/02 - Manufacture or treatment of semiconductor devices or of parts thereof

Abstract

The invention relates to a multilayer fuel cell consisting of a layer stack (8) formed on the front face of a perforated substrate (21, 31), a first electrode corresponding to the stack external surface and a second electrode (27) corresponding to the stack bottom and connected to the rear face of the substrate by a conductor path extending along the perforated part of the substrate.

IPC Classes  ?

• H01M 8/02 - Fuel cells; Manufacture thereof - Details
• H01M 8/10 - Fuel cells with solid electrolytes
• H01M 8/24 - Grouping of fuel cells, e.g. stacking of fuel cells

Abstract

The invention relates to a method and a circuit for controlling an energy recovery stage of a plasma screen comprising a resonant circuit of at least one inductive element (L) and of a capacitive element (Cs), in which the capacitive element is precharged halfway with a supply voltage (Vs) of the screen.

IPC Classes  ?

• G09G 3/28 - Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix using controlled light sources using luminous gas-discharge panels, e.g. plasma panels

Abstract

The invention concerns an inductive coupling reader (50) comprising a passive interface circuit (16) for modulating the impedance of an antenna circuit (13) and extracting from the antenna circuit a data signal (SDTr) and an RF clock signal (CKO), and means (DB3) for connecting the reader to a removable security module (40, 43). The invention is characterized in that the reader comprises an emulation circuit (17) for opening a RF communication channel with another reader, a non removable electrical connection connecting the emulation circuit (17) to the passive interface circuit (16), whereby the data signal (SDTr) and the RF clock signal (CKO) are supplied to the emulation circuit (17) and a data bus (DB3) timed by a bus clock signal of lower frequency than the RF clock signal frequency, to connect the emulation circuit (17) to the removable security module (40, 43). The invention provides the advantage of producing a low energy consuming reader.

IPC Classes  ?

• G06K 7/00 - Methods or arrangements for sensing record carriers
• G06K 19/07 - Record carriers with conductive marks, printed circuits or semiconductor circuit elements, e.g. credit or identity cards with integrated circuit chips

Abstract

The invention concerns a method of fabricating a device, comprising the steps of forming a first silicon oxide layer within a first region of said device and a second silicon oxide layer within a second region of said device, implanting doping ions of a first type into said first region, implanting doping ions of a second type into said second region, and etching said first and second regions for a determined duration such that said first silicon oxide layer is removed and at least a part of said second silicon oxide layer remains.

IPC Classes  ?

• H01L 21/8238 - Complementary field-effect transistors, e.g. CMOS
• H01L 21/311 - Etching the insulating layers

Abstract

The invention relates to a method of block-writing to an electrically-programmable non-volatile memory element, in which a block to be written to the memory comprises at least one word. According to the invention, the method comprises the following steps consisting in: determining the write time of a word by dividing a fixed write time for a block by the number of words from the block to be written, and controlling the memory in order to write each word (D) successively to the memory element during the write time.

IPC Classes  ?

• G11C 16/10 - Programming or data input circuits

Abstract

One delay circuit is inserted in open loop inside a clock recovery circuit for improving the accuracy of clock recovery. One oscillator signal &phgr;(0) to &phgr;(2i-1) is provided with a basic Step of Time. A rational number of Step of Time corresponding to a bit-duration is measured inside a received flow of bits. The oscillator signal &phgr;(0) to j(2i-1) is transformed into a clock signal CK having active edges of said clock signal in phase with at least one oscillator signal &phgr;(0) to &phgr;(2i-1), two consecutive active edges being separated by a time duration proportional to the integer part of the number of Step of Time. A time delay is computed proportional to the fractional part of the number of Step of Time. The next active edge of the clock signal CK is delayed of said computed delay.

IPC Classes  ?

• G06F 1/04 - Generating or distributing clock signals or signals derived directly therefrom
• H03L 7/197 - Indirect frequency synthesis, i.e. generating a desired one of a number of predetermined frequencies using a frequency- or phase-locked loop using a frequency divider or counter in the loop a time difference being used for locking the loop, the counter counting between numbers which are variable in time or the frequency divider dividing by a factor variable in time, e.g. for obtaining fractional frequency division

Abstract

The invention relates to a method of modulating the impedance of an antenna circuit (ACT, W1, W2) which supplies pumping signals (S1, S2) to a charge pump (PMP) comprising at least a first pumping stage (D1, D2, C1, C2) and a last pumping stage (D5, D6, C5, C6), said last pumping stage supplying a DC voltage (Vcc). According to the invention, the output from the first pumping stage (D1, D2, C1, C2) is short-circuited by means of a switch (SW1) and the last pumping stage continues to pump the electric charges and to supply the DC voltage (Vcc). The invention is particularly suitable for RFID passive transponders.

IPC Classes  ?

• G06K 19/07 - Record carriers with conductive marks, printed circuits or semiconductor circuit elements, e.g. credit or identity cards with integrated circuit chips

Abstract

The invention concerns a method for generating a clock signal including the following steps: measuring with a first clock signal (SFo) one characteristic of a reference event (EVT1) in a received signal (RS); determining with the first clock signal, a variation of one characteristic of a second event (EVT1, DO) in a received signal (RS); correcting the measurement (NEVT1, NFC) based on the variation of the characteristic of the second event; and generating a second clock signal (SFC) from the first clock signal based on the corrected measurement (NFC). The invention is applicable to transmitting and receiving circuits of a contact-free chip.

IPC Classes  ?

• H04L 7/033 - Speed or phase control by the received code signals, the signals containing no special synchronisation information using the transitions of the received signal to control the phase of the synchronising-signal- generating means, e.g. using a phase-locked loop

Abstract

The invention concerns a passive contact-free integrated circuit (IC2) comprising an electrically programmable non-volatile data memory (MEM), a booster circuit with load accumulation (HVCT, PMP, HGEN) to supply a high voltage (Vhv) required for writing data (DTW) into the memory. The invention is characterized in that the integrated circuit comprises a volatile memory point (FFI) for storing an indicator flag (THR2); and means (THDET, THRl, FFl) for modifying the value of the indicator flag (THR2) when the high voltage (Vhv) reaches the critical threshold (Vc) for the first time following activation of the booster circuit.

IPC Classes  ?

• G11C 5/14 - Power supply arrangements

Abstract

The invention relates to a remanent volatile memory cell (PVCELL) for storing a binary datum (Fp) for a retention time (Tp) that is independent of the memory cell supply voltage (Vcc). According to the invention, the memory cell comprises: a capacitive memory point (CMP) which supplies a remanent voltage (Vp) and which has a determined discharge time, a switch (T1) which is used to discharge the memory point when an erase signal (RESET) has an active value, a switch (T2) which is used to charge the memory point when a write signal (SET) has an active value, and a detector/amplifier circuit (SACT) comprising an input (INI) which receives the remanent voltage (Vp) and an output (OUT1) which supplies the binary datum (Fp). The invention is particularly suitable for managing an inventory flag in a contactless integrated circuit.

IPC Classes  ?

• G11C 11/24 - Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using capacitors
• G11C 11/401 - Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming cells needing refreshing or charge regeneration, i.e. dynamic cells

Abstract

The invention relates to a method of configuring a memory space (MEM), comprising the following steps consisting in: reading a configuration datum (SZ3) in the memory space (MEM) and dividing at least part of the memory space into memory areas (Z1-Z4) as a function of the configuration datum read; and assigning each memory area with an access number (NBK) that is used to access a datum location in the memory area, together with a logical address of the location in the memory area. The invention is suitable for RFID chips.

IPC Classes  ?

• G06F 12/02 - Addressing or allocation; Relocation

Abstract

The invention relates to a passive resistive dipole (30) in a monolithic form, comprising a series or parallel combination of at least two magnetoresistive memory elements (31, 32, 33, 34).

IPC Classes  ?

• H01L 27/22 - Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate using similar magnetic field effects
• H01L 43/08 - Magnetic-field-controlled resistors
• H03F 3/45 - Differential amplifiers

Abstract

The invention concerns a DC/DC converter-regulator designed to connect a fuel cell (14) to a filter (17) adapted to be connected to means for electrochemical storage (11) of electric power during a charging operation of the storage means. The converter-regulator comprises means (22, 28, 30) adapted to maintain, during the charging operation, the voltage (VFC) at the terminals of the fuel cell, at a given operating voltage.

IPC Classes  ?

• H04M 1/725 - Cordless telephones
• H02M 3/158 - Conversion of dc power input into dc power output without intermediate conversion into ac by static converters using discharge tubes with control electrode or semiconductor devices with control electrode using devices of a triode or transistor type requiring continuous application of a control signal using semiconductor devices only with automatic control of output voltage or current, e.g. switching regulators including plural semiconductor devices as final control devices for a single load
• H02J 7/34 - Parallel operation in networks using both storage and other dc sources, e.g. providing buffering

Abstract

The invention concerns a reading amplifier (SA3) for reading a memory cell (MC (i, j,k) ), comprising: a reading node (Sin) connected to the memory cell, an active stage (RST3) connected to the reading node (Sin) and including means (TP3, TN3) for supplying a reading current (Ic) on the reading node, and a data output (Sout) connected to a node (N1) of the active stage where an electric voltage occurs representing the state of conductivity of the memory cell. The invention is characterized in that the reading amplifier includes means (TN5, R1) for adjusting a voltage (Vs) occurring on the reading node to a value lower than a threshold voltage value (Vtn) related to the manufacturing technology of the reading amplifier. The invention is applicable in particular to reading non-volatile EEPROM, FLASH and PCM memories.

IPC Classes  ?

• G11C 7/06 - Sense amplifiers; Associated circuits

Abstract

The invention concerns a radio frequency device comprising an electrically conductive element associated with at least one first continuous magnetic element including a substrate coated with a magnetic film having a granular structure with grains inclined relative to the normal to the substrate or a fibrous texture inclined relative to the normal to the substrate.

IPC Classes  ?

• H01F 10/00 - Thin magnetic films, e.g. of one-domain structure
• H01F 41/18 - Apparatus or processes specially adapted for manufacturing or assembling magnets, inductances or transformers; Apparatus or processes specially adapted for manufacturing materials characterised by their magnetic properties for applying magnetic films to substrates by cathode sputtering
• H01F 41/20 - Apparatus or processes specially adapted for manufacturing or assembling magnets, inductances or transformers; Apparatus or processes specially adapted for manufacturing materials characterised by their magnetic properties for applying magnetic films to substrates by evaporation
• H01P 1/215 - Frequency-selective devices, e.g. filters using ferromagnetic material
• H01F 17/00 - Fixed inductances of the signal type

Abstract

The invention concerns a method and a circuit for protecting a numerical quantity (d) contained in an integrated circuit (1) on a first number of bits (n), in a modular exponentiation computing of a data (M) by said numerical quantity, which consists in: selecting at least one second number (j) included between the unit and said first number minus two; dividing said numerical quantity into at least two parts, a first part (d(j-1, 0)) comprising, from the bit of rank null, a number of bits equal to said second number, a second part (d(n-1, j)) comprising the remaining bits; for each part of the quantity, computing a first modular exponentiation (32, 33) of said data by the part concerned and a second modular exponentiation (36, 34) of the result of the first by the figure 2 exponentiated to the power of the rank of the first bit of the part concerned; and computing (35) the product of the results of the first and second modular exponentiations.

IPC Classes  ?

• H04L 9/30 - Public key, i.e. encryption algorithm being computationally infeasible to invert and users' encryption keys not requiring secrecy
• G06F 7/72 - Methods or arrangements for performing computations using a digital non-denominational number representation, i.e. number representation without radix; Computing devices using combinations of denominational and non-denominational quantity representations using residue arithmetic

Abstract

Source electrodes (3) and drain electrodes (4) are each constituted of an alternation of first layers (5) and second layers (6) made of a germanium and silicon composite. The first layers (5) have a concentration of germanium ranging from 0 % to 10 %, and the second layers (6) have a concentration of germanium ranging from 10 % to 50 %. At least one channel (1) connects two second layers (6a, 6b), respectively, of the source electrodes (3) and drain electrodes (4). The invention involves the etching of source and drain regions connected by a narrow area, in a stack of layers (5, 6). Next, a superficial thermal oxidation of said stack is effected whereby oxidizing the silicon of the germanium and silicon composite having a concentration of germanium ranging from 10 % to 50 % and condensing the germanium Ge. The silicon oxide of the narrow area is eliminated and a gate dielectric (7) and a gate (2) are deposited on the condensed germanium of the narrow area.

IPC Classes  ?

• H01L 29/10 - Semiconductor bodies characterised by the shapes, relative sizes, or dispositions of the semiconductor regions with semiconductor regions connected to an electrode not carrying current to be rectified, amplified, or switched and such electrode being part of a semiconductor device which comprises three or more electrodes
• H01L 21/336 - Field-effect transistors with an insulated gate

Abstract

La presente invention concerne en particulier une prothese de nucleus d'un disgue intervertebral (1) qui se presente sous Ia forme d'un filament souple (5) d'un elastomere biocompatible. Le materiau de remplissage est adapte a 1' injection au moyen d'une aiguille creuse (4) dans Ia cavite (2) de l'annulus. Le filament serpente au contact des parois (6) et de ses propres segments de mani-re a former un enchevetrement remplissant Ia cavite. Selon un autre aspect, 1' invention concerne une prothese de vertebroplastigue destinee a remplir une cavite osseuse, comprenant ledit materiau de remplissage.

IPC Classes  ?

• H01L 23/498 - Leads on insulating substrates
• H01L 23/482 - Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads or terminal arrangements consisting of lead-in layers inseparably applied to the semiconductor body
• H01L 21/60 - Attaching leads or other conductive members, to be used for carrying current to or from the device in operation

Abstract

The invention relates to a memory (1) protected from fault injection during data readout. The memory includes means for reading reference data (WL(ref)) out of the memory during a step of reading out data stored in the memory; means (CTL) for comparing the read-out reference data with an expected value; and means (CTL) for generating a error signal (ER) when the read-out data differs from the expected value. The invention is useful for protecting smart card memories.

IPC Classes  ?

• G11C 7/24 - Memory cell safety or protection circuits, e.g. arrangements for preventing inadvertent reading or writing; Status cells; Test cells
• G11C 16/22 - Safety or protection circuits preventing unauthorised or accidental access to memory cells

Abstract

The invention relates to an electronic circuit including a plurality of configurable cells (2a, ..., 2Y, 2z) configured by a control circuit such as an access controller (CTAP) when it receives a mode control signal (TEST_MODE): either in a functional condition in which the configurable cells are operably connected to logic cells (10 to 15) with which they cooperate to form at least one logic circuit, when the mode control signal is in a first (inoperative) condition, or in a chained condition in which the configurable cells are operably connected in a chain to form a shift register, when the mode control signal is in a second (operative) condition. The circuit as per the invention further includes a detection circuit for generating an operative condition signal (ETAT) if a chained condition is detected in the configurable cells when the control circuit receives the mode control signal in the first condition.

IPC Classes  ?

• G01R 31/317 - Testing of digital circuits
• G01R 31/3185 - Reconfiguring for testing, e.g. LSSD, partitioning

Abstract

The invention concerns an inductive element for forming an electromagnetic transponder antenna, comprising a first group of mutually parallel conductors (p1') coplanar in a first plane, a second group of mutually parallel conductors (p2') coplanar in a second plane parallel to the first plane, and an insulating material (52') separating the two groups of conductors, one end of each conductor of the first group being connected to one end of a conductor of the second group whereof the other end is connected to one end of another conductor of the first group, the connections between the conductors being conductive via holes (v) in the thickness of the insulating material.

IPC Classes  ?

• G06K 19/077 - Constructional details, e.g. mounting of circuits in the carrier

Abstract

The invention relates to a microresonator comprising a resonant element (160) which is made from monocrystalline silicon and at least one activation electrode (120, 121) which is positioned close to the resonant element, whereby the resonant element is placed in an opening in a semiconductor layer (110) that covers a substrate (110), said activation electrode being formed in the semiconductor layer level with the opening.

IPC Classes  ?

• B81B 3/00 - Devices comprising flexible or deformable elements, e.g. comprising elastic tongues or membranes
• H03H 3/007 - Apparatus or processes specially adapted for the manufacture of impedance networks, resonating circuits, resonators for the manufacture of electromechanical resonators or networks

Abstract

The invention relates to a discharge circuit consisting of an output circuit (20, T22) comprising one output (4) which is connected to an electrical load (CLoad) in order to absorb a discharge current supplied by the load (CLoad) when a logic signal (IN) orders the load (CLoad) to be discharged. According to the invention, the discharge circuit also comprises a control circuit (30, 40) for supplying the output circuit with a suitable control signal (INN) such that the slope of the output potential (OUT) (4) of the output circuit (20, T22) decreases progressively when the logic signal (IN) orders the load (CLoad) to be discharged. Moreover, by varying the slope of the output potential progressively, and not suddenly, the electromagnetic radiation generated by said variations can be limited. The invention can be used to produce power output stages for controlling plasma display cells.

IPC Classes  ?

• G09G 3/28 - Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix using controlled light sources using luminous gas-discharge panels, e.g. plasma panels

Abstract

The invention concerns a method for thinning a first semiconductor wafer (1) from a first side (12), which consists in applying, on the second side of the first wafer, a second wafer (3) with an interposed photoresist layer (2).

IPC Classes  ?

• H01L 21/68 - Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components for positioning, orientation or alignment
• H01L 21/78 - Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices

Abstract

This invention relates to a method for sampling an analogue radiofrequency signal comprising reception of the analogue radiof requency signal, sending of the received signal on two analogue channels (I, Q), each channel performing a first signal sampling operation (9, 10), including a filtering step (13, 14) eliminating signal frequencies that could fold on the useful signal during sampling such that the sampled signal represents a filtered version of the received signal, the said method being characterised in that the sampling frequency (Fsl) is taken to be equal to the frequency (Fc) of the signal carrier divided by a factor Ndivl+1/2, Ndivl being an integer number, to bring the useful signal to half of the sampling frequency after sampling.

IPC Classes  ?

• H03H 17/02 - Frequency-selective networks

Abstract

The invention relates to a method for protecting an integrated circuit. According to said method, the start-up of all, or part, of the circuit is determined in the presence of a key (KEY) which is recorded in a non-volatile manner in the circuit, following the production thereof, and depends on at least one first parameter (A, ID) which is present in a non-volatile manner in the circuit after the production thereof.

IPC Classes  ?

• G06K 19/073 - Special arrangements for circuits, e.g. for protecting identification code in memory

Abstract

The invention concerns the generation of a chip identifier (2) bearing at least one integrated circuit, which consists in providing a cutout of least one conductive path (4) by cutting the chip, the position of the cutting line (3) relative to the chip conditioning the identifier.

IPC Classes  ?

• H01L 23/544 - Marks applied to semiconductor devices, e.g. registration marks, test patterns

Abstract

The invention relates to a method for reading of the state of a non-volatile memory element (4), comprising adjusting the frequency of a first oscillator (1) to the state of said element, comparing the frequency of the first oscillator to the given frequency of a second oscillator (2), selected to fall between two possible frequency values for the first oscillator, according to the state of the memory element and comparing the frequency of the first oscillator to that of a third oscillator (3), with a frequency below that of the first oscillator in the programmed states for the memory element and below that of the second oscillator (2).

IPC Classes  ?

• G11C 7/06 - Sense amplifiers; Associated circuits

Abstract

The invention concerns a circuit (30) for detecting an overload in a load supplied by a switched-mode power supply, comprising: a first comparator (25) of a first voltage based on the supply voltage of the load relative to a first threshold (VFB), supplying a regulating signal (CT) to a pulse generator (6) controlling the switched-mode power supply; a second comparator (31) of a second voltage relative to a second threshold (VOLV), supplying a signal (OVL) indicating the presence of an overload; and means (C33, 34, 35, M35) for automatically controlling said second voltage by a third threshold (VINI) lower than the second and higher than the first, and for deactivating the second comparator as long as said automatic control is maintained.

IPC Classes  ?

• H02M 3/335 - Conversion of dc power input into dc power output with intermediate conversion into ac by static converters using discharge tubes with control electrode or semiconductor devices with control electrode to produce the intermediate ac using devices of a triode or a transistor type requiring continuous application of a control signal using semiconductor devices only

Abstract

An electronic circuit assembly (A1) comprises a casing (1) having two opposite outer faces (S1sup, S1inf) and an inner space (V1) separate from each outer faces by a respective closing portion (4, 5), and a single die (10) incorporating an integrated circuit. The casing (1) includes integrated electrically conducting elements (21) connecting terminals of the die (11) to pads of the casing (31sup). The electrically conducting elements also connect sets of pads respectively located on each one of the opposite outer face of the casing (31sup, 31inf). Such electronic circuit assemblies (A1-A4) are suitable for being stacked with bonding means (300, 303) arranged between respective sets of pads (31sup, 32inf) of two successive electronic circuit assemblies in a stack.

IPC Classes  ?

• H05K 1/18 - Printed circuits structurally associated with non-printed electric components
• H01L 25/10 - Assemblies consisting of a plurality of individual semiconductor or other solid state devices all the devices being of a type provided for in the same subgroup of groups , or in a single subclass of , , e.g. assemblies of rectifier diodes the devices having separate containers
• H05K 7/02 - Arrangements of circuit components or wiring on supporting structure

Abstract

The invention relates to a device consisting of an electromechanical microswitch comprising a mobile beam (2). According to the invention, at least part (14) of the beam forms the piezoelectric element of a piezoelectric actuator.

IPC Classes  ?

• B81B 1/00 - Devices without movable or flexible elements, e.g. microcapillary devices

Abstract

The invention relates to a method for modulating data (D) to be transmitted by an electromagnetic transponder (10') by means of at least one resistive and/or capacitive element (18) for modulating the charge of an oscillating circuit that it comprises. The invention consists of combining, by an involutive function (19), the flow of data to be transmitted with a spread spectrum sequence (ci(t)), said sequence being selected according to a configuration message (SRFU) received from a read/write terminal (1').

IPC Classes  ?

• G06K 19/07 - Record carriers with conductive marks, printed circuits or semiconductor circuit elements, e.g. credit or identity cards with integrated circuit chips
• G06K 7/10 - Methods or arrangements for sensing record carriers by corpuscular radiation
• H04B 1/59 - Responders; Transponders
• H04B 1/707 - Spread spectrum techniques using direct sequence modulation
• H04B 5/02 - Near-field transmission systems, e.g. inductive loop type using transceiver