Abstract

An electronic device includes a doped semiconductor substrate of a first conductivity type. First and second doped wells are provided, separated from each other by trench isolation, within the doped semiconductor substrate. At least one first region and at least one second region are respectively located in the first and second doped wells, with each first and second region having a doping level higher than a doping level of the first and second doped wells. The trench isolation penetrates into the first and second doped wells and extends laterally between the first region and second region. A third region laterally extends between the first and second doped wells at a location under the insulating trench. The third region has a doping level lower than the doping level of the first and second doped wells.

IPC Classes  ?

• H01L 27/02 - Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including integrated passive circuit elements with at least one potential-jump barrier or surface barrier
• H01L 29/74 - Thyristor-type devices, e.g. having four-zone regenerative action

Abstract

An electronic device includes a doped semiconductor substrate of a first conductivity type. A first doped well of a second conductivity type opposite to the first conductivity type extends into the doped semiconductor substrate from a surface thereof. A second doped well of the first conductivity type is located in the first well. A third electrically-insulating well is located in the second well. A fourth doped well of the first conductivity type is located in the third well. First, second, and third doped regions of the first conductivity type are respectively located in the doped semiconductor substrate, the second doped well and the fourth doped well. The first, second, and third doped regions have doping levels greater than a doping level of the doped semiconductor substrate. A fourth doped region the second conductivity type is located in the fourth doped well adjacent the second doped region.

IPC Classes  ?

• H01L 27/02 - Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including integrated passive circuit elements with at least one potential-jump barrier or surface barrier
• H01L 27/146 - Imager structures

Abstract

An embodiment method for estimating a missing or incorrect value in a table of values generated by a photosite matrix comprises a definition of a zone of the table comprising the value to be estimated and other values, referred to as neighboring values, and an estimation of the value to be estimated based on the primary neighboring values and the weight associated with these primary neighboring values, wherein a weight of each neighboring value, referred to as primary neighboring value, of the same colorimetric component as that of the missing or incorrect value to be estimated, is determined according to differences between neighboring values disposed on an axis and neighboring values disposed parallel with this axis and positioned in relation to this axis on the same side as the primary neighboring value for which the weight is determined.

IPC Classes  ?

• H04N 25/60 - Noise processing, e.g. detecting, correcting, reducing or removing noise
• H04N 23/84 - Camera processing pipelines; Components thereof for processing colour signals
• H04N 25/13 - Arrangement of colour filter arrays [CFA]; Filter mosaics characterised by the spectral characteristics of the filter elements
• H04N 25/705 - Pixels for depth measurement, e.g. RGBZ

Abstract

The present invention relates to an electronic device (1) comprising a silicon-on-insulator strip (100) laterally defined by insulating trenches (106); a first gate (112) supported by the strip; a second gate (114), or a third gate (116), parallel to the strip (100), supported by the strip and being separated from the first gate (112) a first gap (e1) or a second gap (e2); two first semiconductor regions (110), or two second semiconductor regions (108), doped and arranged along and on either side of the second gate (114) or the third gate (116); at least one fourth gate (122A, 122B), or at least one fifth gate (126A, 126B), arranged facing the first gap (e1) or the second gap (e2); and a region (130) for biasing a substrate under the strip.

IPC Classes  ?

• H01L 29/06 - Semiconductor bodies characterised by the shapes, relative sizes, or dispositions of the semiconductor regions
• H01L 29/423 - Electrodes characterised by their shape, relative sizes or dispositions not carrying the current to be rectified, amplified or switched
• H01L 29/66 - Types of semiconductor device
• H01L 29/76 - Unipolar devices
• B82Y 10/00 - Nanotechnology for information processing, storage or transmission, e.g. quantum computing or single electron logic

Abstract

A clock generator circuit includes an oscillator circuit coupled to a bias circuit. The bias circuit includes a current mirror, third and fourth transistors, and a cascode transistor. The current mirror includes a reference transistor and a set of copy transistors that are programmable. The third transistor has a source connected to a cold spot, a drain and a gate connected to this drain. The fourth transistor has a source connected to the drain of the third transistor, a drain, and a gate connected to that drain. The cascode transistor has a source connected to a drain of at least one of the copy transistors, a drain, and a gate connected to the gate of the fourth transistor. The gates of the fourth transistor and the cascode transistor are thicker than the gates of the reference transistor, each copy transistor, and the third transistor.

IPC Classes  ?

• H03K 3/03 - Astable circuits
• H03K 5/1252 - Suppression or limitation of noise or interference

Abstract

According to one aspect, the invention relates to a phased array antenna comprising: - a plurality of elementary antennas, - an amplifier circuit (AMPC) for each elementary antenna (ANTE), the amplifier circuit (AMPC) comprising: a power amplifier (PA) configured to amplify at least two useful signals of different frequencies to be transmitted by the elementary antenna, and a third-order intermodulation product control circuit (ICTRL) configured to control a third-order intermodulation product phase generated by the amplifier circuit so as to control an orientation of third-order intermodulation product radiation transmitted by the phased array antenna.

IPC Classes  ?

• H04B 1/04 - Circuits
• H03F 1/32 - Modifications of amplifiers to reduce non-linear distortion

Abstract

The present invention relates to a neutralised amplifier (50) comprising at least one variable-capacitance neutralising capacitor (76, 78), in which the at least one neutralising capacitor (76, 78) is configured to compensate for the phase variations introduced by the amplifier.

IPC Classes  ?

• H03F 1/14 - Modifications of amplifiers to reduce detrimental influences of internal impedances of amplifying elements by use of neutralising means
• H03F 3/26 - Push-pull amplifiers; Phase-splitters therefor
• H03F 3/193 - High-frequency amplifiers, e.g. radio frequency amplifiers with semiconductor devices only with field-effect devices

Abstract

An OFDM (orthogonal frequency division multiplexing) transmitter includes an inverse fast Fourier transform circuit, which, in operation, generates, based on digital input data, a complex time-varying digital signal having real and imaginary components; and a multiplexer adapted to generate a time-multiplexed digital signal by time-multiplexing one or more of the real components with one or more of the imaginary components.

IPC Classes  ?

• H04L 27/26 - Systems using multi-frequency codes
• H04L 27/20 - Modulator circuits; Transmitter circuits
• H04B 10/548 - Phase or frequency modulation
• H04B 10/69 - Electrical arrangements in the receiver

Abstract

The present description relates to a connector that can be configured mechanically between a wireless radio frequency transmission and a wired radio frequency transmission via a cylindrical radio frequency dielectric waveguide (202), the connector (1) comprising a first housing (102) joined to a printed circuit board (104) provided with a radio frequency antenna (108), and a second housing (200) configured to be joined to the waveguide (202), the second housing (200) being configured to be mounted on the first housing (102) in a removable manner in a wired transmission configuration and being detached from the first housing (102) in a wireless transmission configuration.

IPC Classes  ?

• H01P 3/16 - Dielectric waveguides, i.e. without a longitudinal conductor
• H01Q 13/08 - Radiating ends of two-conductor microwave transmission lines, e.g. of coaxial lines, of microstrip lines
• H01P 5/08 - Coupling devices of the waveguide type for linking lines or devices of different kinds
• H01P 1/208 - Cascaded cavities; Cascaded resonators inside a hollow waveguide structure
• H01P 5/107 - Hollow-waveguide/strip-line transitions
• H01R 13/62 - Means for facilitating engagement or disengagement of coupling parts or for holding them in engagement

Abstract

The present description concerns a method of manufacturing a first wafer, intended to be assembled to a second wafer by molecular bonding, including the successive steps of: forming a stack of layers at the surface of a substrate; and successive chemical etchings of the edges of said layers from the layer of the stack most distant from the substrate, across a smaller and smaller width.

IPC Classes  ?

• H01L 21/20 - Deposition of semiconductor materials on a substrate, e.g. epitaxial growth
• H01L 29/06 - Semiconductor bodies characterised by the shapes, relative sizes, or dispositions of the semiconductor regions
• H01L 21/3105 - After-treatment
• H01L 21/762 - Dielectric regions

Abstract

f) in order to generate an output image.

IPC Classes  ?

• G06T 5/00 - Image enhancement or restoration
• G06T 5/50 - Image enhancement or restoration by the use of more than one image, e.g. averaging, subtraction
• H04N 23/741 - Circuitry for compensating brightness variation in the scene by increasing the dynamic range of the image compared to the dynamic range of the electronic image sensors

Abstract

A method tests a plurality of devices, each device including a test chain having a plurality of positions storing test data. The testing includes comparing test data in a last position of the test chain of each of the devices. The test data in the test chains of the devices is shifted forward by one position. The shifting includes writing test data in the last position of a test chain to a first position in the test chain. The comparing and the shifting are repeated until the test data in the last position of each test chain when the testing is started is shifted back into the last position of the respective test chain. The plurality of devices may have a same structure and a same functionality.

IPC Classes  ?

• G01R 31/3185 - Reconfiguring for testing, e.g. LSSD, partitioning
• G01R 31/3177 - Testing of logic operation, e.g. by logic analysers
• G06F 11/267 - Reconfiguring circuits for testing, e.g. LSSD, partitioning
• G06F 11/16 - Error detection or correction of the data by redundancy in hardware
• G06F 11/18 - Error detection or correction of the data by redundancy in hardware using passive fault-masking of the redundant circuits, e.g. by quadding or by majority decision circuits
• G01R 31/3181 - Functional testing

Abstract

A method tests at least three devices, each device including a test chain having a plurality of positions storing test data. The testing includes comparing test data in a last position of the test chain of each of the devices, and shifting test data in the test chains of each of the devices and storing a result of the comparison in a first position of the test chains of each of the devices. The comparing and the shifting and storing are repeated until all the stored test data has been compared. The at least three devices may have a same functionality and a same structure.

IPC Classes  ?

• G01R 31/317 - Testing of digital circuits
• G01R 31/3185 - Reconfiguring for testing, e.g. LSSD, partitioning
• G06F 11/16 - Error detection or correction of the data by redundancy in hardware
• G06F 11/267 - Reconfiguring circuits for testing, e.g. LSSD, partitioning
• G01R 31/319 - Tester hardware, i.e. output processing circuits
• G01R 31/3193 - Tester hardware, i.e. output processing circuits with comparison between actual response and known fault-free response
• G06F 11/18 - Error detection or correction of the data by redundancy in hardware using passive fault-masking of the redundant circuits, e.g. by quadding or by majority decision circuits

Abstract

Methods and devices for adjusting a read threshold voltage of bitlines are provided. One such method includes adjusting a read threshold voltage of bitlines coupled to memory points of a memory circuit. The read threshold voltage is initially set to a first value. First data are written in the memory points and second data are read from the memory points. The second data are compared to the first data, and the threshold voltage is decreased by a second value in response to a comparison error of one of the second data with the corresponding first data.

IPC Classes  ?

• G11C 11/419 - Read-write [R-W] circuits

Abstract

Disclosed is a method for detecting the phase (Φ1) of an analogue signal (SA1) via a hybrid coupler (CH1) operating in a power combiner mode, the hybrid coupler (CH1) comprising a first input (BE1) intended to receive the analogue signal (SA1), a second input (BE2) intended to receive a reference signal (SREF) having a reference phase (Φ2) and a same frequency (FREF) as the analogue signal (SA1), and two outputs (BS1, BS2), and configured to respectively generate, at these two outputs (BS1, BS2), a first output signal (SS1) and a second output signal (SS2), comprising a measurement of the peak values (A1, A2, A3, A4) of the analogue signal (SA1), of the reference signal (SREF) and of at least one of the first and second output signals (SS1, SS2), a calculation of the phase-shift (Φ1-Φ2) between the phase (Φ1) of the analogue signal and the reference phase (Φ2) as a function of the measured peak values (A1, A2, A3, A4), and determination of the phase (Φ1) of the analogue signal (SA1) as a function of this calculated phase shift (Φ1-Φ2) and of the reference phase (Φ2).

IPC Classes  ?

• G01R 25/02 - Arrangements for measuring phase angle between a voltage and a current or between voltages or currents in circuits having distributed constants
• G01R 25/04 - Arrangements for measuring phase angle between a voltage and a current or between voltages or currents involving adjustment of a phase shifter to produce a predetermined phase difference, e.g. zero difference

Abstract

The method for detecting the phase (PI) of an analog signal (SI3) via a hybrid coupler (CH2) operating in a power combiner mode, the hybrid coupler (CH2) comprising a first input (BE3) intended to receive the analog signal (SI3), a second input (BE4) intended to receive an additional analog signal (SI4) phase shifted by 90° in relation to the analog signal (SI3), a first output (BS3) delivering an output signal (SS1), and a second output (BS4), comprises an injection at the second output (BS4) of a test signal (ST1) having an initial test phase (PTI), an iterative generation of a current test phase (PTC) for the test signal (ST1), from the initial test phase (PTI) until a final test phase (PTF) equal to the initial test phase (PTI) increased by at least a portion of a complete revolution, with, in each iteration, a current peak value measurement (AC1) of the output signal (SS1), and a storing of the current test phase (PTC) and the current peak value (AC1) as a maximum peak value (Amax) or minimum peak value (Amin), if there is respectively no stored maximum peak value (Amax) that is greater or stored minimum peak value (Amin) that is less than the current peak value (AC1), and a determination of the phase (PI) of the analog signal (SI3) using the stored test phase (PTM).

IPC Classes  ?

• H04B 1/04 - Circuits
• H04B 1/18 - Input circuits, e.g. for coupling to an antenna or a transmission line

Abstract

A system has an array of pixels including a plurality of active pixels and a plurality of dark reference pixels and processing circuitry coupled to the array of pixels. The processing circuitry sequentially computes, for each of a plurality of pairs of sets of dark reference pixels of the plurality of dark reference pixels, absolute differences in dark signal levels of the pair of sets of dark reference pixels. The absolute differences in dark signal levels are accumulated and a noise level of the dark reference pixels of the array of pixels is estimated based on the accumulated absolute differences. The system may be employed in, for example, a back-up camera of an automobile or a mobile phone.

IPC Classes  ?

• H04N 5/361 - Noise processing, e.g. detecting, correcting, reducing or removing noise applied to dark current
• H04N 5/217 - Circuitry for suppressing or minimising disturbance, e.g. moire or halo in picture signal generation
• H04N 5/232 - Devices for controlling television cameras, e.g. remote control

Abstract

A transponder communicates with a reader using active load modulation. The transponder includes a digital phase locked loop (DPLL), which, in operation, generates an active load modulation (ALM) carrier clock synchronized to carrier clock of the reader. Between transmission of data frames, the DPLL is placed in a lock mode of operation in which a feedback loop of the DPLL is closed. Within a transmitted data frame having a duration, the DPLL is placed, for the duration of the transmitted data frame, in a hold mode of operation in which the feedback loop is opened. A phase of the ALM carrier clock is adjusted at least once during the duration of the transmitted data frame.

IPC Classes  ?

• H03D 3/24 - Modifications of demodulators to reject or remove amplitude variations by means of locked-in oscillator circuits
• H04L 7/033 - Speed or phase control by the received code signals, the signals containing no special synchronisation information using the transitions of the received signal to control the phase of the synchronising-signal- generating means, e.g. using a phase-locked loop
• H04B 5/00 - Near-field transmission systems, e.g. inductive loop type
• G06K 19/07 - Record carriers with conductive marks, printed circuits or semiconductor circuit elements, e.g. credit or identity cards with integrated circuit chips
• H03C 3/09 - Modifications of modulator for regulating the mean frequency
• H03L 7/099 - Automatic control of frequency or phase; Synchronisation using a reference signal applied to a frequency- or phase-locked loop - Details of the phase-locked loop concerning mainly the controlled oscillator of the loop

Abstract

A reader is adapted to wirelessly exchanging information with a wireless apparatus. The reader includes a signal generator configured to generate a modulation signal. An emitter/receptor stage is configured to be driven by the modulation signal. A switched-mode power supply is configured to power the emitter/receptor stage. The switched-mode power supply includes a power switch controlled in function of the modulation signal.

IPC Classes  ?

• H04B 5/00 - Near-field transmission systems, e.g. inductive loop type
• G08C 17/02 - Arrangements for transmitting signals characterised by the use of a wireless electrical link using a radio link
• H02M 3/335 - Conversion of dc power input into dc power output with intermediate conversion into ac by static converters using discharge tubes with control electrode or semiconductor devices with control electrode to produce the intermediate ac using devices of a triode or a transistor type requiring continuous application of a control signal using semiconductor devices only
• G06K 19/07 - Record carriers with conductive marks, printed circuits or semiconductor circuit elements, e.g. credit or identity cards with integrated circuit chips

Abstract

A connector includes a first antenna configured to transmit first signals in a first direction and with a first polarization, a second antenna coupled to the first antenna and configured to transmit second signals in a second direction that is parallel to the first direction and with a second polarization that is orthogonal to the first polarization, and a third antenna coupled to the first and second antennas and configured to transmit third signals in a third direction that is parallel to the first direction and with the first polarization, wherein the second antenna is positioned between the first and third antennas.

IPC Classes  ?

• H01Q 21/06 - Arrays of individually energised antenna units similarly polarised and spaced apart
• H01Q 21/24 - Combinations of antenna units polarised in different directions for transmitting or receiving circularly and elliptically polarised waves or waves linearly polarised in any direction
• H01Q 13/02 - Waveguide horns
• H04B 5/00 - Near-field transmission systems, e.g. inductive loop type
• H01P 5/02 - Coupling devices of the waveguide type with invariable factor of coupling
• H01Q 21/08 - Arrays of individually energised antenna units similarly polarised and spaced apart the units being spaced along, or adjacent to, a rectilinear path
• H01Q 21/28 - Combinations of substantially independent non-interacting antenna units or systems
• H01Q 1/52 - Means for reducing coupling between antennas; Means for reducing coupling between an antenna and another structure

Abstract

The invention relates to a method for calibrating the centre frequency (FC1) of a hybrid coupler (CH1) operating in power-splitter mode, the hybrid coupler (CH1) comprising two inputs (BE1, BE2), two outputs (BS1, BS2), a capacitive module (MC1) coupled between the inputs (BE1, BE2) and the outputs (BS1, BS2) or on each input (BE1, BE2) and each output (BS1, BS2), the capacitive module (MC1) having an adjustable capacitive value (C1) making it possible to adjust the centre frequency (FC1), which comprises outputting a first reference signal (SREF1) having a first reference frequency (FREF1) on a first input (BE1) of said hybrid coupler (CH1), measuring the peak value (VC1) of a first signal (S1) output at a first output (BS1) of the coupler (CH1) and the peak value (VC2) of a second signal (S2) output at the second output (BS2) of the coupler (CH1), comparing the two peak values (VC1, VC2) and adjusting the capacitive value (C1) of the capacitive module (MC1) until obtaining equal peak values (VC1, VC2) to within a close tolerance.

IPC Classes  ?

• H04B 17/21 - Monitoring; Testing of receivers for correcting measurements
• H01P 5/12 - Coupling devices having more than two ports

Abstract

Integrated optical switch formed in and on a semiconductor substrate, comprising a photoconductive body (PC) comprising a first end (1) configured to receive an electrical input signal and a second end (2) configured to provide an electrical output signal, the photoconductive body (PC) having an electrically conductive state activated by the presence of an optical signal (SO) and an electrically blocked state activated by the absence of the optical signal (SO), wherein the direction from the first end to the second end defines a longitudinal direction (D3), and the photoconductive body has a cross section orthogonal to the longitudinal direction (D3) gradually decreasing in the longitudinal direction (D3) from the first end (1) to the second end (2).

IPC Classes  ?

• H03K 17/78 - Electronic switching or gating, i.e. not by contact-making and -breaking characterised by the use of specified components by the use, as active elements, of opto-electronic devices, i.e. light-emitting and photoelectric devices electrically- or optically-coupled
• G01R 13/34 - Circuits for representing a single waveform by sampling, e.g. for very high frequencies
• H01L 31/08 - SEMICONDUCTOR DEVICES NOT COVERED BY CLASS - Details thereof in which radiation controls flow of current through the device, e.g. photoresistors

Abstract

A flip flop includes a data input, a clock input, a test chain input, a test chain output, a monitoring circuit, and an alert transmission circuit. The monitoring circuit is adapted to generate an alert if the time between arrival of a data bit and a clock edge is less than a threshold. The alert transmission circuit is adapted to apply during a monitoring phase an alert level to the test chain output in the event of an alert generated by the monitoring circuit, and to apply the alert level to the test chain output when an alert level is received at the test chain input.

IPC Classes  ?

• G01R 31/3183 - Generation of test inputs, e.g. test vectors, patterns or sequences
• G01R 31/3185 - Reconfiguring for testing, e.g. LSSD, partitioning
• G01R 31/3177 - Testing of logic operation, e.g. by logic analysers
• G01R 31/317 - Testing of digital circuits
• G01R 31/3181 - Functional testing
• G06F 17/50 - Computer-aided design

Abstract

The invention concerns a measurement unit including: an electric ambient energy recovery generator; an element of capacitive storage of the electric energy generated by the generator; an electric battery; a first branch coupling an output node of the generator to a first electrode of the capacitive storage element; a second branch coupling a first terminal of the battery to the first electrode of the capacitive storage element; and an active circuit capable of transmitting a radio event indicator signal each time the voltage across the capacitive storage element exceeds a first threshold, wherein, in operation, the capacitive storage element simultaneously receives a first charge current originating from the generator via the first branch and a second charge current originating from the battery via the second branch.

IPC Classes  ?

• H02J 7/00 - Circuit arrangements for charging or depolarising batteries or for supplying loads from batteries
• G01R 31/3835 - Arrangements for monitoring battery or accumulator variables, e.g. SoC involving only voltage measurements
• H02J 7/35 - Parallel operation in networks using both storage and other dc sources, e.g. providing buffering with light sensitive cells
• H02J 7/34 - Parallel operation in networks using both storage and other dc sources, e.g. providing buffering
• H02J 1/10 - Parallel operation of dc sources
• H02J 1/06 - Two-wire systems
• G01D 21/00 - Measuring or testing not otherwise provided for

Abstract

Method for controlling the matching of an antenna to a transmission path, and corresponding device. The method for controlling the matching of an antenna (3) to a transmission path (2), said transmission path (2) comprising an amplifier stage (4) coupled at input or at output to the antenna (3) and to a resistive load (16), comprises a control phase (PC) comprising a measurement of a first current temperature (Tc1) at the level of the antenna (3) and of a second current temperature (Tc2) at the level of the resistive load (16), a triggering of a matching of the impedance seen at input or at output of the amplifier stage (4) in the presence of a first condition involving at least the first and second current temperatures (Tc1, Tc2) and then a stopping of the matching of the impedance in the presence of a second condition involving at least the second current temperature (Tc2).

IPC Classes  ?

• H04B 1/04 - Circuits

Abstract

The parallel reception system (SYS) comprises a plurality of receiving devices (DIS1-DISN), each comprising an amplifying circuit (CA) in a frequency transformation stage coupled with the antenna and configured to perform a frequency transposition of the signal (Vin) received by said antenna. The analog amplifier circuit (CA) comprises transconductance amplifier units (UAj) in parallel, each comprising a PMOS transistor (PI) and an NMOS transistor (N2) the gates of which are connected to the input node (I) and the drains to the output node (O). A control means (MCOM) is configured to generate a digital control signal, of which each bit (Bj) respectively controls the supply of each amplifier unit (UAj) according to a sinusoidal wave representation at a frequency of interest.

IPC Classes  ?

• H03D 7/12 - Transference of modulation from one carrier to another, e.g. frequency-changing by means of semiconductor devices having more than two electrodes
• H03D 7/14 - Balanced arrangements

Abstract

The coupling device (DC) comprises a 90° hybrid inductive capacitive coupling stage (EC) including two first stage terminals (BE11 and BE12) that are capable of forming two stage inputs or two stage outputs and two second stage terminals (BE21 and BE22) that are capable of respectively forming two stage outputs or two stage inputs. The coupling stage (EC) is advantageously modular, possesses a first axis of stage symmetry (ASE1) and a second axis of stage symmetry (ASE2) that is orthogonal to the first axis of stage symmetry (ASE1), includes neighbouring inductive metal tracks (PM11 and PM12) that overlap in at least one region of crossover (RC) and that form both an inductive circuit (CI1) and a capacitive circuit (CC1), said tracks being coupled to the first stage terminals (BE11, BE12) and to the second stage terminals (BE21, BE22) so that the two first stage terminals (BE11, BE12) are located on one side of the first axis of stage symmetry (ASE1) whereas the two second stage terminals (BE21, B22) are located on the other side of the first axis of stage symmetry (ASE2).

IPC Classes  ?

• H01P 5/18 - Conjugate devices, i.e. devices having at least one port decoupled from one other port consisting of two coupled guides, e.g. directional couplers

Abstract

The invention relates to a driving/assistance method for driving a vehicle (1) on a thoroughfare provided with at least one marking strip (4) for marking said thoroughfare, wherein said method includes burying a plurality of transponders (3) built into said at least one marking strip (4), equipping a vehicle (1) with at least one active communication device (2), performing a series of remote communications between said at least one active communication device (2) and said transponders (3) during the movement of the vehicle (1) on said thoroughfare, and performing a series of distance calculations between said at least one active communication device (2) and the marking strip during said series of remote communications with said consecutive transponders (3).

IPC Classes  ?

• B60W 30/12 - Lane keeping
• G06K 9/00 - Methods or arrangements for reading or recognising printed or written characters or for recognising patterns, e.g. fingerprints
• G06K 7/10 - Methods or arrangements for sensing record carriers by corpuscular radiation
• G01S 13/75 - Systems using reradiation of radio waves, e.g. secondary radar systems; Analogous systems using transponders powered from received waves, e.g. using passive transponders

Abstract

A photonic integrated circuit includes a first insulating region encapsulating at least one metallization level, a second insulating region at least partially encapsulating a gain medium of a laser source, and a stacked structure placed between the two insulating regions. The stacked structure includes a first polycrystalline or single-crystal silicon layer, a second polycrystalline or single-crystal silicon layer, an intermediate layer optically compatible with the wavelength of the laser source and selectively etchable relative to silicon and that separates the first layer from a first portion of the second layer, and the gain medium facing at least one portion of the first layer. The first layer, the intermediate layer, and the first portion of the second layer form an assembly containing a resonant cavity and a waveguide, which are optically coupled to the gain medium, and a second portion of the second layer containing at least one other photonic component.

IPC Classes  ?

• H01S 5/00 - Semiconductor lasers
• H01S 5/026 - Monolithically integrated components, e.g. waveguides, monitoring photo-detectors or drivers
• H01S 5/125 - Distributed Bragg reflector [DBR] lasers
• H01S 5/22 - Structure or shape of the semiconductor body to guide the optical wave having a ridge or a stripe structure
• H01S 5/02 - Structural details or components not essential to laser action
• H01S 5/065 - Mode locking; Mode suppression; Mode selection

Abstract

The invention relates to a method for producing at least one pattern in a film resting on a substrate, including the steps of a) making amorphous at least one first block (131) of an upper film of crystalline material resting on a first amorphous supporting film, while the crystalline structure of a second block (132) of the upper film that adjoins and juxtaposes said first block (131) is preserved, b) partially recrystallising the first block (131) by using at least one side surface of the second block (132) that is in contact with the first block as an area for the start of a recrystallisation front, the partial recrystallisation being carried out so as to preserve a region (1311) of amorphous material in the first block, c) selectively etching the amorphous material of the upper film with respect to the crystalline material of the upper film so as to form at least one first pattern in the upper film.

IPC Classes  ?

• H01L 21/308 - Chemical or electrical treatment, e.g. electrolytic etching using masks
• H01L 21/033 - Making masks on semiconductor bodies for further photolithographic processing, not provided for in group or comprising inorganic layers

Abstract

An OFDM (orthogonal frequency division multiplexing) transmitter includes an inverse fast Fourier transform circuit, which, in operation, generates, based on digital input data, a complex time-varying digital signal having real and imaginary components; and a multiplexer adapted to generate a time-multiplexed digital signal by time-multiplexing one or more of the real components with one or more of the imaginary components.

IPC Classes  ?

• H04L 27/26 - Systems using multi-frequency codes
• H04L 27/20 - Modulator circuits; Transmitter circuits
• H04B 10/548 - Phase or frequency modulation
• H04B 10/69 - Electrical arrangements in the receiver

Abstract

Methods and systems for scrubbing confidential insurance account information are provided. According to embodiments, a scrubbing server can receive a request to scrub confidential insurance data that includes the contents of an insurance account information database and an indication of the category of confidential data stored in the database. The scrubbing server can scrub the valid data contained in the received database, replacing confidential information with “scrambled” data that is not confidential. The scrubbing server can transmit the contents of the scrubbed database back to the requesting party.

IPC Classes  ?

• H04L 29/06 - Communication control; Communication processing characterised by a protocol
• G06F 17/30 - Information retrieval; Database structures therefor
• G06F 21/60 - Protecting data
• H04L 9/06 - Arrangements for secret or secure communications; Network security protocols the encryption apparatus using shift registers or memories for blockwise coding, e.g. D.E.S. systems

Abstract

Method for production of a semiconductor wafer suitable for the manufacture of an SOI substrate, comprising the following steps: - production, on the upper face (2) of a semiconductor support (1), of a first layer (4) of polycrystalline semiconductor; then - formation of an interface area (12) on the upper face (7) of said first layer (4), the interface area (12) having a structure distinct from the crystalline structure of said first layer (4); then - production on said interface area (12) of a second layer (14) of polycrystalline semiconductor.

IPC Classes  ?

• H01L 21/02 - Manufacture or treatment of semiconductor devices or of parts thereof
• H01L 21/762 - Dielectric regions
• H01L 21/763 - Polycrystalline semiconductor regions
• H01L 29/04 - Semiconductor bodies characterised by their crystalline structure, e.g. polycrystalline, cubic or particular orientation of crystalline planes

Abstract

The processing means (MT) of the device determine, for each original sample stream (I), an estimated difference (II) between the time constant of a low pass filter representative of the corresponding converter and a reference time constant of a reference low pass filter, and uses this estimated difference (II) and a filtered stream (III) to correct the original stream and deliver a corrected stream of corrected samples (I).

IPC Classes  ?

• H03M 1/06 - Continuously compensating for, or preventing, undesired influence of physical parameters
• H03M 1/12 - Analogue/digital converters

Abstract

A Silicon On Insulator current source array includes input control for receiving a control voltage, a first reference input for receiving a first reference voltage, and a second reference input for receiving a second reference voltage. A chain of several Silicon On Insulator MOS transistors, of the same type, have control electrodes all connected to the input control, first conduction electrodes are all connected to the first reference input, and second conduction electrodes are respectively connected to the second reference input through several load circuits respectively configured to be traversed by several currents when the several transistors are ON upon application of the control voltage on the input control. An input bias is coupled to a semiconductor well located below an insulating buried layer located below the chain of transistors for receiving a biasing voltage difference.

IPC Classes  ?

• H01L 21/8238 - Complementary field-effect transistors, e.g. CMOS
• H01L 29/66 - Types of semiconductor device
• H03K 3/012 - Modifications of generator to improve response time or to decrease power consumption
• H01L 21/84 - Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being other than a semiconductor body, e.g. being an insulating body
• H01L 29/786 - Thin-film transistors
• H01L 27/12 - Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being other than a semiconductor body, e.g. an insulating body

Abstract

A three-dimensional integrated structure may include two assembled integrated circuits respectively including two metallic lines, and at least two cavities passing through one of the integrated circuits and opening onto two locations respectively in electrical contact with the two metallic lines. The cavities may be sized to place a measuring apparatus at the bottom of the cavities, and in electrical contact with the two locations.

IPC Classes  ?

• H01L 21/66 - Testing or measuring during manufacture or treatment
• H01L 25/065 - Assemblies consisting of a plurality of individual semiconductor or other solid state devices all the devices being of a type provided for in the same subgroup of groups , or in a single subclass of , , e.g. assemblies of rectifier diodes the devices not having separate containers the devices being of a type provided for in group
• H01L 27/06 - Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body including a plurality of individual components in a non-repetitive configuration

Abstract

An apparatus has a data store configured to store access activity information. The access activity information indicates which one or more of a plurality of different access parameter sets is active. The data store is also configured to store access defining information, which defines, at least for each active access parameter set, a number of channels, location information of said channels, and interleaving information associated with said channels.

IPC Classes  ?

• G06F 12/06 - Addressing a physical block of locations, e.g. base addressing, module addressing, address space extension, memory dedication
• H04W 74/08 - Non-scheduled access, e.g. random access, ALOHA or CSMA [Carrier Sense Multiple Access]
• G06F 13/16 - Handling requests for interconnection or transfer for access to memory bus

Abstract

The invention relates to a device (400) for converting energy, comprising an enclosure (430) containing drops of a liquid (427) and an electret capacitive transducer (417, 419, 421) coupled to that enclosure.

IPC Classes  ?

• H02N 1/08 - Influence generators with conductive charge carrier, i.e. capacitor machines

Abstract

A power management circuit including, between a first terminal intended to be connected to an electric power generation source and a second terminal intended to be connected to a load to be powered, a linear regulator and a circuit capable of activating the linear regulator when the power supplied by said source is greater than a first threshold.

IPC Classes  ?

• G06F 1/32 - Means for saving power
• H02J 7/35 - Parallel operation in networks using both storage and other dc sources, e.g. providing buffering with light sensitive cells

Abstract

A reconfigurable hierarchical computer architecture having N levels, where N is an integer value greater than one, wherein said N levels include a first level including a first computation block including a first data input, a first data output and a plurality of computing nodes interconnected by a first connecting mechanism, each computing node including an input port, a functional unit and an output port, the first connecting mechanism capable of connecting each output port to the input port of each other computing node; and a second level including a second computation block including a second data input, a second data output and a plurality of the first computation blocks interconnected by a second connecting means for selectively connecting the first data output of each of the first computation blocks and the second data input to each of the first data inputs and for selectively connecting each of the first data outputs to the second data output.

IPC Classes  ?

• G06F 15/78 - Architectures of general purpose stored program computers comprising a single central processing unit
• G06F 13/36 - Handling requests for interconnection or transfer for access to common bus or bus system
• G06F 15/173 - Interprocessor communication using an interconnection network, e.g. matrix, shuffle, pyramid, star or snowflake
• G06F 15/80 - Architectures of general purpose stored program computers comprising an array of processing units with common control, e.g. single instruction multiple data processors
• G06F 9/38 - Concurrent instruction execution, e.g. pipeline, look ahead
• G06F 13/368 - Handling requests for interconnection or transfer for access to common bus or bus system with decentralised access control

Abstract

Memory circuitry includes memory components operable in response to first edges of an internal clock. The memory circuitry also includes internal clock generating circuitry to generate the internal clock in response to a system clock. The first edges of the internal clock are generated in response to both a rising and a falling edge of the system clock.

IPC Classes  ?

• G11C 8/00 - Arrangements for selecting an address in a digital store
• G11C 8/18 - Address timing or clocking circuits; Address control signal generation or management, e.g. for row address strobe [RAS] or column address strobe [CAS] signals

Abstract

A method for generating a radio frequency signal, wherein a signal to be transmitted is decomposed into a weighted sum of periodic basic signals of different frequencies.

IPC Classes  ?

• H04B 1/02 - Transmitters
• H04B 1/00 - TRANSMISSION - Details of transmission systems not characterised by the medium used for transmission
• H04B 1/403 - Circuits using the same oscillator for generating both the transmitter frequency and the receiver local oscillator frequency
• H04L 27/26 - Systems using multi-frequency codes
• H04B 1/04 - Circuits

Abstract

A device for generating a signal, including: a balun; and a circuit capable of summing up, on a first access terminal of the balun, currents representative of signals received on first input terminals of the device, and on a second access terminal of the balun, currents representative of signals received on second input terminals of the device.

IPC Classes  ?

• G06F 1/04 - Generating or distributing clock signals or signals derived directly therefrom
• H03K 3/00 - Circuits for generating electric pulses; Monostable, bistable or multistable circuits
• H04B 1/00 - TRANSMISSION - Details of transmission systems not characterised by the medium used for transmission
• H04B 1/403 - Circuits using the same oscillator for generating both the transmitter frequency and the receiver local oscillator frequency
• H04B 1/04 - Circuits

Abstract

An integrated circuit may include at least one MOS transistor having a sigmoid response. The at least one MOS transistor may include a substrate, a source region, a drain region, a gate region, and insulating spacer regions on either side of the gate region. The substrate may include a first region situated under the gate region between the insulating spacer regions. At least one of the source and drain regions may be separated from the first region of the substrate by a second region of the substrate situated under an insulating spacer region, which may be of a same type of conductivity as the first region of the substrate.

IPC Classes  ?

• H01L 29/66 - Types of semiconductor device
• H01L 29/78 - Field-effect transistors with field effect produced by an insulated gate
• H01L 29/417 - Electrodes characterised by their shape, relative sizes or dispositions carrying the current to be rectified, amplified or switched
• H01L 27/07 - Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body including a plurality of individual components in a non-repetitive configuration the components having an active region in common

Abstract

An integrated circuit (4) comprises first and second cells, each comprising first (10, 44) and second (12, 42) FDSOI transistors. According to the invention: -the first and second cells are joined together; -first (20) and second (22) boxes of the first cell and a first box (52) of the second cell have a first type of doping, a second box (50) of the second cell has an opposite type of doping -the circuit comprises a control device (5) for applying a same electrical polarisation to the boxes having the first type of doping; -the transistors of the first cell are configured to have a first threshold voltage level, and the transistors of the second cell are configured to have a second threshold voltage level different from the first level.

IPC Classes  ?

• H01L 27/12 - Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being other than a semiconductor body, e.g. an insulating body

Abstract

Adaptive scaling digital techniques attempt to place the system close to the timing failure so as to maximize energy efficiency. Rapid recovery from potential failures is usually by slowing the system clock and/or providing razor solutions (instruction replay.) These techniques compromise the throughput. This application presents a technique to provide local in-situ fault resilience based on dynamic slack borrowing. This technique is non-intrusive (needs no architecture modification) and has minimal impact on throughput.

IPC Classes  ?

• H03B 19/00 - Generation of oscillations by non-regenerative frequency multiplication or division of a signal from a separate source
• H03K 3/02 - Generators characterised by the type of circuit or by the means used for producing pulses
• H03K 3/037 - Bistable circuits

Abstract

The invention concerns a method for producing a capacitor, comprising the forming of a capacitor stack in one portion of a substrate (112), said method comprising: the forming of a cavity (165) along the thickness of the portion of the substrate (112) from an upper face of said substrate (112), the depositing of a plurality of layers contributing to the capacitor stack onto the wall of the cavity (165) and onto the surface of the upper face, and a removal of matter from the layers until the surface of the upper face is reached, characterised in that the formation of the cavity (165) comprises the formation of at least one trench (164) and, associated with each trench (164), of at least one box (163), said at least one trench (164) comprising a trench outlet that opens into the box (163), said box (163) comprising a box outlet that opens at the surface of the upper face, the box outlet being shaped so as to be larger than the trench outlet.

IPC Classes  ?

• H01G 4/33 - Thin- or thick-film capacitors
• H01L 49/02 - Thin-film or thick-film devices
• H01G 4/38 - Multiple capacitors, i.e. structural combinations of fixed capacitors

Abstract

An integrated circuit includes a transistor, an UTBOX buried insulating layer disposed under it and a ground plane disposed under the layer. A well is disposed under the plane and a first trench is at the periphery of the transistor and extends through the layer into the well. There is a substrate under the well and a p-n diode on a side of the transistor. The diode comprises first and second zones of opposite doping and the first zone is configured for electrical connection to a first electrode of the transistor. The first and second zones are coplanar with the plane and a second trench for separating the first and second zones. The second trench extends through the layer into the plane to a depth less than an interface between the plane and the well. There is a third zone under the second trench forming a junction between the zones.

IPC Classes  ?

• H01L 27/12 - Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being other than a semiconductor body, e.g. an insulating body
• H01L 27/02 - Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including integrated passive circuit elements with at least one potential-jump barrier or surface barrier

Abstract

An integrated circuit includes an UTBOX insulating layer under and plumb with first and second electronic components, and corresponding ground planes and oppositely-doped wells made plumb with them. The wells contact with corresponding ground planes. A pair of oppositely doped bias electrodes, suitable for connecting corresponding bias voltages, contacts respective wells and ground planes. A third electrode contacts the first well. A first trench isolates one bias electrode from the third electrode and extends through the layer and into the first well. A second trench isolates the first bias electrode from one component. This trench has an extent that falls short of reaching an interface between the first ground plane and the first well.

IPC Classes  ?

• H01L 27/12 - Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being other than a semiconductor body, e.g. an insulating body
• H01L 27/02 - Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including integrated passive circuit elements with at least one potential-jump barrier or surface barrier
• H01L 27/06 - Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body including a plurality of individual components in a non-repetitive configuration

Abstract

At least three electrically conducting blocks are disposed within an isolating region; and at least two of them are mutually separated and capacitively coupled by a part of the isolating region. At least two of them, being semiconductor, have opposite types of conductivity or identical types of conductivity, but with different concentrations of dopants, and these are in mutual contact by one of their sides. The mutual arrangement of these blocks within the isolating region, their type of conductivity and their concentration of dopants form at least one electronic module. Some of the blocks define input and output blocks.

IPC Classes  ?

• H01L 27/02 - Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including integrated passive circuit elements with at least one potential-jump barrier or surface barrier
• H01L 21/77 - Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
• H01L 27/12 - Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being other than a semiconductor body, e.g. an insulating body
• H01L 21/762 - Dielectric regions
• H01L 27/088 - Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only the components being field-effect transistors with insulated gate
• H01L 29/78 - Field-effect transistors with field effect produced by an insulated gate
• H01L 29/06 - Semiconductor bodies characterised by the shapes, relative sizes, or dispositions of the semiconductor regions
• H01L 29/43 - Electrodes characterised by the materials of which they are formed

Abstract

A three-dimensional integrated structure may include two assembled integrated circuits respectively including two metallic lines, and at least two cavities passing through one of the integrated circuits and opening onto two locations respectively in electrical contact with the two metallic lines. The cavities may be sized to place a measuring apparatus at the bottom of the cavities, and in electrical contact with the two locations.

IPC Classes  ?

• H01L 21/66 - Testing or measuring during manufacture or treatment
• H01L 27/06 - Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body including a plurality of individual components in a non-repetitive configuration

Abstract

System for converting thermal energy into electrical energy (S1) intended to be disposed between a hot source (SC) and a cold source (SF), comprising means for converting the thermal energy into mechanical energy (6) and a piezoelectric material, the means for converting thermal energy into mechanical energy (6) comprising groups (G1, G2) of at least three bimetallic strips (9, 11, 13) linked mechanically together by their longitudinal ends and suspended above a substrate (12), each bimetallic strip (9, 11, 13) comprising two stable states in which it exhibits in each of the states a curvature, two directly adjacent bimetallic strips (9, 11, 13) exhibiting opposite curvatures for a given temperature, the switching from one stable state of the bimetallic strips (9, 11, 13) to the other causing the deformation of a piezoelectric material.

IPC Classes  ?

• H02N 2/18 - Electric machines in general using piezoelectric effect, electrostriction or magnetostriction producing electrical output from mechanical input, e.g. generators
• H02K 35/00 - Generators with reciprocating, oscillating or vibrating coil system, magnet, armature or other part of the magnetic circuit

Abstract

A method for producing at least one deep trench isolation in a semiconductor substrate including silicon and having a front side may include forming at least one cavity in the semiconductor substrate from the front side. The method may include conformally depositing dopant atoms on walls of the cavity, and forming, in the vicinity of the walls of the cavity, a silicon region doped with the dopant atoms. The method may further include filling the cavity with a filler material to form the at least one deep trench isolation.

IPC Classes  ?

• H01L 21/76 - Making of isolation regions between components
• H01L 21/762 - Dielectric regions

Abstract

A device and corresponding fabrication method includes a vertical stack having an intermediate layer between a lower region and an upper region. The intermediate layer is extended by a protection layer. The vertical stack has a free lateral face on which the lower region, the upper region and the protection layer are exposed.

IPC Classes  ?

• H01L 29/06 - Semiconductor bodies characterised by the shapes, relative sizes, or dispositions of the semiconductor regions
• H01L 21/768 - Applying interconnections to be used for carrying current between separate components within a device
• H01L 21/762 - Dielectric regions

Abstract

An integrated capacitive device includes an electrically conducting comb, at least some of whose teeth form first electrodes of capacitors, and electrically conducting fingers extending between the teeth of the comb so as to form second electrodes of the capacitors. The device includes a first finger-teeth set having a single reference finger forming a reference capacitor having a reference capacitive value, at least one second finger-teeth set including several fingers, the reference finger and the number of fingers of the second finger-teeth set or sets forming a geometric series with ratio two. At least one additional set includes a single additional finger forming, with at least one tooth of the comb, an additional capacitor having an additional capacitive value substantially equal to half the reference capacitive value.

IPC Classes  ?

• H01G 4/012 - Form of non-self-supporting electrodes

Abstract

A link device for three-dimensional integrated structure may include a module having a first end face designed to be in front of a first element of the structure, and a second end face designed to be placed in front of a second element of the structure. The two end faces may be substantially parallel, and the module including a substrate having a face substantially perpendicular to the two end faces and carrying an electrically conducting pattern formed in a metallization level on top of the face and enclosed in an insulating region. The electrically conducting pattern may include a first end part emerging onto the first end face and a second end part emerging onto the second end face and connected to the first end part.

IPC Classes  ?

• H05K 1/11 - Printed elements for providing electric connections to or between printed circuits
• H01L 23/498 - Leads on insulating substrates
• H01L 21/48 - Manufacture or treatment of parts, e.g. containers, prior to assembly of the devices, using processes not provided for in a single one of the groups
• H01L 23/14 - Mountings, e.g. non-detachable insulating substrates characterised by the material or its electrical properties

Abstract

A method for controlling a pixel may include first and second photosites, each having a photodiode and a charge-transfer transistor, a read node, and an electronic read element, all of which are common to all the photosites. The method may include an accumulation of photogenerated charges in the photodiode of the first photosite during a first period, an accumulation of photogenerated charges in the photodiode of the second photosite during a second period shorter than the first period, a selection of the signal corresponding to the quantity of charges accumulated in the photodiode of a photosite having the highest unsaturated intensity or else a saturation signal, and a digitization of the selected signal.

IPC Classes  ?

• H01L 27/148 - Charge coupled imagers

Abstract

i), each intermediate node being linked to a single first node and to several second nodes by way of a connection scheme. The string of K initial symbols is encoded by using the said code characteristics and a string of N encoded symbols is obtained, respectively subdivided into NI sub-symbols belonging respectively to mathematical sets whose orders are less than q, according to a subdivision scheme representative of the connection scheme (Π).

IPC Classes  ?

• H03M 1/18 - Automatic control for modifying the range of signals the converter can handle, e.g. gain ranging

Abstract

Switch including a terminal of a first type and at least two terminals of a second type, and a number of circuits capable of ensuring exclusive connection of one of the terminals of the second type to the terminal of the first type as a function of a set of control orders wherein the terminal of the first type is connected to a common point by a first circuit; each terminal of the second type is connected to the common point by a second circuit, with each second circuit including a portion that is magnetically coupled to the first circuit, a static switch mounted in parallel with the portion and capable of being controlled in the “off” state in order to connect the terminal of the first type to the terminal of the second type associated with the second circuit in question.

IPC Classes  ?

• H01H 51/22 - Polarised relays
• H04B 1/48 - Transmit/receive switching in circuits for connecting transmitter and receiver to a common transmission path, e.g. by energy of transmitter
• H04B 1/44 - Transmit/receive switching

Abstract

The invention relates to a housing, including a body (1) comprising a first silicon element (10) and a second porous silicon element (20), at least one first cavity (31) provided in the porous silicon, a first electrically conductive contact area (41), which is electrically coupled to at least a portion (310) of at least one inner wall of said at least one cavity (31), a second electrically conductive contact area (42), which is electrically coupled to a different portion (320) of said second element (20) of the inner walls of said at least one first cavity (31), the two contact areas (41, 42) being electrically insulated from each other.

IPC Classes  ?

• H01M 8/16 - Biochemical fuel cells, i.e. cells in which microorganisms function as catalysts
• H01M 8/10 - Fuel cells with solid electrolytes
• H01G 9/02 - Diaphragms; Separators

Abstract

An integrated circuit (IC) cell may include first and second semiconductor regions, and parallel electrically conductive lines extending above the first and second semiconductor regions. The IC cell may further include electrically conductive line contacts electrically connected to the parallel electrically conductive lines, and may include at least one first line contact between the first semiconductor region and a corresponding end of the IC cell, and at least one second line contact between the first semiconductor region and the second semiconductor region. Adjacent ones of the electrically conductive lines may be respectively coupled to one of the at least one first line contact and to one of the at least one second line contact.

IPC Classes  ?

• H01L 23/52 - Arrangements for conducting electric current within the device in operation from one component to another
• H01L 27/118 - Masterslice integrated circuits
• H01L 27/02 - Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including integrated passive circuit elements with at least one potential-jump barrier or surface barrier
• H01L 23/528 - Layout of the interconnection structure

Abstract

Device for processing an analogue signal, comprising an analogue-digital converter with a pipelined architecture having an offset, and compensation means configured to compensate for the said offset, the said compensation means comprising digital correction means configured to correct the integer portion of the offset based on the digital signal delivered by the analogue-digital converter, and analogue correction means included in the last stage of the analogue-digital converter and configured to correct the decimal portion of the offset.

IPC Classes  ?

• H03M 1/06 - Continuously compensating for, or preventing, undesired influence of physical parameters

Abstract

A dynamic biasing circuit of the substrate of a MOS power transistor may include a first switch configured to connect the substrate to a current source which forward biases the intrinsic source-substrate diode of the transistor, when the gate voltage of the transistor turns the transistor on. The current source may include a stack of diodes in the same conduction direction as the intrinsic diode between the substrate and a supply voltage.

IPC Classes  ?

• G05F 1/10 - Regulating voltage or current

Abstract

A controlled oscillator includes, connected in parallel, a capacitor configured to be tuneable based upon a first signal, an inductor, and an active impedance. The active impedance is formed by a pair of cross-coupled transistors connected so as to produce a negative resistive component at the terminals of the active impedance. Circuitry produces a degeneracy tuneable by a second signal in the cross-coupled pair, such that the cross-coupled pair produces a capacitive component tuneable based upon the second signal at the terminals of the active impedance.

IPC Classes  ?

• H03B 5/12 - Generation of oscillations using amplifier with regenerative feedback from output to input with frequency-determining element comprising lumped inductance and capacitance active element in amplifier being semiconductor device
• H03K 3/282 - Generators characterised by the type of circuit or by the means used for producing pulses by the use, as active elements, of bipolar transistors with internal or external positive feedback using means other than a transformer for feedback using at least two transistors so coupled that the input of one is derived from the output of another, e.g. multivibrator astable
• H03K 3/354 - Astable circuits

Abstract

i-1, processing means (MT) able to receive said phases and arranged so as to deliver an amplitude-modulated output signal (SG) whose envelope exhibits a succession of regions respectively delimited by zones of zero amplitude (ZA, ZB), each amplitude-modulated signal part situated in one of said regions forming a pulse of the ultra wideband type (IMP) whose central frequency is equal to said first frequency and whose width depends on the value of the phase increment, and control means (MC) able to regulate the operation of the digital synthesis device so as to selectively deliver one or more pulses of the ultra wideband type.

IPC Classes  ?

• H03C 1/52 - Modulators in which carrier or one sideband is wholly or partially suppressed

Abstract

A low-pass filter, including: between a first terminal and a second terminal, a series association of a first resistor, of a second resistor, and of a first amplifier; in parallel with the second resistor, a series association of a second amplifier and of a first capacitor; a second capacitor between an input of the first amplifier and a third terminal of application of a reference voltage; and a third capacitor between the second terminal and the third terminal.

IPC Classes  ?

• H03K 5/00 - Manipulation of pulses not covered by one of the other main groups of this subclass

Abstract

A logarithmic analog to digital conversion method for an analog input signal includes a logarithmic amplification with progressive compression of the input signal delivering a sequence of several secondary analog signals. The trend of the values of at least some of the secondary signals is a function of the values of the analog input signal including regions corresponding to a linear trend of the secondary signals as a function of that of the input signal expressed in a logarithmic scale. The method also includes a comparison of at least some of the secondary signals of the sequence with a common reference signal whose value lies within each of regions, supplying a thermometric code information item, and a generation of a first digital word from the thermometric code information item.

IPC Classes  ?

• H03M 1/84 - Non-linear conversion

Abstract

The invention relates to a device and method for controlling an SRAM memory device, including: one bistable circuit and two switching circuits respectively connecting two access terminals of the bistable circuit to two matching bit sites in a first direction, each switching circuit comprising: a first switch (40G, 40D), a second switch (44G, 44D) in series between one of the bit sites and one of said access terminals, the control terminal of the second switch being connected to a word command line in the first direction; and a third switch (46G, 46D) between the middle point of said series connection and a terminal for applying a reference potential, a control terminal of the third switch being connected to the other one of said access terminals.

IPC Classes  ?

• G11C 11/412 - Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming cells with positive feedback, i.e. cells not needing refreshing or charge regeneration, e.g. bistable multivibrator or Schmitt trigger using field-effect transistors only
• G11C 11/413 - Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing, timing or power reduction

Abstract

An electronic device may include a controlled generator configured to generate an adjustable frequency clock signal at at least one part of an integrated circuit coupled to the output of the controller generator and including at least one transistor having a gate of less than forty-five nanometers in length. The electronic device may include determination circuitry configured to determine the temperature of the at least one part of the integrated circuit, and drive circuitry coupled to the determination circuitry and configured to control the generator to increase the frequency of the clock signal when the temperature increases.

IPC Classes  ?

• H01L 35/00 - SEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR - Details thereof

Abstract

A method for capturing a sequence of video images, using an imager including an estimation of the parameters of a model of global motion between successive images. The method may include measurement of local motions on edges of the images, with the estimation of the parameters of the global motion model performed using the result of the measurement of local motions on the edges of the images.

IPC Classes  ?

• G06K 9/00 - Methods or arrangements for reading or recognising printed or written characters or for recognising patterns, e.g. fingerprints
• H04N 5/228 - Circuit details for pick-up tubes
• H04N 5/33 - Transforming infrared radiation

Abstract

The electronic device includes a first (BP) and a second (BN) terminal and electronic means coupled between said two terminals; the electronic means include at least one block (BLC) comprising an MOS transistor (TR) including a parasitic bipolar transistor, the MOS transistor having the drain (D) thereof coupled to the first terminal (BP), the source (S) thereof coupled to the second terminal (BN) and being additionally configured, in the event of a current pulse (IMP) between the two terminals, to operate in a hybrid mode including MOS operation in a subthreshold mode and operation of the parasitic bipolar transistor. The device can comprise two blocks (BLC1, BLC2) connected symmetrically between the two terminals (BP, BN) with a triac (TRC) the trigger of which is connected to the common terminal (BC) of the two blocks.

IPC Classes  ?

• H01L 23/60 - Protection against electrostatic charges or discharges, e.g. Faraday shields
• H01L 27/02 - Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including integrated passive circuit elements with at least one potential-jump barrier or surface barrier

Abstract

A method of processing a digital image which includes at least one contour zone, including a contour zone sharpness processing. The sharpness processing includes a conversion of the cues regarding level of pixels of the contour zone into initial main cues, lying between zero and a main value dependent on the amplitude of the contour, a sharpness sub-processing performed on these initial main cues so as to obtain final main cues, and a conversion of the final main cues into final cues regarding levels.

IPC Classes  ?

• G06K 9/40 - Noise filtering

Abstract

A resistive element having two vertical resistive portions placed in two holes formed in the upper portion of a substrate and a horizontal resistive portion placed in a buried cavity connecting the bottoms of the holes.

IPC Classes  ?

• H01L 21/336 - Field-effect transistors with an insulated gate
• H01L 29/40 - Electrodes

Abstract

A method is for decoding a block of N information items encoded with an error correction code and mutually correlated. The method includes carrying out a first decorrelation of the N information items of a block is carried out, and storing the block decorrelated. The method also includes a performing a processing for decoding a group of P information items of the block, and decorrelating at least part of the P decoded information items. The processing for decoding the group of P information items and the decorrelation are repeated with different successive groups of P information items of the block until the N information items of the block have been processed, until a decoding criterion is satisfied.

IPC Classes  ?

• H03M 13/03 - Error detection or forward error correction by redundancy in data representation, i.e. code words containing more digits than the source words

Abstract

An integrated circuit includes input circuitry for receiving a radio frequency digital signal, output circuitry capable of delivering a radio frequency analog signal, and a processing stage coupled between the input circuitry and the output circuitry and including several processing channels in parallel. Each processing channel may include a voltage switching block the input of which is coupled to the input circuitry and a transmission line substantially of the quarter-wave type at the frequency of the radio frequency analog signal coupled in series between the output of the voltage switching block and the output circuitry.

IPC Classes  ?

• H03M 3/00 - Conversion of analogue values to or from differential modulation

Abstract

A flip-flop may include a first master stage for latching data, a second slave stage for latching data, and an input multiplexer circuit receiving, as input, data to be latched in the flip-flop. The multiplexer may have single clock phase. The first master stage may be clocked based upon a clock phase, whereas the second stage may be clocked based upon another clock phase.

IPC Classes  ?

• H03K 3/289 - Generators characterised by the type of circuit or by the means used for producing pulses by the use, as active elements, of bipolar transistors with internal or external positive feedback using means other than a transformer for feedback using at least two transistors so coupled that the input of one is derived from the output of another, e.g. multivibrator bistable of the master-slave type

Abstract

A method of adjustment on manufacturing of a monolithic oscillator including circuit elements and a BAW resonator, this method including the steps of: a) forming the circuit elements and the resonator and electrically connecting them; b) covering the resonator with a frequency adjustment layer; c) measuring the output frequency of the oscillator; d) modifying the thickness of the frequency adjustment layer to modify the output frequency of the oscillator.

IPC Classes  ?

• H01G 7/00 - Capacitors in which the capacitance is varied by non-mechanical means; Processes of their manufacture

Abstract

The invention concerns a satellite receive unit having an analog to digital converter (302) adapted to sample a satellite signal to generate a data stream; at least one digital channel multiplexer having at least one processing branch (307A, 307B) which includes: a Fourier transform block (307A, 307B); a channel shifter (310A, 310B); and an inverse Fourier transform block (312A, 312B); the satellite receiver comprising a digital to analog converter (316) adapted to convert the output data stream of the processing branch into an analog signal in a transmission band for transmission over a transmission channel to at least one satellite decoder.

IPC Classes  ?

• H04H 40/90 - Arrangements characterised by circuits or components specially adapted for receiving specially adapted for broadcast systems covered by groups specially adapted for satellite broadcast receiving
• H04H 20/63 - Arrangements specially adapted for specific applications, e.g. for traffic information or for mobile receivers for local area broadcast, e.g. instore broadcast to plural spots in a confined site, e.g. MATV [Master Antenna Television]

Abstract

The generation of a chip identifier supporting at least one integrated circuit, which includes providing a cutout of at least one conductive path by cutting the chip, the position of the cutting line relative to the chip conditioning the identifier.

IPC Classes  ?

• H01L 23/58 - Structural electrical arrangements for semiconductor devices not otherwise provided for

Abstract

An embodiment of a discharge circuit comprises an output circuit with one output connected to an electrical load to absorb a discharge current given by the load when a logic signal commands a discharge of the load. The discharge circuit also comprises a control circuit to give the output circuit an appropriate control signal so that a slope of an output potential of the output circuit diminishes gradually when the logic signal commands a discharge of the load. Limiting the slope of the output potential gradually (and not suddenly) may limit the electromagnetic radiation generated by these variations.

IPC Classes  ?

• H03B 1/00 - GENERATION OF OSCILLATIONS, DIRECTLY OR BY FREQUENCY-CHANGING, BY CIRCUITS EMPLOYING ACTIVE ELEMENTS WHICH OPERATE IN A NON-SWITCHING MANNER; GENERATION OF NOISE BY SUCH CIRCUITS - Details

Abstract

The present invention relates to a non-volatile memory comprising a memory array comprising functional memory cells and non-functional memory cells linked to at least one non-functional word line. A word line address decoder comprises a special decoding section linked to the non-functional word line, for selecting the non-functional word line when a functional word line is read-selected, such that non-functional memory cells are selected simultaneously with the functional memory cells, and distort the reading of the functional memory cells. Application particularly to integrated circuits for smart cards.

IPC Classes  ?

• G11C 11/00 - Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor

Abstract

s-1-3 consecutive erroneous bits.

IPC Classes  ?

• H03M 13/00 - Coding, decoding or code conversion, for error detection or error correction; Coding theory basic assumptions; Coding bounds; Error probability evaluation methods; Channel models; Simulation or testing of codes

Abstract

A support wafer made of silicon wafer comprising, on a first surface a porous silicon layer having protrusions, porous silicon pillars extending from the porous silicon layer to the second surface of the wafer, in front of each protrusion. Layers constituting a fuel cell can be formed on the support wafer.

IPC Classes  ?

• H01M 8/10 - Fuel cells with solid electrolytes

Abstract

a of the collector. The substrate includes a lightly doped lateral zone and a highly doped central zone. The dopant species in the zone of the substrate are electrically inactive.

IPC Classes  ?

• H01L 21/331 - Transistors

Abstract

Filtering circuit with coupled resonators comprising : - a substrate (100); an acoustic mirror (101) or a membrane destined to act as a mechanical support of acoustic resonators and to isolate these resonators from the substrate; - a first section (LEFT) comprising an upper resonator (120) and a lower resonator (110) coupled to each other by means of at least one acoustic coupling layer (130), the said upper and lower resonators constituting a first section (Al ); - a second section (RIGHT) comprising an upper resonator (220) and a lower resonator (210) coupled to each other by means of at least one acoustic coupling layer (130), the said upper and lower resonators of the said second section constituting a second section (A2); and metallic vias implementing an inter stage connection between the lower resonator of a section and the upper resonator of the other section.

IPC Classes  ?

• H03H 9/58 - Multiple crystal filters

Abstract

The digital delta-sigma modulator includes a signal input for receiving digital samples of N bits, and a digital filter connected to the signal input. The digital filter performs addition/subtraction and integration operations according to a redundant arithmetic coding for delivering digital filtered samples. A quantizer performs a nonexact quantization operation so as to deliver digital output samples of n bits, with n being less than N. The input of the quantizer is connected within the digital filter.

IPC Classes  ?

• H04L 27/04 - Modulator circuits; Transmitter circuits
• H04L 27/20 - Modulator circuits; Transmitter circuits

Abstract

System for generating a pulsed signal of the ultra wideband type, comprising a device for direct digital frequency synthesis (DDS) comprising a phase accumulator (ACCP) able to deliver at a first frequency (Fclk) phases coded on i bits and spaced apart by a phase increment (Δp) differing by a power of two and situated in the vicinity of 2i-1, processing means (MT) able to receive said phases and arranged so as to deliver an amplitude-modulated output signal (SG) whose envelope exhibits a succession of regions respectively delimited by zones of zero amplitude (ZA, ZB), each amplitude-modulated signal part situated in one of said regions forming a pulse of the ultra wideband type (IMP) whose central frequency is equal to said first frequency and whose width depends on the value of the phase increment, and control means (MC) able to regulate the operation of the digital synthesis device so as to selectively deliver one or more pulses of the ultra wideband type.

IPC Classes  ?

• H04B 1/69 - Spread spectrum techniques

Abstract

The present invention relates to a three-dimensional capacitor that includes a stack of vertically adjacent electrodes formed in respective metallization levels of an integrated circuit. The capacitor also comprises at least two additional vertically adjacent electrodes formed on top of said stack, the additional electrodes each including an assembly of at least one bar (B, B’) extending in a first direction. A portion of said bars comprises branches (R) extending in a second direction.

IPC Classes  ?

• H01G 4/005 - Electrodes
• H01G 4/30 - Stacked capacitors
• H01L 21/02 - Manufacture or treatment of semiconductor devices or of parts thereof

Abstract

The integrated circuit may include at least one electronic protection circuit for protecting against at least one electrostatic discharge and being able to discharge the overvoltage current generated by the electrostatic discharge. The electronic protection circuit includes a controlled short-circuiting switch embodied in CMOS technology including a CMOS technology TRIAC or a CMOS technology thyristor arranged in anti-parallel with a CMOS technology diode, and a triggering circuit for controlling the short-circuiting switch.

IPC Classes  ?

• H02H 3/22 - Emergency protective circuit arrangements for automatic disconnection directly responsive to an undesired change from normal electric working condition, with or without subsequent reconnection responsive to excess voltage of short duration, e.g. lightning

Abstract

A region is locally modified so as to create a zone that extends as far as at least part of the surface of the region and is formed from a material that can be removed selectively with respect to the material of the region. The region is then covered with an insulating material. An orifice is formed in the insulating material emerging at the surface of the zone. The selectively removable material is removed from the zone through the orifice so as to form a cavity in place of the zone. The cavity and the orifice are then filled with at least one electrically conducting material so as to form a contact pad.

IPC Classes  ?

• H01L 21/02 - Manufacture or treatment of semiconductor devices or of parts thereof

Abstract

The invention concerns a switched capacitor amplifier having an amplification unit (102) adapted to amplify a differential signal; a first switched capacitor block (120) including a first plurality of capacitors operable to sample a first differential input signal during a first sampling phase and to drive the amplification unit during a first drive phase; and a second switched capacitor block (122) comprising a second plurality of capacitors operable to sample a second differential input signal during a second sampling phase and to drive the amplification unit during a second drive phase.

IPC Classes  ?

• H03F 3/00 - Amplifiers with only discharge tubes or only semiconductor devices as amplifying elements

Abstract

A self-cooled electronic component comprising a vertical monolithic circuit, in which the vertical monolithic circuit is electrically connected in series with a Peltier cooler so that the D.C. current flowing through the circuit supplies the cooler and in which the circuit and the cooler are placed against each other so that the cold surface of the cooler is in thermal contact with the circuit.

IPC Classes  ?

• F25B 21/02 - Machines, plants or systems, using electric or magnetic effects using Nernst-Ettinghausen effect

Abstract

A Micro Electro Mechanical Systems resonance device includes a substrate, and an input electrode, connected to an alternating current source having an input frequency. The device also includes an output electrode, and at least one anchoring structure, connected to the substrate. The device further includes a vibratile structure connected to an anchoring structure by at least one junction, having a natural acoustic resonant frequency. The vibration under the effect of the input electrode, when it is powered, generates, on the output electrode, an alternating current wherein the output frequency is equal to the natural frequency. The vibratile structure and/or the anchoring structure includes a periodic structure. The periodic structure includes at least first and second zones different from each other, and corresponding respectively to first and second acoustic propagation properties.

IPC Classes  ?

• H01L 29/84 - Types of semiconductor device controllable by variation of applied mechanical force, e.g. of pressure
• H01L 21/00 - Processes or apparatus specially adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof

Abstract

Integrated circuit, incorporating an electronic device (PA), comprising input means (BE) for receiving a radio frequency digital signal (SCH), output means (BS) able to deliver a radio frequency analogue signal (SARF), and a processing stage coupled between the input means and the output means and comprising several parallel processing pathways (VTi), each processing pathway (VTi) including a voltage switching block (BLCi) whose input is coupled to the input means and a transmission line (LTi) substantially of the quarter wave type at the frequency of the radio frequency analogue signal coupled in series between the output of the voltage switching block and said output means.

IPC Classes  ?

• H03F 1/02 - Modifications of amplifiers to raise the efficiency, e.g. gliding Class A stages, use of an auxiliary oscillation
• H03F 3/60 - Amplifiers in which coupling networks have distributed constants, e.g. with waveguide resonators
• H03H 15/00 - Transversal filters
• H04B 1/00 - TRANSMISSION - Details of transmission systems not characterised by the medium used for transmission
• H04B 1/04 - Circuits

Abstract

A memory structure has an access transistor connected in series with a programmable resistive element, wherein the programmable resistive element comprises on a semiconductor substrate; an insulated layer with a cavity comprising: a first layer lining the lateral surfaces and the bottom of the said cavity and impermeable to the diffusion of metal; a second layer made of porous material on the said first layer; a third layer of metallic material allowing to realize a contact electrode susceptible to spread within the said formed porous material of the second layer. Diffusion of metallic ions within the said second layer is controlled by the joint action of an electric field and temperature. A manufacturing process is also described.

IPC Classes  ?

• H01L 45/00 - Solid state devices specially adapted for rectifying, amplifying, oscillating, or switching without a potential-jump barrier or surface barrier, e.g. dielectric triodes; Ovshinsky-effect devices; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof

Abstract

Optical element or module designed to be placed in front of an optical sensor of a semiconductor component, through at least one optically useful part of which (5a) the image to be captured is designed to pass, processing method for obtaining such an optical element, in which at least one through passage (25) runs between its front and rear faces and having a refractive index that varies starting from the wall of the said at least one through passage and into the said optically useful part under the effect of ion doping. Image capture apparatus comprising an optical imaging module comprising at least one such element.

IPC Classes  ?

• G02B 3/00 - Simple or compound lenses
• H01L 27/146 - Imager structures

Abstract

The present disclosure relates to a video surveillance method comprising steps of a video camera periodically capturing an image of a zone to be monitored, analyzing the image to detect a presence therein, and of the video camera transmitting the image only if a presence has been detected in the image.

IPC Classes  ?

• H04N 7/18 - Closed-circuit television [CCTV] systems, i.e. systems in which the video signal is not broadcast

Abstract

A channel equalizer arranged to receive a data signal encoded by a plurality of amplitude levels, the circuitry including a filter having a plurality of taps, each tap generating an output signal based on a coefficient, an input for receiving an error signal for adapting the coefficients, and an output for outputting a filtered signal; and blind error generation circuitry arranged to generate the error signal, the blind error generation circuitry including: error estimating circuitry arranged to estimate the error of the filtered signal based on maximum likelihood; and adding circuitry coupled to the error estimating circuitry and to the output of the filter and arranged to add at least part of the filtered signal to the error estimated by the error estimating circuitry to generate the error signal.

IPC Classes  ?

• H03H 7/30 - Time-delay networks
• H03H 7/40 - Automatic matching of load impedance to source impedance
• H03K 5/159 - Applications of delay lines not covered by the preceding subgroups

Abstract

An image sensor formed of an array of pixels, each pixel including a photodiode coupled between a first reference voltage and a first switch, the first switch being operable to connect the photodiode to a first node; a capacitor arranged to store a charge accumulated by the photodiode, the capacitor being coupled between a second reference voltage and a second node; a second switch coupled between the first and second nodes, the second switch being operable to connect the capacitor to the first node; and read circuitry coupled for reading the voltage at the second node.

IPC Classes  ?

• H01L 27/00 - Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate

Abstract

The invention relates to a method and a circuit for verifying data transferred between a circuit (21) and a processing unit (11), in which: the data originating from the circuit travels through a first temporary storage element (23) having a size representing an integer multiple of the size of data liable to be presented subsequently on a bus (27) of the processing unit; an address provided by the processing unit (11) destined for the circuit is stored temporarily in a second element (22); and the content of the first element is compared with a current data item (CDATA) originating from the circuit, at least when said data item corresponds to an address of a data item already present in this first element.

IPC Classes  ?

• G06F 21/55 - Detecting local intrusion or implementing counter-measures
• G06F 21/60 - Protecting data