Abstract

The present disclosure provides a 3D memory device such as a 3D AND flash memory and a method of forming a seal structure. The 3D memory device includes a chip region including a chip array and a seal region including a seal structure. The seal structure includes a ring-shaped stack structure disposed on a substrate and surrounding the chip array and a dummy channel pillar array penetrating through the ring-shaped stack structure and including a first dummy channel pillar group and a second dummy channel pillar group. The first dummy channel pillar group includes first dummy pillars that are arranged in a first direction and a second direction crossing the first direction to surround the chip array. The second dummy channel pillar group includes second dummy pillars that are arranged in the first direction and the second direction to surround the chip array. The first and the second dummy channel pillars are staggered with each other in the first and second directions.

IPC Classes  ?

• H01L 23/00 - SEMICONDUCTOR DEVICES NOT COVERED BY CLASS - Details of semiconductor or other solid state devices
• H01L 23/58 - Structural electrical arrangements for semiconductor devices not otherwise provided for
• H01L 27/11556 - Electrically programmable read-only memories; Multistep manufacturing processes therefor with floating gate characterised by three-dimensional arrangements, e.g. with cells on different height levels with source and drain on different levels, e.g. with sloping channels the channels comprising vertical portions, e.g. U-shaped channels
• H01L 27/11582 - Electrically programmable read-only memories; Multistep manufacturing processes therefor with charge-trapping gate insulators, e.g. MNOS or NROM characterised by three-dimensional arrangements, e.g. with cells on different height levels with source and drain on different levels, e.g. with sloping channels the channels comprising vertical portions, e.g. U-shaped channels

Abstract

The disclosure provides an in-memory computing (IMC) memory device and an IMC method thereof. The IMC memory device includes; a memory array including a plurality of computing units, each of the computing units including a plurality of parallel-coupling computing cells, the parallel-coupling computing cells of the same computing unit receiving a same input voltage; wherein a plurality of input data is converted into a plurality input voltages; after receiving the input voltages, the computing units generate a plurality of output currents; and based on the output currents, a multiply accumulate (MAC) of the input data and a plurality of conductance of the computing cells is generated.

IPC Classes  ?

• G06F 3/06 - Digital input from, or digital output to, record carriers

Abstract

A data recovery method for a memory device is disclosed. The memory device has a target memory cell, a target word line and an adjacent word line, the adjacent word line is adjacent to the target word line. The target word line is connected to a gate of the target memory cell. The adjacent word line is connected to a gate of an adjacent memory cell, and the adjacent memory cell is adjacent to the target memory cell. The data recovery method includes the following steps. Applying a first program voltage to the target memory cell through the target word line. When applying the first program voltage, concurrently applying a second program voltage to the adjacent memory cell through the adjacent word line.

IPC Classes  ?

• G11C 29/52 - Protection of memory contents; Detection of errors in memory contents
• G11C 11/56 - Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using storage elements with more than two stable states represented by steps, e.g. of voltage, current, phase, frequency
• G11C 16/08 - Address circuits; Decoders; Word-line control circuits
• G11C 16/10 - Programming or data input circuits

Abstract

A memory device, a failure bits detector, and a failure bits detection method thereof are provided. The failure bits detector includes a current generator, a current mirror, and a comparator. The current generator generates a first current according to a reference code. The current mirror mirrors the first current to generate a second current at a second end of the current mirror. The comparator compares a first voltage at a first input end with a second voltage at a second input end to generate a detection result.

IPC Classes  ?

• G11C 29/52 - Protection of memory contents; Detection of errors in memory contents
• G05F 3/26 - Current mirrors

Abstract

A memory device includes a first stack structure including first gate layers and first insulating layers alternately stacked with each other. A first channel pillar extends through the first stack structure. A second stack structure is located on the first stack structure and includes second gate layers and second insulating layers alternately stacked with each other. A second channel pillar extends through the second stack structure and is separated from the first channel pillar. A first conductive pillar and a second conductive pillar are located in and electrically connecting with the first channel pillar and the second channel pillar. A charge storage structure is located between the first gate layers and the first channel pillar, and between the second gate layers and the second channel pillar. The memory device may be applied to a 3D AND flash memory.

IPC Classes  ?

• H01L 27/11582 - Electrically programmable read-only memories; Multistep manufacturing processes therefor with charge-trapping gate insulators, e.g. MNOS or NROM characterised by three-dimensional arrangements, e.g. with cells on different height levels with source and drain on different levels, e.g. with sloping channels the channels comprising vertical portions, e.g. U-shaped channels
• G11C 16/04 - Erasable programmable read-only memories electrically programmable using variable threshold transistors, e.g. FAMOS
• H01L 27/1157 - Electrically programmable read-only memories; Multistep manufacturing processes therefor with charge-trapping gate insulators, e.g. MNOS or NROM characterised by the memory core region with cell select transistors, e.g. NAND

Abstract

A data serializer, a latch data device using the same and a controlling method thereof are provided. The data serializer includes at least one data buffer and a de-skew buffer. The data buffer at least receives an inputting data and a controlling signal. An outputting signal and a complementary outputting signal, which is complementary to the outputting signal, are formed when the controlling signal is at a predetermined level. The de-skew buffer receives the complementary outputting signal to accelerate or slow down forming the outputting signal.

IPC Classes  ?

• G11C 7/10 - Input/output [I/O] data interface arrangements, e.g. I/O data control circuits, I/O data buffers

Abstract

Systems, devices, methods, and circuits for managing content addressable memory (CAM) devices. In one aspect, a semiconductor device includes: a memory cell array configured to store data in memory cells, and a circuitry coupled to the memory cell array and configured to execute a search operation in the memory cell array according to a search instruction. The search instruction includes at least one of search data or an option code, and the option code specifies, for the search operation, at least one of a search length or a search depth.

IPC Classes  ?

• G06F 3/06 - Digital input from, or digital output to, record carriers

Abstract

A memory device and a management method thereof are provided. The memory device includes a controller and at least one memory channel. The memory channel includes at least one memory chip. The at least one memory chip is commonly coupled to the controller through an interrupt signal wire. The at least one memory chip generates at least one local interrupt signal and performs a logic operation on the at least one local interrupt signal to generate a common interrupt signal. The interrupt signal wire is configured to transmit the common interrupt signal to the controller.

IPC Classes  ?

• G06F 3/06 - Digital input from, or digital output to, record carriers

Abstract

Systems, methods, and apparatus including computer-readable mediums for managing status information of logic units are provided. In one aspect, a device includes a semiconductor device including one or more logic units and a reporting bus and a controller coupled to the semiconductor device and configured to store status information of the one or more logic units in the semiconductor device. Each of the one or more logic units is configured to send information associated with the logic unit using a corresponding reporting unit in the semiconductor device through the reporting bus to the controller to indicate a status of the logic unit. The controller is configured to, in response to receiving the information associated with the logic unit, update corresponding status information of the logic unit based on the status of the logic unit.

IPC Classes  ?

• G06F 9/30 - Arrangements for executing machine instructions, e.g. instruction decode
• G06F 1/08 - Clock generators with changeable or programmable clock frequency
• G06F 9/54 - Interprogram communication

Abstract

A memory device having a switching device for a page buffer is provided, and includes a plurality of switching units coupled between a memory cell array and a sense amplification circuit of the page buffer. Each of the plurality of switching units further comprising: a high voltage element and a low voltage element that are connected in series to each other. A first end of the high voltage element is coupled to the sense amplification circuit, and a first end of the low voltage element is coupled to a common source line of the memory cell array. A second end of the high voltage element and a second end of the low voltage element are connected to each other and coupled to a corresponding bit line of the memory cell array. The common source line coupled to each of the plurality of switching units shares a common active region.

IPC Classes  ?

• G11C 7/10 - Input/output [I/O] data interface arrangements, e.g. I/O data control circuits, I/O data buffers
• G11C 7/06 - Sense amplifiers; Associated circuits
• G11C 7/12 - Bit line control circuits, e.g. drivers, boosters, pull-up circuits, pull-down circuits, precharging circuits, equalising circuits, for bit lines

Abstract

A memory device and a method for manufacturing the memory device are provided. The memory device includes a stack and a plurality of memory strings. The stack is disposed on the substrate, and the stack includes a plurality of conductive layers and a plurality of insulating layers alternately stacked. The memory strings pass through the stack along a first direction, wherein a first memory string in the memory strings includes a first conductive pillar and a second conductive pillar, a channel layer, and a memory structure. The first conductive pillar and the second conductive pillar respectively extend along the first direction and are separated from each other. The channel layer is disposed between the first conductive pillar and the second conductive pillar. The memory structure surrounds the second conductive pillar, and the memory structure includes a resistive memory material.

IPC Classes  ?

• H10B 63/00 - Resistance change memory devices, e.g. resistive RAM [ReRAM] devices
• H10B 61/00 - Magnetic memory devices, e.g. magnetoresistive RAM [MRAM] devices
• H10N 50/01 - Manufacture or treatment
• H10N 70/00 - Solid-state devices without a potential-jump barrier or surface barrier, and specially adapted for rectifying, amplifying, oscillating or switching

Abstract

A semiconductor device includes a ground layer including a lower semiconductor material layer, a refilled semiconductor material layer disposed on the lower semiconductor material layer, and an upper conductive layer disposed on the refilled semiconductor material layer; a stacked structure disposed on the ground layer, including insulating layers and conductive layers alternately stacked along a first direction; and a conductive pillar penetrating the stacked structure and extending into the ground layer. The conductive pillar includes a bottom body portion corresponding to the ground layer, a middle body portion corresponding to middle and bottom portions of the stacked structure, and a plug. In a second direction, a first dimension in a portion of the bottom body portion overlapping the upper conductive layer is greater than a second dimension in a portion of the middle body portion overlapping a bottommost insulating layer of the stacked structure.

IPC Classes  ?

• H01L 23/535 - Arrangements for conducting electric current within the device in operation from one component to another including internal interconnections, e.g. cross-under constructions
• H01L 27/1157 - Electrically programmable read-only memories; Multistep manufacturing processes therefor with charge-trapping gate insulators, e.g. MNOS or NROM characterised by the memory core region with cell select transistors, e.g. NAND
• H01L 27/11582 - Electrically programmable read-only memories; Multistep manufacturing processes therefor with charge-trapping gate insulators, e.g. MNOS or NROM characterised by three-dimensional arrangements, e.g. with cells on different height levels with source and drain on different levels, e.g. with sloping channels the channels comprising vertical portions, e.g. U-shaped channels

Abstract

Systems, methods, circuits, and apparatuses for managing integrated circuits in memory devices are provided. In one aspect, a system includes a semiconductor device configured to store data, and a controller communicatively coupled to the semiconductor device. The controller is configured to send, to the semiconductor device, an instruction requesting transmission of the data; in response to determining that a predetermined time duration has elapsed after sending the instruction, initiate transmission of a read enable signal to the semiconductor device; receive, from the semiconductor device, a data strobe signal; and, in response to determining that the data strobe signal has a frequency matching a frequency of the read enable signal, read the data from the semiconductor device.

IPC Classes  ?

• G06F 3/06 - Digital input from, or digital output to, record carriers
• G11C 16/32 - Timing circuits

Abstract

An in-memory-computing method for a memory device includes: storing weight values in cascaded computing cells each including first and second computing memory cells, wherein the first computing memory cells are cascaded in series into a first computing memory cell string and the second computing memory cells are cascaded in series into a second computing memory cell string: receiving input values by the first and the second computing memory cell strings; performing a first logic operation on the input values and the weight values by the first computing memory cell string to generate a first logic operation result, and performing a second logic operation on the input values and the weight values by the second computing memory cell string to generate a second logic operation result: and performing a third logic operation on the first and the second logic operation results to generate an output logic operation result.

IPC Classes  ?

• G11C 13/00 - Digital stores characterised by the use of storage elements not covered by groups , , or
• H03K 19/20 - Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits characterised by logic function, e.g. AND, OR, NOR, NOT circuits

Abstract

A memory device includes a stack structure, a channel pillar, a first conductive pillar, a second conductive pillar, a charge storage structure, a first conductive layer, a second conductive layer, and an insulating liner layer. The stack structure is located on a dielectric substrate and includes gate layers and insulating layers alternately stacked with each other. The channel pillar extends through the stack structure. The first conductive pillar and the second conductive pillar are located in and electrically connecting with the channel pillars. The charge storage structure is located between the gate layers and the channel pillar. The first conductive and the second conductive layers are located between the stack structure and the dielectric substrate. The second conductive layer is closer the channel layer than the first conductive layer. The insulating liner layer separates the second conductive layer from the channel layer and the first conductive layer.

IPC Classes  ?

• H01L 27/11582 - Electrically programmable read-only memories; Multistep manufacturing processes therefor with charge-trapping gate insulators, e.g. MNOS or NROM characterised by three-dimensional arrangements, e.g. with cells on different height levels with source and drain on different levels, e.g. with sloping channels the channels comprising vertical portions, e.g. U-shaped channels
• H01L 27/11565 - Electrically programmable read-only memories; Multistep manufacturing processes therefor with charge-trapping gate insulators, e.g. MNOS or NROM characterised by the top-view layout
• H01L 27/11568 - Electrically programmable read-only memories; Multistep manufacturing processes therefor with charge-trapping gate insulators, e.g. MNOS or NROM characterised by the memory core region

Abstract

A semiconductor structure including a substrate and a pad structure is provided. The pad structure is located on the substrate. The pad structure includes material pairs and pads. The material pairs are stacked on the substrate to form a stair step structure. Each of the material pairs includes a conductive layer and a dielectric layer located on the conductive layer. Each of the pads includes a conductive pillar and a pad layer. The conductive pillar is embedded in the material pair and is connected to the conductive layer of the material pair. The pad layer is located on the conductive pillar.

IPC Classes  ?

• H01L 23/522 - Arrangements for conducting electric current within the device in operation from one component to another including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
• H01L 21/768 - Applying interconnections to be used for carrying current between separate components within a device

Abstract

A semiconductor element and a method for manufacturing the same are provided. The semiconductor element includes a plug and a via on the plug and electrically connected to the plug. The plug includes a tungsten plug and a conductive layer on the tungsten plug. The tungsten plug and the conductive layer include different materials. The tungsten plug has a first width in a lateral direction. The conductive layer has a second width in the lateral direction. The second width is greater than or equal to the first width. The conductive layer is between the via and the tungsten plug.

IPC Classes  ?

• H01L 21/768 - Applying interconnections to be used for carrying current between separate components within a device
• H01L 23/522 - Arrangements for conducting electric current within the device in operation from one component to another including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
• H01L 23/532 - Arrangements for conducting electric current within the device in operation from one component to another including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body characterised by the materials

Abstract

A memory device and a programming method thereof are provided. The programming method includes the following steps. According to a step value, based on an incremental step pulse programming scheme, multiple programming operations are performed for a selected memory page. In a setting mode, multiple program verify operations are respectively performed corresponding to the programming operations to respectively generate multiple pass bit numbers. In the setting mode, a pass bit number difference value of two pass bit numbers corresponding to two programming operations is calculated. In the setting mode, an amount of the step value is adjusted according to the pass bit number difference value.

IPC Classes  ?

• G11C 16/34 - Determination of programming status, e.g. threshold voltage, overprogramming or underprogramming, retention
• G11C 16/08 - Address circuits; Decoders; Word-line control circuits
• G11C 16/10 - Programming or data input circuits
• G11C 16/28 - Sensing or reading circuits; Data output circuits using differential sensing or reference cells, e.g. dummy cells

Abstract

A memory such as a 3D NAND array, having a page buffer having page buffer cells coupled to bit lines has a search word input such as a search word buffer coupled to word lines. A circuit, such as string select gates, is provided to connect a selected set of memory cells in the array to the page buffer. The page buffer includes sensing circuitry configured to apply a match sense signal to a latch in a plurality of storage elements for a stored data word and an input search word. Logic circuitry uses storage elements in the plurality of storage elements of the page buffer to accumulate the match sense signals output by the sensing circuitry over a sequence matching a plurality stored data words to one or more input search words. A match for a search is based on a threshold and the accumulated match sense signals.

IPC Classes  ?

• G11C 16/26 - Sensing or reading circuits; Data output circuits
• G11C 16/24 - Bit-line control circuits
• G11C 16/04 - Erasable programmable read-only memories electrically programmable using variable threshold transistors, e.g. FAMOS

Abstract

A memory device and a method for operating the same are provided. In an erase operation, a switch voltage is applied to at least one of a string select line or a ground select line of a selected sub-block of a selected block, a gate control voltage is applied to selected word lines of the selected sub-block, and an erase voltage is applied to bit lines and a common source line of the selected sub-block. The switch voltage is smaller than the erase voltage. The gate control voltage is smaller than the switch voltage and the erase voltage.

IPC Classes  ?

• G11C 16/16 - Circuits for erasing electrically, e.g. erase voltage switching circuits for erasing blocks, e.g. arrays, words, groups
• G11C 16/04 - Erasable programmable read-only memories electrically programmable using variable threshold transistors, e.g. FAMOS
• G11C 16/10 - Programming or data input circuits
• G11C 16/26 - Sensing or reading circuits; Data output circuits

Abstract

An electrostatic discharge protection circuit includes a N type region, a P type component, a P type region, a N type element, a first conductive terminal, a second conductive terminal, a power clamp circuit and a conductive pad. The P type component is in the N type region. The N type element is in the P type region. The first conductive terminal is electrically connected to the N type region. The second conductive terminal is electrically connected to the P type region and the N type element. The power clamp circuit is electrically connected between the first conductive terminal and the second conductive terminal. The conductive pad is electrically connected to the P type component.

IPC Classes  ?

• H01L 29/74 - Thyristor-type devices, e.g. having four-zone regenerative action
• H01L 29/06 - Semiconductor bodies characterised by the shapes, relative sizes, or dispositions of the semiconductor regions

Abstract

A semiconductor structure is provided. The semiconductor structure includes a first substrate, a device layer, a first dielectric layer, a second dielectric layer, a second substrate, and a circuit layer. The device layer is disposed on the first substrate. The first dielectric layer is disposed on the device layer. The second dielectric layer is disposed on the first dielectric layer. The second substrate is disposed on the second dielectric layer. The circuit layer is disposed on the second substrate.

IPC Classes  ?

• H01L 23/522 - Arrangements for conducting electric current within the device in operation from one component to another including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
• H01L 21/762 - Dielectric regions
• H01L 21/768 - Applying interconnections to be used for carrying current between separate components within a device
• H01L 23/00 - SEMICONDUCTOR DEVICES NOT COVERED BY CLASS - Details of semiconductor or other solid state devices

Abstract

The application provides a memory device and an operation method thereof. The memory device includes: a memory array, for processing model computation having a plurality of input values and a plurality of interact coefficients; and at least one calculation unit. In receiving the input values, a first part and a second part of the memory cells generate a first part and a second part of the common source currents, respectively. The first part of the memory cells is electrically isolated from the second part of the memory cells based on a diagonal of the memory array. The at least one calculation unit calculates a first part and a second part of a local field energy of the model computation based on the first part and the second part of the common source currents.

IPC Classes  ?

• G11C 7/10 - Input/output [I/O] data interface arrangements, e.g. I/O data control circuits, I/O data buffers

Abstract

An embodiment of the present disclosure discloses a memory device. The memory device comprises a memory controller, a buffer and a memory array. The buffer is coupled to the memory controller or embedded in the memory controller. A storage space of the buffer is configured by the memory controller to include a plurality of groups. The memory array is coupled to the memory controller, and comprising a plurality of tiles. The groups are one-to-one corresponding to the tiles. Each of the groups is configured to store data to be written into the corresponding tile. The memory controller performs one or more write operations based on the groups.

IPC Classes  ?

• G06F 3/06 - Digital input from, or digital output to, record carriers

Abstract

A memory device, an error correction device and an error correction method thereof are provided. The error correction device includes a first error correction decoder and a second error correction decoder. The first error correction decoder performs at least one iteration of a first error correction operation on a data chunk, calculates a counting number of syndrome values equal to a set logic value generated in the at least one iteration of the first error correction operation, and generates a control signal according to the counting number. The second error correction decoder receives the control signal and determines whether to be activated to perform a second error correction operation on the data chunk or not according to the control signal. An error correction ability of the second error correction decoder is higher than an error correction ability of the first error correction decoder.

IPC Classes  ?

• H03M 13/00 - Coding, decoding or code conversion, for error detection or error correction; Coding theory basic assumptions; Coding bounds; Error probability evaluation methods; Channel models; Simulation or testing of codes
• G06F 7/501 - Half or full adders, i.e. basic adder cells for one denomination
• H03M 13/11 - Error detection or forward error correction by redundancy in data representation, i.e. code words containing more digits than the source words using block codes, i.e. a predetermined number of check bits joined to a predetermined number of information bits using multiple parity bits
• H03M 13/15 - Cyclic codes, i.e. cyclic shifts of codewords produce other codewords, e.g. codes defined by a generator polynomial, Bose-Chaudhuri-Hocquenghem [BCH] codes

Abstract

A memory device for CIM, applicable to a 3D AND-type flash memory, includes a memory array, input word line pairs, and a signal processing circuit. The memory array includes first and second pairs of memory cells. Each first pair of memory cells includes a first memory cell set coupled to a first GBL and a second memory cell set coupled to a second GBL. Each second pair of memory cells includes a third memory cell set coupled to the first GBL and a fourth memory cell set coupled to the second GBL. Each input word line pair includes a first input word line coupled to the first and the second memory cell sets, and a second input word line coupled to the third and the fourth memory cell sets s. The signal processing circuit is coupled to the first and second global bit lines.

IPC Classes  ?

• G06F 3/06 - Digital input from, or digital output to, record carriers
• G11C 16/28 - Sensing or reading circuits; Data output circuits using differential sensing or reference cells, e.g. dummy cells

Abstract

A memory device for in-memory search is provided. The memory device includes a plurality of memory cells, and each of the memory cells stores a stored data and receives a search data, including a first transistor and a second transistor. The first transistor has a first threshold voltage and receives a first gate bias. The second transistor is connected to the first transistor, and the second transistor has a second threshold voltage and receives a second gate bias. The stored data is encoded according to the first threshold voltage and the second threshold voltage, and the search data is encoded according to the first gate bias and the second gate bias. There is a mismatch distance between the stored data and the search data. An output current generated by each of the memory cells is related to the mismatch distance.

IPC Classes  ?

• G11C 16/34 - Determination of programming status, e.g. threshold voltage, overprogramming or underprogramming, retention
• G11C 16/26 - Sensing or reading circuits; Data output circuits
• G11C 16/30 - Power supply circuits
• G11C 15/04 - Digital stores in which information comprising one or more characteristic parts is written into the store and in which information is read-out by searching for one or more of these characteristic parts, i.e. associative or content-addressed stores using semiconductor elements

Abstract

A memory device includes a plurality of computing memory cells, each of which stores a weight value, receives an input value and generates an output value. Each of the computing memory cells includes a transistor connected to a bit line and a word line, receiving a sensing current through the bit line and receiving an input voltage through the word line. When the sensing current flows through the transistor, the computing memory cell generates a first voltage difference corresponding to the output value. The output value is equal to a product of the input value and the weight value.

IPC Classes  ?

• G11C 13/00 - Digital stores characterised by the use of storage elements not covered by groups , , or
• G06F 7/544 - Methods or arrangements for performing computations using exclusively denominational number representation, e.g. using binary, ternary, decimal representation using unspecified devices for evaluating functions by calculation

Abstract

A memory array is arranged to store data words in respective sets of TCAM cells, where each TCAM cell is configured to store ternary states of a bit of the stored word. A circuit to select a set of TCAM cells in the set of TCAM cells, such as decoders and drivers for word lines, bit lines, block select gates. A circuit to apply an input search word to the TCAM cells in the selected set of TCAM cells, such as a search word buffer or driver on one of word lines or bit lines for the array. A circuit to generate an output indicating similarity of the stored word in the selected set of TCAM cells to the input search word, based on mismatch or possible mismatch of more than one bit of the search word.

IPC Classes  ?

• G11C 7/10 - Input/output [I/O] data interface arrangements, e.g. I/O data control circuits, I/O data buffers
• G11C 7/12 - Bit line control circuits, e.g. drivers, boosters, pull-up circuits, pull-down circuits, precharging circuits, equalising circuits, for bit lines
• G11C 8/08 - Word line control circuits, e.g. drivers, boosters, pull-up circuits, pull-down circuits, precharging circuits, for word lines
• G11C 15/04 - Digital stores in which information comprising one or more characteristic parts is written into the store and in which information is read-out by searching for one or more of these characteristic parts, i.e. associative or content-addressed stores using semiconductor elements

Abstract

A memory device is provided. The memory device includes channel layers, word lines, memory layers disposed between the channel layers and the word lines, and memory cells defined at cross-points of the channel layers and the word lines. The memory device is configured for performing a first operation for m times and a second operation for n times, and m is equal to or larger than n. In the first operation, a first electric field is produced in a portion of the memory layers. The word lines are configured for producing a second electric field in the second operation in the portion of the memory layers, and a field direction of the second electric field is different from a field direction of the first electric field.

IPC Classes  ?

• G06F 3/06 - Digital input from, or digital output to, record carriers

Abstract

A switching device is provided. The device includes a first electrode, a second electrode and a multi-layer ovonic threshold switch (OTS) between the first and second electrodes, the multi-layer OTS including a first layer and a second layer. The first layer and the second layer are different compositions, and the second layer includes germanium Ge and nitrogen N. The switching device can be thermally stable to temperatures over 600° C. Further, the switching device can be used in three-dimensional (3D) cross-point memory.

IPC Classes  ?

• H01L 27/24 - Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including solid state components for rectifying, amplifying, or switching without a potential-jump barrier or surface barrier
• H01L 45/00 - Solid state devices specially adapted for rectifying, amplifying, oscillating, or switching without a potential-jump barrier or surface barrier, e.g. dielectric triodes; Ovshinsky-effect devices; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof

Abstract

A memory structure includes a substrate, a first gate structure, a second gate structure, a third gate structure, and channel bodies separated from each other and passing through the first gate structure, the second gate structure and the third gate structure along a first direction. The first gate structure, the second gate structure and the third gate structure are disposed on the substrate, and are separated from each other along the first direction and extend respectively along a second direction and a third direction. The first gate includes first, second and third island structures respectively extending along the third direction and separated from each other along the second direction. The third gate structure includes fourth, fifth and sixth island structures respectively extending along the third direction and separated from each other along the second direction.

IPC Classes  ?

• H01L 27/108 - Dynamic random access memory structures

Abstract

A hybrid type content addressable memory for implementing in-memory-search and an operation method thereof are provided. The CAM includes a plurality of CAM strings and at least one sense amplifier circuit. Each of the CAM strings includes a plurality of CAM cells. The CAM cells store a plurality of existing data. The sense amplifier circuit is connected to the CAM strings. A plurality of search data are inputted to the CAM strings. A plurality of cell matching results obtained from the CAM cells in each of the CAM strings are integrated via an AND operation to obtain a string matching result. The string matching results obtained from the CAM strings are integrated via an OR operation.

IPC Classes  ?

• G11C 15/04 - Digital stores in which information comprising one or more characteristic parts is written into the store and in which information is read-out by searching for one or more of these characteristic parts, i.e. associative or content-addressed stores using semiconductor elements

Abstract

A memory device and an operation method thereof for performing a multiply-accumulate operation are provided. The memory device includes at least one memory string, a plurality of data lines and a string line. The memory string includes a plurality of unit cells having a plurality of stored values. The data lines are respectively connected to the unit cells to receive a plurality of data signals having a plurality of inputting values. When the data signals are inputted into the unit cells, a plurality of nodes among the unit cells are kept at identical voltages. The string line is connected to the memory string to receive a sensing signal and obtain a measured value representing a sum-of-product result of the inputting values and the stored values. The data signals and the sensing signal are received at different time.

IPC Classes  ?

• G11C 13/00 - Digital stores characterised by the use of storage elements not covered by groups , , or
• G06F 7/544 - Methods or arrangements for performing computations using exclusively denominational number representation, e.g. using binary, ternary, decimal representation using unspecified devices for evaluating functions by calculation

Abstract

A data search method for a memory device is provided. The data search method includes: based on a recorded compression mode, vectoring a search data to generate a search data vector, and based on the recorded compression mode, compressing the search data and a plurality of objects in a database; setting a search condition; searching the objects of the database by the search data vector to determine whether the search data is matched with the objects of the database; and recording and outputting at least one matched object of the database, the at least one matched object matched with the search data.

IPC Classes  ?

• G06F 12/00 - Accessing, addressing or allocating within memory systems or architectures
• G06F 3/06 - Digital input from, or digital output to, record carriers
• G06F 16/9032 - Query formulation

Abstract

A semiconductor device includes a circuit board, a bottom plate, landing pads, a stack, support pillars, and memory pillars. The circuit board includes circuit structures and wires and has a peripheral area, an array area and a staircase area disposed between the peripheral area and the array area. The bottom plate is disposed on the circuit board, and the bottom plate includes a bottom conductive layer. The landing pads are embedded in at least a top portion of the bottom conductive layer and contact the bottom conductive layer in the staircase area. The stack is disposed on the bottom plate, and includes conductive layers and insulating layers alternately stacked along a first direction. The support pillars pass through the stack along the first direction and extend to the landing pads in the staircase area. The memory pillars pass through the stack along the first direction in the array area.

IPC Classes  ?

• H01L 27/11578 - Electrically programmable read-only memories; Multistep manufacturing processes therefor with charge-trapping gate insulators, e.g. MNOS or NROM characterised by three-dimensional arrangements, e.g. with cells on different height levels
• H01L 27/11565 - Electrically programmable read-only memories; Multistep manufacturing processes therefor with charge-trapping gate insulators, e.g. MNOS or NROM characterised by the top-view layout

Abstract

A data search method for a memory device is provided. The data search method includes: based on a recorded compression mode, vectoring a search data to generate a search data vector, and based on the recorded compression mode, compressing the search data and a plurality of objects in a database; setting a search condition; searching the objects of the database by the search data vector to determine whether the search data is matched with the objects of the database; and recording and outputting at least one matched object of the database, the at least one matched object matched with the search data.

IPC Classes  ?

• G06F 16/2457 - Query processing with adaptation to user needs
• G06F 16/22 - Indexing; Data structures therefor; Storage structures
• G06F 16/28 - Databases characterised by their database models, e.g. relational or object models
• G11C 7/12 - Bit line control circuits, e.g. drivers, boosters, pull-up circuits, pull-down circuits, precharging circuits, equalising circuits, for bit lines
• G11C 8/14 - Word line organisation; Word line lay-out

Abstract

A three-dimensional flash memory device may be a AND flash memory device. The three-dimensional flash memory device includes: a substrate, a gate stack structure, a plurality of slit structures, a plurality of memory arrays, and a plurality of conductive pillars. The gate stack structure is located above the substrate. The plurality of slit structures extend through the gate stack structure and divide the gate stack structure into a plurality of blocks. The plurality of memory arrays are disposed in the gate stack structure of the plurality of blocks. The plurality of conductive pillars extends through the gate stack structure in the plurality of blocks, and disposed between the plurality of memory arrays and between the plurality of slit structures.

IPC Classes  ?

• H01L 27/11582 - Electrically programmable read-only memories; Multistep manufacturing processes therefor with charge-trapping gate insulators, e.g. MNOS or NROM characterised by three-dimensional arrangements, e.g. with cells on different height levels with source and drain on different levels, e.g. with sloping channels the channels comprising vertical portions, e.g. U-shaped channels
• H01L 23/535 - Arrangements for conducting electric current within the device in operation from one component to another including internal interconnections, e.g. cross-under constructions
• H01L 27/11573 - Electrically programmable read-only memories; Multistep manufacturing processes therefor with charge-trapping gate insulators, e.g. MNOS or NROM characterised by the peripheral circuit region

Abstract

The application provides a content addressable memory (CAM) memory device, a CAM cell and a method for searching and comparing data thereof. The CAM device includes: a plurality of CAM cells; and an electrical characteristic detection circuit coupled to the CAM cells; wherein in data searching, a search data is compared with a storage data stored in the CAM cells, the CAM cells generate a plurality of memory cell currents, the electrical characteristic detection circuit detects the memory cell currents to generate a plurality of sensing results, or the electrical characteristic detection circuit detects a plurality of match line voltages on a plurality of match lines coupled to the CAM cells to generate the plurality of search results; and the storage data is a single-bit multi-level storage data and/or the search data is a single-bit multi-level search data.

IPC Classes  ?

• G11C 15/04 - Digital stores in which information comprising one or more characteristic parts is written into the store and in which information is read-out by searching for one or more of these characteristic parts, i.e. associative or content-addressed stores using semiconductor elements
• G11C 7/14 - Dummy cell management; Sense reference voltage generators

Abstract

A memory chip, a memory device and an operation method are disclosed. The memory chip includes a number of memory units and a control logic circuit. The memory units could be configured as TLC, MLC or SLC. The control logic circuit is configured to use TLC programming approach to program MLC and SLC.

IPC Classes  ?

• G11C 7/10 - Input/output [I/O] data interface arrangements, e.g. I/O data control circuits, I/O data buffers

Abstract

Methods, devices, and systems for managing data refresh for semiconductor devices are provided. In one aspect, a semiconductor device includes a memory cell array having a plurality of blocks each including multiple pages and one or more integrated circuits coupled to the memory cell array. The one or more integrated circuits are configured to: read specific data from a page of a block in the memory cell array, perform a logic operation on the specific data in the page to obtain a logic operation result, count a number of bits having a specific value among the logic operation result, determine whether the number of bits is within a data refresh criterion for the page, and in response to determining that the number of bits is outside of the data refresh criterion, generate a data refresh warning message for the page in the block.

IPC Classes  ?

• G11C 11/406 - Management or control of the refreshing or charge-regeneration cycles
• G11C 11/4096 - Input/output [I/O] data management or control circuits, e.g. reading or writing circuits, I/O drivers or bit-line switches
• H03K 19/20 - Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits characterised by logic function, e.g. AND, OR, NOR, NOT circuits

Abstract

An integrated circuit structure includes a plurality of gate layers, a laterally stacked multi-layered memory structure, and a vertical channel layer. The gate layers laterally extend above the substrate and spaced apart from each other. The laterally stacked multi-layered memory structure extends upwardly above the substrate and through the gate layers and including a blocking layer, a charge storage stack, and a tunneling layer. The charge storage stack is on the blocking layer and including a first silicon nitride layer, a second silicon nitride layer, and a silicon oxynitride layer sandwiched between the first and second silicon nitride layers. The tunneling layer is on the charge storage stack. The vertical channel layer is on the laterally stacked multi-layered memory structure.

IPC Classes  ?

• H01L 27/11582 - Electrically programmable read-only memories; Multistep manufacturing processes therefor with charge-trapping gate insulators, e.g. MNOS or NROM characterised by three-dimensional arrangements, e.g. with cells on different height levels with source and drain on different levels, e.g. with sloping channels the channels comprising vertical portions, e.g. U-shaped channels

Abstract

The application discloses an analog content addressable memory (CAM) device, an analog CAM cell and a method for data searching and comparing thereof. The CAM cell includes: a first memory cell and a second memory cell coupled to each other, wherein the analog CAM cell stores analog storage data which is corresponding to a match range, the match range is determined based on first and second threshold voltages of the analog CAM cell; an analog search data is converted into first and second analog search voltages; the first and the second memory cells receive the first and the second analog search voltages; and the analog CAM memory cell generates a memory cell current, or the analog CAM memory cell keeps or discharges a match line voltage on a match line coupled to the analog CAM memory cell.

IPC Classes  ?

• G11C 15/04 - Digital stores in which information comprising one or more characteristic parts is written into the store and in which information is read-out by searching for one or more of these characteristic parts, i.e. associative or content-addressed stores using semiconductor elements

Abstract

A memory device comprises an array of memory cells, a physically unclonable function PUF circuit in the memory device to generate a PUF code, a data path connecting a first circuit to a second circuit in the memory device coupled to the array of memory cells, and logic circuitry to encode data on the data path from the first circuit using the PUF code to produce encoded data, and to provide the encoded data to the second circuit.

IPC Classes  ?

• G11C 7/24 - Memory cell safety or protection circuits, e.g. arrangements for preventing inadvertent reading or writing; Status cells; Test cells
• H04L 9/32 - Arrangements for secret or secure communications; Network security protocols including means for verifying the identity or authority of a user of the system
• G06F 21/44 - Program or device authentication

Abstract

An integrated circuit structure includes a substrate, a conductive layer, a plurality of memory devices, a bonding pad, and a source line. The conductive layer is over the substrate. The memory devices are stacked in a vertical direction over the conductive layer. The bonding pad is over the conductive layer. The source line extends upwardly from the bonding pad and has a lower portion inlaid in the bonding pad and an upper portion having a sidewall coterminous with a sidewall of the bonding pad. A top end of the source line has a first lateral dimension greater than a second lateral dimension of the bonding pad.

IPC Classes  ?

• H01L 27/11575 - Electrically programmable read-only memories; Multistep manufacturing processes therefor with charge-trapping gate insulators, e.g. MNOS or NROM characterised by the boundary region between the core and peripheral circuit regions
• H01L 27/11582 - Electrically programmable read-only memories; Multistep manufacturing processes therefor with charge-trapping gate insulators, e.g. MNOS or NROM characterised by three-dimensional arrangements, e.g. with cells on different height levels with source and drain on different levels, e.g. with sloping channels the channels comprising vertical portions, e.g. U-shaped channels

Abstract

A semiconductor structure is provided. The semiconductor structure includes a substrate and a via structure. The via structure is through the substrate. The via structure includes a first conductive portion, a second conductive portion, a first barrier portion, a second barrier portion, and a third barrier portion. The first conductive portion has a ring-shaped cross section. The second conductive portion is disposed at an inner side of the first conductive portion. The second conductive portion has a ring-shaped cross section. The first barrier portion is disposed at an outer side of the first conductive portion. The second barrier portion is disposed between the first conductive portion and the second conductive portion. The third barrier portion is disposed at an inner side of the second conductive portion. At least one of the first barrier portion, the second barrier portion, or the third barrier portion includes an insulating 2D material.

IPC Classes  ?

• H01L 23/522 - Arrangements for conducting electric current within the device in operation from one component to another including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
• H01L 23/532 - Arrangements for conducting electric current within the device in operation from one component to another including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body characterised by the materials

Abstract

A three dimension memory device, such as an AND-type memory, includes a memory cell tile, multiple source line switches, multiple first bit line switches to fourth bit line switches. The memory cell tile is divided into a first and a second memory cell sub-tiles. The first bit line switches are respectively coupled to multiple first bit lines of a first part of the first memory cell sub-tile. The second bit line switches are respectively coupled to multiple second bit lines of a second part of the first memory cell sub-tile. The third bit line switches are respectively coupled to multiple third bit lines of a first part of the second memory cell sub-tile. The fourth bit line switches are respectively coupled to multiple fourth bit lines of a second part of the second memory cell sub-tile.

IPC Classes  ?

• G11C 11/4094 - Bit-line management or control circuits
• G11C 11/408 - Address circuits
• G11C 11/4096 - Input/output [I/O] data management or control circuits, e.g. reading or writing circuits, I/O drivers or bit-line switches
• G11C 11/4072 - Circuits for initialization, powering up or down, clearing memory or presetting
• G11C 11/4091 - Sense or sense/refresh amplifiers, or associated sense circuitry, e.g. for coupled bit-line precharging, equalising or isolating
• G11C 11/4093 - Input/output [I/O] data interface arrangements, e.g. data buffers
• G11C 5/06 - Arrangements for interconnecting storage elements electrically, e.g. by wiring

Abstract

A memory device and a data approximation search method thereof are proposed. The memory device includes a plurality of selection switch pairs, a plurality of memory cell string pairs, a sense amplifier, and a page buffer. The selection switch pairs receive multiple search data pairs, respectively. The memory cell string pairs are respectively coupled to a global bit line through the selection switch pairs. Each of the memory cell string pairs determines whether to provide current on the global bit line according to stored data of a selected memory cell pair and each of the search data pairs. The sense amplifier obtains multiple search results according to the current on the global bit line and at least one reference currents respectively corresponding to at least one similarity. The page buffer records the search results and generates similarity information by accumulating the search results.

IPC Classes  ?

• G11C 7/08 - Control thereof
• G11C 7/12 - Bit line control circuits, e.g. drivers, boosters, pull-up circuits, pull-down circuits, precharging circuits, equalising circuits, for bit lines
• G11C 7/10 - Input/output [I/O] data interface arrangements, e.g. I/O data control circuits, I/O data buffers
• G06F 7/501 - Half or full adders, i.e. basic adder cells for one denomination

Abstract

A memory cell for an analog content-addressable memory is provided. The memory cell includes an N-type transistor, a P-type transistor, and a current control circuit. The gate of the N-type transistor is configured to receive a first input signal. The gate of the P-type transistor is configured to receive a second input signal. The current control circuit is coupled to at least one of the N-type transistor and the P-type transistor. The current control circuit is configured to generate at least one passing current. When the input voltages of the first input signal and the second input signal are within a matching range, the N-type transistor and the P-type transistor are turned on, and the passing current is substantially a fixed current value. The matching range is related to the threshold voltages of the N-type transistor and the P-type transistor, and the fixed current value.

IPC Classes  ?

• G11C 15/04 - Digital stores in which information comprising one or more characteristic parts is written into the store and in which information is read-out by searching for one or more of these characteristic parts, i.e. associative or content-addressed stores using semiconductor elements

Abstract

A ternary content addressable memory, disposed in a stacked memory device, includes a first memory cell string and a second memory cell string. The first memory cell string is coupled between a matching line and a first source line and receives multiple first word line signals. The first memory cell string has a first memory cell string selection switch controlled by a first search signal. The second memory cell string is coupled between the matching line and a second source line and receives multiple second word line signals. The second memory cell string has a second memory cell string selection switch controlled by a second search signal.

IPC Classes  ?

• G11C 15/04 - Digital stores in which information comprising one or more characteristic parts is written into the store and in which information is read-out by searching for one or more of these characteristic parts, i.e. associative or content-addressed stores using semiconductor elements

Abstract

A three-dimension memory device, a memory circuit and a production method are provided. The three-dimension memory circuit includes a peripheral circuit, a metal layer, a buffer layer, a poly silicon layer, and a via array. The peripheral circuit is disposed on a substrate. The metal layer covers on the peripheral circuit and is electrically coupled to the peripheral circuit. The buffer layer is disposed on the metal layer. The poly silicon layer receives a reference ground voltage and is disposed on the buffer layer. The via array is disposed in the buffer layer and is used to electrically connect the metal layer and the poly silicon layer.

IPC Classes  ?

• H01L 27/11526 - Electrically programmable read-only memories; Multistep manufacturing processes therefor with floating gate characterised by the peripheral circuit region
• H01L 23/522 - Arrangements for conducting electric current within the device in operation from one component to another including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
• H01L 23/528 - Layout of the interconnection structure
• H01L 27/11551 - Electrically programmable read-only memories; Multistep manufacturing processes therefor with floating gate characterised by three-dimensional arrangements, e.g. with cells on different height levels
• H01L 27/11573 - Electrically programmable read-only memories; Multistep manufacturing processes therefor with charge-trapping gate insulators, e.g. MNOS or NROM characterised by the peripheral circuit region
• H01L 27/11578 - Electrically programmable read-only memories; Multistep manufacturing processes therefor with charge-trapping gate insulators, e.g. MNOS or NROM characterised by three-dimensional arrangements, e.g. with cells on different height levels

Abstract

The present disclosure provides a 3D memory structure such as 3D Flash memory structure applying for 3D AND flash memory and a method of forming the same. An etching stop layer is formed on a substrate including active elements. A stacked layer is formed on the etching stop layer. The stacked layer includes insulation layers and sacrificed layers stacked alternatively on the etching stop layer. A patterning process is performed on the stacked layer to form a first stacked structure above the active elements, a second stacked structure surrounding the first stacked structure, and a trench pattern separating the first stacked structure and the second stacked structure and exposing the etching stop layer. The trench pattern includes asymmetric inner sidewalls and outer sidewalls. The inner sidewalls define sidewalls of the first stacked structure. The outer sidewalls define sidewalls of the second stacked structure that face the first stacked structure.

IPC Classes  ?

• H01L 21/768 - Applying interconnections to be used for carrying current between separate components within a device
• H01L 23/528 - Layout of the interconnection structure

Abstract

A memory device and an operation method thereof are provided. The operation method includes: in a programming operation, programming a plurality of threshold voltages of a plurality of switches on a plurality of string select lines and a plurality of ground select lines as a first reference threshold voltage, and programming a plurality of threshold voltages of a plurality of dummy memory cells on a plurality of dummy word lines as being gradually increased along a first direction or a second direction, and the threshold voltages of the dummy memory cells being higher than the first reference threshold voltage; wherein the first direction being from the string select lines to a plurality of word lines and the second direction being from the ground select lines to the word lines.

IPC Classes  ?

• G11C 16/34 - Determination of programming status, e.g. threshold voltage, overprogramming or underprogramming, retention
• G11C 16/10 - Programming or data input circuits

Abstract

A memory device is provided. The memory device includes a memory array of a plurality of memory elements, a plurality of word lines or word line pairs, a plurality of bit line pairs, and a plurality of common source lines. Each of the memory elements includes two memory cells. The memory device is configured for calculating an energy value based on a plurality of state signals and a plurality of coefficients, and the two memory cells of each of the memory elements are configured for performing an individual selection such that one of the two memory cells of each of the memory elements receives two corresponding state signals from a corresponding word line or a corresponding word line pair and a corresponding bit line pair and generates an output current into a corresponding common source line for calculating the energy value.

IPC Classes  ?

• G11C 11/40 - Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors
• G11C 11/408 - Address circuits
• G11C 11/4094 - Bit-line management or control circuits
• G11C 11/4096 - Input/output [I/O] data management or control circuits, e.g. reading or writing circuits, I/O drivers or bit-line switches

Abstract

A memory device may be applicated in a 3D AND flash memory device. The memory device includes a gate stack structure, a doped channel stack structure, a source pillar and a drain pillar, and a plurality of dielectric structures. The gate stack structure is located on a substrate. The gate stack structure includes a plurality of gate layers and a plurality of insulating layers stacked alternately with each other. The doped channel stack structure extends through the gate stack structure. The doped channel stack structure includes a plurality of doped channel rings spaced apart from each other. The source pillar and the drain pillar extend through the doped channel stack structure. The source pillar and the drain pillar are respectively electrically connected to the plurality of doped channel rings. The plurality of dielectric structures are located between the plurality of gate layers and the plurality of doped channel rings.

IPC Classes  ?

• H01L 27/11582 - Electrically programmable read-only memories; Multistep manufacturing processes therefor with charge-trapping gate insulators, e.g. MNOS or NROM characterised by three-dimensional arrangements, e.g. with cells on different height levels with source and drain on different levels, e.g. with sloping channels the channels comprising vertical portions, e.g. U-shaped channels

Abstract

A semiconductor device may be applicated in a three-dimensional AND flash memory device. The semiconductor device includes a dielectric substrate, a composite stack structure, a vertical pillar array and a resistor. The dielectric substrate includes a first region and a second region. The composite stack structure is located over the dielectric substrate in the first region and the second region. The vertical pillar array is disposed in the composite stack structure in the first region. The resistor is laterally adjacent to the vertical pillar array, extends below the composite stack structure in the second region, extends through the composite stack structure, and extends above the composite stack structure.

IPC Classes  ?

• H01L 23/522 - Arrangements for conducting electric current within the device in operation from one component to another including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
• H01L 27/11565 - Electrically programmable read-only memories; Multistep manufacturing processes therefor with charge-trapping gate insulators, e.g. MNOS or NROM characterised by the top-view layout
• H01L 27/11573 - Electrically programmable read-only memories; Multistep manufacturing processes therefor with charge-trapping gate insulators, e.g. MNOS or NROM characterised by the peripheral circuit region
• H01L 27/11582 - Electrically programmable read-only memories; Multistep manufacturing processes therefor with charge-trapping gate insulators, e.g. MNOS or NROM characterised by three-dimensional arrangements, e.g. with cells on different height levels with source and drain on different levels, e.g. with sloping channels the channels comprising vertical portions, e.g. U-shaped channels
• H01L 23/528 - Layout of the interconnection structure

Abstract

A memory device may be applicated in a 3D AND flash memory device. The memory device includes a dielectric substrate, a plurality of memory cells, a slit structure, and a middle section of a seal ring. The gate composite stack structure disposed on the dielectric substrate in a first region and a second region of the dielectric substrate. The plurality of memory cells disposed in the composite stack structure. The slit structure extends through the composite stack structure in first region. The composite stack structure is divided into a plurality of blocks. The middle section of a seal ring extends through the composite stack structure in the second region. The middle section of the seal ring includes a body part extending through the composite stack structure in the second region and a liner layer located between the body part and the composite stack structure.

IPC Classes  ?

• H01L 27/11582 - Electrically programmable read-only memories; Multistep manufacturing processes therefor with charge-trapping gate insulators, e.g. MNOS or NROM characterised by three-dimensional arrangements, e.g. with cells on different height levels with source and drain on different levels, e.g. with sloping channels the channels comprising vertical portions, e.g. U-shaped channels
• H01L 27/11519 - Electrically programmable read-only memories; Multistep manufacturing processes therefor with floating gate characterised by the top-view layout
• H01L 27/11556 - Electrically programmable read-only memories; Multistep manufacturing processes therefor with floating gate characterised by three-dimensional arrangements, e.g. with cells on different height levels with source and drain on different levels, e.g. with sloping channels the channels comprising vertical portions, e.g. U-shaped channels
• H01L 27/11565 - Electrically programmable read-only memories; Multistep manufacturing processes therefor with charge-trapping gate insulators, e.g. MNOS or NROM characterised by the top-view layout
• H01L 23/528 - Layout of the interconnection structure
• H01L 23/522 - Arrangements for conducting electric current within the device in operation from one component to another including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
• H01L 23/04 - Containers; Seals characterised by the shape

Abstract

A memory device and a method for manufacturing the same are provided. The memory device includes a stacked structure, a lower isolation structure in the stacked structure and two memory strings in the stacked structure. The stacked structure includes conductive layers. The lower isolation structure has an upper surface in a lower portion of the stacked structure. The lower isolation structure separates at least one conductive layer of the conductive layers into a first conductive strip and a second conductive strip. The first conductive strip and the second conductive strip are electrically isolated from each other. Two memory strings are electrically connected to the first conductive strip and the second conductive strip respectively.

IPC Classes  ?

• G11C 16/04 - Erasable programmable read-only memories electrically programmable using variable threshold transistors, e.g. FAMOS
• H01L 27/11556 - Electrically programmable read-only memories; Multistep manufacturing processes therefor with floating gate characterised by three-dimensional arrangements, e.g. with cells on different height levels with source and drain on different levels, e.g. with sloping channels the channels comprising vertical portions, e.g. U-shaped channels
• H01L 27/11519 - Electrically programmable read-only memories; Multistep manufacturing processes therefor with floating gate characterised by the top-view layout

Abstract

The application provides a content addressable memory (CAM) memory device, a CAM memory cell and a method for searching and comparing data thereof. The CAM memory device includes: a plurality of CAM memory strings; and an electrical characteristic detection circuit. In data searching, a search data is compared with a storage data stored in the CAM memory strings, the CAM memory strings generate a plurality of memory string currents, the electrical characteristic detection circuit detects the memory string currents to generate a plurality of sensing results, or detects a plurality of match line voltages on a plurality of match lines coupled to the CAM memory string to generate the plurality of search results. The storage data and the search data is a range storage data and a single-bit search data, or the storage data and the search data is a single-bit storage data and a range search data.

IPC Classes  ?

• G11C 15/04 - Digital stores in which information comprising one or more characteristic parts is written into the store and in which information is read-out by searching for one or more of these characteristic parts, i.e. associative or content-addressed stores using semiconductor elements

Abstract

An integrated circuit structure includes a substrate, an interconnect stack, a first memory array, and a source line. The interconnect stack is over the substrate. The first memory array is over the interconnect stack and includes memory elements stacked in a vertical direction each comprising a conductive layer. The first memory array further includes a memory layer electrically connecting to the conductive layers of the memory elements and extending downwardly from a topmost one of the conductive layers to a lowermost one of the conductive layers; and a channel layer extending along a sidewall of the memory layer. The source line is in contact with a top end of the channel layer and laterally extends across the first memory array.

IPC Classes  ?

• H01L 27/11582 - Electrically programmable read-only memories; Multistep manufacturing processes therefor with charge-trapping gate insulators, e.g. MNOS or NROM characterised by three-dimensional arrangements, e.g. with cells on different height levels with source and drain on different levels, e.g. with sloping channels the channels comprising vertical portions, e.g. U-shaped channels
• H01L 23/535 - Arrangements for conducting electric current within the device in operation from one component to another including internal interconnections, e.g. cross-under constructions
• H01L 27/11556 - Electrically programmable read-only memories; Multistep manufacturing processes therefor with floating gate characterised by three-dimensional arrangements, e.g. with cells on different height levels with source and drain on different levels, e.g. with sloping channels the channels comprising vertical portions, e.g. U-shaped channels

Abstract

A memory device is provided that includes a memory array including a first array, a first redundant array that is local to the first array, a second array, and a second redundant array that is local to the second array, a cache array including a first cache, a first redundant cache that is local to the first cache, a second cache and a second redundant cache that is local to the second cache, and circuits comprising logic to execute operations. The operations include, responsive to an identification of a defective column in the first array, performing a local defect write repair and responsive to an identification of another defective column in the first array and a determination that the first redundant array is fully utilized, performing a global defect write repair by transferring data into the second redundant array through the first cache and the second redundant cache.

IPC Classes  ?

• G06F 11/00 - Error detection; Error correction; Monitoring
• G06F 11/10 - Adding special bits or symbols to the coded information, e.g. parity check, casting out nines or elevens
• G06F 12/0806 - Multiuser, multiprocessor or multiprocessing cache systems
• G06F 11/20 - Error detection or correction of the data by redundancy in hardware using active fault-masking, e.g. by switching out faulty elements or by switching in spare elements
• G11C 29/04 - Detection or location of defective memory elements
• G06F 11/16 - Error detection or correction of the data by redundancy in hardware

Abstract

Systems, methods, circuits, and apparatus including computer-readable mediums for testing bonding pads in multi-die packages, e.g., chiplet systems. In one aspect, a chiplet system includes multiple integrated circuit devices electrically connected together. The integrated circuit devices include an integrated circuit device including: an integrated circuit, a plurality of first type bonding pads electrically connected to the integrated circuit and electrically connected to at least one other of the integrated circuit devices, and one or more second type bonding pads electrically isolated from the at least one other of the integrated circuit devices. At least one of the plurality of first type bonding pads is configured to be electrically connected to a corresponding one of the one or more second type bonding pads.

IPC Classes  ?

• H01L 21/66 - Testing or measuring during manufacture or treatment
• G01R 31/28 - Testing of electronic circuits, e.g. by signal tracer
• H01L 23/498 - Leads on insulating substrates
• H01L 23/00 - SEMICONDUCTOR DEVICES NOT COVERED BY CLASS - Details of semiconductor or other solid state devices

Abstract

At least one embodiment of the disclosure is directed to a memory circuit having a leakage current blocking mechanism and a memory device having the memory circuit. In an aspect, one embodiment of the disclosure describes a memory circuit which includes not limited to a memory array which includes a first memory cell connected to a first bit line and a second memory cell connected to a second bit line, a pre-charge circuit which is connected to the memory array and includes a first pre-charge device, and a programming circuit which is connected to the pre-charge circuit and comprises a programming transistor which has a higher drive capability than the first pre-charge device so as to drive the first bit line to a ground voltage in response to the first write operation, wherein in response to a first write operation on the first memory cell, a current flow exists between the programming circuit and the first pre-charge device.

IPC Classes  ?

• G11C 11/419 - Read-write [R-W] circuits

Abstract

A 3D AND flash memory device includes a gate stack structure, a channel pillar, a source pillar, a charge storage structure, a first transistor and a second transistor. The gate stack structure is located on a dielectric substrate, wherein the gate stack structure includes a plurality of gate layers and a plurality of insulating layers alternately stacked. The channel pillar extends through the gate stack structure. The source pillar and the drain pillar are disposed in the channel pillar and electrically connected to the channel pillar. The charge storage structure is located between the plurality of gate layers and the channel pillar. The first transistor is located above the gate stack structure and electrically connected to the drain pillar. The second transistor is located above the gate stack structure and electrically connected to the source pillar.

IPC Classes  ?

• H01L 27/11556 - Electrically programmable read-only memories; Multistep manufacturing processes therefor with floating gate characterised by three-dimensional arrangements, e.g. with cells on different height levels with source and drain on different levels, e.g. with sloping channels the channels comprising vertical portions, e.g. U-shaped channels
• H01L 27/11519 - Electrically programmable read-only memories; Multistep manufacturing processes therefor with floating gate characterised by the top-view layout
• H01L 27/11565 - Electrically programmable read-only memories; Multistep manufacturing processes therefor with charge-trapping gate insulators, e.g. MNOS or NROM characterised by the top-view layout
• H01L 27/11582 - Electrically programmable read-only memories; Multistep manufacturing processes therefor with charge-trapping gate insulators, e.g. MNOS or NROM characterised by three-dimensional arrangements, e.g. with cells on different height levels with source and drain on different levels, e.g. with sloping channels the channels comprising vertical portions, e.g. U-shaped channels
• G11C 16/04 - Erasable programmable read-only memories electrically programmable using variable threshold transistors, e.g. FAMOS

Abstract

Methods, systems and apparatus for managing capacitors in memory devices, e.g., three-dimensional (3D) memory devices are provided. In one aspect, a capacitor includes: a first terminal, a second terminal conductively insulated from the first terminal, and a capacitance structure that includes a plurality of layers sequentially stacked together. At least one layer includes: one or more first conductive parts and one or more second conductive parts that are conductively insulated in the layer, the one or more first conductive parts being conductively coupled to the first terminal, the one or more second conductive parts being conductively coupled to the second terminal. The at least one layer is configured such that at least one of the one or more second conductive parts forms at least one subordinate capacitor with at least one adjacent first conductive part.

IPC Classes  ?

• H01L 27/11553 - Electrically programmable read-only memories; Multistep manufacturing processes therefor with floating gate characterised by three-dimensional arrangements, e.g. with cells on different height levels with source and drain on different levels, e.g. with sloping channels
• H01L 27/11529 - Electrically programmable read-only memories; Multistep manufacturing processes therefor with floating gate characterised by the peripheral circuit region of memory regions comprising cell select transistors, e.g. NAND

Abstract

A phase-change material (PCM) includes elements in a composition of germanium Ge from 9 to 14 at %, antimony Sb from 15 to 22 at %, tellurium Te from 44 to 55 at %, silicon Si from 5.5 to 9 at %, and carbon C from 14.5 to 20 at %. It has a crystallization transition temperature higher than 250° C., a crystallization time of less than 200 ns, and an endurance above ten million (107) write cycles. A memory device includes the PCM, and the PCM has a thickness below 100 nm. Memory elements including the PCM are arranged in an array to form a crosspoint memory, or in a stack of two or more arrays to form a 3D crosspoint memory. The memory elements may each include the PCM, a buffer layer, and a selector device.

IPC Classes  ?

• H01L 45/00 - Solid state devices specially adapted for rectifying, amplifying, oscillating, or switching without a potential-jump barrier or surface barrier, e.g. dielectric triodes; Ovshinsky-effect devices; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof
• H01L 27/24 - Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including solid state components for rectifying, amplifying, or switching without a potential-jump barrier or surface barrier

Abstract

A memory device includes a gate stack structure, a channel pillar, a plurality of conductive pillars, and a charge storage structure. The gate stack structure is located over a dielectric substrate, and includes a plurality of gate layers and a plurality of insulating layers stacked alternately with each other. The channel pillar extends through the gate stack structure. Each of the conductive pillars includes a body portion and an extension portion. The body portion extends through the gate stack structure and is electrically connected to the channel pillar. The extension portion is below and is electrically isolated from the channel pillar. The charge storage structure is between the channel pillar and the plurality of gate layers.

IPC Classes  ?

• H01L 27/11582 - Electrically programmable read-only memories; Multistep manufacturing processes therefor with charge-trapping gate insulators, e.g. MNOS or NROM characterised by three-dimensional arrangements, e.g. with cells on different height levels with source and drain on different levels, e.g. with sloping channels the channels comprising vertical portions, e.g. U-shaped channels
• H01L 27/11556 - Electrically programmable read-only memories; Multistep manufacturing processes therefor with floating gate characterised by three-dimensional arrangements, e.g. with cells on different height levels with source and drain on different levels, e.g. with sloping channels the channels comprising vertical portions, e.g. U-shaped channels
• H01L 27/11519 - Electrically programmable read-only memories; Multistep manufacturing processes therefor with floating gate characterised by the top-view layout
• H01L 27/11565 - Electrically programmable read-only memories; Multistep manufacturing processes therefor with charge-trapping gate insulators, e.g. MNOS or NROM characterised by the top-view layout
• H01L 23/528 - Layout of the interconnection structure

Abstract

A semiconductor structure is provided. The semiconductor structure includes a substrate, a stack, active structures connecting structures and isolation layers. The stack is disposed on the substrate. The active structures penetrate through the stack in sub-array regions thereof. A plurality of memory cells are defined by cross points of gate electrodes in the stack and the active structures. The connecting structures penetrate through the stack between the sub-array regions. Each connecting structure includes a first portion, a second portion and a third portion. The first portion is formed as an outermost layer of the connecting structure and formed of polysilicon. The second portion is disposed in a space defined by the first portion and formed of amorphous silicon. The third portion is disposed on the second portion and formed of amorphous silicon. The isolation layers are disposed between sidewalls of the stack and the connecting structures.

IPC Classes  ?

• H01L 27/11582 - Electrically programmable read-only memories; Multistep manufacturing processes therefor with charge-trapping gate insulators, e.g. MNOS or NROM characterised by three-dimensional arrangements, e.g. with cells on different height levels with source and drain on different levels, e.g. with sloping channels the channels comprising vertical portions, e.g. U-shaped channels
• H01L 21/768 - Applying interconnections to be used for carrying current between separate components within a device

Abstract

Systems, methods, circuits, and apparatuses for managing integrated circuits in memory devices are provided. In one aspect, an integrated circuit includes: a latch circuit including a latch and a sensing transistor coupled to the latch, and a compensation circuit coupled to the sensing transistor. The sensing transistor includes a gate terminal coupled to a sensing node and an additional terminal coupled to the compensation circuit, and the compensation circuit is configured to apply a control voltage to the additional terminal to compensate for a variation of a threshold voltage of the sensing transistor.

IPC Classes  ?

• G11C 11/06 - Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using magnetic elements using multi-aperture plates in which each individual aperture forms a storage element
• G11C 7/06 - Sense amplifiers; Associated circuits
• G11C 7/08 - Control thereof

Abstract

A transistor structure including a substrate, a gate structure, first pocket doped regions, second pocket doped regions, and source/drain extension regions, and source/drain regions is provided. The gate structure is located on the substrate. The first pocket doped regions are located in the substrate aside the gate structure. A dopant of the first pocket doped region includes a group IVA element. The second pocket doped regions are located in the substrate aside the gate structure. A depth of the second pocket doped region is greater than a depth of the first pocket doped region. The source/drain extension regions are located in the first pocket doped regions. The source/drain regions are located in the substrate aside the gate structure. The source/drain extension region is located between the source/drain region and the gate structure.

IPC Classes  ?

• H01L 29/08 - Semiconductor bodies characterised by the shapes, relative sizes, or dispositions of the semiconductor regions with semiconductor regions connected to an electrode carrying current to be rectified, amplified, or switched and such electrode being part of a semiconductor device which comprises three or more electrodes
• H01L 29/78 - Field-effect transistors with field effect produced by an insulated gate
• H01L 29/66 - Types of semiconductor device
• H01L 21/265 - Bombardment with wave or particle radiation with high-energy radiation producing ion implantation
• H01L 29/167 - Semiconductor bodies characterised by the materials of which they are formed including, apart from doping materials or other impurities, only elements of Group IV of the Periodic System in uncombined form further characterised by the doping material

Abstract

A memory device includes a high density or 3D data memory and a 3D reference memory. The reference memory is used to generate a reference signal used to sense data in the data memory. Conversion circuitry converts signals from one memory cell or a group of memory cells in the reference memory into a reference signal. The reference signal is applied to a sense amplifier to sense data stored in a selected memory cell in the data memory.

IPC Classes  ?

• G11C 11/4091 - Sense or sense/refresh amplifiers, or associated sense circuitry, e.g. for coupled bit-line precharging, equalising or isolating
• G11C 11/4074 - Power supply or voltage generation circuits, e.g. bias voltage generators, substrate voltage generators, back-up power, power control circuits
• G11C 11/408 - Address circuits
• G11C 11/4094 - Bit-line management or control circuits
• G11C 11/4099 - Dummy cell treatment; Reference voltage generators
• G11C 16/10 - Programming or data input circuits
• G11C 16/28 - Sensing or reading circuits; Data output circuits using differential sensing or reference cells, e.g. dummy cells

Abstract

A capacitor string structure, a memory device and a charge pump circuit thereof are provided. The capacitor string structure includes a plurality of conductive plates. The conductive plates are disposed in the memory device. The conductive plates are stacked to each other, and respectively form a plurality of word lines of the memory device, where two neighbored conductive plates form a capacitor.

IPC Classes  ?

• G11C 5/14 - Power supply arrangements
• H01L 23/528 - Layout of the interconnection structure
• H01L 23/522 - Arrangements for conducting electric current within the device in operation from one component to another including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
• G11C 5/06 - Arrangements for interconnecting storage elements electrically, e.g. by wiring

Abstract

An analog content-address memory (analog CAM) having approximation matching and an operation method thereof are provided. The analog CAM includes an inputting circuit, at least one analog CAM cell and an outputting circuit. The inputting circuit is configured to provide an inputting data. The analog CAM cell is connected to the inputting circuit and receives the inputting data. The analog CAM cell has a mild swing match curve whose highest point corresponds to a stored data. A segment from the highest point of the mild swing match curve to a lowest point of the mild swing match curve corresponds to at least three data values. The outputting circuit is connected to the analog CAM cell and receives a match signal from the analog CAM cell. The outputting circuit outputs a match approximation level according to the match signal.

IPC Classes  ?

• G11C 15/04 - Digital stores in which information comprising one or more characteristic parts is written into the store and in which information is read-out by searching for one or more of these characteristic parts, i.e. associative or content-addressed stores using semiconductor elements

Abstract

A compute in memory device comprises a memory array including a plurality of data lines for parallel access to memory array data, and an input/output interface. Data path circuits between the memory array and the input/output interface include a page buffer, each buffer cell of the page buffer including a plurality of storage elements. A plurality of computation circuits is provided connected to respective buffer cells. The computation circuits execute a function of data in the storage elements of the respective buffer cells and can be configured in parallel to generate a results data page including operation results for the plurality of buffer cells. A data analysis circuit is connected to the data path circuits to execute a function of the results data page to generate an analysis result. A register can be provided to store the analysis result accessible via the input/output interface.

IPC Classes  ?

• G11C 7/10 - Input/output [I/O] data interface arrangements, e.g. I/O data control circuits, I/O data buffers

Abstract

A memory array is provided and including a plurality of bit lines and a plurality word lines; a plurality of memory cell units, arranged at cross points of the plurality of bit lines and the plurality of word lines; a bit line switch circuit, coupled to the plurality of memory cell units and being operated to select one of the plurality of bit lines; a word line switch circuit, coupled to the plurality of memory cell units and being operated to select one of the plurality of word lines; and a voltage clamper circuit, provided in at least one of the word line switch circuit and the bit line switch circuit.

IPC Classes  ?

• G11C 13/00 - Digital stores characterised by the use of storage elements not covered by groups , , or

Abstract

A memory device and a word line driver thereof are provided. The word line driver includes a first word line signal generator, a second word line signal generator, a first voltage generator, and a second voltage generator. The first word line signal generator selects one of a first voltage and a second voltage to generate a first word line signal according a control signal. The second word line signal generator selects one of a third voltage and a fourth voltage to generate a second word line signal according the control signal. The first voltage generator provides the second voltage, and the second voltage generator provides the fourth voltage, where the first voltage generator is independent to the second voltage generator.

IPC Classes  ?

• G11C 11/34 - Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices
• G11C 8/00 - Arrangements for selecting an address in a digital store
• G11C 16/08 - Address circuits; Decoders; Word-line control circuits
• G11C 16/04 - Erasable programmable read-only memories electrically programmable using variable threshold transistors, e.g. FAMOS
• G11C 16/14 - Circuits for erasing electrically, e.g. erase voltage switching circuits
• G11C 16/26 - Sensing or reading circuits; Data output circuits
• G11C 16/30 - Power supply circuits

Abstract

A memory device includes a command decoder that implements security logic to detect a command sequence to read a security region of a memory array with continuous encrypted data and to output/input specific contexts for the data. Output/input of specific contexts can be during a dummy cycle to achieve greater performance. A host interfacing can, for example, execute a single command to both get the encrypted data and specific contexts that were used to encrypt the data. Our technology can implement transferring data on the system bus in ciphertext and encrypted by a different Nonce or a different session key than used in a previous transfer operation. In this way, data will be represented with different ciphertext on the bus at different sessions; thereby defending against a replay attack.

IPC Classes  ?

• G06F 3/06 - Digital input from, or digital output to, record carriers

Abstract

A memory device includes a dielectric substrate, an interlayer structure, a plurality of channel pillars, a plurality of charge storage structures, a plurality of slit structures and an assistance structure. The dielectric substrate includes an array region and an iso region aside the array region. The interlayer structure is disposed in the array region and the iso region. The channel pillars penetrate through the interlayer structure in the array region. The charge storage structures are disposed between the interlayer structure and the plurality of channel pillars. The slit structures are disposed between the plurality of channel pillars, penetrate through the interlayer structure in the array region, and divide the interlayer structure into a plurality of blocks. The assistance structure is arranged in the iso region. The assistance structure includes at least one dummy slit structure having an extension direction different from an extension direction of the plurality of slit structures.

IPC Classes  ?

• H01L 27/11582 - Electrically programmable read-only memories; Multistep manufacturing processes therefor with charge-trapping gate insulators, e.g. MNOS or NROM characterised by three-dimensional arrangements, e.g. with cells on different height levels with source and drain on different levels, e.g. with sloping channels the channels comprising vertical portions, e.g. U-shaped channels
• H01L 27/1157 - Electrically programmable read-only memories; Multistep manufacturing processes therefor with charge-trapping gate insulators, e.g. MNOS or NROM characterised by the memory core region with cell select transistors, e.g. NAND
• H01L 27/11556 - Electrically programmable read-only memories; Multistep manufacturing processes therefor with floating gate characterised by three-dimensional arrangements, e.g. with cells on different height levels with source and drain on different levels, e.g. with sloping channels the channels comprising vertical portions, e.g. U-shaped channels
• H01L 27/11524 - Electrically programmable read-only memories; Multistep manufacturing processes therefor with floating gate characterised by the memory core region with cell select transistors, e.g. NAND
• H01L 27/11519 - Electrically programmable read-only memories; Multistep manufacturing processes therefor with floating gate characterised by the top-view layout
• H01L 27/11565 - Electrically programmable read-only memories; Multistep manufacturing processes therefor with charge-trapping gate insulators, e.g. MNOS or NROM characterised by the top-view layout

Abstract

A sensing module, a memory device, and a sensing method are provided to perform a read operation so that the un-programmed/programmed state of a memory cell is identified. The sensing module includes a sensing amplifier and a current sink, and both are electrically connected to the memory cell. The sensing amplifier generates a sensing current and identifies the un-programmed/programmed state of the memory cell accordingly. The current sink receives a reference current being equivalent to the summation of the sensing current and a cell current flowing through the memory cell. The reference current is constant, and the sensing current is changed with the cell current. The cell current is generated based on a high read voltage and a low read voltage applied to the memory cell. The sensing current is higher if the memory cell is un-programmed, and the sensing current is lower if the memory cell is programmed.

IPC Classes  ?

• G11C 7/08 - Control thereof
• G11C 17/14 - Read-only memories programmable only once; Semi-permanent stores, e.g. manually-replaceable information cards in which contents are determined by selectively establishing, breaking or modifying connecting links by permanently altering the state of coupling elements, e.g. PROM
• G11C 7/06 - Sense amplifiers; Associated circuits

Abstract

A routing pattern is provided. The routing pattern includes a first routing region, a second routing region and an interconnection region. The first routing region includes a plurality of first conductive lines extending along a first direction. The plurality of first conductive lines has a first pitch along a second direction perpendicular to the first direction. The second routing region includes a plurality of second conductive lines extending along the first direction. The plurality of second conductive lines has a second pitch along the second direction, and the second pitch is approximately equal to the first pitch. The interconnection region includes two body parts and a connecting part connecting to the body parts. The body parts are disposed separately along the first direction. A width of the connecting part along the second direction is smaller than a width of the body parts along the second direction.

IPC Classes  ?

• H01L 23/528 - Layout of the interconnection structure

Abstract

A memory device for artificial intelligence calculation includes a memory structure, a controller chip, and a processer chip. The memory structure includes a first memory chip, and a stack of second memory chips, in which a memory density of each of the second memory chips is greater than a memory density of the first memory chip. The controller chip is electrically connected to the first memory chip and the second memory chips. The processer chip is electrically connected to the controller chip.

IPC Classes  ?

• H01L 27/11524 - Electrically programmable read-only memories; Multistep manufacturing processes therefor with floating gate characterised by the memory core region with cell select transistors, e.g. NAND
• G11C 16/04 - Erasable programmable read-only memories electrically programmable using variable threshold transistors, e.g. FAMOS
• H01L 23/528 - Layout of the interconnection structure
• H01L 23/522 - Arrangements for conducting electric current within the device in operation from one component to another including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
• H01L 27/11551 - Electrically programmable read-only memories; Multistep manufacturing processes therefor with floating gate characterised by three-dimensional arrangements, e.g. with cells on different height levels
• H01L 27/1157 - Electrically programmable read-only memories; Multistep manufacturing processes therefor with charge-trapping gate insulators, e.g. MNOS or NROM characterised by the memory core region with cell select transistors, e.g. NAND
• H01L 27/11578 - Electrically programmable read-only memories; Multistep manufacturing processes therefor with charge-trapping gate insulators, e.g. MNOS or NROM characterised by three-dimensional arrangements, e.g. with cells on different height levels
• H01L 27/108 - Dynamic random access memory structures

Abstract

The application provides a sense amplifier and an operation method thereof. The operation method for the sense amplifier includes: during a first phase, initializing a first sensing input voltage and a second input sensing voltage; and recording a first sensing output voltage and a second sensing output voltage of a previous round by charges stored in a plurality of transistors of the sense amplifier; during a second phase, sampling the first sensing output voltage and the second sensing output voltage of a current round as a plurality of transit points; during a first sub-phase of a third phase, amplifying a voltage difference between an input signal and a first reference voltage; and during a second sub-phase of the third phase, pulling the first sensing output voltage and the second sensing output voltage into a full-swing voltage range, and recording charges to the transistors of the sense amplifier.

IPC Classes  ?

• G11C 16/16 - Circuits for erasing electrically, e.g. erase voltage switching circuits for erasing blocks, e.g. arrays, words, groups
• G11C 11/4091 - Sense or sense/refresh amplifiers, or associated sense circuitry, e.g. for coupled bit-line precharging, equalising or isolating
• G11C 11/4096 - Input/output [I/O] data management or control circuits, e.g. reading or writing circuits, I/O drivers or bit-line switches
• G11C 11/4074 - Power supply or voltage generation circuits, e.g. bias voltage generators, substrate voltage generators, back-up power, power control circuits
• G11C 11/4099 - Dummy cell treatment; Reference voltage generators

Abstract

A memory device includes a memory interposer, memory array regions, logic chips, and interconnection lines. The memory array regions are in the memory interposer, in which the memory array regions include at least one memory having NAND architecture. The logic chips are over the memory interposer. The interconnection lines connect the logic chips to each other, and connect the logic chips to the memory array regions.

IPC Classes  ?

• H01L 27/11524 - Electrically programmable read-only memories; Multistep manufacturing processes therefor with floating gate characterised by the memory core region with cell select transistors, e.g. NAND
• G11C 16/04 - Erasable programmable read-only memories electrically programmable using variable threshold transistors, e.g. FAMOS
• H01L 23/528 - Layout of the interconnection structure
• H01L 23/522 - Arrangements for conducting electric current within the device in operation from one component to another including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
• H01L 27/11551 - Electrically programmable read-only memories; Multistep manufacturing processes therefor with floating gate characterised by three-dimensional arrangements, e.g. with cells on different height levels
• H01L 27/1157 - Electrically programmable read-only memories; Multistep manufacturing processes therefor with charge-trapping gate insulators, e.g. MNOS or NROM characterised by the memory core region with cell select transistors, e.g. NAND
• H01L 27/11578 - Electrically programmable read-only memories; Multistep manufacturing processes therefor with charge-trapping gate insulators, e.g. MNOS or NROM characterised by three-dimensional arrangements, e.g. with cells on different height levels
• H01L 27/108 - Dynamic random access memory structures

Abstract

Provided is a memory device including a stack structure. The stack structure is in the memory array region of a substrate. The stack structure comprises a plurality of first insulating layers and a plurality of conductive layers stacked alternately on each other. A first staircase structure and a second staircase structure are located in a first staircase region and a second staircase region of the substrate respectively. The second staircase structure has steps descending from an upper layer proximal to the memory array region to a lower layer distal to the memory array region. Block slits and zone slit are disposed over the substrate in the second staircase region. The block slits divide the stack structure, the first staircase structure and the second staircase structure into memory blocks. The zone slits divide one of the memory blocks into a plurality of zones separately within the memory blocks.

IPC Classes  ?

• G11C 8/14 - Word line organisation; Word line lay-out
• H10B 41/10 - Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates characterised by the top-view layout
• H10B 41/27 - Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates characterised by three-dimensional arrangements, e.g. with cells on different height levels with source and drain on different levels, e.g. with sloping channels the channels comprising vertical portions, e.g. U-shaped channels
• H10B 41/35 - Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates characterised by the memory core region with a cell select transistor, e.g. NAND
• H10B 41/41 - Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates characterised by the peripheral circuit region of a memory region comprising a cell select transistor, e.g. NAND
• H10B 43/10 - EEPROM devices comprising charge-trapping gate insulators characterised by the top-view layout
• H10B 43/27 - EEPROM devices comprising charge-trapping gate insulators characterised by three-dimensional arrangements, e.g. with cells on different height levels with source and drain on different levels, e.g. with sloping channels the channels comprising vertical portions, e.g. U-shaped channels
• H10B 43/35 - EEPROM devices comprising charge-trapping gate insulators characterised by the memory core region with cell select transistors, e.g. NAND
• H10B 43/40 - EEPROM devices comprising charge-trapping gate insulators characterised by the peripheral circuit region

Abstract

A three-dimensional memory structure is provided and including a memory array, including a first and a second sub-arrays, each having a first selection line, plural word lines, and a second selection line; a connection structure, including plural connection areas, and at least one of extension structures of the first selection line, the plural of word lines, and the second selection line is coupled to a corresponding connection area of the plurality of connection areas; a pass gate set, arranged under the connection structure and between the first and the second sub-arrays, the pass gate set including plural pass gates, and, the word lines and the second selection line, and the pass gates are respectively coupled to the corresponding connection areas; and a drive circuit, coupled to the pass gate set, and disposed under the connection structure.

IPC Classes  ?

• G11C 7/18 - Bit line organisation; Bit line lay-out

Abstract

An IC is provided and includes a memory array, an address register holding at least one address of a securely stored file and configured to output three or more addresses of the securely stored filed and computation-in-memory (CIM) logic coupled with the memory array. The CIM logic is configured to perform a majority function on three or more bits of the securely stored file, wherein the three or more bits are redundantly stored in three or more different locations in the memory array and wherein the three locations are associated with the three or more addresses in the memory array.

IPC Classes  ?

• G06F 11/07 - Responding to the occurrence of a fault, e.g. fault tolerance
• G06F 11/10 - Adding special bits or symbols to the coded information, e.g. parity check, casting out nines or elevens
• G06F 3/06 - Digital input from, or digital output to, record carriers

Abstract

A memory device includes a stacked structure including conductive layers and first insulating layers alternately stacked along a first direction; a first array region; a second array region; and a connection region disposed between the first array region and the second array region, and including a staircase region, an unprocessed region, a bottom isolating member and a common wall, wherein the unprocessed region extends along the first direction and has an isolating sidewall, the isolating sidewall electrically isolates the conductive layers from the unprocessed region, the staircase region is adjacent to a first side of the unprocessed region, and the common wall is adjacent to a second side of the unprocessed region. A portion of the conductive layers continuously extends in the staircase region, the first array region, the common wall and the second array region.

IPC Classes  ?

• H01L 23/535 - Arrangements for conducting electric current within the device in operation from one component to another including internal interconnections, e.g. cross-under constructions
• H01L 27/11582 - Electrically programmable read-only memories; Multistep manufacturing processes therefor with charge-trapping gate insulators, e.g. MNOS or NROM characterised by three-dimensional arrangements, e.g. with cells on different height levels with source and drain on different levels, e.g. with sloping channels the channels comprising vertical portions, e.g. U-shaped channels
• H01L 27/11573 - Electrically programmable read-only memories; Multistep manufacturing processes therefor with charge-trapping gate insulators, e.g. MNOS or NROM characterised by the peripheral circuit region

Abstract

A 3D AND flash memory device includes a gate stack structure, a channel stack structure, a source pillar and a drain pillar, and a plurality of charge storage structures. The gate stack structure is located on the dielectric substrate. The gate stack structure includes a plurality of gate layers and a plurality of insulating layers stacked alternately with each other. The channel stack structure extends through the gate stack structure. The channel stack structure includes a plurality of channel rings spaced apart from each other. The source pillar and the drain pillar are located in the channel stack structure and are respectively electrically connected to the plurality of channel rings. The plurality of charge storage structures are located between the plurality of gate layers and the plurality of channel rings.

IPC Classes  ?

• H01L 27/11582 - Electrically programmable read-only memories; Multistep manufacturing processes therefor with charge-trapping gate insulators, e.g. MNOS or NROM characterised by three-dimensional arrangements, e.g. with cells on different height levels with source and drain on different levels, e.g. with sloping channels the channels comprising vertical portions, e.g. U-shaped channels

Abstract

A memory device, which includes a first driving circuit, a second driving circuit, a sensing circuit and an in-memory search (IMS) array. Memory units of the in-memory search array are arranged as a plurality of horizontal rows and vertical columns. Control terminal of each the memory unit in the same vertical column is coupled to the first driving circuit through a word line. The memory units of the same vertical column are connected in series and coupled to the second driving circuit through a bit line, and coupled to the sensing circuit through a source line. Every 2N adjacent memory units in the same vertical column are arranged as a memory unit to store an encoded data of 2N bits corresponding to an original data of M bits, where N and M are positive integers, and N is greater than or equal to two.

IPC Classes  ?

• G11C 16/34 - Determination of programming status, e.g. threshold voltage, overprogramming or underprogramming, retention
• G11C 16/10 - Programming or data input circuits
• G11C 16/26 - Sensing or reading circuits; Data output circuits
• G11C 16/08 - Address circuits; Decoders; Word-line control circuits
• G11C 16/30 - Power supply circuits

Abstract

A semiconductor structure is provided. The semiconductor structure includes a staircase structure including a first stair layer and a second stair layer on the first stair layer. The first stair layer includes a first conductive film. The semiconductor structure includes a first landing pad disposed on the first conductive film. The first landing pad has a first pad sidewall facing toward the second stair layer, and a second pad sidewall opposite to the first pad sidewall. The second pad sidewall includes an inclined sidewall portion.

IPC Classes  ?

• H01L 21/768 - Applying interconnections to be used for carrying current between separate components within a device
• H01L 21/02 - Manufacture or treatment of semiconductor devices or of parts thereof
• H01L 21/3065 - Plasma etching; Reactive-ion etching
• H01L 21/48 - Manufacture or treatment of parts, e.g. containers, prior to assembly of the devices, using processes not provided for in a single one of the groups

Abstract

A memory structure and a manufacturing method for the same are provided. The memory structure includes a memory element, a spacer structure, and an upper element structure. The memory element includes a lower memory layer and an upper memory layer on the lower memory layer. The spacer structure is on a sidewall surface of the lower memory layer. The upper element structure is electrically connected on the upper memory layer. A recess is defined by a lower surface of the upper element structure, an upper surface of the lower memory layer and a sidewall surface of the upper memory layer.

IPC Classes  ?

• H01L 27/24 - Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including solid state components for rectifying, amplifying, or switching without a potential-jump barrier or surface barrier
• H01L 45/00 - Solid state devices specially adapted for rectifying, amplifying, oscillating, or switching without a potential-jump barrier or surface barrier, e.g. dielectric triodes; Ovshinsky-effect devices; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof

Abstract

An operation method of memory device, comprising: selecting a target block for performing an error correction operation; reading the target block row by row; transmitting the read data to an error correction circuit; and checking and correcting read data to generate a corrected data.

IPC Classes  ?

• G06F 12/00 - Accessing, addressing or allocating within memory systems or architectures
• G06F 11/10 - Adding special bits or symbols to the coded information, e.g. parity check, casting out nines or elevens
• G06F 3/06 - Digital input from, or digital output to, record carriers

Abstract

A semiconductor structure includes a substrate, a common source plane disposed on the substrate, a plurality of memory cells vertically disposed on the substrate and electrically connected to the common source plane, a common source line disposed on the substrate and electrically connected to the common source plane, and an isolation pillar. The common source line extends along a first direction and has a first segment and a second segment. The isolation pillar interposes the first segment and the second segment of the common source line.

IPC Classes  ?

• H01L 27/11578 - Electrically programmable read-only memories; Multistep manufacturing processes therefor with charge-trapping gate insulators, e.g. MNOS or NROM characterised by three-dimensional arrangements, e.g. with cells on different height levels
• H01L 27/11519 - Electrically programmable read-only memories; Multistep manufacturing processes therefor with floating gate characterised by the top-view layout
• H01L 27/11551 - Electrically programmable read-only memories; Multistep manufacturing processes therefor with floating gate characterised by three-dimensional arrangements, e.g. with cells on different height levels
• H01L 27/11565 - Electrically programmable read-only memories; Multistep manufacturing processes therefor with charge-trapping gate insulators, e.g. MNOS or NROM characterised by the top-view layout

Abstract

A memory device and an operation method thereof are provided. The operation method includes: when a read operation or a write-verify operation is completed, during a word line voltage lowering phase, synchronously applying a plurality of different gradually lowering signal line reference voltages to a plurality of ground select lines and a plurality of string select lines, wherein values of the different gradually lowering signal line reference voltages are corresponding to a plurality of signal line positions of the ground select lines and the string select lines.

IPC Classes  ?

• G11C 16/34 - Determination of programming status, e.g. threshold voltage, overprogramming or underprogramming, retention
• G11C 16/04 - Erasable programmable read-only memories electrically programmable using variable threshold transistors, e.g. FAMOS
• G11C 16/10 - Programming or data input circuits
• G11C 16/24 - Bit-line control circuits
• G11C 16/28 - Sensing or reading circuits; Data output circuits using differential sensing or reference cells, e.g. dummy cells
• G11C 16/30 - Power supply circuits
• G11C 16/08 - Address circuits; Decoders; Word-line control circuits

Abstract

An integrated circuit includes a memory and peripheral circuits with a temperature sensor used to automatically adjust operating voltages. The temperature sensor includes a first circuit to generate a temperature-dependent voltage (TDV) that is dependent on an operating temperature of the integrated circuit, and a second circuit to generate a plurality of temperature reference voltages, based on or more codes. One or more comparator circuits compare individual ones of the plurality of reference voltages with the TDV, to generate one or more comparison signals that are indicative of the operating temperature of the integrated circuit.

IPC Classes  ?

• G11C 16/30 - Power supply circuits
• G11C 16/04 - Erasable programmable read-only memories electrically programmable using variable threshold transistors, e.g. FAMOS

Abstract

Provided are a 3D flash memory and an array layout thereof. The 3D flash memory includes a gate stack structure, a annular channel pillar, a first source/drain pillar, a second source/drain pillar and a charge storage structure. The gate stack structure is disposed on a dielectric base and includes a plurality of gate layers electrically insulated from each other. The annular channel pillar is disposed on the dielectric base and penetrates through the gate stack structure. The first source/drain pillar and the second source/drain pillar are disposed on the dielectric base, are located within the channel pillar and penetrate through the gate stack structure. The first source/drain pillar and the second source/drain pillar are separated from each other and are each connected to the channel pillar. The charge storage structure is disposed between each of the plurality of gate layers and the channel pillar.

IPC Classes  ?

• H10B 43/27 - EEPROM devices comprising charge-trapping gate insulators characterised by three-dimensional arrangements, e.g. with cells on different height levels with source and drain on different levels, e.g. with sloping channels the channels comprising vertical portions, e.g. U-shaped channels
• H01L 23/528 - Layout of the interconnection structure
• H10B 43/10 - EEPROM devices comprising charge-trapping gate insulators characterised by the top-view layout

Abstract

A semiconductor structure and a method for manufacturing the same are provided. The semiconductor structure includes a conductive pillar having a sidewall and a multi-layer isolation structure on the sidewall of the conductive pillar. The multi-layer isolation structure includes a first isolation layer and a second isolation layer. The first isolation layer is between the conductive pillar and the second isolation layer. The first isolation layer includes protrusions extending toward the second isolation layer. A density of the first isolation layer is different from that of the second isolation layer.

IPC Classes  ?

• H01L 23/535 - Arrangements for conducting electric current within the device in operation from one component to another including internal interconnections, e.g. cross-under constructions
• H01L 27/11582 - Electrically programmable read-only memories; Multistep manufacturing processes therefor with charge-trapping gate insulators, e.g. MNOS or NROM characterised by three-dimensional arrangements, e.g. with cells on different height levels with source and drain on different levels, e.g. with sloping channels the channels comprising vertical portions, e.g. U-shaped channels

Abstract

A memory device includes a dielectric substrate, a conductive layer, a gate stack structure, a plurality of ring-shaped slits and a plurality of inner slits. The conductive layer is located on the dielectric substrate. The gate stack structure is located on a first part of the conductive layer. The dielectric layer is located on the gate stack structure and a second part of the conductive layer. The plurality of ring-shaped slits extends through the dielectric layer, the gate stack structure and the conductive layer to define a plurality of tiles. The plurality of inner slits are arranged in the ring-shaped slits to define a plurality of blocks in each ring-shaped slit. A height of the plurality of inner slits is the same as a height of the plurality of ring-shaped slits.

IPC Classes  ?

• H01L 27/11582 - Electrically programmable read-only memories; Multistep manufacturing processes therefor with charge-trapping gate insulators, e.g. MNOS or NROM characterised by three-dimensional arrangements, e.g. with cells on different height levels with source and drain on different levels, e.g. with sloping channels the channels comprising vertical portions, e.g. U-shaped channels

Abstract

Systems, devices, methods, and circuits for managing secure writes in semiconductor devices. In one aspect, a semiconductor device includes a memory array and logic circuitry coupled to the memory array. The logic circuitry is configured to execute a secure write operation in the memory array in response to receiving encrypted information. The encrypted information includes at least one of information of data to be written, an option code, or multiple addresses in the memory array, the option code specifying a way of writing the data on at least one of the multiple addresses in the memory array.

IPC Classes  ?

• G06F 3/06 - Digital input from, or digital output to, record carriers

Abstract

A memory device and an associated control method are provided. The memory device includes a non-volatile memory array and a memory control circuit. The non-volatile memory array includes M secured memory zones. The memory control circuit is electrically connected to the non-volatile memory array. The memory control circuit provides a set of mapping information and searches a request key in the set of mapping information. The set of mapping information represents correspondences between N access keys and the M secured memory zones. The memory control circuit acquires at least one of the M secured memory zones if the request key is one of the N access keys, and performs an access command to the at least one of the M secured memory zones. M and N are positive integers.

IPC Classes  ?

• G06F 3/06 - Digital input from, or digital output to, record carriers