Abstract

The present disclosure discloses a memory access interface device. A clock generation circuit generates reference signals. A transmitter transmits an output command and address signal to a memory device according to the reference signals. A signal training circuit executes a training process in a training mode that includes steps outlined below. A training signal is generated such that the training signal is transmitted as the output command and address signal. The training signal and the data signal generated by the memory device are compared to generate a comparison result indicating whether the data signal matches the training signal. The comparison result is stored. The clock generation circuit is controlled to modify a phase of at least one of the reference signals to be one of a plurality of under-test phases to execute a new loop of the training process until all the under-test phases are trained.

IPC Classes  ?

• G06F 1/12 - Synchronisation of different clock signals
• G06F 1/08 - Clock generators with changeable or programmable clock frequency
• G06F 1/10 - Distribution of clock signals

Abstract

The present disclosure discloses a memory access interface device. A clock generation circuit generates reference clock signals. Each of access signal transmission circuits each includes a duty cycle adjusting circuit, a duty cycle detection circuit, a frequency division circuit and an asynchronous first-in-first-out circuit. The duty cycle adjusting circuit performs duty cycle adjustment on one of the reference clock signals according to a duty cycle detection signal to generate an output clock signal having a duty cycle. The duty cycle detection circuit detects a variation of the duty cycle to generate the duty cycle detection signal. The frequency division circuit divides a frequency of the output clock signal to generate a read clock signal. The asynchronous first-in-first-out circuit receives an access signal from a memory access controller and outputs an output access signal according to the read clock signal to access the memory device accordingly.

IPC Classes  ?

• G11C 16/32 - Timing circuits
• G11C 16/26 - Sensing or reading circuits; Data output circuits

Abstract

A test device is configured to test an on-chip clock controller having a debug function. The test device includes a scan chain and a test circuit. The scan chain includes N flip-flop circuit(s), each of which stores a first input signal as a storage signal, then stores a second input signal as the storage signal or keeps the current storage signal according to an input clock, and then output the storage signal. Since the first and second input signals are different, the outputted storage signal indicates whether the flip-flop circuit stores the second input signal or keeps the current storage signal according to the input clock under predetermined test setting, and indicates whether circuits under test (CUTs) for transmitting the input clock operate normally. The test circuit outputs an observation clock of the on-chip clock controller or an independent clock as the input clock according to the predetermined test setting.

IPC Classes  ?

• G01R 31/317 - Testing of digital circuits

Abstract

A radio frequency receiving circuit includes a first amplification circuit, an oscillation circuit, a frequency mixing and amplification circuit and a dividing circuit. The first amplification circuit is configured to amplify an input signal so as to generate an amplified input signal. The oscillation circuit is configured to provide a local oscillation signal. The frequency mixing and amplification circuit is configured to mix and amplify the amplified input signal according to the local oscillation signal. The dividing circuit is configured to form a dividing loop at a preset frequency for the amplified input signal according to the local oscillation signal when the dividing circuit is driven. A chip including the radio frequency receiving circuit and a main circuit is also provided. The main circuit is configured to drive the dividing circuit when the second input signal is determined to include a signal of the preset frequency.

IPC Classes  ?

• H04B 1/18 - Input circuits, e.g. for coupling to an antenna or a transmission line
• H04B 1/16 - Circuits

Abstract

A computing device includes: a storage circuit, for storing an arbitration interframe space (AIFS) time, at least one expected value of at least one backoff time, a preamble time, a short interframe space (SIFS) time and an acknowledgement (ACK) time; a first computing circuit, for computing a payload time according to a packet length and a packet rate; a second computing circuit, coupled to the storage circuit and the first computing circuit, for computing at least one packet transmission time according to the AIFS time, the at least one expected value of the at least one backoff time, the preamble time, the SIFS time, the ACK time and the payload time; and a third computing circuit, coupled to the second computing circuit, for computing a total packet transmission time according to the at least one packet transmission time and an estimated packet error rate.

IPC Classes  ?

• H04L 1/20 - Arrangements for detecting or preventing errors in the information received using signal-quality detector
• H04L 1/1867 - Arrangements specially adapted for the transmitter end

Abstract

An audio signal amplifying device processes an input signal to provide an output signal for a balanced headphone. The device includes a signal detection circuit, a voltage supply circuit, and an amplifying circuit. The signal detection circuit detects the variation in the input signal to generate a detection result. The voltage supply circuit outputs one of multiple voltages as a supply voltage according to the detection result; when the detection result indicates the amplitude of the input signal satisfying a first condition, the supply voltage is a first voltage; when the detection result indicates the amplitude of the input signal satisfying a second condition, the supply voltage is a second voltage lower than the first voltage; and the amplitude satisfying the first condition is greater than the amplitude satisfying the second condition. The amplifying circuit generates the output signal according to the input signal based on the supply voltage.

IPC Classes  ?

• H03F 1/02 - Modifications of amplifiers to raise the efficiency, e.g. gliding Class A stages, use of an auxiliary oscillation

Abstract

A low dropout regulator includes output terminal circuit and amplifier. The output terminal circuit is configured to generate output voltage according to input voltage and is configured to generate feedback voltage according to the output voltage. The amplifier is configured to generate control voltage to the output terminal circuit according to reference voltage and the feedback voltage, so as to adjust the output voltage, wherein the amplifier includes input stage circuit, current mirror circuit and filter circuit. The input stage circuit is configured to receive the reference voltage and the feedback voltage to generate a differential output. The filter circuit is configured to filter the input voltage to generate dependent current related to noise of the input voltage on the current mirror circuit, wherein the current mirror circuit is configured to output the control voltage according to the differential output and the dependent current.

IPC Classes  ?

• G05F 1/575 - Regulating voltage or current wherein the variable actually regulated by the final control device is dc using semiconductor devices in series with the load as final control devices characterised by the feedback circuit
• G05F 1/595 - Regulating voltage or current wherein the variable actually regulated by the final control device is dc using semiconductor devices in series with the load as final control devices including plural semiconductor devices as final control devices for a single load semiconductor devices connected in series

Abstract

A method for responding to a command is adapted for a storage device. The method for responding to a command includes following steps of: sequentially receiving a first command and a second command by a bridge of the storage device from a host; executing the first command and the second command to generate a status completion signal or a status error signal by the bridge; and detecting an error state of at least one of the first command and the second command to execute a response mode or an idle mode by the bridge according to the error state so as to respond to the host.

IPC Classes  ?

• G06F 11/07 - Responding to the occurrence of a fault, e.g. fault tolerance
• G06F 13/40 - Bus structure

Abstract

A memory management method includes the following operations: setting a first data value of first frame data to a first value to assign a first decoder in a plurality of decoders that corresponds to the first value to decode the first frame data, setting a second data value of the first frame data to a second value, and outputting the first frame data to an application layer; based on a control of the application layer, setting a third data value of the first frame data to a third value, in order to assign a first video output transmitter in a plurality of video output transmitters to output the first frame data; and determining whether to clear a storage space in a memory that stores the first frame data according to the first data value, the second data value, and the third data value.

IPC Classes  ?

• H04N 19/423 - Methods or arrangements for coding, decoding, compressing or decompressing digital video signals - characterised by implementation details or hardware specially adapted for video compression or decompression, e.g. dedicated software implementation characterised by memory arrangements
• H04N 19/172 - Methods or arrangements for coding, decoding, compressing or decompressing digital video signals using adaptive coding characterised by the coding unit, i.e. the structural portion or semantic portion of the video signal being the object or the subject of the adaptive coding the unit being an image region, e.g. an object the region being a picture, frame or field

Abstract

An integrated transformer is provided. The integrated transformer includes a first inductor and second inductors. The first inductor includes a first winding having a first outer turn and a second winding having a second outer turn. The second inductor includes a third winding having a third outer turn and a fourth winding having a fourth outer turn. The first and third outer turns substantially overlap, and the second and fourth outer turns substantially overlap. The first and second outer turns are connected to each other through a first segment and a second segment that together form a crossing structure, and the third and fourth outer turns are connected to each other through a third segment and a fourth segment that together form a crossing structure. The first and third segments are in the first metal layer, while the second and fourth segments are in the second metal layer.

IPC Classes  ?

• H01F 27/28 - Coils; Windings; Conductive connections

Abstract

An integrated circuit includes a power-on reset (POR) circuit, a watchdog timer, a first AND gate and a power management control circuit. The POR circuit is used to receive an input voltage to generate a POR signal and generate a clock signal. The watchdog timer is used to generate a timeout signal according to the clock signal when the POR signal has an enabling voltage, the clock signal enabling generation of timeout pulses in the timeout signal at predetermined time intervals. The first AND gate including a first input terminal for receiving the POR signal; a second input terminal for receiving the timeout signal; and an output terminal for outputting a reset signal according to the POR signal and the timeout signal. The power management control circuit is used to reset an output current in response to a reset pulse in the reset signal.

IPC Classes  ?

• H03K 17/22 - Modifications for ensuring a predetermined initial state when the supply voltage has been applied
• H03K 19/20 - Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits characterised by logic function, e.g. AND, OR, NOR, NOT circuits

Abstract

An all-digital duty cycle corrector and a method for correcting a duty cycle of an output clock are provided. The all-digital duty cycle corrector includes a duty cycle adjustment circuit, an asynchronous sampler, a counter and a correction control circuit. The duty cycle adjustment circuit performs duty cycle adjustment on an input clock to generate the output clock according to a digital control code. The asynchronous sampler performs asynchronous sampling on the output clock to generate N sampling results at N time points, respectively. The counter counts a number of first logic values among the N sampling results to generate a counting result. The correction control circuit compares the counting result with a reference value to generate a comparison result, and selectively adjusts the digital control code according to the comparison result, in order to correct the duty cycle of the output clock.

IPC Classes  ?

• H03K 5/156 - Arrangements in which a continuous pulse train is transformed into a train having a desired pattern

Abstract

The present disclosure discloses an image enlarging apparatus having deep learning mechanism. A deep learning circuit includes an image downsizing circuit, an image characteristic analyzing circuit, a weighting reallocating circuit and an image upsizing circuit. The image downsizing circuit downsizes an input image to generate a downsized image. The image characteristic analyzing circuit analyzes the downsized image according to image characteristics to generate categorized images. The weighting reallocating circuit performs weighting reallocating on the categorized images according to image weighting parameters corresponding to the image characteristics to generate weighting reallocated images. The image upsizing circuit upsizes the weighting reallocated images to generate adjusted images. A concatenating circuit concatenates the input image and the adjusted images to generate concatenated images. A super-resolution enlarging circuit performs super-resolution enlarging on the concatenated images to generate an output image.

IPC Classes  ?

• G06T 3/40 - Scaling of a whole image or part thereof

Abstract

A charge pump filtering circuit includes a charge pump circuit and a filter circuit. The charge pump circuit includes a first switch and a second switch. The first switch and the second switch are coupled at a first node and are coupled between a power terminal and a ground terminal. The filter circuit includes a first capacitor, a second capacitor, and a first voltage switching circuit. The first capacitor is coupled between the first node and the ground terminal. The second capacitor is coupled between the first voltage switching circuit and the first node.

IPC Classes  ?

• H03L 7/089 - Automatic control of frequency or phase; Synchronisation using a reference signal applied to a frequency- or phase-locked loop - Details of the phase-locked loop concerning mainly the frequency- or phase-detection arrangement including the filtering or amplification of its output signal the phase or frequency detector generating up-down pulses
• H03L 7/091 - Automatic control of frequency or phase; Synchronisation using a reference signal applied to a frequency- or phase-locked loop - Details of the phase-locked loop concerning mainly the frequency- or phase-detection arrangement including the filtering or amplification of its output signal the phase or frequency detector using a sampling device
• H03L 7/099 - Automatic control of frequency or phase; Synchronisation using a reference signal applied to a frequency- or phase-locked loop - Details of the phase-locked loop concerning mainly the controlled oscillator of the loop

Abstract

A time-interleaved analog to digital converter includes first and second capacitor array circuits, first and second transfer circuits, a fine converter circuitry, and an encoder circuit. The capacitor array circuits sample an input signal and generate first residues according to first quantization signals. The first and second transfer circuits transfer first and second residues respectively. The fine converter circuitry performs a noise shaping signal conversion on the first and second residues to generate a second quantization signal. A turn-on time of the corresponding first transfer circuit is determined based on the coarse conversion corresponding to a first capacitor array circuit and the noise shaping signal conversion corresponding to a second capacitor array circuit to selectively bring forward a start time of the noise shaping signal conversion. The encoder circuit generates a digital output according to the first and the second quantization signals.

IPC Classes  ?

• H03M 1/12 - Analogue/digital converters
• H03M 1/06 - Continuously compensating for, or preventing, undesired influence of physical parameters

Abstract

An electronic device and a method for performing clock gating in the electronic device are provided. The electronic device includes at least one function circuit, a device under test (DUT) circuit and at least one gating circuit. The function circuit is configured to operate according to at least one primary clock, and the DUT circuit is configured to operate according to at least one secondary clock. In addition, the clock gating circuit is configured to control whether to enable the primary clock according to at least one primary enable signal, and control whether to enable the secondary clock according to the primary enable signal and a secondary enable signal.

IPC Classes  ?

• G01R 31/317 - Testing of digital circuits

Abstract

A media docking device includes an input module, an output module and a processing module. The input module is electrically connected to a media source device for receiving media data. The output module is electrically connected to a media play device. The processing module determines if an instruction is received from the media source device or a remote device. If the instruction is not received, the processing module transfers the media data to the output module to transmit to the media play device. If the instruction is received, the processing module limits a transmission of the media data according to the instruction, such that the media data will not be completely played by the media play device.

IPC Classes  ?

• H04N 21/454 - Content filtering, e.g. blocking advertisements
• G06F 3/14 - Digital output to display device
• H04N 21/4363 - Adapting the video stream to a specific local network, e.g. a IEEE 1394 or Bluetooth® network

Abstract

A time-interleaved analog to digital converter includes capacitor array circuits, first and second transfer circuits, a fine converter circuitry, a control circuitry, and an encoder circuit. The capacitor array circuits sample an input signal and generate first residues according to first quantization signals. The first and second transfer circuits transfer first and second residues respectively. The fine converter circuitry performs a signal conversion on the first and second residues according to a conversion control signal to generate a second quantization signal. The control circuitry generates a count signal according to the second quantization signal, and outputs the count signal as a switching signal. The capacitor array circuits generate the second residues in response to the signal conversion, and adjusts those residues according to the switching signal. The encoder circuit generates a digital output according to a corresponding first quantization signal and the second quantization signal.

IPC Classes  ?

• H03M 1/50 - Analogue/digital converters with intermediate conversion to time interval
• H03M 1/12 - Analogue/digital converters

Abstract

A time-interleaved analog to digital converter (ADC) includes capacitor array circuits, a flash ADC, first and second circuits, a converter, and an encoder circuit. The capacitor array circuits sample an input signal and generate first residue signals according to first quantization signals. The flash ADC samples the input signal and generates the first quantization signals. The first circuits transfer the first residue signals from the capacitor array circuits. The converter performs a signal conversion according to the first and the second residue signals to generate a second quantization signal. The second circuits transfer second residue signals to the converter. The capacitor array circuits further generate the second residue signal in response to the signal conversion. The encoder circuit generates a digital output according to one of the first quantization signals and the second quantization signals.

IPC Classes  ?

• H03M 1/08 - Continuously compensating for, or preventing, undesired influence of physical parameters of noise

Abstract

The present disclosure discloses a firmware update method having firmware update troubleshooting mechanism. Partial data included in firmware data is used as test data to perform a test process to write the test data to a firmware storage terminal by using a control interface of a processing terminal according to the setting of access parameters, read the written test data from the firmware storage terminal through the control interface and compare the written test data and the test data to generate a comparison result. A parameter adjustment process is performed when the comparison result indicates a mismatching condition such that the test process is performed again and the parameter adjustment process is further performed. When the comparison result indicates a matching condition, the firmware data is transmitted to the processing terminal and is written to the firmware storage terminal by using the control interface.

IPC Classes  ?

• G06F 11/36 - Preventing errors by testing or debugging of software

Abstract

A media docking device includes an input circuit, an output circuit and a processing circuit. The input circuit is electrically connected to a media source device for receiving media data. The output circuit is electrically connected to a media play device. The processing circuit is electrically connected to the input circuit and the output circuit. The processing circuit determines if a verification procedure is passed. If the verification procedure is passed, the processing circuit transfers the media data to the media play device. If the verification procedure is not passed, the processing circuit limits a transmission of the media data, such that the media data will not be completely played by the media play device.

IPC Classes  ?

• G06F 21/32 - User authentication using biometric data, e.g. fingerprints, iris scans or voiceprints
• G06F 1/16 - Constructional details or arrangements
• G06F 13/38 - Information transfer, e.g. on bus
• G06F 13/42 - Bus transfer protocol, e.g. handshake; Synchronisation
• G06F 21/31 - User authentication

Abstract

An image outputting device includes a sensing circuit for generating an image signal according to a configuration; a processing circuit, coupled to the sensing circuit, for performing an image processing on the image signal according to the configuration to generate an image processing result; and a controlling circuit, coupled to the sensing circuit and the processing circuit, for setting the configuration and entering an operating system after setting the configuration.

IPC Classes  ?

• G06V 10/56 - Extraction of image or video features relating to colour
• G06T 5/00 - Image enhancement or restoration
• G06T 9/00 - Image coding
• H04N 9/69 - Circuits for processing colour signals for controlling the amplitude of colour signals, e.g. automatic chroma control circuits for modifying the colour signals by gamma correction

Abstract

The address conversion system includes a storage device, a memory bus, and a processor. The processor is configured to execute the following steps: generating a real buffer on the storage device; generating a fake buffer in a fake capacity of the storage device by a fake buffer algorithm; establishing a coupling relationship between the real buffer and the fake buffer through a coupling algorithm by the coupler of the memory bus; receiving a compressed data from a first device by the real buffer; when a second device wants to read the fake buffer, the coupler guides the second device to the real buffer through the coupling relationship for reading; transmitting the compressed data of the real buffer to the coupler by the memory bus; decompressing the compressed data into a decompressed data by the coupler; and transmitting the decompressed data to the second device by the memory bus.

IPC Classes  ?

• G06F 13/16 - Handling requests for interconnection or transfer for access to memory bus
• G06F 13/40 - Bus structure

Abstract

A method of duty cycle adjustment includes conditionally inverting an input clock into a conditionally inverted clock; and adjusting a duty cycle of the conditionally inverted clock in one direction in accordance with an integer that represents an amount of duty cycle adjustment, using an uneven clock buffer and a plurality of uneven clock multiplexers that are cascaded and incrementally activated as a value of the integer increments.

IPC Classes  ?

• H03K 7/08 - Duration or width modulation
• H03K 3/017 - Adjustment of width or dutycycle of pulses
• H03K 17/687 - Electronic switching or gating, i.e. not by contact-making and -breaking characterised by the use of specified components by the use, as active elements, of semiconductor devices the devices being field-effect transistors
• H03K 17/693 - Switching arrangements with several input- or output-terminals, e.g. multiplexers, distributors
• H03K 19/20 - Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits characterised by logic function, e.g. AND, OR, NOR, NOT circuits
• H03M 7/16 - Conversion to or from unit-distance codes, e.g. Gray code, reflected binary code

Abstract

A programmable secure management device and a control method for performing key forwarding between secure devices are provided. The programmable secure management device includes a key generating device, a key accepting device and a forwarding controller circuit, wherein the forwarding controller circuit is electrically coupled to the key generating device and the key accepting device. The key generating device is configured to output a source key, and the key accepting device is configured to accept a destination key, wherein the forwarding controller circuit is configured to receive a forwarding command from a host device outside the programmable secure management device, to allow the host device to request the forwarding controller circuit via the forwarding command for taking the source key as the destination key to be loaded in the key accepting device.

IPC Classes  ?

• H04L 9/08 - Key distribution

Abstract

A method for fast starting up a television display function and a television system are provided. In the method, when a television device is powered on, the television system operated in the television device performs a hardware initialization and a fast start-up procedure. In the fast start-up procedure, a set of picture-quality parameters is loaded to the television system from a storage circuit. Display parameters of the television device are configured according to the picture-quality parameters, accordingly, a display of the television device starts to display a picture. The picture can be produced from image signals received through an external source such as a high-definition multimedia interface (HDMI) or a Display Port, a type-C interface, or other sources of the television device. The picture-quality parameters are collected and stored in the storage circuit during operation of the television system after the operating system booting procedure is completed.

IPC Classes  ?

• H04N 21/443 - OS processes, e.g. booting an STB, implementing a Java virtual machine in an STB or power management in an STB
• H04N 21/4363 - Adapting the video stream to a specific local network, e.g. a IEEE 1394 or Bluetooth® network

Abstract

A self-loopback radio transmitter having a transmitter with a modulator configured to up-convert a first baseband signal into a first RF (radio frequency) signal in accordance with a first LO (local oscillator) signal, and a power amplifier configured to receive the first RF signal and output a second RF signal to be emitted by an antenna and a third RF signal to be looped back, wherein the third RF signal is magnetically coupled from the second RF signal; and a loopback network having a shielded serial inductor configured to receive the third RF signal and output a fourth RF signal, and a demodulator configured to down-convert the fourth RF signal into a second baseband signal in accordance with a second LO signal, wherein the shielded serial inductor has a serial inductor of spiral topology and a coil laid out on a lower metal layer.

IPC Classes  ?

• H04B 1/04 - Circuits
• H03F 3/24 - Power amplifiers, e.g. Class B amplifiers, Class C amplifiers of transmitter output stages

Abstract

A circuit layout for improving the power supply rejection ratio includes a radio frequency (RF) choke and an inductor. The RF choke receives a supply voltage and includes: a first choke coil positioned in an ultra-thick metal (UTM) layer, the coil including a first choke electrode; and a second choke coil positioned in a redistribution layer (RDL), the coil including a second choke electrode. The inductor belongs to a main circuit and includes: a primary-side coil surrounding the first choke coil in the UTM layer, and being coupled to the first/second chock electrode and the main circuit's signal input circuit; and a secondary-side coil surrounding the first choke coil in the UTM layer and surrounding the second choke coil in the RDL, and being used for signal output. The inductor and the RF choke jointly form mutual induction to suppress the noise of the supply voltage.

IPC Classes  ?

• G05F 1/46 - Regulating voltage or current wherein the variable actually regulated by the final control device is dc

Abstract

A signal transmission device has an initial signal stabilization mechanism and includes a driver and a bypass circuit. The driver includes: a first current source circuit coupled between a high voltage terminal and a first node; a second current source circuit coupled between a low voltage terminal and a second node; and a driving circuit coupled between the first node and the second node. The driving circuit outputs an output signal according to a first bias voltage of the first node, a second bias voltage of the second node, and an input signal during a signal output operation. The bypass circuit is coupled between the first node and the second node. In the beginning of the signal output operation, the bypass circuit conducts a current from the first node to the second node to assist in establishing the first and second bias voltages and thereby stabilize the output signal.

IPC Classes  ?

• H04L 25/02 - Baseband systems - Details
• H03K 17/687 - Electronic switching or gating, i.e. not by contact-making and -breaking characterised by the use of specified components by the use, as active elements, of semiconductor devices the devices being field-effect transistors
• H03K 19/0185 - Coupling arrangements; Interface arrangements using field-effect transistors only

Abstract

A video switching method includes the following operations: decoding second video data during a period when a panel is driven to display image content corresponding to first video data to generate frame parameter data and image data; and processing the image data according to the frame parameter data in response to a control command to drive the panel to display image content corresponding to the second video data.

IPC Classes  ?

• H04N 19/423 - Methods or arrangements for coding, decoding, compressing or decompressing digital video signals - characterised by implementation details or hardware specially adapted for video compression or decompression, e.g. dedicated software implementation characterised by memory arrangements
• H04N 5/268 - Signal distribution or switching
• H04N 19/172 - Methods or arrangements for coding, decoding, compressing or decompressing digital video signals using adaptive coding characterised by the coding unit, i.e. the structural portion or semantic portion of the video signal being the object or the subject of the adaptive coding the unit being an image region, e.g. an object the region being a picture, frame or field
• H04N 19/30 - Methods or arrangements for coding, decoding, compressing or decompressing digital video signals using hierarchical techniques, e.g. scalability
• H04N 19/44 - Decoders specially adapted therefor, e.g. video decoders which are asymmetric with respect to the encoder
• H04N 19/463 - Embedding additional information in the video signal during the compression process by compressing encoding parameters before transmission

Abstract

A waterproof-state recognition and processing method and device is applicable to a capacitive touch screen. The method and device can differentiate a water-affected region from a water-free region, and allow a touch-responding operation for the water-free region when the water-affected region exists. The method includes: scanning the screen to obtain data of multiple channels of the screen; determining whether any of the data reaches a waterproof threshold; when any of the data reaches the waterproof threshold, performing a waterproof-state process; when none of the data reaches the waterproof threshold, determining whether any of the data reaches a finger-touch threshold; when any of the data reaches the finger-touch threshold, performing a finger-touch-state process; and when none of the data reaches the finger-touch threshold, performing an idle-state process.

IPC Classes  ?

• G06F 3/041 - Digitisers, e.g. for touch screens or touch pads, characterised by the transducing means
• G06F 3/01 - Input arrangements or combined input and output arrangements for interaction between user and computer
• G06F 3/044 - Digitisers, e.g. for touch screens or touch pads, characterised by the transducing means by capacitive means

Abstract

An electronic device includes a processor circuit, a frequency-domain-to-time-domain conversion circuit, a transmitter circuit, a hybrid circuit, a receiver circuit, and a time-domain-to-frequency-domain conversion circuit. The processor circuit generates a frequency-domain transmitting signal. The frequency-domain-to-time-domain conversion circuit converts the frequency-domain transmitting signal into a first time-domain transmitting signal. The transmitter circuit generates a second time-domain transmitting signal. The hybrid circuit includes an echo noise cancelling path and an echo noise path. When the echo noise cancelling path is turned off, the processor circuit receives a first frequency-domain receiving signal. When the echo noise cancelling path is turned on, the processor circuit receives a second frequency-domain receiving signal. The processor circuit determines an echo noise cancelling ability of the hybrid circuit according to the first frequency-domain receiving signal and the second frequency-domain receiving signal.

IPC Classes  ?

• H04L 5/14 - Two-way operation using the same type of signal, i.e. duplex

Abstract

A memory device includes a resistor and a controller chip. The controller chip includes a first controller, a second controller, a first set of input/output (I/O) circuits, a second set of I/O circuits, a first calibration circuit, a second calibration circuit, and an arbitration circuit. The first controller transmits a first controller calibration request. The second controller transmits a second controller calibration request. The arbitration circuit instructs the first calibration circuit to perform a first controller calibration on the first set of I/O circuits using the resistor in response to the first controller calibration request, and instructs the second calibration circuit to perform a second controller calibration on the second set of I/O circuits using the resistor in response to the second controller calibration request. A first time interval of performing the first controller calibration and a second time interval of performing the second controller calibrations are non-overlapping.

IPC Classes  ?

• G11C 7/10 - Input/output [I/O] data interface arrangements, e.g. I/O data control circuits, I/O data buffers

Abstract

A clock management circuit and a clock management method are used for managing an operating clock of a processor circuit, and the processor circuit changes the level of a state signal according to an interrupt signal. The clock management circuit includes a delay circuit for delaying a wake-up interrupt to generate a delayed wake-up interrupt; and a clock control circuit for generating the operating clock according to a reference clock, generating the wake-up interrupt according to the state signal, and adjusting the frequency of the operating clock according to the delayed wake-up interrupt.

IPC Classes  ?

• G06F 1/08 - Clock generators with changeable or programmable clock frequency

Abstract

The present disclosure discloses an amplifier circuit having reset mechanism. A pair of upper-half branches are electrically coupled between a first supply voltage and a pair of differential output terminals, are symmetrical and each includes at least one P-type transistor. A pair of lower-half branches are electrically coupled between the pair of differential output terminals and a second supply voltage, are symmetrical and each includes at least one N-type transistor. The P-type transistors and the N-type transistors are categorized into transistor groups that perform differential signal receiving process in turn in an interlaced manner under an interlaced input mode and perform reset signal receiving process to be turned on and be AC grounded when the differential signal receiving process is not performed such that the differential output terminals generate differential outputs.

IPC Classes  ?

• H03F 3/45 - Differential amplifiers
• H03K 5/24 - Circuits having more than one input and one output for comparing pulses or pulse trains with each other according to input signal characteristics, e.g. slope, integral the characteristic being amplitude

Abstract

A network control method is configured to balance the loading of a plurality of processes. The method includes obtaining an IP address of a packet; deleting a portion of bits of the IP address to generate a series according to an IP address entropy distribution; performing a hash function to the series to generate a hash value; performing a modulo operation to the hash value to obtain a remainder; and assigning the packet to a processor of the plurality of processes corresponding to the remainder.

IPC Classes  ?

• H04L 61/5007 - Internet protocol [IP] addresses

Abstract

The present disclosure provides an USB device and a system type determining method thereof. The system type determining method includes: determining, by the USB device, whether an USB host transmit at least one of an HID interrupt signal and an UAC1 status interrupt signal; and determining, by the USB device, a system type of the USB host according to the result of determining whether the USB host transmit at least one of the HID interrupt signal and the UAC1 status interrupt signal.

IPC Classes  ?

• G06F 13/42 - Bus transfer protocol, e.g. handshake; Synchronisation

Abstract

An image display method, comprising the following steps: receiving an image signal from a graphics processor by an image processor, wherein the image signal is configured to drive a display panel to display a main image; enlarging a target area in the main image to form a first enlarged image according to an enlargement command; modifying the first enlarged image into a non-rectangular image to use the non-rectangular image as a second enlarged image; and driving the display panel to display the main image and the second enlarged image simultaneously by the image processor, wherein the second enlarged image is overlapped on the main image.

IPC Classes  ?

• G06T 3/40 - Scaling of a whole image or part thereof
• G06T 7/62 - Analysis of geometric attributes of area, perimeter, diameter or volume
• G06T 7/68 - Analysis of geometric attributes of symmetry

Abstract

The present disclosure discloses an image processing apparatus having lens color-shading correction mechanism. A first and a second calibration circuits perform lens color-shading correction on an input image according to a first and a second calibration parameters to generate a first and a second calibrated images. A first and a second statistic circuits perform statistic on the first and the second calibrated images to generate a first and a second statistic results. A calibration operation circuit adjusts the second calibration parameters when the first calibrated image is determined to have a color-shading condition according to the first statistic result and when the second calibrated image is determined to not satisfy a color-shading criteria, and sets the second calibration parameters as the first calibration parameters when the second calibration parameters satisfies the color-shading criteria such that the first calibrated image generated by the first calibration circuit is outputted as an output calibrated image.

IPC Classes  ?

• H04N 25/611 - Correction of chromatic aberration
• G06T 5/00 - Image enhancement or restoration
• G06T 7/80 - Analysis of captured images to determine intrinsic or extrinsic camera parameters, i.e. camera calibration
• G06T 7/90 - Determination of colour characteristics
• G06V 10/56 - Extraction of image or video features relating to colour
• G06V 10/75 - Image or video pattern matching; Proximity measures in feature spaces using context analysis; Selection of dictionaries

Abstract

The present disclosure discloses an image processing circuit having output timing adjustment mechanism. An image enhancement circuit performs image enhancement on an input image to generate an enhanced image. A first image processing path and a second image processing path respectively perform processing on the enhanced image having a first timing and the enhanced image having a second timing to generate a first output image and a second output image. A timing control circuit adjusts the timing of the enhanced image according to requirements of the first image processing path and the second image processing path to generate the enhanced image having the first timing and the enhanced image having the second timing. A first image output interface outputs the first output image. A second image output interface outputs the second output image.

IPC Classes  ?

• G06T 5/00 - Image enhancement or restoration
• G06T 3/40 - Scaling of a whole image or part thereof

Abstract

A neural network system and an operation method for a neural network system are provided. The neural network system includes at least one edge device and a server. Each edge device stores a neural network architecture. The neural network architecture includes at least one operator and a model identifier, and the at least one operator of the neural network architecture stored in the each edge device includes an operator identifier. The server is connected to the each edge device. The each edge device is configured to, upon being powered on, transmit the operator identifier of each operator to the server to request the server to return parameters for the each operator; receive the parameters of the each operator and combine the parameters of the each operator with the neural network architecture to obtain a neural network model; and execute a predetermined task based on the neural network model.

IPC Classes  ?

• G06N 3/04 - Architecture, e.g. interconnection topology

Abstract

A first packet flow and a second packet flow support a first protocol, a third packet flow and a fourth packet flow support a second protocol, and a priority of the first protocol is lower than a priority of the second protocol. The first packet flow and the third packet flow are transmitted from a first ingress port to a first egress port. The second packet flow and the fourth packet flow are transmitted from a second ingress port to a second egress port. When the packet processing device is in a congested state, a bandwidth modulator performs a first suppression process on the first packet flow at the first ingress port, and the bandwidth modulator performs a second suppression process on the second packet flow at the second egress port or on the third packet flow at the first ingress port.

IPC Classes  ?

• H04L 47/12 - Avoiding congestion; Recovering from congestion
• H04L 47/24 - Traffic characterised by specific attributes, e.g. priority or QoS

Abstract

A signal compensation device includes a first receiving circuit, a second receiving circuit, a first buffer, a second buffer, a third buffer, and a processing circuit. The first receiving circuit receives a first video signal from a first video source. The second receiving circuit receives a second video signal from a second video source, wherein both the first video signal and the second video signal correspond to a same program. The first buffer stores a first transport stream (TS) packet group corresponding to the first video signal. The second buffer stores a second TS packet group corresponding to the second video signal. The processing circuit dynamically stores a first TS packet of the first TS packet group or a second TS packet of the second TS packet group to the third buffer according to a predetermined source in response to TS packet status.

IPC Classes  ?

• H04L 49/9047 - Buffering arrangements including multiple buffers, e.g. buffer pools
• H04L 65/752 - Media network packet handling adapting media to network capabilities
• H04N 21/462 - Content or additional data management e.g. creating a master electronic program guide from data received from the Internet and a Head-end or controlling the complexity of a video stream by scaling the resolution or bit-rate based on the client capabi
• H04N 21/44 - Processing of video elementary streams, e.g. splicing a video clip retrieved from local storage with an incoming video stream or rendering scenes according to MPEG-4 scene graphs
• H04N 21/438 - Interfacing the downstream path of the transmission network originating from a server, e.g. retrieving MPEG packets from an IP network
• H04N 21/239 - Interfacing the upstream path of the transmission network, e.g. prioritizing client requests

Abstract

A method and apparatus for simulating breakdown of an electronic component are provided. The method includes: when a terminal of an equivalent circuit model receives test charges, pulling up a voltage level of a first node of the equivalent circuit model; when the voltage level of the first node reaches a first threshold, turning on a first voltage controlled switch to pull up a voltage level of a second node of the equivalent circuit model; when the voltage level of the second mode reaches a second threshold, turning on a second voltage controlled switch to pull down a voltage level of the terminal to a holding voltage level to simulate snapback breakdown of the electronic component; and turning on a third voltage controlled switch to pull down the voltage level of the second node to turn off the second voltage controlled switch, thereby simulating second breakdown of the electronic component.

IPC Classes  ?

• H02H 9/04 - Emergency protective circuit arrangements for limiting excess current or voltage without disconnection responsive to excess voltage
• G06F 30/367 - Design verification, e.g. using simulation, simulation program with integrated circuit emphasis [SPICE], direct methods or relaxation methods

Abstract

An audio real-time processing system, an audio real-time processing program product and method for training speech analysis model are provided. The speech analysis model is firstly trained to obtain, from an original audio, mask information which is used to mask the original audio to get a target audio. The system obtains a plurality of analyzed audio according to the target audio and the original audio, obtains repeated audio section according to the plurality of the analyzed and output the repeated audio section.

IPC Classes  ?

• G10L 21/0272 - Voice signal separating
• G10L 21/0356 - Speech enhancement, e.g. noise reduction or echo cancellation by changing the amplitude for synchronising with other signals, e.g. video signals

Abstract

An image processing method includes receiving an image frame, retrieving luminance information and chrominance information from the image frame, respectively, encoding the luminance information to generate an encoded luminance frame, encoding the chrominance information to generate an encoded chrominance frame, writing the encoded luminance frame to a first memory portion of a memory, and writing the encoded chrominance frame to a second memory portion of the memory. The image processing method further includes reading the encoded luminance frame from the first memory portion and decoding the encoded luminance frame to generate decoded luminance information, and reading the encoded chrominance frame from the second memory portion and decoding the encoded chrominance frame to generate decoded chrominance information.

IPC Classes  ?

• H04N 19/186 - Methods or arrangements for coding, decoding, compressing or decompressing digital video signals using adaptive coding characterised by the coding unit, i.e. the structural portion or semantic portion of the video signal being the object or the subject of the adaptive coding the unit being a colour or a chrominance component
• H04N 19/423 - Methods or arrangements for coding, decoding, compressing or decompressing digital video signals - characterised by implementation details or hardware specially adapted for video compression or decompression, e.g. dedicated software implementation characterised by memory arrangements
• H04N 19/172 - Methods or arrangements for coding, decoding, compressing or decompressing digital video signals using adaptive coding characterised by the coding unit, i.e. the structural portion or semantic portion of the video signal being the object or the subject of the adaptive coding the unit being an image region, e.g. an object the region being a picture, frame or field
• H04N 9/77 - Circuits for processing the brightness signal and the chrominance signal relative to each other, e.g. adjusting the phase of the brightness signal relative to the colour signal, correcting differential gain or differential phase

Abstract

An image processing circuit includes a first buffer circuit, a first selector circuit, a processor circuit, a second buffer circuit, and an assigning circuit. The first buffer circuit receives pixels in a sliding window of an image. The first selector circuit outputs the pixels according to a mode signal. The processor circuit performs a first filtering process on the pixels to generate first processed pixels. The assigning circuit transmits the first processed pixels to a back-end circuit or transmits the first processed pixels to the second buffer circuit. When the assigning circuit transmits the first processed pixels to the second buffer circuit, the first selector circuit transm its the first processed pixels to the processor circuit, the processor circuit performs a second filtering process on the first processed pixels to generate second processed pixels, and the assigning circuit transmits the second processed pixels to the back-end circuit.

IPC Classes  ?

• G06T 1/20 - Processor architectures; Processor configuration, e.g. pipelining
• G06T 5/00 - Image enhancement or restoration
• G06T 5/20 - Image enhancement or restoration by the use of local operators

Abstract

A system on a chip (SoC) with a Universal Asynchronous Receiver/Transmitter (UART) interface includes a UART interface circuit, a detection circuit, and a control circuit. The UART interface circuit includes: a plurality of UART signal pads for receiving and transmitting signals; and a UART voltage pad for receiving an external operating voltage. The detection circuit is configured to detect the magnitude of the external operating voltage and thereby generate a detection result. The control circuit is configured to determine setting of a supply voltage for the plurality of UART signal pads according to the detection result. The control circuit makes the setting of the supply voltage be compatible with the external operating voltage according to the detection result, wherein the external operating voltage is a lower first voltage or a higher second voltage, and the first lower voltage is equal to an internal device operating voltage of the SoC.

IPC Classes  ?

• G06F 13/38 - Information transfer, e.g. on bus

Abstract

A television includes a remote control, a receiving element, a speaker, a speech analysis model, and a processor. The processor analyzes video sound to get a repeated audio section after receiving a volume adjustment command from the remote control. Then, the speaker outputs the repeated audio. So that, according to user needs, the television adjusts the video sound before outputting.

IPC Classes  ?

• G10L 15/22 - Procedures used during a speech recognition process, e.g. man-machine dialog
• H04R 3/00 - Circuits for transducers

Abstract

An image processing device includes an image encoder, a memory and an image decoder. The image encoder receives an input image frame, retrieves luminance information and chrominance information from the input image frame, respectively, encodes the luminance information to generate an encoded luminance frame, and encodes the chrominance information to generate an encoded chrominance frame. The memory includes a first memory portion, a second memory portion and a third memory portion. The first memory portion stores the encoded luminance frame, and the second memory portion or the third memory portion stores the encoded chrominance frame. The image decoder reads the encoded luminance frame from the first memory portion to perform decoding, and reads the encoded chrominance frame from the second memory portion or the third memory portion for decoding.

IPC Classes  ?

• H04N 19/423 - Methods or arrangements for coding, decoding, compressing or decompressing digital video signals - characterised by implementation details or hardware specially adapted for video compression or decompression, e.g. dedicated software implementation characterised by memory arrangements
• H04N 19/186 - Methods or arrangements for coding, decoding, compressing or decompressing digital video signals using adaptive coding characterised by the coding unit, i.e. the structural portion or semantic portion of the video signal being the object or the subject of the adaptive coding the unit being a colour or a chrominance component
• H04N 19/172 - Methods or arrangements for coding, decoding, compressing or decompressing digital video signals using adaptive coding characterised by the coding unit, i.e. the structural portion or semantic portion of the video signal being the object or the subject of the adaptive coding the unit being an image region, e.g. an object the region being a picture, frame or field

Abstract

A ball grid array and a configuration method of the same are provided. The ball grid array is formed on a printed circuit board and includes an inner row region and an outer row region. The inner row region includes a plurality of first solder balls that are arranged by a first ball pitch. The first solder balls respectively correspond to a plurality of predetermined vias, and the first ball pitch is determined according to a minimum trace width that is relative to a via size of the predetermined vias. The outer row region surrounds the inner row region and includes a plurality of second solder balls that are arranged by a second ball pitch. The second ball pitch is smaller than the first ball pitch.

IPC Classes  ?

• H01L 23/498 - Leads on insulating substrates
• H05K 3/34 - Assembling printed circuits with electric components, e.g. with resistor electrically connecting electric components or wires to printed circuits by soldering
• H01L 23/00 - SEMICONDUCTOR DEVICES NOT COVERED BY CLASS - Details of semiconductor or other solid state devices

Abstract

An image processing method and a display device are provided. The image processing method is suitable for the display device. The display device includes an image processor and a panel module. The image processing method includes: when the image processor receives a notification signal from a source to switch the display format, the image processor stores a current image frame in a memory. The image processor provides the current image frame to the panel module, so that the panel module displays the current image frame. The image processor is re-handshaking with the source and the panel module to receive a new image frame provided by the source, and the image processor transmits the new image frame to the panel module, so that the panel module displays the new image frame.

IPC Classes  ?

• G09G 3/20 - Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix
• G09G 3/34 - Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix by control of light from an independent source

Abstract

An inductor device includes an 8-shaped inductor and a ring-type wire. The ring-type wire is disposed around an outer side of the 8-shaped inductor. The 8-shaped inductor includes an input terminal and a center-tapped terminal. The input terminal of the 8-shaped inductor is located on a first side of the inductor device, and the center-tapped terminal is located on a second side of the inductor device. The ring-type wire includes an input terminal and a ground terminal. The input terminal of the ring-type wire is located on the first side of the inductor device, and the ground terminal is located on the second side of the inductor device. The input terminal of the ring-type wire is coupled to the input terminal of the 8-shaped inductor.

IPC Classes  ?

• H01F 27/29 - Terminals; Tapping arrangements
• H04B 15/02 - Reducing interference from electric apparatus by means located at or near the interfering apparatus
• H04B 1/04 - Circuits

Abstract

A SSB (single sideband) mixer is configured to mix a first signal with a second signal, both the first signal and the second signal being a four-phase signal, and comprises eight gated inverters, each receiving a respective phase of the first signal and conditionally outputting a respective current in accordance with a control of a respective phase of the second signal, wherein currents output from the eight gated inverters are summed to establish a third signal that is a two-phase signal.

IPC Classes  ?

• H03D 7/16 - Multiple frequency-changing
• H03D 7/14 - Balanced arrangements

Abstract

A digital filtering method is applicable to a photoplethysmography (PPG) device. The PPG device samples a mixed-light signal M time(s) to obtain M mixed-light digital value(s), and samples an ambient-light signal N time(s) to obtain N ambient-light digital value(s), wherein each mixed-light digital value includes a controllable-light component and an ambient-light component. The method includes: preparing a digital filter whose filter order is (M+N−1); using the digital filter to multiply the M mixed-light digital value(s) by M coefficient(s) respectively and thereby generate M value(s); using the digital filter to multiply N ambient-light digital value(s) by N coefficient(s) respectively and thereby generate N value(s); and using the digital filter to add up the M value(s) and the N value(s) and thereby generate an output value.

IPC Classes  ?

• A61B 5/00 - Measuring for diagnostic purposes ; Identification of persons
• A61B 5/024 - Measuring pulse rate or heart rate

Abstract

A video processing method for performing partial highlighting with the aid of hand gesture detection and an associated SoC are provided. The SoC includes a person recognition circuit, a hand gesture detection circuit, a sound detection circuit and a processing circuit. The person recognition circuit obtains image data from an image capturing device, and performs person recognition on the image data to generate a recognition result. The hand gesture detection circuit performs hand gesture detection on hand gesture image data to generate a hand gesture detection result. The sound detection circuit receives multiple sound signals from multiple microphones, and determines a voice characteristic value of a main sound. The processing circuit determines a specific region in the image data according to the recognition result, the hand gesture detection result, and the voice characteristic value, and processes the image data to highlight the specific region.

IPC Classes  ?

• G06V 40/20 - Movements or behaviour, e.g. gesture recognition
• G06V 40/10 - Human or animal bodies, e.g. vehicle occupants or pedestrians; Body parts, e.g. hands
• G06V 10/25 - Determination of region of interest [ROI] or a volume of interest [VOI]
• G06T 3/40 - Scaling of a whole image or part thereof
• G10L 17/02 - Preprocessing operations, e.g. segment selection; Pattern representation or modelling, e.g. based on linear discriminant analysis [LDA] or principal components; Feature selection or extraction
• G10L 25/78 - Detection of presence or absence of voice signals
• G10L 17/10 - Multimodal systems, i.e. based on the integration of multiple recognition engines or fusion of expert systems

Abstract

A method for acquiring telecommunication regulations and a system applying the same are provided. The method allows a wireless communication device to acquire the telecommunication regulations, and the system is applicable in the wireless communication device. In the method, a driver installed in the wireless communication device is executed to drive a wireless communication module of the wireless communication device. In the meantime, the driver can obtain location data from a BIOS or an operating system, or through environment detection. The driver uses the location data to compare the multiple telecommunication regulations recorded in program codes of the driver, so as to obtain the telecommunication regulation corresponding to the location data. Therefore, the system having the wireless communication module can operate according to the telecommunication regulation corresponding to the location data.

IPC Classes  ?

• H04W 48/04 - Access restriction performed under specific conditions based on user or terminal location or mobility data, e.g. moving direction or speed
• H04W 64/00 - Locating users or terminals for network management purposes, e.g. mobility management

Abstract

A static timing analysis method and a static timing analysis system are provided. The static timing analysis methods includes: obtaining a standard cell library file for describing a plurality of standard cells; performing topology mapping on the standard cell library file to find out a target sequential cell from the standard cells, in which the sequential cell includes a logic gate, a selection circuit and a register circuit; executing a logic test process to find out a pin combination that has a mutual non-controllable relationship, and removing timing constraints related to the pin combination that are taken as redundant timing constraints from the standard cell library file, so as to generate an optimized standard library file; and perform a static timing analysis on a target circuit design according to the optimized standard cell library file.

IPC Classes  ?

• G06F 30/3315 - Design verification, e.g. functional simulation or model checking using static timing analysis [STA]

Abstract

A system on chip (SoC) for performing partial highlighting with the aid of auxiliary information detection includes a person recognition circuit, a sound detection circuit, an auxiliary information detection circuit and a processing circuit. The person recognition circuit obtains image data from an image capturing device, and performs person recognition on the image data to generate a recognition result. The sound detection circuit receives a plurality of sound signals from a plurality of microphones, and determines a voice characteristic value of a main sound. The auxiliary information detection circuit generates auxiliary information for calibrating the voice characteristic value of the main sound. The processing circuit determines a specific region in the image data according to the recognition result, the auxiliary information, and the voice characteristic value, and processes the image data to highlight the specific region.

IPC Classes  ?

• H04N 5/262 - Studio circuits, e.g. for mixing, switching-over, change of character of image, other special effects
• G06V 40/16 - Human faces, e.g. facial parts, sketches or expressions
• G10L 17/06 - Decision making techniques; Pattern matching strategies
• G10L 25/78 - Detection of presence or absence of voice signals
• G06V 40/20 - Movements or behaviour, e.g. gesture recognition

Abstract

A signal receiving method, comprising: receiving a first communication signal and/or a second communication signal through an antenna; when the antenna receives the first communication signal and the second communication signal simultaneously, transmitting, by a first receiving circuit, the first communication signal to a first amplifying circuit, and receiving the second communication signal by a second receiving circuit; and When the antenna does not receive the first communication signal and the second communication signal simultaneously, transmitting, by the first receiving circuit, the first communication signal to the first amplifying circuit, and transmitting, by the first receiving circuit, the second communication signal to a second amplifying circuit. The first communication signal and the second communication signal correspond to different communication protocols respectively.

IPC Classes  ?

• H04B 1/16 - Circuits
• H04B 1/12 - Neutralising, balancing, or compensation arrangements

Abstract

The present application discloses an amplification circuit. The amplification circuit includes an amplifier, a feedback unit, a second feedback unit, a first correlated double sampling unit, and a second correlated double sampling unit. The amplifier has a first positive input terminal, a second positive input terminal, a first negative input terminal, a second negative input terminal, a positive output terminal, and a negative output terminal. First terminals of the first feedback unit and the second feedback unit are coupled to the positive output terminal. The first correlated double sampling unit is coupled to the first negative input terminal and a second terminal of the first feedback unit, and performs a sample operation and an output operation. The second correlated double sampling unit is coupled to the second negative input terminal and a second terminal of the second feedback unit, and performs the sample operation and the output operation.

IPC Classes  ?

• H03F 3/45 - Differential amplifiers

Abstract

An audio-visual managing system, applied to at least one data receiving circuit which receives audio-visual data and outputs processed audio-visual data, each of the data receiving circuit comprising a tuner or a demodulator, the audio-visual managing system comprising: a plurality of transmitting circuits, configured to stream the processed audio-visual data; wherein the processed audio-visual data output by a first data receiving circuit of the data receiving circuit can be used by a first transmitting circuit and a second transmitting circuit of the transmitting circuits simultaneously, when the first transmitting circuit and the second transmitting circuit receive the processed audio-visual data output by the first data receiving circuit.

IPC Classes  ?

• H04N 21/426 - Internal components of the client
• H04N 21/438 - Interfacing the downstream path of the transmission network originating from a server, e.g. retrieving MPEG packets from an IP network

Abstract

A signal generating circuit and a signal generating method are provided. The signal generating circuit includes a first synchronization circuit configured to synchronize a beacon signal and a first signal edge of a clock signal to generate a first synchronization signal; a frequency dividing circuit configured to receive the clock signal and perform frequency division operation on the clock signal to generate a frequency division signal, wherein the duty cycle of the frequency division signal is 50%; a second synchronization circuit configured to receive the first synchronization signal and the frequency division signal and synchronize the first synchronization signal and a second signal edge of frequency division signal to generate a second synchronization signal; and a synthesis circuit configured to receive the second synchronization signal and the frequency division signal and perform AND operation on the second synchronization signal and the frequency division signal to output full-cycle signals.

IPC Classes  ?

• H03L 7/07 - Automatic control of frequency or phase; Synchronisation using a reference signal applied to a frequency- or phase-locked loop using several loops, e.g. for redundant clock signal generation
• H03K 3/037 - Bistable circuits
• H03K 5/00 - Manipulation of pulses not covered by one of the other main groups of this subclass

Abstract

A signal predistortion method applied to a transmission device. The transmission device includes a signal processing circuit, a transmission chain and a power amplifier, the power amplifier is configured to amplify a radio-frequency (RF) input signal outputted by the transmission chain to generate a RF output signal. The signal predistortion method includes: performing a first signal processing operation on a baseband signal by the signal processing circuit, to generate an in-band predistortion output; performing a second signal processing operation on the in-band predistortion output by the signal processing circuit, to generate an out-of-band predistortion output; and generating a full-band predistortion signal to the transmission chain according to the in-band predistortion output and the out-of-band predistortion output by the signal processing circuit, so that the transmission chain generates the RF input signal according to the full-band predistortion signal.

IPC Classes  ?

• H04B 1/62 - TRANSMISSION - Details of transmission systems not characterised by the medium used for transmission for providing a predistortion of the signal in the transmitter and corresponding correction in the receiver, e.g. for improving the signal/noise ratio
• H04B 1/04 - Circuits

Abstract

An image brightness adjusting method, comprising: (a) computing or predicting a first input frame rate according to at least one first input image; (b) generating a first brightness according to a first brightness curve and the first input frame rate, wherein the first brightness curve corresponds to a first frame rate; (c) generating a second brightness according to a second brightness curve and the first input frame rate, wherein the second brightness curve corresponds to a second frame rate; (d) generating a first brightness compensating curve according to the first input frame rate and a brightness difference between the first brightness and the second brightness; and (e) setting a first compensating brightness of at least one second input image according to the first brightness compensating curve.

IPC Classes  ?

• G09G 3/20 - Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix

Abstract

The present disclosure provides a network packet transmission device and a network packet transmission method thereof. The network packet transmission method includes: receiving a network packet, wherein the network packet has at least one packet attribute; determining at least one destination VID for the network packet according to the at least one packet attribute; determining a transmission speed corresponding to the at least one destination VID based on at least one LAN speed table; and transmitting the network packet to a VLAN corresponding to the at least one destination VID according to the transmission speed.

IPC Classes  ?

• H04L 45/00 - Routing or path finding of packets in data switching networks
• H04L 12/46 - Interconnection of networks
• H04L 45/121 - Shortest path evaluation by minimising delays

Abstract

A method for calibrating compensation values utilized by a compensation device in a transmitter includes: obtaining a plurality of output signals sequentially generated by the transmitter by processing a pair of input signals based on a plurality of pairs of compensation values as a plurality of feedback signals, where each feedback signal corresponds to one of the plurality of pairs of compensation values; obtaining a signal component of the feedback signals at a predetermined frequency as a portion of the feedback signals; determining a pair of equivalent impairment parameters in a calibration operation according to the plurality of pairs of compensation values and the portion of the feedback signals; and determining a pair of calibrated compensation values according to the pair of equivalent impairment parameters and providing the pair of calibrated compensation values to the compensation device.

IPC Classes  ?

• H04B 1/04 - Circuits

Abstract

An electronic system includes a first electronic device and a second electronic device. The first electronic device includes a monitoring chip and a hub chip. The monitoring chip is coupled to an upstream port of the hub chip through a first connection and is coupled to the hub chip through a second connection. The second electronic device is configured to couple a downstream port of the hub chip. The monitoring chip is configured to acquire connection information of the second electronic device through the first connection, and acquire status information of the second electronic device through the second connection. The first electronic device is configured to control at least one third electronic device according to the connection information and the status information.

IPC Classes  ?

• G06F 11/30 - Monitoring
• G06F 11/32 - Monitoring with visual indication of the functioning of the machine

Abstract

An analog to digital converter includes voltage divider circuits, front-end circuits, at least one converter circuit, and a controller circuit. The voltage divider circuits are configured to divide an input signal to generate first signals, in which the first signals have different levels. The front-end circuits are configured to respectively sample the first signals to generate second signals. The at least one converter circuit is configured to generate at least one digital output according to the second signals and a reference voltage. The controller circuit is configured to determine a level of the input signal according to the at least one digital output and select one of the at least one digital output according to the level of the input signal.

IPC Classes  ?

• H03M 1/12 - Analogue/digital converters
• H03M 1/38 - Analogue value compared with reference values sequentially only, e.g. successive approximation type

Abstract

A scheduling method of scheduling a target wake time (TWT) communication between an access point and at least one station. The scheduling method includes the access point adjusting a broadcast TWT schedule according to a power saving setting, and the access point transmitting the broadcast TWT schedule. The broadcast TWT schedule includes a broadcast TWT SP start time, a broadcast TWT service period and a broadcast TWT interval.

IPC Classes  ?

• H04W 52/02 - Power saving arrangements

Abstract

A method for training a super-resolution model, a super-resolution method, and a system are provided, and the super-resolution method and the system are implemented through an AI super-resolution model that is trained by the method. In the method, an input image is provided, and a magnification ratio and an image quality threshold are set. Pixel values of the input image are retrieved, and image features of the input image are extracted. Multiple channel images are obtained through a super-resolution model based on the image features and the magnification ratio. Phase information can be obtained according to the magnification ratio and positions of output pixels, and the phase information is used to obtain masks mapping to the channel images. Therefore, an output image can be reshuffled. After a comparison with the image quality threshold, model parameters of the output image can be assessed for training the AI super-resolution model.

IPC Classes  ?

• G06T 3/40 - Scaling of a whole image or part thereof
• G06T 5/50 - Image enhancement or restoration by the use of more than one image, e.g. averaging, subtraction
• G06T 1/60 - Memory management
• G06T 5/20 - Image enhancement or restoration by the use of local operators
• G06T 5/00 - Image enhancement or restoration

Abstract

An output control interface circuit for a static random access memory (SRAM) and an output control method for the same are provided. The output control interface circuit includes an SRAM control detector circuit and an SRAM data controller circuit. The SRAM control detector circuit receives a control signal, determines whether the control signal is stable, and outputs an indication signal correspondingly. The SRAM data controller circuit receives the indication signal and the SRAM output data signal output by the SRAM control detector circuit, and outputs an output data signal according to the indication signal. In response to determining that the control signal is not stable, the SRAM data controller circuit correspondingly outputs the output data signal with a preset value. In response to determining that the control signal is stable, the SRAM data controller circuit outputs the SRAM output data signal as the output data signal correspondingly.

IPC Classes  ?

• G11C 7/20 - Memory cell initialisation circuits, e.g. when powering up or down, memory clear, latent image memory
• G11C 7/10 - Input/output [I/O] data interface arrangements, e.g. I/O data control circuits, I/O data buffers
• G11C 7/22 - Read-write [R-W] timing or clocking circuits; Read-write [R-W] control signal generators or management

Abstract

The present invention discloses a data transmission apparatus having clock gating mechanism. Each of data transmission circuits has a flip-flop depth of N and receives a write clock signal and one of read clock signals to receive and output one of data signals. A write clock gating circuit receives a write clock gating enabling signal to transmit the write clock signal to the data transmission circuits. Each of read clock gating circuits receives one of read clock gating enabling signals to transmit one of the read clock signals. The gating signal transmission circuit has a flip-flop depth of N+M and receives the write and the read clock signals to receive the write clock gating enabling signal and output the read clock gating enabling signals. A largest timing difference among the read clock signals is P clock cycles and M is at least [P].

IPC Classes  ?

• G11C 7/22 - Read-write [R-W] timing or clocking circuits; Read-write [R-W] control signal generators or management
• G11C 7/10 - Input/output [I/O] data interface arrangements, e.g. I/O data control circuits, I/O data buffers

Abstract

An input/output port circuit includes an input/output pad, a transistor, and a conductive routing wire. The transistor has a first connection terminal and a second connection terminal. The first connection terminal of the transistor is electrically connected to the input/output pad through a conductive connection wire, and the second connection terminal is electrically connected to another transistor. The conductive routing wire is electrically connected to the first terminal of the transistor. The conductive routing wire is configured to provide a serial resistance, thereby forcing a surge current to flow toward the another transistor when the surge current is inputted in the input/output circuit through the input/output pad.

IPC Classes  ?

• H01L 27/02 - Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including integrated passive circuit elements with at least one potential-jump barrier or surface barrier

Abstract

A Bluetooth network establishing system and method are provided. The system includes a plurality of node devices and a gateway device. The gateway device is used to connect a Bluetooth network to an external network. A first node device of the node devices broadcasts a first inquiry operation. In response to the first inquiry operation, the gateway device in a first inquiry scan state sends a first extended inquiry response and executes a first page scan state. The first node device executes a first page operation, wherein the first page operation determines whether to establish a first communication connection with the gateway device to join the Bluetooth network according to the first extended inquiry response. After the first node device joins the Bluetooth network, the first node device executes a second inquiry scan state.

IPC Classes  ?

• H04W 76/10 - Connection setup
• H04W 8/00 - Network data management

Abstract

A Bluetooth network establishing system and method are provided. The system includes a plurality of node devices and a gateway device. The gateway device is used to connect a Bluetooth network to an external network and broadcast a first connectable undirected advertising packet. A first node device among the node devices executes a first scan operation to receive a first advertising packet, wherein the first advertising packet includes the first connectable undirected advertising packet. The first node device determines whether to establish a first communication connection with the gateway devices to join the Bluetooth network according to the first advertising packet. After joining the Bluetooth network, the first node device broadcasts a second connectable undirected advertising packet.

IPC Classes  ?

• H04W 76/10 - Connection setup
• H04W 40/24 - Connectivity information management, e.g. connectivity discovery or connectivity update

Abstract

A Bluetooth internet protocol packet transmitting device and method are provided. The device includes a Bluetooth protocol stack, a Bluetooth controller and a host control interface. The Bluetooth protocol stack is configured to store an internet protocol stack and a host control interface driver. The Bluetooth controller generates at least one data packet based on an internet protocol packet, wherein the at least one data packet corresponds to an asynchronous connection data format. The Bluetooth controller transmits the at least one data packet to the host control interface driver. The host control interface driver determines whether the at least one data packet is an asynchronous connection data packet. When the host control interface driver determines that the at least one data packet is the asynchronous connection data packet, the at least one data packet is transmitted to the internet protocol stack.

IPC Classes  ?

• H04L 69/30 - Definitions, standards or architectural aspects of layered protocol stacks

Abstract

The present disclosure discloses a signal relay apparatus having frequency locking mechanism that includes a receiving circuit, a frequency generation circuit, a frequency tracking circuit and a transmission circuit. The receiving circuit receives a receiving signal to retrieve data included therein according a corresponding receiving frequency signal. The frequency generation circuit receives a source clock signal and generates a target frequency signal according to a conversion parameter. The frequency tracking circuit calculates a frequency difference between the receiving frequency signal and the target frequency signal to adjust the conversion parameter accordingly. The transmission circuit generates a transmission signal that includes the data according to the target frequency signal.

IPC Classes  ?

• H04L 7/033 - Speed or phase control by the received code signals, the signals containing no special synchronisation information using the transitions of the received signal to control the phase of the synchronising-signal- generating means, e.g. using a phase-locked loop
• H03L 7/08 - Automatic control of frequency or phase; Synchronisation using a reference signal applied to a frequency- or phase-locked loop - Details of the phase-locked loop

Abstract

The present disclosure discloses a transceiver apparatus having self-calibration mechanism that includes a signal transmission path, a signal receiving path, a path switching circuit, a transceiver circuit and a self-calibration circuit. The path switching circuit includes a switch to switch a connection relation among an antenna, the signal transmission path and the signal receiving path. The transceiver circuit is coupled to the signal transmission path and the signal receiving path. The self-calibration circuit controls the transceiver circuit to transmit a transmission signal through the signal transmission path to the path switching circuit and receives a leakage signal generated according to the transmission signal through the signal receiving path, so as to perform a self-calibration process on the transceiver circuit based on the transmission signal and the leakage signal. The leakage signal has a leakage signal strength larger than a predetermined level.

IPC Classes  ?

• H04B 1/44 - Transmit/receive switching

Abstract

An integrated circuit includes a functional circuit and a first power switch chain. The first power switch chain includes a first power switch circuit and a second power switch circuit and is coupled between a power source and the functional circuit. The first power switch chain is configured to receive a first control signal, and the first control signal is configured to turn on or turn off the first power switch circuit and the second power switch circuit. A first resistance value of the first power switch circuit is different from a second resistance value of the second power switch circuit.

IPC Classes  ?

• G06F 30/367 - Design verification, e.g. using simulation, simulation program with integrated circuit emphasis [SPICE], direct methods or relaxation methods
• G06F 30/392 - Floor-planning or layout, e.g. partitioning or placement
• H03K 17/14 - Modifications for compensating variations of physical values, e.g. of temperature
• H03K 17/693 - Switching arrangements with several input- or output-terminals, e.g. multiplexers, distributors

Abstract

A data accessing method includes providing a first memory including a plurality of memory pages, acquiring a usage order value of each memory page of the plurality of memory pages, acquiring a first usage order value having a highest priority from a plurality of usage order values corresponding to the plurality of memory pages in the first memory, updating the first memory after a first memory page having the first usage order value is used, acquiring a second usage order value having a highest priority from the updated first memory after the first memory is updated, and using a second memory page having the second usage order.

IPC Classes  ?

• G06F 12/0882 - Page mode
• G06F 12/126 - Replacement control using replacement algorithms with special data handling, e.g. priority of data or instructions, handling errors or pinning
• G06F 12/0804 - Addressing of a memory level in which the access to the desired data or data block requires associative addressing means, e.g. caches with main memory updating

Abstract

A controlling device for handling a low latency transmission includes: a storage module, for maintaining a list, wherein the list includes a plurality of transmission information of a plurality of transmitting devices, and the plurality of transmission information includes a plurality of statuses, a plurality of priorities and a plurality of airtime resources, wherein each of the plurality of priorities indicates a priority level of a plurality of priority levels; and a scheduling module, coupled to the storage module, for generating a high priority window, and selecting a transmitting device from the plurality of transmitting devices in the high priority window according to the plurality of statuses, the plurality of priorities and the plurality of airtime resources to control the transmitting device to perform a transmission.

IPC Classes  ?

• H04W 72/56 - Allocation or scheduling criteria for wireless resources based on priority criteria
• H04W 72/1263 - Mapping of traffic onto schedule, e.g. scheduled allocation or multiplexing of flows

Abstract

An amplifier system includes an output circuit, a processor circuit, a feedback circuit, and a controller circuit. The output circuit outputs an output signal and returns a digital output feedback signal. The processor circuit receives a filtered error audio signal and outputs a pulse width modulation control signal to the output circuit. An addition unit of the feedback circuit adds the negative value of the digital output feedback signal to the digital input signal to obtain the error audio signal. A variable filter unit of the feedback circuit filters the error audio signal and outputs the filtered error audio signal. A compensation unit of the variable filter unit changes the gain characteristics of the variable filter unit. The controller circuit adjusts one or more parameters of the compensation unit according to a pre-compensation signal so as to change the gain characteristics of the variable filter unit.

IPC Classes  ?

• H03G 3/30 - Automatic control in amplifiers having semiconductor devices
• H03F 1/02 - Modifications of amplifiers to raise the efficiency, e.g. gliding Class A stages, use of an auxiliary oscillation
• H03F 3/181 - Low-frequency amplifiers, e.g. audio preamplifiers
• H04R 3/04 - Circuits for transducers for correcting frequency response

Abstract

An amplifier includes a first stage of amplification circuit and a second stage of amplification circuit. The first stage of amplification circuit includes a first transistor, a second transistor, and a voltage gap generation unit. The first transistor has a first terminal, a second terminal for outputting an amplified signal, and a control terminal for receiving an input signal. The second transistor has a first terminal, a second terminal, and a control terminal for receiving a bias voltage. The voltage gap generation unit provides a voltage gap between a first terminal and a second terminal of the voltage gap generation unit according to a current flowing through the first transistor and the second transistor. The second stage of amplification circuit uses the voltages at the first terminal and the second terminal of the voltage gap generation unit as input signals.

IPC Classes  ?

• H03F 1/02 - Modifications of amplifiers to raise the efficiency, e.g. gliding Class A stages, use of an auxiliary oscillation
• H03F 3/45 - Differential amplifiers

Abstract

An eye diagram measuring method includes: sampling a compensated input signal according to a reference voltage and a reference clock to obtain a first sampling result; and sampling a to-be-compensated input signal according to a scan voltage and a scan clock to obtain a second sampling result, including: (b1) storing a minimum phase and a voltage level which render the first sampling result identical to the second sampling result; (b2) increasing the voltage level and repeating operation (b1); (b3) decreasing the voltage level and repeating operation (b1); (b4) storing a maximum phase and the voltage level which render the first sampling result identical to the second sampling result; (b5) increasing the voltage level and repeating operation (b4); and (b6) decreasing the voltage level and repeating operation (b4). Voltage levels, maximum phases and minimum phases that are stored are for adjusting the reference voltage and the reference clock.

IPC Classes  ?

• H04B 17/345 - Interference values

Abstract

An electronic system and a display method are provided. The following steps are performed by central processing units: a first central processing unit loads and checks a display firmware; a second central processing unit determines whether the electronic system is in a first connected state based on the display firmware; in response to that the electronic system is in the first connected state, the first central processing unit and the second central processing unit, together with collaborating central processing units of the central processing units, execute a first pre-defined procedure and an external device display procedure based on settings stored in a data area to display a content transmitted by the external device corresponding to the first connected state; and, in response to that the electronic system is not in the first connected state, the first central processing unit executes a second pre-defined procedure.

IPC Classes  ?

• G06F 9/4401 - Bootstrapping

Abstract

A control device is configured to control a display panel according to a trigger signal transmitted from an input device to a host. The control device includes a connector unit and a signal capture unit. The connector unit is configured to receive the trigger signal, and transmit the same to the host. The signal capture unit is configured to capture the trigger signal, and control the display panel according to the trigger signal while the connector unit is transmitting the trigger signal to the host.

IPC Classes  ?

• G09G 5/00 - Control arrangements or circuits for visual indicators common to cathode-ray tube indicators and other visual indicators
• G09G 5/18 - Timing circuits for raster scan displays

Abstract

The present invention discloses a computation circuit. Each of a first and a second term computation circuits includes higher bit computation circuits, a lowest bit computation circuit and a first adder. Each of the higher bit computation circuits left-shifts a multiplier, outputs the effective shifted multiplier having a sign determined and further performs left-shifts without performing 2's complement computation to generate a higher bit computation result. The lowest bit computation circuit outputs the effective multiplier having the sign determined to generate a lowest bit computation result. The first adder adds the bit computation results to generate a term computation result. The third term computation circuit outputs an effective addend having the sign determined and adds the addend to the summation of a number of 2's complement to generate a third term computation result. The second adder adds the term computation results and the third term computation result to generate a total computation result.

IPC Classes  ?

• G06F 7/523 - Multiplying only
• G06F 7/501 - Half or full adders, i.e. basic adder cells for one denomination
• G06F 5/01 - Methods or arrangements for data conversion without changing the order or content of the data handled for shifting, e.g. justifying, scaling, normalising

Abstract

The present invention discloses a SAADC circuit having optimized linearity. A lower-bit capacitor array includes lower-bit capacitors. A higher-bit capacitor array includes unit capacitors. In an initializing mode, a control circuit sorts the unit capacitors according to unit capacitances thereof such that the unit capacitors are configured to be higher-bit capacitors having a linearity parameter within a predetermined range. In an operation mode, the capacitor array receives an analog input signal and a reference voltage to generate an analog output signal, a comparator generates a comparison result according to the analog output signal and the control circuit generates an enabling signal according to the comparison result based on the successive approximation mechanism to selectively enable the higher-bit and the lower-bit capacitors to connect to the reference voltage by using the capacitor enabling circuit and outputs a digital output signal according to the final comparison result.

IPC Classes  ?

• H03M 1/06 - Continuously compensating for, or preventing, undesired influence of physical parameters

Abstract

A method and a control circuit for performing synchronization on playback of multiple electronic devices are provided, where the multiple electronic devices include a master device and a slave device. The method includes: utilizing the master device to receive audio data from a far-end device to be master audio data, and transmitting the master audio data to the slave device to be slave audio data, where the slave device generates ultrasound data according to the slave audio data, to make the slave device play the slave audio data and the ultrasound data; utilizing a calibration circuit to estimate a delay value between the ultrasound data received by a microphone of the master device and the master audio data; and utilizing a delay circuit to control a delay of the master audio data according to the delay value, to generate master output audio data for being played by the master device.

IPC Classes  ?

• H04R 3/12 - Circuits for transducers for distributing signals to two or more loudspeakers
• H04R 29/00 - Monitoring arrangements; Testing arrangements

Abstract

An electronic device and an antenna control method are provided. The electronic device includes an antenna, a line switching circuit, a first communication chip, a second communication chip, and a logic circuit. The line switching circuit is coupled to the antenna. The first communication chip is coupled to the antenna through the line switching circuit and configured to generate a slot allocation signal. The second communication chip is coupled to the antenna through the line switching circuit and configured to generate a packet transceiving request signal. The first communication chip and the second communication chip are communication chips of different types. The logic circuit is coupled to the first communication chip and the second communication chip and configured to control the line switching circuit according to the slot allocation signal and the packet transceiving request signal.

IPC Classes  ?

• H04B 1/00 - TRANSMISSION - Details of transmission systems not characterised by the medium used for transmission
• H04B 1/04 - Circuits

Abstract

An electronic device, an antenna control method, and a communication chip are provided. The electronic device includes an antenna, a line switching circuit, a first communication chip, and a second communication chip. The line switching circuit is coupled to the antenna. The first communication chip is coupled to the antenna through the line switching circuit and configured to generate a slot allocation signal. The second communication chip is coupled to the antenna through the line switching circuit and configured to generate a packet distribution signal. The first communication chip and the second communication chip are communication chips of different types. The line switching circuit switches the antenna to the first communication chip or the second communication chip according to the packet distribution signal.

IPC Classes  ?

• H04B 1/00 - TRANSMISSION - Details of transmission systems not characterised by the medium used for transmission
• H04W 72/0446 - Resources in time domain, e.g. slots or frames

Abstract

A transmitter includes a transmitter circuit, a calibration circuit, and a transmitter signal strength indicator circuit. The transmitter circuit is coupled to a power node to receive a supply voltage and transmits an output signal via an antenna. The calibration circuit senses a current of the power node when the transmitter circuit operates in a first frequency band and operates in a second frequency band to generate a signal having different values and generates a calibration signal according to the signals having the different values. The transmitter signal strength indicator circuit detects power of the output signal to generate a first detection signal, and generate a second detection signal according to the calibration signal and the first detection signal. The transmitter circuit adjusts the power of the output signal to be target power according to the second detection signal.

IPC Classes  ?

• H04B 17/12 - Monitoring; Testing of transmitters for calibration of transmit antennas, e.g. of amplitude or phase
• H04B 17/10 - Monitoring; Testing of transmitters
• H04B 17/318 - Received signal strength

Abstract

The present application discloses a semiconductor packaging structure and a manufacturing method of the same that could be commonly used for lead frame products and substrate products. The semiconductor packaging structure includes: a base layer (lead frame or organic substrate); a die, disposed on the base layer; a molding compound, filled over the base layer and surrounding the die; a shielding layer, covering the top surface and a side surface of the molding compound; and a bonding wire, having a first terminal and a second terminal, wherein the bonding wire extends the side surface of the molding compound, thus allowing the first terminal of the bonding wire to contact an inner side of the shielding layer.

IPC Classes  ?

• H01L 23/552 - Protection against radiation, e.g. light
• H01L 23/31 - Encapsulation, e.g. encapsulating layers, coatings characterised by the arrangement
• H01L 23/00 - SEMICONDUCTOR DEVICES NOT COVERED BY CLASS - Details of semiconductor or other solid state devices
• H01L 21/56 - Encapsulations, e.g. encapsulating layers, coatings

Abstract

An embedded device detection method, comprising the following steps: executing a task by an embedded device, wherein the task comprises multiple functions; when an abnormal interruption occurs to the task, obtaining a stack pointer and a program counter corresponding to the abnormal interruption by a detection device, wherein the program counter is configured to record a memory address in use when the abnormal interruption occurs to the task; obtaining a stack space corresponding to a first target function being executed according to the program counter when the abnormal interruption occurs to the task; finding out a second target function before the first target function is executed according to the stack pointer and the stack space; and correcting the task according to the second target function.

IPC Classes  ?

• G06F 11/00 - Error detection; Error correction; Monitoring
• G06F 11/07 - Responding to the occurrence of a fault, e.g. fault tolerance
• G06F 11/28 - Error detection; Error correction; Monitoring by checking the correct order of processing

Abstract

A method for resuming topology of a single loop network and a network switch system are provided. The network switch system includes one or more first network switches each having a first port and a second port and a second network switch having a third port and a fourth port. When the first port of one of the first network switches is abnormal, a recovery control frame is transmitted through the second port. The second network switch sets the third port in a disabled state to an enabled state. When the abnormal port is resumed, the first network switch transmits a block control frame through the second port. The second network switch sets the third port in the enabled state to the disabled state and transmits a forward control frame through the fourth port. The first network switch sets the first port in the disabled state to the enabled state.

IPC Classes  ?

• H04L 41/12 - Discovery or management of network topologies

Abstract

An electronic device includes a receiving unit, a signal processing unit, a transmitting unit, and an audio timing unit. The receiving unit receives audio data and first video data. The signal processing unit generates second video data and a pixel clock signal for playing the second video data according to the first video data. The transmitting unit transmits the second video data, the audio data, the pixel clock signal, and a cycle time stamp (CTS) to a receiver. The audio timing unit generates an internal reference signal adjusts a frequency of the internal reference signal according to a receiving speed of the audio data, and generates the CTS according to the internal reference signal and the pixel clock signal so that the receiver can generate an audio clock signal for playing the audio data according to the pixel clock signal and the CTS.

IPC Classes  ?

• H04N 7/06 - Systems for the simultaneous transmission of one television signal, i.e. both picture and sound, by more than one carrier

Abstract

A low-dropout regulator includes an amplifier circuit, a buffer circuit, a control circuit, a power transistor, and a feedback circuit. The amplifier circuit is configured to operate based on an input voltage and generate a first voltage at a first node according to a reference voltage and a feedback voltage. The buffer circuit is configured to generate a second voltage at a second node according to the first voltage. The control circuit is configured to work with the buffer circuit to form a noise canceller. The noise canceller is coupled between the first node, the second node, and a voltage terminal. The power transistor is configured to generate an output voltage according to the input voltage and the second voltage. The feedback circuit is configured to generate the feedback voltage according to the output voltage.

IPC Classes  ?

• G05F 1/575 - Regulating voltage or current wherein the variable actually regulated by the final control device is dc using semiconductor devices in series with the load as final control devices characterised by the feedback circuit
• G05F 1/59 - Regulating voltage or current wherein the variable actually regulated by the final control device is dc using semiconductor devices in series with the load as final control devices including plural semiconductor devices as final control devices for a single load
• G05F 1/46 - Regulating voltage or current wherein the variable actually regulated by the final control device is dc

Abstract

A transmitter includes an analog transmission circuit, a power amplifier, a voltage detector, a comparator, and a control circuit. The analog transmission circuit is configured to provide a first gain to a first analog signal, so as to generate a second analog signal. The power amplifier is configured to provide a second gain to the second analog signal, so as to generate an output signal to an antenna. The voltage detector is configured to detect a voltage level of the second analog signal. The comparator is configured to generate an indication signal according to the voltage level and a reference level. The control circuit is configured to adjust the first gain of the analog transmission circuit according to the indication signal.

IPC Classes  ?

• H04B 1/04 - Circuits
• H03F 3/24 - Power amplifiers, e.g. Class B amplifiers, Class C amplifiers of transmitter output stages
• H03F 1/02 - Modifications of amplifiers to raise the efficiency, e.g. gliding Class A stages, use of an auxiliary oscillation

Abstract

A method for system profiling and controlling and a computer system performing the same are provided. In the method, an operating system is operated after the computer system is booted, in which a profiling-controlling system is operated. When the operating system loads and executes a system profiling-controlling program, the profiling-controlling system that simultaneously operates a profiling routine and a controlling routine is initiated. The profiling routine is used to retrieve system kernel data that is generated during operation of the operating system and analyze the system kernel data through a kernel tracing tool. When it is determined that controlling is required, the profiling routine notifies the controlling routine. The controlling routine controls operating parameters of the operating system in real time according to an analysis result generated by the profiling routine.

IPC Classes  ?

• G06F 11/34 - Recording or statistical evaluation of computer activity, e.g. of down time, of input/output operation
• G06F 11/07 - Responding to the occurrence of a fault, e.g. fault tolerance