An electromagnetic pulse detector in an integrated circuit includes one or more peak hold circuits coupled to one or more traces in the integrated circuit and configured to asynchronously detect voltage spike(s) on the one or more traces and store voltage value(s) corresponding to the voltage spike(s). One or more comparator circuits are coupled to the peak hold circuits to compare the voltage values corresponding to the voltage spikes to one or more threshold voltage values. Storage locations are coupled to the comparator circuits to store indications of the voltage spike(s) being greater than the threshold voltage value to thereby indicate detection of an electromagnetic pulse.
Memory is allocated according to lifespan. The memory manager allocates requests for short-term memory to one portion of memory and allocates requests for long-term memory to another portion of the memory. The memory manager looks for free space for requests for long-term memory starting at a first location in the memory and the memory manager looks for free space beginning at a second location in the memory for requests for short-term memory. In that way, more memory banks are likely to be free and can be powered down to save power consumption, particularly during sleep states.
Modulation testing separately enables slices of an analog varactor array of an LC oscillator. For each enabled slice, a reference voltage supplying a resistor ladder is set to a plurality of different reference voltage values. Resistor ladder voltages generated for the different reference voltage values are supplied to the enabled slice and a control voltage coupled to the enabled slice is swept for each of the reference voltage values. Respective frequencies of an oscillator signal coupled to an output of the LC oscillator are measured for each enabled slice for each combination of the reference voltage values and the control voltage values. The linearity of LC oscillator gain is determined for each of the reference voltage values for each slice based on the respective frequencies and the control voltage values. Passing/failing the modulation testing is based on the linearity of the LC oscillator gain.
In one aspect, an apparatus comprises: a driver circuit to receive first and second ramp signals and output first and second drive signals under control of a first bias signal and a second bias signal, the first bias signal having a first edge and a second edge, the second edge having a different edge rate than the first edge, the second bias signal having a third edge and a fourth edge, the third edge having a different edge rate than the fourth edge; and an output circuit coupled to the driver circuit, the output circuit comprising at least one first active device to be driven by the first drive signal and at least one second active device to be driven by the second drive signal, where the output circuit is to amplify and output a radio frequency (RF) signal.
An apparatus includes a module. The module includes an antenna structure. The antenna structure includes a printed monopole antenna. The antenna structure further includes first and second inductive-capacitive (LC) resonant networks that are coupled to the printed monopole antenna. The antenna structure further includes a double slotted loop coupled to the first and second LC resonant networks.
H01Q 7/00 - Loop antennas with a substantially uniform current distribution around the loop and having a directional radiation pattern in a plane perpendicular to the plane of the loop
H01Q 1/38 - Structural form of radiating elements, e.g. cone, spiral, umbrella formed by a conductive layer on an insulating support
A method for operating a wireless communications device having a low energy mode of operation and a second mode of operation includes providing a first clock signal and a second clock signal in the second mode of operation. The first clock signal has a first frequency within a first frequency offset range. The second clock signal has a second frequency within a second frequency offset range. The first frequency is lower than the second frequency, and the first frequency offset range is greater than the second frequency offset range. The method includes generating a calibrated version of the first clock signal in the second mode of operation using a measurement of the first clock signal measured using a timer controlled by the second clock signal. The method includes using the calibrated version of the first clock signal in the low energy mode while the second clock signal is disabled.
In one embodiment, an apparatus includes: a clock generator to receive a reference clock signal and generate a first clock signal using the reference clock signal; a counter coupled to the clock generator to maintain a first count regarding a number of cycles of the first clock signal; and a controller coupled to the counter. The controller may be configured to detect a potential security violation when the first count varies from a predetermined value.
G06F 21/72 - Protecting specific internal or peripheral components, in which the protection of a component leads to protection of the entire computer to assure secure computing or processing of information in cryptographic circuits
G06F 1/08 - Clock generators with changeable or programmable clock frequency
8.
FAST RF POWER MEASUREMENT APPARATUS FOR PRODUCTION TESTING
A system and method for performing production testing on high power semiconductor devices is disclosed. The system includes signal generators, RF meters, sockets, couplers and connectors which also function as switches when connected to an external cable. A calibration process is executed which allows the controller to create a correlation between measurements taken by the RF meter and the actual voltages, and power levels present at the device under test. By performing this calibration, it is possible to perform production testing of devices much more quickly and reliably.
A system and method for determine the spatial position of a network device is disclosed. A locator device having an antenna array is used to perform an AoX calculation to find the direction to the network device. The AoX calculation utilizes a plurality of the antennas in the antenna array. The locator device also performs a high accuracy distance measurement (HADM). In certain embodiments, only one antenna in the antenna array is used for the HADM calculation. Using the direction and the distance to the network device, the locator is able to determine the spatial position of the network device. In some embodiments, the antenna array may a rotational symmetry array having a plurality of outer antenna elements and one central antenna element.
In one embodiment, an apparatus includes: a transmit path to receive, process and output a transmit radio frequency (RF) signal, the transmit path including a first power amplifier; a receive path to receive, process and output a receive RF signal, the receive path including a first low noise amplifier (LNA); and switching circuitry coupled to the transmit path and the receive path. In a transmit mode, the switching circuitry is to cause a RF filter to couple into the transmit path to filter the transmit RF signal and cause the filtered transmit RF signal to be provided to the first power amplifier and thereafter to an antenna. In a receive mode, the switching circuitry is to cause the receive RF signal to be provided to the RF filter and the first LNA, and thereafter to be provided to a digital processor.
A system that is capable of detecting a Man in the Middle attack is disclosed. The system includes a receive circuit for receiving incoming packets. The system also includes a digitized model of at least part of the receive circuit and optionally part of the transmit circuit. The system compares the output from the digitized model with the output from the read circuit to determine the likelihood of a Man in the Middle Attack. In certain embodiments, the digitized model is a finite impulse response filter with multiple taps. The system correctly identifies Man in the Middle attacks more than 90% of the time when the signal to noise ratio is greater than 20 dB.
G01S 7/02 - RADIO DIRECTION-FINDING; RADIO NAVIGATION; DETERMINING DISTANCE OR VELOCITY BY USE OF RADIO WAVES; LOCATING OR PRESENCE-DETECTING BY USE OF THE REFLECTION OR RERADIATION OF RADIO WAVES; ANALOGOUS ARRANGEMENTS USING OTHER WAVES - Details of systems according to groups , , of systems according to group
G01S 13/76 - Systems using reradiation of radio waves, e.g. secondary radar systems; Analogous systems wherein pulse-type signals are transmitted
12.
Man in the Middle Attack Detection in BLE High Accuracy Distance Measurement
A system that is capable of detecting a Man in the Middle attack is disclosed. The system includes a receive circuit for receiving incoming packets. The system also includes a digitized model of at least part of the receive circuit and optionally part of the transmit circuit. The system compares the output from the digitized model with the output from the read circuit to determine the likelihood of a Man in the Middle Attack. In certain embodiments, the digitized model is a finite impulse response filter with multiple taps. The system correctly identifies Man in the Middle attacks more than 90% of the time when the signal to noise ratio is greater than 20 dB.
A system and method for detecting the preamble of a wireless packet is disclosed. The system utilizes one or more received fragments as inputs to a correlator, forming correlator content inside the correlator memory. After every sample from the received fragment is provided to the correlator, the correlator then compares the correlator content to a known pattern pre-programmed as a set of correlation coefficients. The correlation coefficients may not align with the correlator content because the symbol boundaries are not known a-priori. By cyclic rotation of the correlation coefficients relative to the correlator content, or cyclic rotation of the correlator content relative to the known correlation coefficients, a match with one or more preamble symbols may be found. This technique may be used to reduce power during the preamble detection process. Alternatively, this technique can also be used for antenna diversity, multi PHY and multichannel applications.
H03M 13/00 - Coding, decoding or code conversion, for error detection or error correction; Coding theory basic assumptions; Coding bounds; Error probability evaluation methods; Channel models; Simulation or testing of codes
H03M 13/11 - Error detection or forward error correction by redundancy in data representation, i.e. code words containing more digits than the source words using block codes, i.e. a predetermined number of check bits joined to a predetermined number of information bits using multiple parity bits
In one embodiment, an integrated circuit includes: a first radio frequency (RF) circuit configured to receive and process a first RF signal having a sub-gigahertz (GHz) frequency to output a first lower frequency signal and to transmit RF signals having the sub-GHz frequency; a second RF circuit configured to receive and process a second RF signal having a frequency of at least substantially 2.4 GHz to output a second lower frequency signal and to transmit RF signals at the at least substantially 2.4 GHz; shared analog circuitry coupled to the first RF circuit and the second RF circuit, the shared analog circuitry to receive at least one of the first RF signal or the second RF signal and output a digital output signal; and a digital circuit coupled to the shared analog circuit, the digital circuit to recover message information from the digital output signal.
A system for securing the contents of an external nonvolatile memory associated with a main processing device is disclosed. The system stores additional information associated with each cache line in the nonvolatile memory. In some embodiments, this additional information comprises a NONCE (number used once) and a MAC (Message Authentication Code). When the main processing device reads a cache line from the nonvolatile memory, the NONCE, address and data from the cache line are used to generate a MAC, which is then compared to the MAC stored in the nonvolatile memory. If the MACs match, the cache line is stored in the on-board cache of the main processing device. If the MACs do not match, a countermeasure may be implemented. The use of a NONCE addresses an information leakage issue that is present when stream ciphers, such as AES-CTR or AES-GCM, are used in data storage applications.
An antenna array that utilizes ground guard rings and metamaterial structures is disclosed. In certain embodiments, the antenna array is constructed from a plurality of antenna unit cells, wherein each antenna unit cell is identical. The antenna unit cell comprises a top surface, that contains a patch antenna and a ground guard ring. A reactive impedance surface (RIS) layer is disposed beneath the top surface and contains the metamaterial structures. The metamaterial structures are configured to present an inductance to the patch antennas, thereby allowing the patch antennas to be smaller than would otherwise be possible. In some embodiments, the metamaterial structures comprise hollow square frames. An antenna array constructed using this antenna unit cell has less coupling than conventional antenna arrays, which results in better performance. Furthermore, this new antenna array also requires less space than conventional antenna arrays.
H01Q 21/20 - Arrays of individually energised antenna units similarly polarised and spaced apart the units being spaced along, or adjacent to, a curvilinear path
H01Q 1/52 - Means for reducing coupling between antennas; Means for reducing coupling between an antenna and another structure
In one aspect, a method comprises: initializing a front end circuit of a wireless device into a first mode in which a radio frequency (RF) signal processing path comprises a low noise amplifier (LNA) having an output coupled to an RF filter; and in response to an RF signal received in the front end circuit having a level greater than a first threshold, reconfiguring the front end circuit into a second mode in which the RF filter is coupled to an input of the LNA.
In one aspect, a method comprises: reconfiguring a front end circuit of a device from a first mode having a receiver radio frequency (RF) signal processing path with a first relative order into a second mode having the receiver RF signal processing path with a different relative order; determining that a timeout period has completed; and reconfiguring the front end circuit from the second mode to the first mode in response to determining that the timeout period has completed.
In one aspect, a method comprises: receiving, in a controller of a wireless device, at least one of a first interrupt or a second interrupt, where: the first interrupt is to indicate that a receive radio frequency (RF) signal received in a front end circuit of the wireless device is overloading at least a low noise amplifier (LNA) of the front end circuit; and the second interrupt is to indicate that the receive RF signal is overloading at least a passive network of a system on chip (SoC) of the wireless device; and in response to the at least one of the first interrupt or the second interrupt, reconfiguring the front end circuit from a first mode into a second mode, where a relative order of a receiver RF signal processing path is different in the first mode than in the second mode.
In one aspect, a method comprises: monitoring, via at least one computer system of a central entity, performance information of a plurality of wireless devices present in a network environment remotely coupled to the central entity; updating a monitoring database based on monitoring the performance information; and causing at least some of the plurality of wireless devices to be reconfigured from a first mode to a second mode based at least in part on the performance information.
In one aspect, an apparatus includes a receive path to receive, process and output a receive radio frequency (RF) signal, the receive path comprising at least one low noise amplifier (LNA) and a plurality of signal nodes. The receive path may be configurable to operate in a plurality of modes. The apparatus also may include at least one filter to filter the receive RF signal and at least one detector circuit to detect one or more levels present at one or more of the plurality of signal nodes. The apparatus may configure an order of the at least one LNA and the at least one filter, based at least in part on the one or more levels detected in the at least one detector circuit.
In one aspect, a method comprises: comparing, in a comparator, a signal level of a receive radio frequency (RF) signal to a first threshold, the receive RF signal obtained from a controllable location in an RF front end circuit; and in response to the signal level of the receive RF signal exceeding the first threshold, causing the RF front end circuit to be reconfigured from a first mode in which an input to a low noise amplifier (LNA) is coupled an antenna to a second mode in which the input to the LNA is coupled to an RF filter.
In one aspect, an apparatus comprises a transmit path including a power amplifier to receive, process and output a transmit radio frequency (RF) signal the transmit path comprising a power amplifier. A detection circuit coupled to the transmit path may be configured to: detect, during a first portion of a packet of the transmit RF signal, a level of the transmit RF signal at an input to the power amplifier; and detect, during a second portion of the packet of the transmit RF signal the level of the transmit RF signal at an output of the power amplifier. Based at least in part on the detected level at at least one of the power amplifier input or output, a level of at least one component of the transmit path upstream to the power amplifier is to be updated, to control a transmit power variation of the transmit RF signal.
An apparatus includes a radio-frequency (RF) receiver for receiving an RF signal using a plurality of antennas. The RF receiver includes a demodulator to provide a switch signal to cause the RF receiver to use an antenna in the plurality of antennas. The RF receiver further includes a carrier frequency offset (CFO) correction circuit that estimates and removes a carrier frequency offset.
A system and method of performing an AES encryption, while also determining whether a potentially successful DFA attack is underway is disclosed. When interim results are not visible, the DFA attack that is most likely to be succeed is initiated by introducing the fault between the MixColumns operation in the second to last round and the MixColumns operation in the next to last round. To detect this, the present system and method performs the next to last round and then repeats this next to last round. The results of the original round and repeated round are compared to identify a possible DFA attack. Importantly, the same hardware is used for the original round and the repeated round. In this way, the amount of additional hardware needed to detect a possibly successful DFA attack is minimized. Further, the impact on execution time may be 10% or less.
H04L 9/00 - Arrangements for secret or secure communications; Network security protocols
H04L 9/06 - Arrangements for secret or secure communications; Network security protocols the encryption apparatus using shift registers or memories for blockwise coding, e.g. D.E.S. systems
In one aspect, an apparatus includes: a volatile memory to store a dynamic portion of a hybrid generic attribute (GATT) database structure; and a non-volatile memory coupled to the volatile memory to store a static portion of the hybrid GATT database structure, where the volatile memory is to store an attribute index array to identify whether an attribute datum of the hybrid GATT database structure is stored in the volatile memory or the non-volatile memory.
In one embodiment, a method includes: receiving, in an access point, a configuration request from a user, the configuration request comprising a first SSID; in response to the user request, entering into a monitor mode to identify one or more existing SSIDs of one or more existing access points in a local environment with the access point; and informing the user if the first SSID matches at least one of the existing SSIDs.
A method for operating a switched-mode power converter includes providing to a maximum voltage node as a maximum voltage, a version of the higher of a first voltage on a first node and a second voltage on a second node. The method includes generating a first signal indicating whether to operate the switched-mode power converter in a buck mode of operation or a boost mode of operation based on the first voltage and a first voltage domain based on the maximum voltage. The method includes generating a second signal indicating whether to operate the switched-mode power converter in a buck mode of operation or a boost mode of operation based on the first voltage and a second voltage domain of the first voltage. The method includes combining the first signal and the second signal to generate a digital configuration indicator signal.
H02M 3/158 - Conversion of dc power input into dc power output without intermediate conversion into ac by static converters using discharge tubes with control electrode or semiconductor devices with control electrode using devices of a triode or transistor type requiring continuous application of a control signal using semiconductor devices only with automatic control of output voltage or current, e.g. switching regulators including plural semiconductor devices as final control devices for a single load
H02M 1/36 - Means for starting or stopping converters
H02M 1/08 - Circuits specially adapted for the generation of control voltages for semiconductor devices incorporated in static converters
H02M 3/157 - Conversion of dc power input into dc power output without intermediate conversion into ac by static converters using discharge tubes with control electrode or semiconductor devices with control electrode using devices of a triode or transistor type requiring continuous application of a control signal using semiconductor devices only with automatic control of output voltage or current, e.g. switching regulators with digital control
29.
LOW POWER BOOST CONVERTER STARTUP WITH SOFT START AND OUTPUT VOLTAGE OVERSHOOT LIMITING
A method for operating a DC-DC converter circuit includes, in response to detecting a startup condition, charging an output capacitance coupled to an output node of the DC-DC converter circuit at a first rate in a first phase of a multi-phase startup mode of operation of the DC-DC converter circuit. The method includes, in response to an indication of an output voltage on the output node approaching an input voltage on an input node of the DC-DC converter circuit, controlling a current through an inductor using an oscillating signal in a second phase of the multi-phase startup mode of operation, thereby adjusting the output voltage to equal a target voltage level. The first rate may be the rate of charging an RC circuit including the output capacitance coupled to the output node.
H02M 3/158 - Conversion of dc power input into dc power output without intermediate conversion into ac by static converters using discharge tubes with control electrode or semiconductor devices with control electrode using devices of a triode or transistor type requiring continuous application of a control signal using semiconductor devices only with automatic control of output voltage or current, e.g. switching regulators including plural semiconductor devices as final control devices for a single load
H02M 1/36 - Means for starting or stopping converters
30.
DYNAMICALLY BIASING A BULK NODE AND A GATE NODE OF A TRANSISTOR IN A DC-DC VOLTAGE CONVERTER
A method for operating a DC-DC converter includes generating an output voltage on an output node of the DC-DC converter based on an input voltage on an input node of the DC-DC converter using a transistor having a bulk terminal and a gate terminal, the output voltage being greater than the input voltage. The method includes coupling the input node to the bulk terminal and the gate terminal in response to the output voltage being less than the input voltage. The method includes coupling the output node to the bulk terminal in response to the output voltage exceeding the input voltage or a predetermined threshold voltage.
H02M 3/158 - Conversion of dc power input into dc power output without intermediate conversion into ac by static converters using discharge tubes with control electrode or semiconductor devices with control electrode using devices of a triode or transistor type requiring continuous application of a control signal using semiconductor devices only with automatic control of output voltage or current, e.g. switching regulators including plural semiconductor devices as final control devices for a single load
H02M 1/36 - Means for starting or stopping converters
H02M 1/00 - APPARATUS FOR CONVERSION BETWEEN AC AND AC, BETWEEN AC AND DC, OR BETWEEN DC AND DC, AND FOR USE WITH MAINS OR SIMILAR POWER SUPPLY SYSTEMS; CONVERSION OF DC OR AC INPUT POWER INTO SURGE OUTPUT POWER; CONTROL OR REGULATION THEREOF - Details of apparatus for conversion
In one aspect, a method includes: enabling, via a controller of a network device, a receiver of the network device for a plurality of receive fragments during a receive duration; analyzing a signal fragment received during at least one of the plurality of receive fragments to identify possible presence of a wake-up frame sent by a coordinator device; and in response to the identification of the possible presence of the wake-up frame, enabling the receiver to receive and detect another wake-up frame.
A wireless communication device has a receiver to listen to a sequence of channels. A controller responds to a preamble being detected on a first channel while the receiver is tuned to the first channel by causing the receiver to stay on the first channel and decode packet(s) associated with the preamble. The controller responds to detection of a first symbol of a first transmission protocol and the preamble not being detected to cause the receiver to stay on the first channel for a predetermined time waiting for a retry. The controller responds to detection of a second symbol of a second transmission protocol and the preamble not being detected to cause the receiver to switch to an advertising channel of the second transmission protocol. If no preambles, noise, or symbols are detected, the receiver switches to listening to a next channel in the sequence after a fixed time.
H04L 5/00 - Arrangements affording multiple use of the transmission path
H04W 4/80 - Services using short range communication, e.g. near-field communication [NFC], radio-frequency identification [RFID] or low energy communication
H04W 4/23 - Services signalling; Auxiliary data signalling, i.e. transmitting data via a non-traffic channel for mobile advertising
33.
DETECTING ANOMALOUS EVENTS IN A DISCRIMINATOR OF AN EMBEDDED DEVICE
In an embodiment, an apparatus includes: a sensor to sense real world information; a digitizer coupled to the sensor to digitize the real world information into digitized information; a signal processor coupled to the digitizer to process the digitized information into an image; a discriminator coupled to the signal processor to determine, based at least in part on the image, whether the real world information comprises an anomaly, where the discriminator is trained via a generative adversarial network; and a controller coupled to the discriminator.
In at least one embodiment, a method for measuring a distance between a first communications device including a first local oscillator and a second communications device including a second local oscillator includes unwrapping N phase values to generate N unwrapped phase values. N is an integer greater than one. Each of the N phase values indicate an instantaneous phase of a received signal. The method includes averaging the N unwrapped phase values to generate an average phase value. The method includes wrapping the average phase value to generate a final phase measurement of the first local oscillator with respect to the second local oscillator.
A phase-locked loop (PLL) that provides a local oscillator signal for a radio. An oscillator of the PLL supplies an oscillator output signal. Control logic receives a request to change the oscillator output signal to a new frequency and responds to the request by setting a first capacitor circuit of the oscillator to a first capacitance that corresponds to a predetermined frequency of the oscillator output signal. The control logic also responds to the request by setting one or more other capacitor circuits of the oscillator according to temperature and according to a frequency difference between the predetermined frequency and the new frequency. After responding to the request by setting the first capacitor circuit and the one or more other capacitor circuits, the PLL locks to the new frequency using a signal from the PLL loop filter to adjust another capacitor circuit in the oscillator.
H03L 7/107 - Automatic control of frequency or phase; Synchronisation using a reference signal applied to a frequency- or phase-locked loop - Details of the phase-locked loop for assuring initial synchronisation or for broadening the capture range using a variable transfer function for the loop, e.g. low pass filter having a variable bandwidth
H03L 7/099 - Automatic control of frequency or phase; Synchronisation using a reference signal applied to a frequency- or phase-locked loop - Details of the phase-locked loop concerning mainly the controlled oscillator of the loop
36.
Commissioning of Lighting Systems using Bluetooth Direction Finding
A system and method for the commissioning of a lighting system is disclosed. The lighting system includes a plurality of lighting devices and a plurality of locators. Each lighting device includes a light emitting element and a wireless tag. After the lighting system is installed, each lighting device transmits one or more packets that contain a constant tone extension (CTE). This CTE allows the locators to determine the angle of arrival of the incoming packet. By combining the angles of arrival from several locators, it is possible to ascertain the physical location of the lighting device that transmitted the CTE. In this way, the physical location of each lighting device can be correlated to its network address.
A receiver concurrently demodulates data transmitted with a plurality of protocols. The receiver utilizes multiple and simultaneous protocol detections at preamble and/or packet payload phases. To provide robust detection and achieve fewer false detections, the receiver extends the cross correlation length once a short cross-correlation is valid. The receiver includes a first demodulator path and a second demodulator path with different filter bandwidths. The second demodulator path includes a decimator that reduces data by two. A correlator bank is coupled to the first and second demodulator paths and concurrently detects preamble symbols associated with a plurality of protocols. A first noise detector is coupled to the first demodulator path and a second noise detector is coupled to the second demodulator path. A first symbol identifier circuit is coupled to the first demodulator path and a second symbol identifier circuit coupled to the second demodulator path to provide packet payload symbol detection.
An external nonvolatile memory device that includes a rewritable nonvolatile memory and a CMOS interface is disclosed. The interface includes a clock signal which is input to the external nonvolatile memory device. This clock signal is multiplied by an integer to create a memory serdes clock which is used to clock outgoing data. The memory serdes clock is also used to create a clock that is used to clock the incoming data from the main processing device. The external nonvolatile memory device also includes an encryption/decryption block that encrypts data read from the nonvolatile memory before it is transmitted over the interface, and decrypts data received from the interface before storing it in the nonvolatile memory. The encryption/decryption block may utilize a stream cipher.
In one embodiment, an analog-to-digital converter includes: a sum circuit to receive an analog input signal and a feedback reference signal and generate a sum signal; a feedback circuit coupled to the sum circuit to provide the feedback reference signal to the sum circuit; a filter coupled to the sum circuit to receive the sum signal and generate a filtered signal; and a punctured quantizer coupled to the filter to receive the filtered signal and quantize the filtered signal to a digital output and to output the digital output and to provide the digital output to the feedback circuit.
An interface between two devices is disclosed. To consume power, the signals used in the interface utilize CMOS signalling. Further, to achieve high speed, a reduced frequency clock is transmitted from one device to the second device. The second device has a clock multiplier to recreate the original clock. Both devices utilize a clock phase alignment block which aligns the phase of the clock with the incoming data. The clock phase alignment block utilizes a digital PLL to consume power. Further, since the digital PLL retains its state, the reduced frequency clock may be disabled when data is not being transmitted. This interface may be used to transmit serial data at rates up to and exceeding 2.5 Gbits/sec.
An ultra low power network device is disclosed. The network device utilizes a Near Field Communications (NFC) tag to enable ultra low power communications with a configuration tool. The configuration tool writes information to the NFC tag that is accessible by the processing unit on the ultra low power network device. Additionally, the processing unit can write information into the NFC tag that is readable by the configuration tool. By exchanging messaged in this manner, the ultra low power network device and the configuration tool may create a shared encryption key. The ultra low power network device utilizes this shared encryption key when transmitting BLUETOOTH® packets. The configuration tool may then transmit the shared encryption key to either another BLUETOOTH® device or to a remote server. The ultra low power network device may also periodically refresh the shared encryption key.
H04W 4/80 - Services using short range communication, e.g. near-field communication [NFC], radio-frequency identification [RFID] or low energy communication
H04L 9/30 - Public key, i.e. encryption algorithm being computationally infeasible to invert and users' encryption keys not requiring secrecy
H04L 9/32 - Arrangements for secret or secure communications; Network security protocols including means for verifying the identity or authority of a user of the system
A system for securely transmitting data between two devices is disclosed. Each device comprises an interface, an encryption module, a decryption module and a message authentication code (MAC) generator. The encryption and decryption modules may utilize a stream cipher, while the MAC generator utilizes a hashing algorithm. A MAC is transmitted after a predetermined amount of time, regardless of the amount of activity on the interface. The device receiving the MAC compares it to the MAC that it generated to ensure that they match. This guarantees that a breach of integrity can be detected in a reasonable amount of time and addressed accordingly. This system may utilize an interface having bidirectional data signals or unidirectional data signals.
H04L 9/32 - Arrangements for secret or secure communications; Network security protocols including means for verifying the identity or authority of a user of the system
A mesh receiver has a wakeup receiver for reception of a wakeup sequence formed by keyed RF or a sequence of wireless packets and gaps, a transmitter forming low speed RF wakeup sequence to other mesh stations, a mesh receiver for reception of high speed WLAN packets, the transmitter sending a wireless ACK packet in response to a wakeup sequence, the mesh receiver thereafter receiving wireless packets from a remote station, the mesh transmitter sending an ACK, the mesh station thereafter identifying a next hop station, and sending a wakeup sequence to that station, after receipt of an ACK, sending the data, the mesh receiver and mesh transmitter thereafter going to sleep.
A system that includes a Viterbi Equalizer having adaptive signal levels is disclosed. Each branch metric of the Viterbi Equalizer compares the value of the incoming bit to one of a plurality of different expected signal levels. A set of default signal values may be used by the Viterbi Equalizer. The system is also configured to determine whether these default expected signal levels are acceptable by monitoring the incoming data bits. If it is determined that the actual signal levels of the incoming data bits differ from the default expected signal levels by more than a predetermined amount, the signal levels used by the Viterbi Equalizer may be changed from default signal levels to the adaptive signal levels. The adaptive signal levels may be determined using the synchronization pattern.
09 - Scientific and electric apparatus and instruments
42 - Scientific, technological and industrial services, research and design
Goods & Services
Integrated circuits; computers; semi-conductors; modems; integrated radio frequency transceivers, synthesizers and tuners; transmitters of electronic signals; data processing apparatus; circuit boards; downloadable computer software development tools; downloadable software development kits (SDK) Integrated circuit design; computer software design; design of synthesizers and tuners; technical support services, namely, troubleshooting problems related to semiconductor components; technical support services and training in the field of product integration, product programming, product configuration and product evaluation
09 - Scientific and electric apparatus and instruments
42 - Scientific, technological and industrial services, research and design
Goods & Services
(1) Integrated circuits; computers; semi-conductors; modems; integrated radio frequency transceivers, synthesizers and tuners; transmitters of electronic signals; software development tools; software development kits. (1) Integrated circuit design; computer software design; design of synthesizers and tuners; technical support services, namely, troubleshooting problems related to semiconductor components.
09 - Scientific and electric apparatus and instruments
42 - Scientific, technological and industrial services, research and design
Goods & Services
(1) Integrated circuits; computers; semi-conductors; modems; integrated radio frequency transceivers, synthesizers and tuners; transmitters of electronic signals; software development tools; software development kits. (1) Integrated circuit design; computer software design; design of synthesizers and tuners; technical support services, namely, troubleshooting problems related to semiconductor components.
09 - Scientific and electric apparatus and instruments
42 - Scientific, technological and industrial services, research and design
Goods & Services
(1) Integrated circuits; computers; semi-conductors; modems; integrated radio frequency transceivers, synthesizers and tuners; transmitters of electronic signals; software development tools; software development kits. (1) Integrated circuit design; computer software design; design of synthesizers and tuners; technical support services, namely, troubleshooting problems related to semiconductor components.
49.
SYSTEM AND METHOD FOR DETECTING OF CHANNEL CONDITIONS AND CHANNEL ESTIMATION IN AN ORTHOGONAL FREQUENCY DIVISION MULTIPLEXING (OFDM) RECEIVER
In one aspect, an apparatus includes: a front end circuit to receive and process incoming radio frequency (RF) signals into orthogonal frequency division multiplexing (OFDM) samples; a fast Fourier transform (FFT) engine to receive and convert the OFDM samples into frequency domain sub-carriers; a demodulator to demodulate the frequency domain sub-carriers; a channel estimator to: compute a first pilot channel estimate for a first channel condition comprising a flat channel condition and a second pilot channel estimate for a second channel condition comprising a selective channel condition based on a first set of pilot sub-carriers of the frequency domain sub-carriers; and select one of the first and second pilot channel estimates using the first and second pilot channel estimate; and a control circuit to configure at least the demodulator based at least in part on the selected first or second pilot channel estimate.
A first three state driver injects a first clock signal into a crystal through an input node during a startup phase of a crystal oscillator and a second three state driver injects a second signal into the crystal through an output node during the startup phase. The first and second signals are anti-phase signals. The crystal oscillator circuit includes a first amplifier that is used during starting up and steady-state operation and includes a second amplifier. The injection through the input and output nodes is disabled after a fixed time. After injection ends, the second amplifier is turned on if voltage on the output node has reached a desired voltage and left off otherwise. If the second amplifier is turned on, the second amplifier is turned off when the voltage on the output node reaches the desired voltage.
H03B 5/06 - Modifications of generator to ensure starting of oscillations
H03B 5/36 - Generation of oscillations using amplifier with regenerative feedback from output to input with frequency-determining element being electromechanical resonator being a piezoelectric resonator active element in amplifier being semiconductor device
H03L 7/099 - Automatic control of frequency or phase; Synchronisation using a reference signal applied to a frequency- or phase-locked loop - Details of the phase-locked loop concerning mainly the controlled oscillator of the loop
51.
Utilizing the LC oscillator of a frequency synthesizer as an injection source for crystal oscillator startup
A frequency synthesizer on an integrated circuit provides a local oscillator (LO) signal for RF operations and also functions as an injection clock signal source during crystal oscillator startup. The integrated circuit goes into a sleep mode in which the crystal oscillator is off and responsive to a wakeup event the crystal oscillator starts up again using the injection clock signal sourced from the frequency synthesizer. Parameters that cause the injection clock signal to match the crystal oscillator frequency are stored. The frequency synthesizer includes a phase-locked loop having an LC oscillator. A digital to analog converter controls the LC oscillator during injection. During an initial power up of the integrated circuit, a PLL in the frequency synthesizer locks to the crystal oscillator frequency to determine the parameters to store for injection.
H03B 5/06 - Modifications of generator to ensure starting of oscillations
H03B 5/36 - Generation of oscillations using amplifier with regenerative feedback from output to input with frequency-determining element being electromechanical resonator being a piezoelectric resonator active element in amplifier being semiconductor device
H03L 7/099 - Automatic control of frequency or phase; Synchronisation using a reference signal applied to a frequency- or phase-locked loop - Details of the phase-locked loop concerning mainly the controlled oscillator of the loop
52.
Delayed Preamble Detection for Bluetooth Receiver based on Interferer Metrics
The present invention relates to a method and apparatus for reducing power consumption in a receiver of a time slotted communication system. An RF front end has power applied after the start of a preamble or after the start of a header, or upon the start of a packet payload based on connection status, signal level, and interference level. Where the signal level is constant, the communication system is in a connected state, and the interference level is low, the system bypasses packet header destination address matching, or optionally, uses only the least significant bits of the header destination address for matching purposes.
In one embodiment, a dual-mode power amplifier that can operate in different modes includes: a first pair of metal oxide semiconductor field effect transistors (MOSFETs) to receive and pass a constant envelope signal; a second pair of MOSFETs to receive and pass a variable envelope signal, where first terminals of the first pair of MOSFETs are coupled to first terminals of the second pair of MOSFETs, and second terminals of the first pair of MOSFETs are coupled to. second terminals of the second pair of MOSFETs; and a shared MOSFET stack coupled to the first pair of MOSFETs and the second pair of MOSFETs.
A system and method for accurately determining a distance between two network devices using a Channel Sounding application is disclosed. The network devices each guarantee a fixed phase relationship between the transmit circuit and the receive circuit. In one embodiment, this is achieved by disposing the divider outside the phase locked loop and using the output of the divider to create the clocks for both the transmit circuit and receive circuit. In another embodiment, one or more dividers are disposed outside the phase locked loop, each having a reset, such that they can be initialized to a predetermined state. Further, by utilizing a divider with a reset, the quadrature signal generator is guaranteed to output clocks for the transmit circuit and the receive circuit that have a constant phase relationship.
H04W 64/00 - Locating users or terminals for network management purposes, e.g. mobility management
H04L 7/033 - Speed or phase control by the received code signals, the signals containing no special synchronisation information using the transitions of the received signal to control the phase of the synchronising-signal- generating means, e.g. using a phase-locked loop
55.
SYSTEM, METHOD AND APPARATUS TO REDUCE ERROR IN UNUSED TONES IN PARTIAL BANDWIDTH WIRELESS TRANSMISSION SYSTEM
In one embodiment, an apparatus includes: a compensation circuit to select one of a plurality of compensation sets based on an allocated resource unit (RU) and compensate a digital complex signal using the selected compensation set; a digital-to-analog converter to convert the compensated digital complex signal to a compensated analog complex signal; a mixer coupled to the digital-to-analog converter to upconvert the compensated analog complex signal to a radio frequency (RF) signal; and a power amplifier coupled to the mixer to amplify the RF signal.
In one embodiment, an apparatus includes: a radio frequency (RF) front end circuit to receive and downconvert a RF signal to a second frequency signal, the RF signal comprising an orthogonal frequency division multiplexing (OFDM) transmission; a digitizer coupled to the RF front end circuit to digitize the second frequency signal to a digital signal; and a baseband processor coupled to the digitizer to process the digital signal. The baseband circuit comprises a first circuit having a first plurality of correlators having an irregular comb structure, each of the first plurality of correlators associated with a carrier frequency offset and to calculate a first correlation on a first portion of a preamble of the OFDM transmission.
In one embodiment, a method includes: enabling a pulse pair circuit of an integrated circuit in response to determining that a receiver associated with the integrated circuit is active; identifying that at least one comparator of a multi-output DC-DC converter trips, the DC-DC converter having a plurality of comparators each to compare a regulated voltage output by the DC-DC converter to a corresponding reference voltage; and generating, in the pulse pair circuit, a control pulse pair according to the tripped output, and driving a driver circuit of the DC-DC converter using the control pulse pair.
H02M 3/157 - Conversion of dc power input into dc power output without intermediate conversion into ac by static converters using discharge tubes with control electrode or semiconductor devices with control electrode using devices of a triode or transistor type requiring continuous application of a control signal using semiconductor devices only with automatic control of output voltage or current, e.g. switching regulators with digital control
H02M 1/00 - APPARATUS FOR CONVERSION BETWEEN AC AND AC, BETWEEN AC AND DC, OR BETWEEN DC AND DC, AND FOR USE WITH MAINS OR SIMILAR POWER SUPPLY SYSTEMS; CONVERSION OF DC OR AC INPUT POWER INTO SURGE OUTPUT POWER; CONTROL OR REGULATION THEREOF - Details of apparatus for conversion
59.
SWITCHING POWER AMPLIFIER WITH OUTPUT HARMONIC SUPPRESSION
A switching power amplifier with harmonic suppression including a polyphase converter and a power amplifier stage. The polyphase converter converts a frequency or phase modulated input signal into a 50% duty cycle rail-to-rail signal, a positive 25% duty cycle rail-to-rail signal that is centered with the 50% duty cycle signal when high, and a negative 25% duty cycle rail-to-rail signal that is centered with the 50% duty cycle signal when low. The power amplifier stage includes first and second branches coupled between upper and lower nodes, each including series-coupled P-channel and N-channel transistors forming an intermediate output node. The transistors of the first branch are controlled by the 50% duty cycle signal, and the transistors of the second branch are controlled by the positive and negative 25% duty cycle signals. The first and second branches generate output currents that are superimposed with each other to suppress third and fifth harmonics.
H03F 3/217 - Class D power amplifiers; Switching amplifiers
H03L 7/081 - Automatic control of frequency or phase; Synchronisation using a reference signal applied to a frequency- or phase-locked loop - Details of the phase-locked loop provided with an additional controlled phase shifter
60.
Transceiver With Multi-Channel Clear Channel Assessment
A wireless network device configured to monitor multiple channels for clear channel assessment (CCA) is disclosed. The receiver circuit of the network device comprises at least one CCA block, which is used to indicated whether a particular channel is clear. In certain embodiments, the network device checks each channel sequentially, and if both channels are free, transmits at least one packet. The at least one packet may include a MODE SWITCH packet and a second packet sent using the new PHY mode. The network device may also have multiple CCA blocks. In this scenario, the channels may be checked concurrently, and if both channels are free, the network device transmits at least one packet. Alternatively, the network device monitors multiple channels concurrently and selected one of the channels on which to transmit a preferred PHY mode, thereby avoiding the need for a MODE SWITCH packet.
In one embodiment, an apparatus includes: an oscillator to output a clock signal on a first line; a switch coupled to the first line; and a voltage divider coupled to the switch. The switch may be controlled to output the clock signal through the voltage divider via the first line to a pin in a non-reset mode and prevent the clock signal from being provided to the pin in a reset mode.
H03K 5/135 - Arrangements having a single output and transforming input signals into pulses delivered at desired time intervals by the use of time reference signals, e.g. clock signals
G01R 31/28 - Testing of electronic circuits, e.g. by signal tracer
In one embodiment, a method includes: powering on an integrated circuit (IC) and causing the IC to enter into a reset mode, where in the reset mode, a switch coupled between an oscillator of the IC and a reset pin is open; releasing the reset pin to cause the IC to enter into a non-reset mode, where in the non-reset mode the switch is closed to cause the clock signal to be superimposed on a reset signal at the reset pin; and determining, via a monitoring circuit coupled to the IC, the IC as functional in response to identifying the clock signal superimposed on the reset signal at the reset pin.
A flip-flop including a scan enable input for receiving a scan enable signal, a clock input for receiving a clock signal, input select circuitry that is configured to select between a data input and a scan input based on a state of the scan enable signal for providing a selected input, latching circuitry that is configured to latch the selected input to a preliminary output node in response to transitions of the clock signal, and output select circuitry that is configured to provide a state of the preliminary output node to a selected one of a scan output and a data output based on a state of the scan enable signal. The flip-flop may be implemented using fast yet leaky transistors. The data output may be disabled to prevent toggling other circuitry when scanning into or out of a memory for data retention.
In one embodiment, a method includes: laser ablating an encapsulant of a semiconductor package, until a threshold amount of the encapsulant remains above one or more die of the semiconductor package; and providing at least one drop of acid onto a surface of the ablated semiconductor package to acid etch for a first time duration, to remove a remaining portion of the encapsulant above the one or more die, where after the acid etch, a die of interest is exposed and the silver bond wires of the semiconductor package are preserved.
H01L 21/56 - Encapsulations, e.g. encapsulating layers, coatings
H01L 23/00 - SEMICONDUCTOR DEVICES NOT COVERED BY CLASS - Details of semiconductor or other solid state devices
H01L 23/31 - Encapsulation, e.g. encapsulating layers, coatings characterised by the arrangement
H01L 23/552 - Protection against radiation, e.g. light
H01L 21/67 - Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components
A temperature sensor that is insensitive to process variation and mismatch is disclosed. The temperature sensor includes a PTAT voltage generator, a sampling and gain boosting circuit, a filter and a controller. The PTAT voltage generator utilizes a plurality of current sources, each of which is in electrical communication with the same diode, or diode stack. The output of the PTAT voltage generator is sampled and amplified with the sampling and gain boosting circuit. The output of the sampling and gain boosting circuit is then filtered using a low pass filter. The selection of the current mirrors, the sampling timing and other signals are provided by the controller. In some simulations, the output from the temperature sensor was accurate to within 1.5° C., using a one temperature calibration process.
An apparatus includes a module comprising an antenna having at least one antenna component. The apparatus further includes at least one tuning component coupled to the at least one antenna component. The at least one tuning component is external to the module.
H01Q 1/14 - Supports; Mounting means for wire or other non-rigid radiating elements
H01Q 7/00 - Loop antennas with a substantially uniform current distribution around the loop and having a directional radiation pattern in a plane perpendicular to the plane of the loop
In one embodiment, an integrated circuit includes: a first radio frequency (RF) circuit configured to receive and process a first RF signal having a sub-gigahertz (GHz) frequency to output a first lower frequency signal and to transmit RF signals having the sub-GHz frequency; a second RF circuit configured to receive and process a second RF signal having a frequency of at least substantially 2.4 GHz to output a second lower frequency signal and to transmit RF signals at the at least substantially 2.4 GHz; shared analog circuitry coupled to the first RF circuit and the second RF circuit, the shared analog circuitry to receive at least one of the first RF signal or the second RF signal and output a digital output signal; and a digital circuit coupled to the shared analog circuit, the digital circuit to recover message information from the digital output signal.
A switch activation system including a charge pump, a load monitor, and a switch driver. The charge pump drives a negative voltage node to a predetermined negative voltage level. The load monitor monitors the charge pump and to assert a break done signal after the charge pump begins driving the negative voltage back to the predetermined negative voltage level after being increased. The switch driver turns on a first electronic switch in response to assertion of a corresponding activation signal and assertion of the break done signal. The break done signal is asserted only after electronic switches being turned off are fully turned off to avoid conflict. The charge pump operates at a frequency based on a difference between a voltage level of the negative voltage node and the predetermined negative voltage level to drive the negative voltage node back to its predetermined level within a predetermined period of time.
H02M 3/07 - Conversion of dc power input into dc power output without intermediate conversion into ac by static converters using resistors or capacitors, e.g. potential divider using capacitors charged and discharged alternately by semiconductor devices with control electrode
69.
System, apparatus and method for acquisition of signals in wireless systems with adverse oscillator variations
In one aspect, a radio device comprises: an analog front end (AFE) circuit to receive and process an incoming radio frequency (RF) signal comprising a packet; an analog-to-digital converter (ADC) coupled to the AFE circuit to receive and digitize the processed incoming RF signal into a digital signal; a detector coupled to the ADC to detect a carrier frequency offset (CFO) in the digital signal based at least in part on a preamble of the packet; and a controller coupled to the detector. The controller may generate a compensation value for the CFO based on the detected CFO and cause one or more components of the radio device to compensate for the CFO using the compensation value.
An apparatus for measuring a current being supplied to a load includes a first pass transistor to couple a first sense resistance to the load when the first pass transistor is enabled and a second pass transistor to couple a second sense resistance to the load when the second pass transistor is enabled. An error amplifier determines a difference between a voltage being supplied to the load and a reference voltage and to supplies an error amplifier output signal according to the difference. A switch couples the error amplifier output signal to a gate of the first pass transistor or to a gate of the second pass transistor. Control logic controls the switch according to a value of the current being supplied to the load. The voltage being supplied to the load is controlled using the error amplifier output signal that is selectively coupled to the gate of the first pass transistor or the gate of the second pass transistor.
G05F 1/575 - Regulating voltage or current wherein the variable actually regulated by the final control device is dc using semiconductor devices in series with the load as final control devices characterised by the feedback circuit
In one embodiment, an apparatus includes: a radio frequency (RF) front end circuit to receive and downconvert a RF signal to a second frequency signal, the RF signal comprising an orthogonal frequency division multiplexing (OFDM) transmission; a digitizer coupled to the RF front end circuit to digitize the second frequency signal to a digital signal; and a baseband processor coupled to the digitizer to process the digital signal. The baseband circuit comprises a first circuit having a first plurality of correlators having an irregular comb structure, each of the first plurality of correlators associated with a carrier frequency offset and to calculate a first correlation on a first portion of a preamble of the OFDM transmission.
A software system for use with a network controller is disclosed. The software system comprises a plurality of modules, wherein some of the modules are specific to the network protocol used by the network controller. Other modules are usable for a variety of network protocols without modification. In this way, the development of the software for a network controller may be simplified resulting in less development time. Further, this system allows for flexibility to add attributes and rules at any time without modification to most of the system. The software system includes an attribute store, a resolver engine, a frame handler, a frame transmitter and a frame receiver.
The present invention relates to a method and apparatus for reducing power consumption in a receiver of a time slotted communication system. An RF front end has power applied after the start of a preamble or after the start of a header, or upon the start of a packet payload based on connection status, signal level, and interference level. Where the signal level is constant, the communication system is in a connected state, and the interference level is low, the system bypasses packet header destination address matching, or optionally, uses only the least significant bits of the header destination address for matching purposes.
H04W 52/52 - Transmission power control [TPC] using AGC [Automatic Gain Control] circuits or amplifiers
H04W 4/80 - Services using short range communication, e.g. near-field communication [NFC], radio-frequency identification [RFID] or low energy communication
A receiver for OFDM subcarriers has a first mode and a second mode. In the first mode, a tunable system clock is output at a nominal frequency, and in the second mode, the tunable system clock is offset so that a harmonic of the tunable system clock coincides with a particular OFDM subcarrier. The tunable system clock is coupled to a programmable modem PLL clock generator which generates clocks for an A/D converter coupled to a baseband processor which is also coupled to the programmable modem PLL clock generator. The programmable modem PLL clock generator is programmed to maintain a constant output frequency of each output in the first mode and the second mode.
H04L 5/00 - Arrangements affording multiple use of the transmission path
H03L 7/07 - Automatic control of frequency or phase; Synchronisation using a reference signal applied to a frequency- or phase-locked loop using several loops, e.g. for redundant clock signal generation
G06F 1/08 - Clock generators with changeable or programmable clock frequency
H04B 1/10 - Means associated with receiver for limiting or suppressing noise or interference
75.
One-way phase-based high accuracy distance measurement apparatus and algorithm
A system and method for one-way ranging is disclosed. The system comprises a transmitter, also referred to as a tag, transmitting a first frequency in a first frequency group. The receiver, also referred to as the locator, receives the first frequency and measures the phase at a first point in time. At a later time, the transmitter switches to a second frequency, which is close in frequency to the first frequency so as to also be part of the first frequency group. The receiver also switches to the second frequency. The receiver then measures the phase of the second frequency at a second point in time. The transmitter and receiver then repeat this sequence for a second frequency group. The four phase measurements are used to determine the distance from the transmitter to the receiver. In this way, improved accuracy may be achieved by having a large separation between the first frequency group and the second frequency group.
A system and method for one-way ranging is disclosed. The system comprises a transmitter, also referred to as tag, transmitting a packet having a first frequency. The receiver, also referred to as the locator, receives the first frequency and measures the phase at a specific point in time. At a predetermined time, the transmitter switches to a second frequency. This is performed while maintaining phase continuity. The receiver also switches to the second frequency at nearly the same time. The receiver then measures the phase of the second frequency at a second point in time. Based on these two phase measurements, the distance between the transmitter and the receiver may be calculated.
G01S 13/40 - Systems for measuring distance only using transmission of continuous waves, whether amplitude-, frequency-, or phase-modulated, or unmodulated with phase comparison between the received signal and the contemporaneously transmitted signal wherein the frequency of transmitted signal is adjusted to give a predetermined phase relationship
G01S 5/02 - Position-fixing by co-ordinating two or more direction or position-line determinations; Position-fixing by co-ordinating two or more distance determinations using radio waves
77.
Generating a preamble portion of an orthogonal frequency division multiplexing transmission using complex sequence values optimized for minimum Peak-to-Average Power Ratio
In one embodiment, an apparatus includes: a baseband processor having a preamble generation circuit to generate a preamble for an orthogonal frequency division multiplexing (OFDM) transmission, the preamble generation circuit to generate the preamble having a first portion comprising a first plurality of symbols, each of the first plurality of symbols having a plurality of carriers, where a subset of the plurality of carriers have non-zero values, the preamble generation circuit to generate the non-zero values using a sequence of complex values selected to optimize a peak-to-average power ratio (PAPR); a digital-to-analog converter (DAC) coupled to the baseband processor to convert the first plurality of symbols to analog signals; a mixer coupled to the DAC to upconvert the analog signals to radio frequency (RF) signals; and a power amplifier coupled to the mixer to amplify the RF signals.
In one embodiment, a dual-mode power amplifier that can operate in different modes includes: a first pair of metal oxide semiconductor field effect transistors (MOSFETs) to receive and pass a constant envelope signal; a second pair of MOSFETs to receive and pass a variable envelope signal, where first terminals of the first pair of MOSFETs are coupled to first terminals of the second pair of MOSFETs, and second terminals of the first pair of MOSFETs are coupled to. second terminals of the second pair of MOSFETs; and a shared MOSFET stack coupled to the first pair of MOSFETs and the second pair of MOSFETs.
Systems and methods for improving encrypted transmissions between nodes in a network are disclosed. In one embodiment, two sets of nonce values are used to monitor communications between each pair of network devices, wherein one set of nonce values is used for packets transmitted from a first node to a second node, and the second set of nonce values is used for packets transmitted from the second node to the first node. These nonce values are used to encrypt packets transmitted between the two nodes. In this way, the probability of loss of synchronization may be reduced, especially in configurations where there is an intermediate node between the first node and the second node. In another embodiment, the possibility of a delay attack is minimized by the intentional resetting of security parameters.
An apparatus includes an array processor to process array data. The array data are arranged in a memory. The array data are specified with programmable per-dimension size and stride values.
An apparatus includes an array processor to process array data in response to information contained in a packet, wherein the packet comprises a set of fields specifying configuration information for processing the array.
G06F 15/80 - Architectures of general purpose stored program computers comprising an array of processing units with common control, e.g. single instruction multiple data processors
G06F 13/28 - Handling requests for interconnection or transfer for access to input/output bus using burst mode transfer, e.g. direct memory access, cycle steal
G06F 9/30 - Arrangements for executing machine instructions, e.g. instruction decode
82.
Metamaterial Antenna Array with Isolated Antennas And Ground Skirt Along the Perimeter
An antenna array that utilizes ground guard rings and metamaterial structures is disclosed. In certain embodiments, the antenna array is constructed from a plurality of antenna unit cells, wherein each antenna unit cell is identical. The antenna unit cell comprises a top surface, that contains a patch antenna and a ground guard ring. A reactive impedance surface (RIS) layer is disposed beneath the top surface and contains the metamaterial structures. The metamaterial structures are configured to present an inductance to the patch antennas, thereby allowing the patch antennas to be smaller than would otherwise be possible. In some embodiments, the metamaterial structures comprise hollow square frames. An antenna array constructed using this antenna unit cell has less coupling than conventional antenna arrays, which results in better performance. A ground skirt surrounds the perimeter of the antenna array to improve radiation phase pattern balance within the array.
A printed circuit board having an AoX antenna array and a feeding circuit is disclosed. The AoX antenna array has patch antenna disposed on a top layer of the printed circuit board, while the feeding circuit is disposed on the bottom layer. The signal traces that connect the ports of the antenna unit cells to the antenna selection switches are routed so that all are roughly equal in length with a minimal length of parallel sections between signal traces. Thus, the signal traces in the feeding circuit are created so as to minimize phase difference between signal traces and to minimize coupling. Coplanar waveguides, which utilize blind vias are used to further reduce coupling.
A system and method for selecting a polarization for a particular antenna in an antenna array is disclosed. The system comprises an antenna array, wherein each antenna is adapted to receive and transmit horizontally and vertically polarized signals. The system also includes a switching network that is adapted to select the vertical or horizontal polarized signal for each antenna in the antenna array. The switching network also allows selection of a circular polarized signal from one or more of the antenna elements in the antenna array. This allows the AoX to be more accurate, as it is able to receive horizontally and vertically polarized signals, rather than just circular polarized signals, thereby improving its accuracy. The ability to receive circular polarized signals may be beneficial during reference periods to acquire the proper gain and frequency.
H01Q 21/24 - Combinations of antenna units polarised in different directions for transmitting or receiving circularly and elliptically polarised waves or waves linearly polarised in any direction
An antenna array that utilizes ground guard rings and metamaterial structures is disclosed. In certain embodiments, the antenna array is constructed from a plurality of antenna unit cells, wherein each antenna unit cell is identical. The antenna unit cell comprises a top surface, that contains a patch antenna and a ground guard ring. A reactive impedance surface (RIS) layer is disposed beneath the top surface and contains the metamaterial structures. The metamaterial structures are configured to present an inductance to the patch antennas, thereby allowing the patch antennas to be smaller than would otherwise be possible. In some embodiments, the metamaterial structures comprise hollow square frames. An antenna array constructed using this antenna unit cell has less coupling than conventional antenna arrays, which results in better performance. Furthermore, this new antenna array also requires less space than conventional antenna arrays.
An apparatus includes an array processor to process array data in response to a set of macro-instructions. A macro-instruction in the set of macro-instructions performs loop operations, array iteration operations, and/or arithmetic logic unit (ALU) operations.
An apparatus includes an array processor to process at least one array. The apparatus further includes a memory coupled to the array processor. The at least one array is stored in memory with programmable per-dimension size and stride values.
A wireless transceiver circuit with an impedance matching network within an integrated circuit is disclosed. In some embodiments, the impedance matching network utilizes an inductor, having two portions, disposed on two different metal layers of the integrated circuit. The first end of the first portion of the inductor is in communication with an antenna. The second end of the second portion is in communication with a low noise amplifier for receiving signals and a power amplifier for transmitting RF signals. The second end of the first portion is connected to the first end of the second portion using a via. In another embodiment, the two portions are disposed on the same metal layer, wherein one portion is disposed within the other with a gap separating the two portions. These configurations require less space than using two separate inductors and also have a low coupling coefficient.
An integrated circuit includes a capacitor with a bottom conductive plate and a top conductive plate. A passivation layer is disposed above the top conductive plate. An intermetal dielectric layer is disposed between the bottom conductive plate and the top conductive plate and is formed of a first dielectric material. Shield layers are disposed between the top conductive plate and above the intermetal dielectric layer and extend horizontally to at least past guard rings. The shield layers include a dielectric layer formed of dielectric material having a dielectric constant greater than the material of the intermetal dielectric layer. The shield layers include horizontally offset trenches to stop horizontal flow of current in the shield layers. The offset ensures there is no vertical path from the passivation layer to lower/ground potentials through the shield layers.
H01L 23/522 - Arrangements for conducting electric current within the device in operation from one component to another including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
H01L 21/71 - Manufacture of specific parts of devices defined in group
H01L 23/00 - SEMICONDUCTOR DEVICES NOT COVERED BY CLASS - Details of semiconductor or other solid state devices
A system and method for embedding a tool into an Integrated Development Environment (IDE) is disclosed. The system includes a special application programming interface (API) that is used to embed any tool into any IDE. The API provides a way for the tool to indicate what functions are supported by the tool. These functions may include save, print, edit and others. The API also provides a mechanism for the IDE to communicate to the tool that one of the supported functions is to be executed. Finally, the API provides a mechanism for the tool to report information to the IDE as necessary.
G06F 3/00 - Input arrangements for transferring data to be processed into a form capable of being handled by the computer; Output arrangements for transferring data from processing unit to output unit, e.g. interface arrangements
A system and method for detecting a multipath environment is disclosed. A first pseudospectrum based on azimuth angle and elevation angle is created. The result of this first pseudospectrum are used to create a second pseudospectrum based on polarization and field ratio. The sharpness of the results for these two pseudospectrums is determined and may be used to detect whether a multipath environment exists. If a multipath environment is believed to exist, the results from this device are ignored in determining the spatial position of the object.
G01S 3/02 - Direction-finders for determining the direction from which infrasonic, sonic, ultrasonic, or electromagnetic waves, or particle emission, not having a directional significance, are being received using radio waves
G01S 5/02 - Position-fixing by co-ordinating two or more direction or position-line determinations; Position-fixing by co-ordinating two or more distance determinations using radio waves
G01S 5/04 - Position of source determined by a plurality of spaced direction-finders
92.
FREQUENCY SELECTIVE ATTENUATOR FOR OPTIMIZED RADIO FREQUENCY COEXISTENCE
A wireless transceiver including a receiver circuit coupled to an RF transceiver node, a tunable notch filter coupled between the RF transceiver node and a reference node, and a controller that programs the tunable notch filter with a selected blocker frequency and that selectively enables the tunable notch filter to attenuate at least one blocker signal. The tunable notch filter may include a variable capacitor and an inductor coupled in series between the RF transceiver node and ground. The inductor of the tunable notch filter may include a bondwire coupled between a semiconductor die and a semiconductor package. The inductance may include a physical inductor mounted on the package or a printed circuit board. The tunable notch filter may be enabled by a switch selectively coupling the filter to either the RF transceiver node or ground. The variable capacitor may be digitally programmed with digital values stored in a memory.
In one embodiment, an apparatus includes a baseband circuit to generate a plurality of subcarriers of a complex sample of a message to be transmitted, and a compensation circuit coupled to the baseband circuit, the compensation circuit to compensate for IQ mismatch. The compensation circuit may include: a calibration circuit to determine, using a tone signal, gain correction values and phase correction values for a subset of the plurality of subcarriers; and a correction circuit to apply the gain correction values and the phase correction values to the plurality of subcarriers to compensate for the IQ mismatch.
In one embodiment, an apparatus comprises: a baseband processor having a preamble generation circuit to generate a preamble for an orthogonal frequency division multiplexing (OFDM) transmission, the preamble generation circuit to generate the preamble having a first portion comprising a first plurality of symbols and a second portion comprising a second plurality of symbols, where the preamble generation circuit is to generate at least some of the second plurality of symbols having at least one frequency disruption between successive symbols of the second portion; a digital-to-analog converter (DAC) coupled to the baseband processor to convert the first plurality of symbols and the second plurality of symbols to analog signals; a mixer coupled to the DAC to upconvert the analog signals to radio frequency (RF) signals; and a power amplifier coupled to the mixer to amplify the RF signals.
A loop type ground radiating antenna having dual resonance is disclosed. The antenna including a feeding path that traverses the ground clearance, creating a first portion and a second portion. One or more first capacitors are disposed along a first conductive path between the ground clearance and the edge of the ground layer, proximate the first portion, while one or more second capacitors are disposed along a second conductive path between the ground clearance and the edge of the ground layer, proximate the second portion. An input capacitor is used to feed the feeding path. The values of the input capacitor and the first capacitors determine a resonant frequency of the first feeding loop, while the values of the input capacitor and the second capacitors determine a resonant frequency of the second feeding loop. By proper selection of the capacitor values, a wide bandwidth may be created.
H01Q 7/00 - Loop antennas with a substantially uniform current distribution around the loop and having a directional radiation pattern in a plane perpendicular to the plane of the loop
96.
Apparatus for determining when an automatic gain control circuit has settled
In one embodiment, an apparatus includes: a low noise amplifier (LNA) to receive and amplify a radio frequency (RF) signal, the LNA having a first controllable gain; a mixer to downconvert the RF signal to a second frequency signal; a programmable gain amplifier (PGA) coupled to the mixer to amplify the second frequency signal, the PGA having a second controllable gain; a digitizer to digitize the second frequency signal to a digitized signal; a demodulator coupled to the digitizer to demodulate the digitized signal; an automatic gain control (AGC) circuit to control one or more of the first controllable gain and the second controllable gain; and an AGC settling circuit to cause the demodulator to begin operation in response to determining that the AGC circuit has settled.
A system and method for creating firmware patch files is disclosed. The method utilizes the Executable Linkable Format file that is created when the firmware image is created. By analyzing the ELF file, the patch creation software is able to identify functions and other data in the new firmware image. The patch creation software then compares these functions to corresponding functions in the old firmware image. The method then creates an edit sequence that may be used to transform the old firmware image into the new firmware image. The edit sequence is then converted into a series of opcodes, where each opcode is followed by at least one parameter. A patch program, disposed on a network device, is able to apply the patch file to update its firmware. This method creates a smaller patch file than other popular tools.
Bias circuit for a low noise amplifier of a front end interface of a radio frequency communication device that enables fast transitions between different operating modes
A bias circuit for a low noise amplifier of a front end interface of a radio frequency communication device including a bias generator providing a bias voltage on a bias node for the low noise amplifier, a first resistive device coupled between the bias node and an input of the low noise amplifier, a first switch coupled in parallel with the first resistive device, and mode control circuitry receiving a mode signal indicative of a mode change, in which the mode control circuitry, in response to a mode change, momentarily activates the first switch to bypass the first resistive device and momentarily increases current capacity of the bias generator. The mode control circuitry may also momentarily activate a second switch to bypass a second resistive device of the bias circuit. The mode control circuitry may increase a sink current of the bias generator in response to the mode change.
A power limiting system and method for a low noise amplifier of a front end interface of a radio frequency communication device. A voltage regulator provides a source voltage to the low noise amplifier having a nominal voltage level that optimizes linearity of the low noise amplifier while a power level of a radio frequency input signal provided to an input of the low noise amplifier does not exceed a predetermined power level threshold. Detection circuitry detects when the power level of a radio frequency input signal exceeds the predetermined power level threshold and provides an adjust signal indicative thereof to the voltage regulator to reduce the source voltage below the nominal voltage level.
An apparatus includes a digitally controlled oscillator (DCO), which includes an inductor coupled in series with a first capacitor. The DCO further includes a second capacitor coupled in parallel with the series-coupled inductor and first capacitor, a first inverter coupled in parallel with the second capacitor, and a second inverter coupled back-to-back to the first inverter. The DCO further includes a digital-to-analog-converter (DAC) to vary a capacitance of the first capacitor.
H03L 7/099 - Automatic control of frequency or phase; Synchronisation using a reference signal applied to a frequency- or phase-locked loop - Details of the phase-locked loop concerning mainly the controlled oscillator of the loop
H03L 7/085 - Automatic control of frequency or phase; Synchronisation using a reference signal applied to a frequency- or phase-locked loop - Details of the phase-locked loop concerning mainly the frequency- or phase-detection arrangement including the filtering or amplification of its output signal
H03B 5/12 - Generation of oscillations using amplifier with regenerative feedback from output to input with frequency-determining element comprising lumped inductance and capacitance active element in amplifier being semiconductor device
H03L 7/14 - Automatic control of frequency or phase; Synchronisation using a reference signal applied to a frequency- or phase-locked loop - Details of the phase-locked loop for assuring constant frequency when supply or correction voltages fail
H03L 7/189 - Indirect frequency synthesis, i.e. generating a desired one of a number of predetermined frequencies using a frequency- or phase-locked loop using a frequency divider or counter in the loop a time difference being used for locking the loop, the counter counting between fixed numbers or the frequency divider dividing by a fixed number using means for coarse tuning the voltage controlled oscillator of the loop comprising a D/A converter for generating a coarse tuning voltage
H03L 7/197 - Indirect frequency synthesis, i.e. generating a desired one of a number of predetermined frequencies using a frequency- or phase-locked loop using a frequency divider or counter in the loop a time difference being used for locking the loop, the counter counting between numbers which are variable in time or the frequency divider dividing by a factor variable in time, e.g. for obtaining fractional frequency division
