Abstract

An electronic module is disclosed. The electronic module includes an electronic component and an interconnection structure disposed over the electronic component. The interconnection structure comprises a first region and a second region different from the first region. The first region is configured to transmit a power from outside of the electronic module to the electronic component. The second region is configured to dissipate heat from the electronic component.

IPC Classes  ?

• H01L 23/538 - Arrangements for conducting electric current within the device in operation from one component to another the interconnection structure between a plurality of semiconductor chips being formed on, or in, insulating substrates
• H01L 23/00 - SEMICONDUCTOR DEVICES NOT COVERED BY CLASS - Details of semiconductor or other solid state devices
• H01L 23/367 - Cooling facilitated by shape of device
• H01L 23/498 - Leads on insulating substrates
• H01L 23/552 - Protection against radiation, e.g. light
• H01L 25/16 - Assemblies consisting of a plurality of individual semiconductor or other solid state devices the devices being of types provided for in two or more different main groups of groups , or in a single subclass of , , e.g. forming hybrid circuits

Abstract

The present disclosure provides an electronic wearable device. The electronic wearable device includes a first module having a first contact and a second module having a second contact. The first contact is configured to keep electrical connection with the second contact in moving with respect to each other during a wearing period.

IPC Classes  ?

• G06F 1/16 - Constructional details or arrangements

Abstract

A semiconductor device package comprises a semiconductor device, a first encapsulant surrounding the semiconductor device, a second encapsulant covering the semiconductor device and the first encapsulant, and a redistribution layer extending through the second encapsulant and electrically connected to the semiconductor device.

IPC Classes  ?

• H01L 23/00 - SEMICONDUCTOR DEVICES NOT COVERED BY CLASS - Details of semiconductor or other solid state devices
• H01L 21/48 - Manufacture or treatment of parts, e.g. containers, prior to assembly of the devices, using processes not provided for in a single one of the groups
• H01L 21/56 - Encapsulations, e.g. encapsulating layers, coatings
• H01L 23/16 - Fillings or auxiliary members in containers, e.g. centering rings
• H01L 23/31 - Encapsulation, e.g. encapsulating layers, coatings characterised by the arrangement
• H01L 23/538 - Arrangements for conducting electric current within the device in operation from one component to another the interconnection structure between a plurality of semiconductor chips being formed on, or in, insulating substrates

Abstract

An electronic device is disclosed. The electronic device includes a system board and a first set of electronic devices disposed over the system board. Each of the first set of electronic devices comprises a processing unit and a carrier carrying the processing unit. The electronic device also includes a first interconnection structure electrically connected with the processing unit through the carrier and configured to receive a first power from a first power supply unit and to transmit the first power to the processing unit.

IPC Classes  ?

• H05K 1/14 - Structural association of two or more printed circuits

Abstract

An electronic device and a method for manufacturing the same are provided. The electronic device includes a carrier, an antenna element and a cladding element. The carrier defines a first area and a second area adjacent to the first area. The antenna element is in the first area. The cladding element covers the antenna element and is configured for enhancing antenna gain of the antenna element. The second area is exposed from the cladding element and is distant from the antenna element.

IPC Classes  ?

• H01Q 1/22 - Supports; Mounting means by structural association with other equipment or articles
• H01L 23/66 - High-frequency adaptations
• H01Q 1/38 - Structural form of radiating elements, e.g. cone, spiral, umbrella formed by a conductive layer on an insulating support

Abstract

An electronic device and a method for manufacturing the same are provided. The electronic device includes a substrate, an encapsulant and an electronic component. The encapsulant is disposed over the substrate, and has a first top surface, a second top surface and a first lateral surface extending between the first top surface and the second top surface. A roughness of the first lateral surface is less than or equal to a roughness of the second top surface. The electronic component is disposed over the second top surface of the encapsulant and electrically connected to the substrate.

IPC Classes  ?

• H01L 23/552 - Protection against radiation, e.g. light
• H01L 21/48 - Manufacture or treatment of parts, e.g. containers, prior to assembly of the devices, using processes not provided for in a single one of the groups
• H01L 21/56 - Encapsulations, e.g. encapsulating layers, coatings
• H01L 23/00 - SEMICONDUCTOR DEVICES NOT COVERED BY CLASS - Details of semiconductor or other solid state devices
• H01L 23/31 - Encapsulation, e.g. encapsulating layers, coatings characterised by the arrangement
• H01L 23/498 - Leads on insulating substrates

Abstract

An electronic device package includes a circuit layer, a first semiconductor die, a second semiconductor die, a plurality of first conductive structures and a second conductive structure. The first semiconductor die is disposed on the circuit layer. The second semiconductor die is disposed on the first semiconductor die, and has an active surface toward the circuit layer. The first conductive structures are disposed between a first region of the second semiconductor die and the first semiconductor die, and electrically connecting the first semiconductor die to the second semiconductor die. The second conductive structure is disposed between a second region of the second semiconductor die and the circuit layer, and electrically connecting the circuit layer to the second semiconductor die.

IPC Classes  ?

• H01L 23/00 - SEMICONDUCTOR DEVICES NOT COVERED BY CLASS - Details of semiconductor or other solid state devices

Abstract

A package structure is provided. The package structure includes an electronic component and a connection element. The electronic component includes a conductive wire and a magnetic layer encapsulating the conductive wire. The connection element penetrates and contacts the magnetic layer and the conductive wire.

IPC Classes  ?

• H01F 27/28 - Coils; Windings; Conductive connections
• H01F 27/24 - Magnetic cores

Abstract

A sensor device package and method of manufacturing the same are provided. The sensor device package includes a carrier, a sensor component, an encapsulation layer and a protection film. The sensor component is disposed on the carrier, and the sensor component includes an upper surface and edges. The encapsulation layer is disposed on the carrier and encapsulates the edges of the sensor component. The protection film covers at least a portion of the upper surface of the sensor component.

IPC Classes  ?

• B81B 7/00 - Microstructural systems
• B81C 1/00 - Manufacture or treatment of devices or systems in or on a substrate
• G01D 11/24 - Housings

Abstract

An electronic package is provided. The electronic package includes an insulating carrier, a first conductive layer, and an electronic component. The first conductive layer is disposed over the insulating carrier. The electronic component is disposed over the first conductive layer and electrically connected to the first conductive layer, wherein the insulating carrier is configured to dissipate heat from the electronic component to a second side of the insulating carrier opposite to a first side facing the electronic component.

IPC Classes  ?

• H01L 23/373 - Cooling facilitated by selection of materials for the device
• H01L 23/00 - SEMICONDUCTOR DEVICES NOT COVERED BY CLASS - Details of semiconductor or other solid state devices
• H01L 23/31 - Encapsulation, e.g. encapsulating layers, coatings characterised by the arrangement
• H01L 23/538 - Arrangements for conducting electric current within the device in operation from one component to another the interconnection structure between a plurality of semiconductor chips being formed on, or in, insulating substrates

Abstract

An optical module includes: a carrier; an optical element disposed on the upper side of the carrier; and a housing disposed on the upper side of the carrier, the housing defining an aperture exposing at least a portion of the optical element, an outer sidewall of the housing including at least one singulation portion disposed on the upper side of the carrier, wherein the singulation portion of the housing is a first portion of the housing, and wherein the housing further includes a second portion and a surface of the singulation portion of the housing is rougher than a surface of the second portion of the housing.

IPC Classes  ?

• G01C 3/08 - Use of electric radiation detectors

Abstract

An optical device includes an optical component and an electrical component. The optical component has a sensing surface and a backside surface opposite to the sensing surface. The electrical component is disposed adjacent to the backside surface of the optical component and configured to support the optical component. A portion of the backside surface of the optical component is exposed from the electrical component.

IPC Classes  ?

• H01L 25/16 - Assemblies consisting of a plurality of individual semiconductor or other solid state devices the devices being of types provided for in two or more different main groups of groups , or in a single subclass of , , e.g. forming hybrid circuits
• G01J 1/04 - Optical or mechanical part

Abstract

A flexible package is provided. The flexible package includes a first carrier and a second carrier. The second carrier is electrically connected to the first carrier. The second carrier is at least partially embedded in the first carrier, and an electrical connection interface between the first carrier and the second carrier is within the first carrier.

IPC Classes  ?

• H01L 23/498 - Leads on insulating substrates
• H01L 23/31 - Encapsulation, e.g. encapsulating layers, coatings characterised by the arrangement
• H01L 23/538 - Arrangements for conducting electric current within the device in operation from one component to another the interconnection structure between a plurality of semiconductor chips being formed on, or in, insulating substrates

Abstract

An optoelectronic package is provided. The optoelectronic package includes a photonic component, a connection structure, and an electronic component. The photonic component has an active surface. The connection structure is in contact with the active surface of the photonic component. The electronic component is embedded in the connection structure. The connection structure includes a first redistribution structure in contact with the active surface of the photonic component.

IPC Classes  ?

• G02B 6/12 - Light guides; Structural details of arrangements comprising light guides and other optical elements, e.g. couplings of the optical waveguide type of the integrated circuit kind
• G02B 6/122 - Basic optical elements, e.g. light-guiding paths
• G02B 6/30 - Optical coupling means for use between fibre and thin-film device

Abstract

An optical module is disclosed. The optical module includes a carrier, an optical emitter disposed over the carrier, and a monitor disposed over the carrier and configured to adjust a property of a first light emitted from the optical emitter.

IPC Classes  ?

• G01J 1/44 - Electric circuits

Abstract

A semiconductor package and a lid structure are disclosed. The semiconductor package includes a carrier, a lid structure, a first die, and a second die. The lid structure is disposed over the carrier and includes a gas inlet and a gas outlet. The first die is disposed over the carrier. The second die is disposed over the carrier. The lid structure includes a first protrusion pattern protruding toward the carrier and extending between the first die and the second die.

IPC Classes  ?

• H01L 25/16 - Assemblies consisting of a plurality of individual semiconductor or other solid state devices the devices being of types provided for in two or more different main groups of groups , or in a single subclass of , , e.g. forming hybrid circuits
• G01F 1/66 - Measuring the volume flow or mass flow of fluid or fluent solid material wherein the fluid passes through a meter in a continuous flow by measuring frequency, phase shift or propagation time of electromagnetic or other waves, e.g. using ultrasonic flowmeters
• G01L 11/02 - Measuring steady or quasi-steady pressure of a fluid or a fluent solid material by means not provided for in group or by optical means
• G01N 33/00 - Investigating or analysing materials by specific methods not covered by groups
• H01L 31/0203 - Containers; Encapsulations
• H01L 31/0232 - Optical elements or arrangements associated with the device
• H01L 33/48 - SEMICONDUCTOR DEVICES NOT COVERED BY CLASS - Details thereof characterised by the semiconductor body packages
• H01L 33/60 - Reflective elements

Abstract

A method for manufacturing a package structure includes: providing a first electrical element and a second electrical element on a surface of a first carrier, wherein the second electrical element is shifted with respect to the first electrical element; and moving the first electrical element along at least one direction substantially parallel with the surface of the first carrier until a first surface of the first electrical element is substantially aligned with a first surface of the second electrical element from a top view.

IPC Classes  ?

• H01L 23/00 - SEMICONDUCTOR DEVICES NOT COVERED BY CLASS - Details of semiconductor or other solid state devices

Abstract

A semiconductor device package includes a carrier, an electronic component, a connection element and an encapsulant. The electronic component is disposed on a surface of the carrier. The connection element is disposed on the surface and adjacent to an edge of the carrier. The encapsulant is disposed on the surface of the carrier. A portion of the connection element is exposed from an upper surface and an edge of the encapsulant.

IPC Classes  ?

• H01L 23/498 - Leads on insulating substrates
• H01L 21/48 - Manufacture or treatment of parts, e.g. containers, prior to assembly of the devices, using processes not provided for in a single one of the groups
• H01L 21/56 - Encapsulations, e.g. encapsulating layers, coatings
• H01L 23/31 - Encapsulation, e.g. encapsulating layers, coatings characterised by the arrangement
• H05K 1/18 - Printed circuits structurally associated with non-printed electric components
• H05K 3/34 - Assembling printed circuits with electric components, e.g. with resistor electrically connecting electric components or wires to printed circuits by soldering

Abstract

An electronic device and a method for manufacturing the same are provided. The electronic device includes a first electronic component, a second electronic component and a conductive element. The conductive element includes a first portion and a second portion. The first portion is configured to block an electromagnetic interference between the first electronic component and the second electronic component. The second portion protrudes from the first portion and contacts a shielding layer.

IPC Classes  ?

• H01L 23/552 - Protection against radiation, e.g. light
• H01L 21/48 - Manufacture or treatment of parts, e.g. containers, prior to assembly of the devices, using processes not provided for in a single one of the groups
• H01L 21/56 - Encapsulations, e.g. encapsulating layers, coatings
• H01L 23/498 - Leads on insulating substrates
• H01L 25/16 - Assemblies consisting of a plurality of individual semiconductor or other solid state devices the devices being of types provided for in two or more different main groups of groups , or in a single subclass of , , e.g. forming hybrid circuits

Abstract

An electronic device is provided. The electronic device includes an antenna array including a plurality of antenna patterns collectively configured to provide a scan-angle coverage. Each of the antenna patterns includes a curved surface.

IPC Classes  ?

• H01Q 1/22 - Supports; Mounting means by structural association with other equipment or articles
• H01Q 1/52 - Means for reducing coupling between antennas; Means for reducing coupling between an antenna and another structure
• H01Q 21/06 - Arrays of individually energised antenna units similarly polarised and spaced apart
• H01Q 25/00 - Antennas or antenna systems providing at least two radiating patterns

Abstract

A semiconductor package structure includes a semiconductor device with an active surface, a conductive pillar on the conductive pad, an adhesion strengthening layer, and an encapsulant in contact with the adhesion strengthening layer. The conductive pillar has a side surface and a top surface. The adhesion strengthening layer is conformally disposed on the side surface of the conductive pillar and the active surface of the semiconductor device.

IPC Classes  ?

• H01L 23/00 - SEMICONDUCTOR DEVICES NOT COVERED BY CLASS - Details of semiconductor or other solid state devices
• H01L 23/31 - Encapsulation, e.g. encapsulating layers, coatings characterised by the arrangement
• H01L 23/29 - Encapsulation, e.g. encapsulating layers, coatings characterised by the material
• H01L 23/498 - Leads on insulating substrates
• H01L 25/10 - Assemblies consisting of a plurality of individual semiconductor or other solid state devices all the devices being of a type provided for in the same subgroup of groups , or in a single subclass of , , e.g. assemblies of rectifier diodes the devices having separate containers
• H01L 21/683 - Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components for supporting or gripping
• H01L 21/78 - Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
• H01L 21/56 - Encapsulations, e.g. encapsulating layers, coatings

Abstract

A package structure is disclosed. The package structure includes a substrate including a conductive element and a plurality of wires having a surface area through which heat of the conductive element can be dissipated, lowering a bonding temperature of the conductive element. The package structure also includes a conductive layer disposed between the conductive element of the substrate and the plurality of wires. The conductive contact layer attaches the plurality of wires over the conductive element.

IPC Classes  ?

• H01L 23/00 - SEMICONDUCTOR DEVICES NOT COVERED BY CLASS - Details of semiconductor or other solid state devices
• H01L 25/065 - Assemblies consisting of a plurality of individual semiconductor or other solid state devices all the devices being of a type provided for in the same subgroup of groups , or in a single subclass of , , e.g. assemblies of rectifier diodes the devices not having separate containers the devices being of a type provided for in group
• H01L 23/498 - Leads on insulating substrates

Abstract

An electronic device is disclosed. The electronic device includes a first interconnection structure, and a first electronic component disposed over the first interconnection structure and having an active surface and a lateral surface. The electronic device also includes a power connection disposed between the first interconnection structure and the active surface of the first electronic component, and a first non-power connection extending along the lateral surface of the first electronic component and electrically connected to the first interconnection structure. The electronic device also includes a second non-power connection disposed between the first interconnection structure and the active surface of the first electronic component. The second non-power connection is configured to block an electromagnetic interference (EMI) between the power connection and the first non-power connection.

IPC Classes  ?

• H01L 23/552 - Protection against radiation, e.g. light
• H01L 23/48 - Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads or terminal arrangements
• H01L 23/66 - High-frequency adaptations

Abstract

A semiconductor device package and a method of manufacturing a semiconductor device package are provided. The semiconductor device package includes a carrier, a protective element, and a sensor device. The protective element encapsulates the carrier. The sensor device is embedded in the carrier and the protective element. The sensor device includes a sensing portion and a protective portion adjacent to the sensing portion, and the protective portion of the sensor device has a first surface exposed from the protective element and the carrier.

IPC Classes  ?

• H01L 23/552 - Protection against radiation, e.g. light
• H01L 25/16 - Assemblies consisting of a plurality of individual semiconductor or other solid state devices the devices being of types provided for in two or more different main groups of groups , or in a single subclass of , , e.g. forming hybrid circuits
• H01L 23/498 - Leads on insulating substrates

Abstract

The present disclosure provides an electronic device. The electronic device includes a first electronic component, a first conductive element, and a voltage regulator. The voltage regulator is disposed adjacent to the first electronic component. The voltage regulator is configured to regulate a first voltage from the first EMI shielding layer and to provide the first electronic component with a second voltage.

IPC Classes  ?

• H01L 23/552 - Protection against radiation, e.g. light
• H01L 23/31 - Encapsulation, e.g. encapsulating layers, coatings characterised by the arrangement
• H01L 23/00 - SEMICONDUCTOR DEVICES NOT COVERED BY CLASS - Details of semiconductor or other solid state devices

Abstract

A package structure is provided. The package structure includes a substrate, a conductive pad, and a conductive wire. The conductive pad is disposed over the substrate. The conductive wire includes an end portion connected to the conductive pad, wherein a grain arrangement of the end portion is distinct from a grain arrangement of the conductive pad.

IPC Classes  ?

• H01L 23/00 - SEMICONDUCTOR DEVICES NOT COVERED BY CLASS - Details of semiconductor or other solid state devices
• H01L 23/498 - Leads on insulating substrates

Abstract

A semiconductor device package and a method of manufacturing a semiconductor device package are provided. The semiconductor device package includes a carrier, a first component, a second component, and a protective element. The first component and the second component are arranged side by side in a first direction over the carrier. The protective element is disposed over a top surface of the carrier and extending from space under the first component toward a space under the second component. The protective element includes a first portion and a second portion protruded oppositely from edges of the first component by different distances, and the first portion and the second portion are arranged in a second direction angled with the first direction.

IPC Classes  ?

• H01L 23/00 - SEMICONDUCTOR DEVICES NOT COVERED BY CLASS - Details of semiconductor or other solid state devices
• H01L 21/56 - Encapsulations, e.g. encapsulating layers, coatings
• H01L 25/065 - Assemblies consisting of a plurality of individual semiconductor or other solid state devices all the devices being of a type provided for in the same subgroup of groups , or in a single subclass of , , e.g. assemblies of rectifier diodes the devices not having separate containers the devices being of a type provided for in group
• H01L 23/31 - Encapsulation, e.g. encapsulating layers, coatings characterised by the arrangement

Abstract

The present disclosure provides an electronic device. The electronic device includes a first interposer, a first interconnection array, a first shielding wall, and a second interconnection array. The first interconnection array is disposed in the first interposer and electrically connected to ground. The first shielding wall continuously extends at a side of the first interconnection array. The second interconnection array is disposed between the first shielding wall and the first interconnection array. The second interconnection array is configured to transmit a signal.

IPC Classes  ?

• H01L 23/552 - Protection against radiation, e.g. light
• H01L 25/10 - Assemblies consisting of a plurality of individual semiconductor or other solid state devices all the devices being of a type provided for in the same subgroup of groups , or in a single subclass of , , e.g. assemblies of rectifier diodes the devices having separate containers
• H01L 23/498 - Leads on insulating substrates
• H01L 23/538 - Arrangements for conducting electric current within the device in operation from one component to another the interconnection structure between a plurality of semiconductor chips being formed on, or in, insulating substrates

Abstract

An electronic device is disclosed. The electronic device includes a carrier including a first region and a second region distinct from the first region. The electronic device also includes an electronic component covering the first region and at least partially exposing the second region. The electronic device also includes a first power regulating element in the second region of the carrier and a second power regulating element. The second power regulating element is disposed adjacent to the first power regulating element and electrically connected to the electronic component through the first power regulating element to provide a first power path.

IPC Classes  ?

• H01L 23/528 - Layout of the interconnection structure
• H01L 23/48 - Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads or terminal arrangements
• H01L 23/522 - Arrangements for conducting electric current within the device in operation from one component to another including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
• H01L 23/498 - Leads on insulating substrates
• H01L 23/00 - SEMICONDUCTOR DEVICES NOT COVERED BY CLASS - Details of semiconductor or other solid state devices

Abstract

An electronic device is disclosed. The electronic device includes a first circuit structure, a first die, a second die, and a third die. The first die is disposed below the first circuit structure. The second die is disposed below the first circuit structure. The third die is disposed above the first circuit structure and electrically connects the first die to the second die. The first die communicates with the second die through the third die.

IPC Classes  ?

• H01L 23/522 - Arrangements for conducting electric current within the device in operation from one component to another including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
• H01L 23/528 - Layout of the interconnection structure
• H01L 23/31 - Encapsulation, e.g. encapsulating layers, coatings characterised by the arrangement
• H01L 23/498 - Leads on insulating substrates
• H01L 23/50 - Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads or terminal arrangements for integrated circuit devices
• H01L 23/00 - SEMICONDUCTOR DEVICES NOT COVERED BY CLASS - Details of semiconductor or other solid state devices

Abstract

A substrate includes a first dielectric layer having a first surface and a second dielectric layer having a first surface disposed adjacent to the first surface of the first dielectric layer. The substrate further includes a first conductive via disposed in the first dielectric layer and having a first end adjacent to the first surface of the first dielectric layer and a second end opposite the first end. The substrate further includes a second conductive via disposed in the second dielectric layer and having a first end adjacent to the first surface of the second dielectric layer. A width of the first end of the first conductive via is smaller than a width of the second end of the first conductive via, and a width of the first end of the second conductive via is smaller than the width of the first end of the first conductive via.

IPC Classes  ?

• H01L 23/498 - Leads on insulating substrates
• H01L 23/31 - Encapsulation, e.g. encapsulating layers, coatings characterised by the arrangement
• H01L 21/48 - Manufacture or treatment of parts, e.g. containers, prior to assembly of the devices, using processes not provided for in a single one of the groups

Abstract

An optoelectronic package is provided. The optoelectronic package includes a photonic component, an optical component, and a connection element. The photonic component includes an optical transmission portion, which includes a plurality of first terminals exposed from a first surface of the photonic component. The optical component faces the first surface of the photonic component. The optical component is configured to transmit optical signals to or receive optical signals from the optical transmission portion. The connection element is disposed between the first surface of the photonic component and the optical component. The connection element is configured to reshape the optical signals.

IPC Classes  ?

• G02B 6/42 - Coupling light guides with opto-electronic elements

Abstract

A package structure includes a wiring structure, a first electronic device, a second electronic device and a reinforcement structure. The wiring structure includes at least one dielectric layer, and at least one circuit layer in contact with the dielectric layer. The at least one circuit layer includes at least one interconnection portion. The first electronic device and the second electronic device are electrically connected to the wiring structure. The second electronic device is electrically connected to the first electronic device through the at least one interconnection portion of the at least one circuit layer. The reinforcement structure is disposed above the at least one interconnection portion of the at least one circuit layer.

IPC Classes  ?

• H01L 23/00 - SEMICONDUCTOR DEVICES NOT COVERED BY CLASS - Details of semiconductor or other solid state devices
• H01L 23/31 - Encapsulation, e.g. encapsulating layers, coatings characterised by the arrangement
• H01L 23/367 - Cooling facilitated by shape of device
• H01L 23/538 - Arrangements for conducting electric current within the device in operation from one component to another the interconnection structure between a plurality of semiconductor chips being formed on, or in, insulating substrates
• H01L 21/48 - Manufacture or treatment of parts, e.g. containers, prior to assembly of the devices, using processes not provided for in a single one of the groups
• H01L 21/56 - Encapsulations, e.g. encapsulating layers, coatings

Abstract

An electronic device is disclosed. The electronic device includes a carrier, a computing element disposed over the carrier, and a first data storage element disposed over the carrier and electrically connected with the computing element through the carrier. The computing element is configured to receive a first power provided from the first data storage element.

IPC Classes  ?

• H05K 1/02 - Printed circuits - Details
• H05K 1/14 - Structural association of two or more printed circuits

Abstract

An optical device is provided. The optical device includes a processing component, a first electronic component, a second electronic component, a first pillar, and an encapsulant. The first electronic component is disposed over and electrically connected to the processing component. The second electronic component is disposed over the processing component and electrically connected to the first electronic component. The first pillar is disposed between the first electronic component and the second electronic component and electrically connected to the processing component. The encapsulant is disposed over the processing component. The encapsulant encapsulates the first electronic component, the second electronic component, and the first pillar.

IPC Classes  ?

• H01L 25/16 - Assemblies consisting of a plurality of individual semiconductor or other solid state devices the devices being of types provided for in two or more different main groups of groups , or in a single subclass of , , e.g. forming hybrid circuits
• H01L 23/31 - Encapsulation, e.g. encapsulating layers, coatings characterised by the arrangement
• H01L 23/538 - Arrangements for conducting electric current within the device in operation from one component to another the interconnection structure between a plurality of semiconductor chips being formed on, or in, insulating substrates
• H01L 23/34 - Arrangements for cooling, heating, ventilating or temperature compensation
• H01L 23/498 - Leads on insulating substrates
• H01L 23/00 - SEMICONDUCTOR DEVICES NOT COVERED BY CLASS - Details of semiconductor or other solid state devices
• G02B 6/42 - Coupling light guides with opto-electronic elements

Abstract

An electronic device is disclosed. The electronic device includes a carrier including a first portion, a second portion over the first portion, and a third portion connecting the first portion and the second portion. The electronic device also includes a first electronic component disposed between the first portion and the second portion. An active surface of the first electronic component faces the second portion. The electronic device also includes a second electronic component disposed over the second portion. The first portion is configured to transmit a first power signal to a backside surface of the first electronic component opposite to the active surface.

IPC Classes  ?

• H05K 1/18 - Printed circuits structurally associated with non-printed electric components
• H05K 1/02 - Printed circuits - Details

Abstract

A semiconductor package structure is provided. The semiconductor package structure includes a carrier, a first electronic component, a second electronic component, a third electronic component, a fourth electronic component, and a connection element. The first electronic component is disposed over a surface of the carrier. The second electronic component is disposed over the first electronic component. The third electronic component is spaced apart from the first electronic component and disposed over the surface of the carrier. The fourth electronic component is disposed over the third electronic component. The connection element is electrically connecting the second electronic component to the fourth electronic component.

IPC Classes  ?

• H01L 25/065 - Assemblies consisting of a plurality of individual semiconductor or other solid state devices all the devices being of a type provided for in the same subgroup of groups , or in a single subclass of , , e.g. assemblies of rectifier diodes the devices not having separate containers the devices being of a type provided for in group

Abstract

An electronic device is provided. The electronic device includes a first die and a second die. The second die is disposed over the first die. A backside surface of the second die faces a backside surface of the first die. An active surface of the second die is configured to receive a first power. The second die is configured to provide the first die with a second power through the backside surface of the second die and the backside surface of the first die.

IPC Classes  ?

• H01L 25/065 - Assemblies consisting of a plurality of individual semiconductor or other solid state devices all the devices being of a type provided for in the same subgroup of groups , or in a single subclass of , , e.g. assemblies of rectifier diodes the devices not having separate containers the devices being of a type provided for in group

Abstract

The present disclosure provides an electronic device. The electronic device includes a first electronic component and a second electronic component. The first electronic component is configured to receive a radio frequency (RF) signal and amplify a power of the RF signal. The second electronic component is disposed under the first electronic component. The second electronic component includes an interconnection structure passing through the second electronic component. The interconnection structure is configured to provide a path for a transmission of the RF signal.

IPC Classes  ?

• H01L 23/66 - High-frequency adaptations
• H01L 23/367 - Cooling facilitated by shape of device
• H01L 23/48 - Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads or terminal arrangements
• H01L 23/538 - Arrangements for conducting electric current within the device in operation from one component to another the interconnection structure between a plurality of semiconductor chips being formed on, or in, insulating substrates
• H01L 21/48 - Manufacture or treatment of parts, e.g. containers, prior to assembly of the devices, using processes not provided for in a single one of the groups

Abstract

A semiconductor device package includes a first conductive layer, a second conductive layer and a third conductive layer. The first conductive layer has a first pitch. The second conductive layer has a second pitch and is arranged at two different sides of the first conductive layer. The third conductive layer has a third pitch and is disposed above the first conductive layer and the second conductive layer. The third conductive layer is electrically connected to the first conductive layer. The first pitch is smaller than the third pitch, and the third pitch is smaller than the second pitch.

IPC Classes  ?

• H01L 25/065 - Assemblies consisting of a plurality of individual semiconductor or other solid state devices all the devices being of a type provided for in the same subgroup of groups , or in a single subclass of , , e.g. assemblies of rectifier diodes the devices not having separate containers the devices being of a type provided for in group
• H01L 23/00 - SEMICONDUCTOR DEVICES NOT COVERED BY CLASS - Details of semiconductor or other solid state devices
• H01L 23/528 - Layout of the interconnection structure
• H01L 21/56 - Encapsulations, e.g. encapsulating layers, coatings

Abstract

A semiconductor device package includes a display device, an encapsulation layer disposed in direct contact with the display device, and a reinforced structure surrounded by the encapsulation layer. The reinforced structure is spaced apart from a surface of the display device. A method of manufacturing a semiconductor device package is also disclosed.

IPC Classes  ?

• H05K 5/00 - Casings, cabinets or drawers for electric apparatus
• H05K 5/06 - Hermetically-sealed casings
• H05K 1/18 - Printed circuits structurally associated with non-printed electric components
• H05K 9/00 - Screening of apparatus or components against electric or magnetic fields
• H05K 3/28 - Applying non-metallic protective coatings
• H05K 1/14 - Structural association of two or more printed circuits

Abstract

A system including optical devices is provided. The system includes a first substrate and a first device for optical communication. The first device has a first surface, a second surface opposite to the first surface, and a first side contiguous with the first surface and the second surface. Moreover, the first side is smaller than one of the first surface and the second surface in terms of area. The first device is attached at the first side thereof to the first substrate.

IPC Classes  ?

• H04B 10/40 - Transceivers
• G02B 6/42 - Coupling light guides with opto-electronic elements

Abstract

A semiconductor device package is provided that includes a substrate, a first support structure disposed on the substrate and a first antenna. The first support structure includes a first surface spaced apart from the substrate by a first distance. The first antenna is disposed above the first surface of the first support structure. The first antenna has a first surface, a second surface opposite the first surface and a third surface extending from the first surface to the second surface, wherein the first surface and the second surface of the first antenna are exposed.

IPC Classes  ?

• H01Q 1/22 - Supports; Mounting means by structural association with other equipment or articles
• H01L 23/66 - High-frequency adaptations
• H01L 21/48 - Manufacture or treatment of parts, e.g. containers, prior to assembly of the devices, using processes not provided for in a single one of the groups
• H01Q 1/38 - Structural form of radiating elements, e.g. cone, spiral, umbrella formed by a conductive layer on an insulating support
• H01L 23/498 - Leads on insulating substrates

Abstract

The present disclosure provides an electronic package. The electronic package includes a photonic component including a first input/output (I/O) port and a second I/O port both at a side of the photonic component. The electronic package also includes a connector disposed adjacent to the side of the photonic component and configured to guide a first light carrying medium to be optically coupled with at least one of the first I/O port and second I/O port of the photonic component.

IPC Classes  ?

• G02B 6/42 - Coupling light guides with opto-electronic elements
• H01L 25/16 - Assemblies consisting of a plurality of individual semiconductor or other solid state devices the devices being of types provided for in two or more different main groups of groups , or in a single subclass of , , e.g. forming hybrid circuits

Abstract

A package structure and a testing method are provided. The package structure includes a wiring structure, a first electronic device and a second electronic device. The wiring structure includes at least one dielectric layer, at least one conductive circuit layer in contact with the dielectric layer, and at least one test circuit structure in contact with the dielectric layer. The test circuit structure is disposed adjacent to the interconnection portion of the conductive circuit layer. The first electronic device is electrically connected to the wiring structure. The second electronic device is electrically connected to the wiring structure. The second electronic device is electrically connected to the first electronic device through the interconnection portion of the conductive circuit layer.

IPC Classes  ?

• G01R 31/28 - Testing of electronic circuits, e.g. by signal tracer
• H01L 23/498 - Leads on insulating substrates
• H01L 23/538 - Arrangements for conducting electric current within the device in operation from one component to another the interconnection structure between a plurality of semiconductor chips being formed on, or in, insulating substrates
• H01L 23/552 - Protection against radiation, e.g. light
• H01L 25/18 - Assemblies consisting of a plurality of individual semiconductor or other solid state devices the devices being of types provided for in two or more different subgroups of the same main group of groups , or in a single subclass of ,
• H01L 23/00 - SEMICONDUCTOR DEVICES NOT COVERED BY CLASS - Details of semiconductor or other solid state devices

Abstract

A semiconductor device package includes an electronic component and a substrate. The electronic component has a first surface and a second surface. The substrate is connected to the first surface of the electronic component through an adhesive layer. The substrate includes a first antenna disposed over the second surface of the electronic components through the adhesive layer.

IPC Classes  ?

• H01L 23/66 - High-frequency adaptations
• H01L 21/48 - Manufacture or treatment of parts, e.g. containers, prior to assembly of the devices, using processes not provided for in a single one of the groups
• H01L 23/498 - Leads on insulating substrates
• H01Q 1/38 - Structural form of radiating elements, e.g. cone, spiral, umbrella formed by a conductive layer on an insulating support
• H01L 23/00 - SEMICONDUCTOR DEVICES NOT COVERED BY CLASS - Details of semiconductor or other solid state devices

Abstract

A semiconductor device package includes a first conductive structure, a stress buffering layer and a second conductive structure. The first conductive structure includes a substrate, at least one first electronic component embedded in the substrate, and a first circuit layer disposed on the substrate and electrically connected to the first electronic component. The first circuit layer includes a conductive wiring pattern. The stress buffering layer is disposed on the substrate. The conductive wiring pattern of the first circuit layer extends through the stress buffering layer. The second conductive structure is disposed on the stress buffering layer and the first circuit layer.

IPC Classes  ?

• H01L 25/16 - Assemblies consisting of a plurality of individual semiconductor or other solid state devices the devices being of types provided for in two or more different main groups of groups , or in a single subclass of , , e.g. forming hybrid circuits
• H01L 23/31 - Encapsulation, e.g. encapsulating layers, coatings characterised by the arrangement
• H01L 23/00 - SEMICONDUCTOR DEVICES NOT COVERED BY CLASS - Details of semiconductor or other solid state devices
• H01L 23/522 - Arrangements for conducting electric current within the device in operation from one component to another including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
• H01L 21/56 - Encapsulations, e.g. encapsulating layers, coatings
• H01L 23/528 - Layout of the interconnection structure

Abstract

A conductive structure includes a core portion, a plurality of electronic devices and a filling material. The core portion defines a cavity. The electronic devices are disposed in the cavity of the core portion. The filling material is disposed between the electronic devices and a sidewall of the cavity of the core portion.

IPC Classes  ?

• H01L 23/538 - Arrangements for conducting electric current within the device in operation from one component to another the interconnection structure between a plurality of semiconductor chips being formed on, or in, insulating substrates
• H01L 23/31 - Encapsulation, e.g. encapsulating layers, coatings characterised by the arrangement
• H01L 21/52 - Mounting semiconductor bodies in containers
• H01L 21/56 - Encapsulations, e.g. encapsulating layers, coatings
• H01L 21/48 - Manufacture or treatment of parts, e.g. containers, prior to assembly of the devices, using processes not provided for in a single one of the groups

Abstract

A wiring structure and a method for manufacturing the same are provided. The wiring structure includes a lower conductive structure, an upper conductive structure and a conductive via. The lower conductive structure includes a first dielectric layer and a first circuit layer in contact with the first dielectric layer. The upper conductive structure is attached to the lower conductive structure. The upper conductive structure includes a plurality of second dielectric layers, a plurality of second circuit layers in contact with the second dielectric layers, and defines an accommodating hole. An insulation material is disposed in the accommodating hole. The conductive via extends through the insulation material, and electrically connects the lower conductive structure.

IPC Classes  ?

• H01L 23/498 - Leads on insulating substrates
• H01L 23/00 - SEMICONDUCTOR DEVICES NOT COVERED BY CLASS - Details of semiconductor or other solid state devices
• H01L 21/48 - Manufacture or treatment of parts, e.g. containers, prior to assembly of the devices, using processes not provided for in a single one of the groups

Abstract

The present disclosure provides an electronic device. The electronic device includes a first insulating layer, a first antenna pattern, a second insulating layer, and a second antenna pattern. The first antenna pattern is configured to operate at a first frequency and at least partially disposed over the first insulating layer. The second insulating layer is disposed over the first insulating layer. The second antenna pattern is configured to operate at a second frequency different from the first frequency and at least partially disposed over the second insulating layer. A dielectric constant of the first insulating layer is different from a dielectric constant of the second insulating layer.

IPC Classes  ?

• H05K 1/02 - Printed circuits - Details
• H05K 1/16 - Printed circuits incorporating printed electric components, e.g. printed resistor, capacitor, inductor

Abstract

An electronic device, a package structure and an electronic manufacturing method are provided. The electronic device includes a substrate, a first bump, a second bump and a first reflowable material. The first bump is disposed over the substrate, and has a first width. An end portion of the first bump defines a first recess portion. The second bump is disposed over the substrate, and has a second width less than the first width. The first reflowable material is disposed on the first bump and extends in the first recess portion.

IPC Classes  ?

• H01L 23/00 - SEMICONDUCTOR DEVICES NOT COVERED BY CLASS - Details of semiconductor or other solid state devices
• H01L 23/498 - Leads on insulating substrates

Abstract

A method for manufacturing a package includes generating an electric field between an anode and a cathode in an electroplating solution to electroplate a substrate electrically connected to the cathode; depositing metal on a central region of the substrate with a first deposition rate; depositing metal on an outer region of the substrate with a second deposition rate lower than the first deposition rate; and reducing the first deposition rate.

IPC Classes  ?

• C25D 5/18 - Electroplating using modulated, pulsed or reversing current
• C25D 7/12 - Semiconductors
• C25D 5/08 - Electroplating with moving electrolyte, e.g. jet electroplating
• H01L 23/00 - SEMICONDUCTOR DEVICES NOT COVERED BY CLASS - Details of semiconductor or other solid state devices
• H01L 21/56 - Encapsulations, e.g. encapsulating layers, coatings
• C25D 5/00 - Electroplating characterised by the process; Pretreatment or after-treatment of workpieces

Abstract

A semiconductor package structure is provided. The semiconductor package structure includes a substrate, a first electronic component, and an electronic device. The first electronic component is disposed over the substrate. The electronic device is at least partially embedded in the substrate. The electronic device includes a second electronic component and a reinforcement. The second electronic component is configured for providing a regulated voltage to the first electronic component. The reinforcement supports the second electronic component.

IPC Classes  ?

• H01L 23/498 - Leads on insulating substrates
• H01L 23/00 - SEMICONDUCTOR DEVICES NOT COVERED BY CLASS - Details of semiconductor or other solid state devices
• H01L 23/31 - Encapsulation, e.g. encapsulating layers, coatings characterised by the arrangement
• H01L 25/065 - Assemblies consisting of a plurality of individual semiconductor or other solid state devices all the devices being of a type provided for in the same subgroup of groups , or in a single subclass of , , e.g. assemblies of rectifier diodes the devices not having separate containers the devices being of a type provided for in group

Abstract

A package structure and a method for manufacturing the same are provided. The package structure includes an electronic device, a heat spreader, an intermediate layer and an encapsulant. The electronic device includes a plurality of electrical contacts. The intermediate layer is interposed between the electronic device and the heat spreader. The intermediate layer includes a sintered material. The encapsulant encapsulates the electronic device. A surface of the encapsulant is substantially coplanar with a plurality of surfaces of the electrical contacts.

IPC Classes  ?

• H01L 23/31 - Encapsulation, e.g. encapsulating layers, coatings characterised by the arrangement
• H01L 23/373 - Cooling facilitated by selection of materials for the device
• H01L 23/367 - Cooling facilitated by shape of device
• H01L 21/48 - Manufacture or treatment of parts, e.g. containers, prior to assembly of the devices, using processes not provided for in a single one of the groups
• H01L 23/00 - SEMICONDUCTOR DEVICES NOT COVERED BY CLASS - Details of semiconductor or other solid state devices
• H01L 21/56 - Encapsulations, e.g. encapsulating layers, coatings

Abstract

An electronic device package includes a first substrate, a second substrate and a conductive layer. The first substrate includes a first bonding pad, and a cavity exposing the first bonding pad. The second substrate is laminated on the first substrate. The second substrate includes a second bonding pad at least partially inserting into the cavity of the first substrate. The conductive layer is disposed in the cavity and at least between the first bonding pad and the second bonding pad to connect the first bonding pad and the second bonding pad.

IPC Classes  ?

• H01L 23/66 - High-frequency adaptations
• H01L 23/31 - Encapsulation, e.g. encapsulating layers, coatings characterised by the arrangement
• H01L 23/498 - Leads on insulating substrates
• H01L 21/48 - Manufacture or treatment of parts, e.g. containers, prior to assembly of the devices, using processes not provided for in a single one of the groups
• H01Q 1/22 - Supports; Mounting means by structural association with other equipment or articles
• H01L 23/00 - SEMICONDUCTOR DEVICES NOT COVERED BY CLASS - Details of semiconductor or other solid state devices

Abstract

An electronic package includes an electronic structure, a first circuit pattern structure, a plurality of first solders and an encapsulant. The electronic structure includes an electronic device, and has a top surface and a bottom surface opposite to the top surface. The first circuit pattern structure is disposed over the top surface of the electronic structure. The first solders are disposed on the bottom surface of the electronic structure. The encapsulant encapsulates the electronic structure. At least a portion of the encapsulant is disposed between at least two of the plurality of first solders.

IPC Classes  ?

• H01L 23/498 - Leads on insulating substrates
• H01L 23/31 - Encapsulation, e.g. encapsulating layers, coatings characterised by the arrangement
• H01L 23/528 - Layout of the interconnection structure

Abstract

A power module is disclosed. The power module includes a first conductive plate, a first power component, and a second power component. The first conductive plate has a first side and a second side opposite to the first side; The first power component is disposed at the first side. The second power component is disposed at a first location of the second side distinct from a second location of the second side. The second location is configured to transfer most heat from the first power component to the second power component if the second power component is disposed at the second location.

IPC Classes  ?

• H01L 23/433 - Auxiliary members characterised by their shape, e.g. pistons
• H01L 23/373 - Cooling facilitated by selection of materials for the device

Abstract

A wireless earphone comprises a battery, a speaker and a chamber/space. The battery has a first surface, a second surface opposite the first surface, and a third surface extended between the first surface and the second surface. The battery is disconnected from any protecting circuits. The speaker is disposed adjacent to the first surface of the battery. The chamber/space is defined by the battery and the speaker. The chamber/space is devoid of any electronic component.

IPC Classes  ?

• H04R 1/10 - Earpieces; Attachments therefor
• H01L 23/31 - Encapsulation, e.g. encapsulating layers, coatings characterised by the arrangement
• H01L 23/552 - Protection against radiation, e.g. light
• H01L 23/66 - High-frequency adaptations

Abstract

The present disclosure provides a sensing package. The sensing package includes a carrier configured to face an object to be inspected and an emitter disposed adjacent to the carrier. The emitter is configured to emit a first light propagating in a first direction. The sensing package further includes a component configured to change the first light into a second light propagating in a second direction different from the first direction. An optical module and a method for detecting light are also provided.

IPC Classes  ?

• G01N 21/17 - Systems in which incident light is modified in accordance with the properties of the material investigated

Abstract

A semiconductor device includes: a substrate having a first surface and a second surface opposite to the first surface; an electronic component disposed on the first surface of the substrate; a sensor disposed adjacent to the second surface of the substrate; an electrical contact disposed on the first surface of the substrate; and a package body exposing a portion of the electrical contact.

IPC Classes  ?

• H01L 21/56 - Encapsulations, e.g. encapsulating layers, coatings
• H01L 23/31 - Encapsulation, e.g. encapsulating layers, coatings characterised by the arrangement
• H01L 27/146 - Imager structures
• H01L 23/00 - SEMICONDUCTOR DEVICES NOT COVERED BY CLASS - Details of semiconductor or other solid state devices
• H01L 23/544 - Marks applied to semiconductor devices, e.g. registration marks, test patterns

Abstract

A testing device is disclosed. The testing device includes a socket configured to support a DUT and a first detection module disposed at a first side of the socket and configured to detect a location relationship between the DUT and the socket.

IPC Classes  ?

• G01R 1/04 - Housings; Supporting members; Arrangements of terminals
• G01R 31/28 - Testing of electronic circuits, e.g. by signal tracer

Abstract

The present disclosure provides a semiconductor device package including a first device, a second device, and a spacer. The first device includes a substrate having a first dielectric constant. The second device includes a dielectric element, an antenna, and a reinforcing element. The dielectric element has a second dielectric constant less than the first dielectric constant. The antenna is at least partially within the dielectric element. The reinforcing element is disposed on the dielectric element, and the reinforcing element has a third dielectric constant greater than the first dielectric constant. The spacer is disposed between the first device and the second device and configured to define a distance between the first device and the second device

IPC Classes  ?

• H01L 23/31 - Encapsulation, e.g. encapsulating layers, coatings characterised by the arrangement
• H01L 23/66 - High-frequency adaptations
• H01L 21/56 - Encapsulations, e.g. encapsulating layers, coatings

Abstract

The present disclosure provides a semiconductor device package including a substrate having a first surface and a second surface opposite to the first surface, a first package body disposed on the first surface, and a conductive layer covering the first package body and the substrate. The conductive layer includes a first portion on the top surface of the first package body and a second portion on the lateral surface of the first package body and a sidewall of the substrate. The second portion of the conductive layer has a tapered shape. A method for manufacturing a semiconductor device package is also provided.

IPC Classes  ?

• H01L 23/552 - Protection against radiation, e.g. light
• H01L 21/768 - Applying interconnections to be used for carrying current between separate components within a device
• H01L 21/78 - Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
• H01L 21/50 - Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the groups
• H01L 23/00 - SEMICONDUCTOR DEVICES NOT COVERED BY CLASS - Details of semiconductor or other solid state devices

Abstract

A semiconductor device package includes a substrate, a first antenna pattern and a second antenna pattern. The substrate has a first surface and a second surface opposite to the first surface. The first antenna pattern is disposed over the first surface of the substrate. The first antenna pattern has a first bandwidth. The second antenna pattern is disposed over the first antenna pattern. The second antenna pattern has a second bandwidth different from the first bandwidth. The first antenna pattern and the second antenna pattern are at least partially overlapping in a direction perpendicular to the first surface of the substrate.

IPC Classes  ?

• H01Q 1/52 - Means for reducing coupling between antennas; Means for reducing coupling between an antenna and another structure
• H01Q 1/24 - Supports; Mounting means by structural association with other equipment or articles with receiving set
• H01Q 1/48 - Earthing means; Earth screens; Counterpoises
• H01Q 1/22 - Supports; Mounting means by structural association with other equipment or articles
• H01Q 21/06 - Arrays of individually energised antenna units similarly polarised and spaced apart
• H01Q 5/378 - Combination of fed elements with parasitic elements

Abstract

An electronic device is disclosed. The electronic device includes a carrier, an optical component disposed on the carrier and a humidity indicator within the electronic package. A position of the humidity indicator within the electronic package is arranged such that at least a part of the humidity indicator is visible from a viewpoint outside of the electronic package.

IPC Classes  ?

• G01N 21/81 - Indicating humidity
• H01L 23/31 - Encapsulation, e.g. encapsulating layers, coatings characterised by the arrangement

Abstract

A semiconductor device package and a method for manufacturing a semiconductor device package are provided. The semiconductor device package includes a substrate, a clip, and a support structure. The clip is disposed on the substrate. The clip includes a first portion and a second portion separated from each other by a slit. The support structure is above the substrate and supports the clip. The support structure has a first surface and a second surface facing the first surface, and the first surface and the second surface define a gap.

IPC Classes  ?

• H01L 23/00 - SEMICONDUCTOR DEVICES NOT COVERED BY CLASS - Details of semiconductor or other solid state devices
• H01L 23/31 - Encapsulation, e.g. encapsulating layers, coatings characterised by the arrangement
• H01L 23/498 - Leads on insulating substrates
• H01L 21/48 - Manufacture or treatment of parts, e.g. containers, prior to assembly of the devices, using processes not provided for in a single one of the groups
• H01L 21/56 - Encapsulations, e.g. encapsulating layers, coatings

Abstract

An electronic package is provided. The electronic package includes a first processing component, a second processing component, and a first memory unit. The first memory unit is over the first processing component and the second processing component. The first processing component and the second processing component are configured to access data stored in the first memory unit.

IPC Classes  ?

• H01L 23/538 - Arrangements for conducting electric current within the device in operation from one component to another the interconnection structure between a plurality of semiconductor chips being formed on, or in, insulating substrates
• H01L 23/00 - SEMICONDUCTOR DEVICES NOT COVERED BY CLASS - Details of semiconductor or other solid state devices
• H01L 25/065 - Assemblies consisting of a plurality of individual semiconductor or other solid state devices all the devices being of a type provided for in the same subgroup of groups , or in a single subclass of , , e.g. assemblies of rectifier diodes the devices not having separate containers the devices being of a type provided for in group
• H01L 23/48 - Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads or terminal arrangements

Abstract

An electronic package is provided. The electronic package includes a processing component and a memory unit. The processing component has a side including a first region and a second region distinct from the first region. The memory unit is disposed over the first region. The first region is configured to provide interconnection between the processing component and the memory unit, and the second region is configured to provide external connection.

IPC Classes  ?

• H01L 23/00 - SEMICONDUCTOR DEVICES NOT COVERED BY CLASS - Details of semiconductor or other solid state devices
• H01L 25/065 - Assemblies consisting of a plurality of individual semiconductor or other solid state devices all the devices being of a type provided for in the same subgroup of groups , or in a single subclass of , , e.g. assemblies of rectifier diodes the devices not having separate containers the devices being of a type provided for in group
• H01L 23/48 - Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads or terminal arrangements

Abstract

An electronic device is disclosed. The electronic device includes a carrier and a first interposer disposed on the carrier. The first interposer has a first region configured for providing an external electrical connection to outside the electronic device and a second region distinct from the first region. The electronic device also includes a first antenna component disposed on the second region of the first interposer.

IPC Classes  ?

• H01Q 5/307 - Individual or coupled radiating elements, each element being fed in an unspecified way

Abstract

A method for manufacturing an electronic package and a suction device are provided. The method includes: providing an electronic component having a first surface and including at least one conductive stud on the first surface; providing a suction device having at least one recess; and moving the electronic component with the suction device, wherein an edge of the at least one recess does not overlap the at least one conductive stud from a top view while moving the electronic component with the suction device.

IPC Classes  ?

• H01L 21/683 - Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components for supporting or gripping
• H01L 21/67 - Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components

Abstract

A package structure includes a first die, a second die, an encapsulant and at least one electrical contact. The first die has an active surface. The second die is disposed on the first die, and has an active surface and a backside surface opposite to the active surface. The active surface of the second die is closer to the active surface of the first die than the backside surface of the second die is. The encapsulant encapsulates the first die and the second die, and has a top surface far away from the active surface of the first die. The electrical contact is exposed from the top surface of the encapsulant and is configured for connecting at least one conductive wire.

IPC Classes  ?

• H01L 23/498 - Leads on insulating substrates
• H01L 25/16 - Assemblies consisting of a plurality of individual semiconductor or other solid state devices the devices being of types provided for in two or more different main groups of groups , or in a single subclass of , , e.g. forming hybrid circuits
• H01L 23/31 - Encapsulation, e.g. encapsulating layers, coatings characterised by the arrangement
• H01L 23/49 - Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads or terminal arrangements consisting of soldered or bonded constructions wire-like
• H01L 23/00 - SEMICONDUCTOR DEVICES NOT COVERED BY CLASS - Details of semiconductor or other solid state devices
• H01L 21/56 - Encapsulations, e.g. encapsulating layers, coatings

Abstract

An electronic device is disclosed. The electronic device includes a first part, a second part adjacent to the first part and a rotational shaft. The rotational shaft includes an antenna and configured to allow the first part and the second part to rotate about a rotation axis defined by the rotational shaft.

IPC Classes  ?

• G06F 1/16 - Constructional details or arrangements

Abstract

An electronic device is provided. The electronic device includes a flexible body having a first portion and a second portion, an electronic component in the first portion and the second portion of the flexible body, a first magnetic element in the first portion of the flexible body and a second magnetic element in the second portion of the flexible body. The first magnetic and the second magnetic generate a repulsive force with each other when the flexible body is bent and the first portion and the second portion of the flexible body are moved toward each other.

IPC Classes  ?

• H05K 5/00 - Casings, cabinets or drawers for electric apparatus
• A61B 5/00 - Measuring for diagnostic purposes ; Identification of persons
• H01F 7/02 - Permanent magnets
• H05K 5/02 - Casings, cabinets or drawers for electric apparatus - Details

Abstract

A semiconductor device package is disclosed. The semiconductor device package includes a carrier, a first electronic component disposed on the carrier and a support component disposed on the carrier. The semiconductor device package also includes a second electronic component disposed on the first electronic component and supported by the support component.

IPC Classes  ?

• H01L 23/00 - SEMICONDUCTOR DEVICES NOT COVERED BY CLASS - Details of semiconductor or other solid state devices
• H01L 25/18 - Assemblies consisting of a plurality of individual semiconductor or other solid state devices the devices being of types provided for in two or more different subgroups of the same main group of groups , or in a single subclass of ,
• H01L 23/538 - Arrangements for conducting electric current within the device in operation from one component to another the interconnection structure between a plurality of semiconductor chips being formed on, or in, insulating substrates

Abstract

A semiconductor device package includes a carrier, an electronic component and a connector. The electronic component is disposed on the carrier. The connector is disposed on the carrier and electrically connected to the electronic component. A S 11 parameter of the connector is less than −20 dB.

IPC Classes  ?

• H01L 23/498 - Leads on insulating substrates
• H01L 21/48 - Manufacture or treatment of parts, e.g. containers, prior to assembly of the devices, using processes not provided for in a single one of the groups
• H01L 23/66 - High-frequency adaptations

Abstract

A semiconductor package includes: (1) a package substrate including an upper surface; (2) a semiconductor device disposed adjacent to the upper surface of the package substrate, the semiconductor device including an inactive surface; and (3) an antenna substrate disposed on the inactive surface of the semiconductor device.

IPC Classes  ?

• H01Q 1/22 - Supports; Mounting means by structural association with other equipment or articles
• H01L 23/66 - High-frequency adaptations
• H01L 25/16 - Assemblies consisting of a plurality of individual semiconductor or other solid state devices the devices being of types provided for in two or more different main groups of groups , or in a single subclass of , , e.g. forming hybrid circuits
• H01L 23/31 - Encapsulation, e.g. encapsulating layers, coatings characterised by the arrangement
• H01L 23/00 - SEMICONDUCTOR DEVICES NOT COVERED BY CLASS - Details of semiconductor or other solid state devices
• H01Q 9/04 - Resonant antennas

Abstract

An electronic device is provided. The electronic device includes an electronic component and a heat dissipation structure. The electronic component has a passive surface and a plurality of conductive vias exposed from the passive surface. The heat dissipation structure is disposed on the passive surface and configured to transmit a plurality of independent powers to the conductive vias through the passive surface.

IPC Classes  ?

• H01L 23/367 - Cooling facilitated by shape of device
• H01L 23/50 - Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads or terminal arrangements for integrated circuit devices
• H01L 23/48 - Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads or terminal arrangements
• H01L 25/18 - Assemblies consisting of a plurality of individual semiconductor or other solid state devices the devices being of types provided for in two or more different subgroups of the same main group of groups , or in a single subclass of ,
• H01L 23/538 - Arrangements for conducting electric current within the device in operation from one component to another the interconnection structure between a plurality of semiconductor chips being formed on, or in, insulating substrates

Abstract

An electronic device is disclosed. The electronic device includes an active component, a power regulating component disposed on the active component, and a patterned conductive element disposed between the active component and the power regulating component. The patterned conductive element is configured to provide one or more heat dissipation paths for the active component and to provide a power path between the active component and the power regulating component.

IPC Classes  ?

• H01L 23/367 - Cooling facilitated by shape of device
• H01L 23/538 - Arrangements for conducting electric current within the device in operation from one component to another the interconnection structure between a plurality of semiconductor chips being formed on, or in, insulating substrates
• H01L 25/065 - Assemblies consisting of a plurality of individual semiconductor or other solid state devices all the devices being of a type provided for in the same subgroup of groups , or in a single subclass of , , e.g. assemblies of rectifier diodes the devices not having separate containers the devices being of a type provided for in group
• H01L 25/18 - Assemblies consisting of a plurality of individual semiconductor or other solid state devices the devices being of types provided for in two or more different subgroups of the same main group of groups , or in a single subclass of ,
• H01L 23/495 - Lead-frames

Abstract

The present disclosure provides a semiconductor device. The semiconductor device includes a carrier having a first side and a second side adjacent to the first side. The semiconductor device also includes a first antenna adjacent to the first side and configured to operate at a first frequency and a second antenna adjacent to the second side and configured to operate at a second frequency different from the first frequency. An method of manufacturing a semiconductor device is also provided.

IPC Classes  ?

• H01L 23/66 - High-frequency adaptations
• H01Q 1/22 - Supports; Mounting means by structural association with other equipment or articles
• H01L 23/552 - Protection against radiation, e.g. light
• H01L 23/498 - Leads on insulating substrates

Abstract

The present disclosure provides a semiconductor device package. The semiconductor device package includes a first antenna pattern disposed at a first elevation and a second antenna pattern disposed at a second elevation different from the first elevation. The first antenna pattern and the second antenna pattern define an air cavity. The semiconductor device package also includes a circuit layer. The air cavity is between the first antenna pattern, the second antenna pattern, and the circuit layer.

IPC Classes  ?

• H01Q 1/22 - Supports; Mounting means by structural association with other equipment or articles
• H01L 23/66 - High-frequency adaptations

Abstract

A semiconductor device package and a fabrication method thereof are disclosed. The semiconductor package comprises: a package component having a first mounting surface and a second mounting surface; and a first electronic component having a first conductive pad signal communicatively mounted on the first mounting surface through a first type connector; wherein the first type connector comprises a first solder composition having a lower melting point layer sandwiched between a pair of higher melting point layers, wherein the lower melting point layer is composed of alloys capable of forming a room temperature eutectic.

IPC Classes  ?

• H01L 23/00 - SEMICONDUCTOR DEVICES NOT COVERED BY CLASS - Details of semiconductor or other solid state devices
• H01L 25/10 - Assemblies consisting of a plurality of individual semiconductor or other solid state devices all the devices being of a type provided for in the same subgroup of groups , or in a single subclass of , , e.g. assemblies of rectifier diodes the devices having separate containers

Abstract

A wiring structure includes a test pattern layer. The test pattern layer includes a test circuit pattern and a heat dissipating structure. The heat dissipating structure is disposed adjacent to the test circuit pattern, and is configured to reduce temperature rise of the test circuit pattern when a power is applied to the test circuit pattern.

IPC Classes  ?

• H05K 1/02 - Printed circuits - Details
• H01L 23/498 - Leads on insulating substrates
• H01L 23/367 - Cooling facilitated by shape of device

Abstract

An electronic device is provided. The electronic device includes a circuit pattern layer. The circuit pattern layer includes a first surface, a second surface recessed with respect to the first surface; and a third surface recessed with respect to the first surface and adjacent to and spaced apart from the second surface. The second surface and the third surface are mis-aligned with each other.

IPC Classes  ?

• H01L 23/495 - Lead-frames

Abstract

An electronic device is disclosed. The electronic device includes a first electronic component and a power regulating structure configured to provide a first power to the first electronic component. The power regulating structure includes a first component and a second component at least partially overlapped with the first component from a top view.

IPC Classes  ?

• H01L 23/64 - Impedance arrangements
• H01L 25/065 - Assemblies consisting of a plurality of individual semiconductor or other solid state devices all the devices being of a type provided for in the same subgroup of groups , or in a single subclass of , , e.g. assemblies of rectifier diodes the devices not having separate containers the devices being of a type provided for in group

Abstract

An electronic device is provided. The electronic device includes a carrier, a first electronic component, a second electronic component, and an encapsulant. The first electronic component is disposed at a first side of the carrier. The second electronic component is disposed at a second side of the carrier opposite to the first side. The encapsulant encapsulates the first electronic component and has an uneven thickness. The encapsulant is configured to reduce a warpage of the carrier.

IPC Classes  ?

• H05K 1/02 - Printed circuits - Details
• H05K 1/18 - Printed circuits structurally associated with non-printed electric components

Abstract

A semiconductor device package includes a substrate, a first patterned conductive layer, a second patterned conductive layer, a dielectric layer, a third patterned conductive layer and a connector. The substrate has a top surface. The first patterned conductive layer is on the top surface of the substrate. The second patterned conductive layer contacts the first patterned conductive layer. The second patterned conductive layer includes a first portion, a second portion and a third portion. The second portion is connected between the first portion and the third portion. The dielectric layer is on the top surface of the substrate. The dielectric layer covers the first patterned conductive layer and surrounds the second portion and the third portion of the second patterned conductive layer. The first portion of the second patterned conductive layer is disposed on the dielectric layer. The third patterned conductive layer is on the second patterned conductive layer, and the connector is directly on the third patterned conductive layer.

IPC Classes  ?

• H01L 27/08 - Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body including only semiconductor components of a single kind
• H01L 23/522 - Arrangements for conducting electric current within the device in operation from one component to another including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body

Abstract

An electronic structure includes a packaging structure, a circuit pattern structure, an underfill and a protrusion structure. The circuit pattern structure is disposed over the packaging structure. A gap is between the circuit pattern structure and the packaging structure. The underfill is disposed in the gap. The protrusion structure is disposed in the gap, and is configured to facilitate the distributing of the underfill in the gap.

IPC Classes  ?

• H01L 23/00 - SEMICONDUCTOR DEVICES NOT COVERED BY CLASS - Details of semiconductor or other solid state devices
• H01L 23/498 - Leads on insulating substrates

Abstract

An electronic package is disclosed. The electronic package includes an electronic component and a plurality of power regulating components. The plurality of power regulating components includes a first power regulating component and a second power regulating component. A first power path is established from the first power regulating component to a backside surface of the electronic component. A second power path is established from the second power regulating component to the backside surface of the electronic component.

IPC Classes  ?

• H01L 23/498 - Leads on insulating substrates
• H01L 25/16 - Assemblies consisting of a plurality of individual semiconductor or other solid state devices the devices being of types provided for in two or more different main groups of groups , or in a single subclass of , , e.g. forming hybrid circuits

Abstract

An electronic package is provided. The electronic package includes a power regulating component, an electronic component, and a circuit structure. The circuit structure separates the power regulating component and the electronic component. The circuit structure is configured to provide a first power to the power regulating component. The power regulating component is configured to provide a second power to the electronic component through the circuit structure.

IPC Classes  ?

• H01L 23/50 - Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads or terminal arrangements for integrated circuit devices
• H01L 23/31 - Encapsulation, e.g. encapsulating layers, coatings characterised by the arrangement
• H01L 23/498 - Leads on insulating substrates

Abstract

An electronic package is provided. The electronic package includes an electronic component and a leadframe. The electronic component has a passive surface. The leadframe includes a first patterned part under the electronic component and configured to provide a power to the electronic component by the passive surface.

IPC Classes  ?

• H01L 23/495 - Lead-frames
• H01L 23/498 - Leads on insulating substrates
• H01L 23/31 - Encapsulation, e.g. encapsulating layers, coatings characterised by the arrangement

Abstract

A semiconductor device package includes a first substrate, a second substrate, a conductive structure, a first solder and a second solder. The second substrate is disposed over the first substrate. The conductive structure is disposed between the first substrate and the second substrate. The conductive structure includes a first wetting portion, a second wetting portion, and a non-wetting portion disposed between the first wetting portion and the second wetting portion. The first solder covers the first wetting portion and connects the conductive structure to the first substrate. The second solder covers the second wetting portion and connects the conductive structure to the second substrate. The first solder is spaced apart from the second solder by the non-wetting portion.

IPC Classes  ?

• H01L 23/498 - Leads on insulating substrates
• H01L 21/48 - Manufacture or treatment of parts, e.g. containers, prior to assembly of the devices, using processes not provided for in a single one of the groups
• H01L 25/16 - Assemblies consisting of a plurality of individual semiconductor or other solid state devices the devices being of types provided for in two or more different main groups of groups , or in a single subclass of , , e.g. forming hybrid circuits

Abstract

The present disclosure relates to an electronic device that includes a waveguide, a plurality of transceiving portions over the waveguide, and a cavity between the waveguide and the transceiving portions and connecting the waveguide with the transceiving portions. The cavity is configured for resonating of an electromagnetic wave from the waveguide or the transceiving portions.

IPC Classes  ?

• G02B 6/43 - Arrangements comprising a plurality of opto-electronic elements and associated optical interconnections
• G02B 6/42 - Coupling light guides with opto-electronic elements

Abstract

An electronic device is disclosed. The electronic device includes a first electronic component, a first power regulator disposed above the first electronic component. The first power regulator is configured to receive a first power along a lateral surface of the first electronic component without passing the first electronic component and to provide a second power to the first electronic component. The electronic device also includes a passive component disposed in an electrical path between the first electronic component and the first power regulator.

IPC Classes  ?

• H05K 1/18 - Printed circuits structurally associated with non-printed electric components
• H05K 7/20 - Modifications to facilitate cooling, ventilating, or heating
• H05K 1/02 - Printed circuits - Details

Abstract

A method for manufacturing a semiconductor package structure is provided. The method includes: (a) providing a semiconductor structure including a first device and a second device; (b) irradiating the first device by a first energy-beam with a first irradiation area; and (c) irradiating the first device and the second device by a second energy-beam with a second irradiation area greater than the first irradiation area of the first energy-beam.

IPC Classes  ?

• H01L 23/00 - SEMICONDUCTOR DEVICES NOT COVERED BY CLASS - Details of semiconductor or other solid state devices

Abstract

The present disclosure provides an electronic package. The electronic package includes a substrate, a first component disposed on the substrate and configured to detect an external signal, and an encapsulant disposed on the substrate. The electronic package also includes a protection element disposed on the substrate and physically separating the first device from the encapsulant and exposing the first device. The present disclosure also provides an electronic device.

IPC Classes  ?

• H01L 25/16 - Assemblies consisting of a plurality of individual semiconductor or other solid state devices the devices being of types provided for in two or more different main groups of groups , or in a single subclass of , , e.g. forming hybrid circuits
• H01L 31/12 - SEMICONDUCTOR DEVICES NOT COVERED BY CLASS - Details thereof structurally associated with, e.g. formed in or on a common substrate with, one or more electric light sources, e.g. electroluminescent light sources, and electrically or optically coupled thereto
• H01L 31/0216 - Coatings
• H01L 23/31 - Encapsulation, e.g. encapsulating layers, coatings characterised by the arrangement
• H05K 1/02 - Printed circuits - Details
• H05K 1/11 - Printed elements for providing electric connections to or between printed circuits

Abstract

A semiconductor device package includes a substrate and an antenna module. The substrate has a first surface and a second surface opposite to the first surface. The antenna module is disposed on the first surface of the substrate with a gap. The antenna module has a support and an antenna layer. The support has a first surface facing away from the substrate and a second surface facing the substrate. The antenna layer is disposed on the first surface of the support. The antenna layer has a first antenna pattern and a first dielectric layer.

IPC Classes  ?

• H01Q 1/22 - Supports; Mounting means by structural association with other equipment or articles
• H01Q 1/40 - Radiating elements coated with, or embedded in, protective material
• H01L 23/66 - High-frequency adaptations
• H01Q 21/00 - Antenna arrays or systems
• H01L 23/31 - Encapsulation, e.g. encapsulating layers, coatings characterised by the arrangement
• H01Q 21/06 - Arrays of individually energised antenna units similarly polarised and spaced apart

Abstract

A semiconductor device package includes a substrate having a surface, a conductive element disposed on the surface of the substrate, and an encapsulant disposed on the surface of the substrate and covering the conductive element. The conductive element has an upper surface facing away from the substrate and exposed from the encapsulant. Further, a roughness of the upper surface of the conductive element is greater than a roughness of a side surface of the conductive element.

IPC Classes  ?

• H01L 23/552 - Protection against radiation, e.g. light
• H01L 21/56 - Encapsulations, e.g. encapsulating layers, coatings
• H01L 23/04 - Containers; Seals characterised by the shape
• H01L 21/3213 - Physical or chemical etching of the layers, e.g. to produce a patterned layer from a pre-deposited extensive layer
• H01L 23/31 - Encapsulation, e.g. encapsulating layers, coatings characterised by the arrangement

Abstract

A semiconductor package structure and a method for manufacturing a semiconductor package structure are provided. The semiconductor package structure includes a first passivation layer, a first metal layer and a first semiconductor die. The first metal layer is embedded in the first passivation layer. The first metal layer defines a first through-hole. The first semiconductor die is disposed on the first passivation layer.

IPC Classes  ?

• H01L 23/544 - Marks applied to semiconductor devices, e.g. registration marks, test patterns
• H01L 21/56 - Encapsulations, e.g. encapsulating layers, coatings
• H01L 23/31 - Encapsulation, e.g. encapsulating layers, coatings characterised by the arrangement
• H01L 23/18 - Fillings characterised by the material, its physical or chemical properties, or its arrangement within the complete device
• H01L 27/148 - Charge coupled imagers
• H01L 23/00 - SEMICONDUCTOR DEVICES NOT COVERED BY CLASS - Details of semiconductor or other solid state devices

Abstract

An electronic package is provided. The electronic package includes an amplifier component, a control component, and a first circuit layer. The control component is disposed above the amplifier component. The first circuit layer is disposed between the amplifier component and the control component. The control component is configured to transmit a first signal to the amplifier component and to output a second signal amplified by the amplifier component.

IPC Classes  ?

• H01L 23/66 - High-frequency adaptations
• H01L 25/18 - Assemblies consisting of a plurality of individual semiconductor or other solid state devices the devices being of types provided for in two or more different subgroups of the same main group of groups , or in a single subclass of ,
• H01L 23/498 - Leads on insulating substrates
• H01L 23/367 - Cooling facilitated by shape of device
• H01L 23/31 - Encapsulation, e.g. encapsulating layers, coatings characterised by the arrangement
• H03F 3/04 - Amplifiers with only discharge tubes or only semiconductor devices as amplifying elements with semiconductor devices only

Abstract

A semiconductor package structure is provided. The semiconductor package structure includes an electronic component, and an inductance component. The protection layer encapsulates the electronic component and has a top surface and a bottom surface. The top surface and the bottom surface collectively define a space to accommodate the electronic component. The inductance component outflanks the space from the top surface and the bottom surface of the protection layer.

IPC Classes  ?

• H01L 23/552 - Protection against radiation, e.g. light
• H01L 23/31 - Encapsulation, e.g. encapsulating layers, coatings characterised by the arrangement
• H01L 49/02 - Thin-film or thick-film devices
• H01L 25/16 - Assemblies consisting of a plurality of individual semiconductor or other solid state devices the devices being of types provided for in two or more different main groups of groups , or in a single subclass of , , e.g. forming hybrid circuits