A semiconductor package (100) includes a first layer (128) including a semiconductor die (130) and a shunt (140) embedded within a first dielectric substrate layer (128), and metal pillars (122A –122C) extending therethrough. The semiconductor package further includes a second layer stacked on the first layer, the second layer including a metal trace (150A –150C) patterned on the first dielectric substrate layer, and a second dielectric substrate layer (158) over the metal trace. The metal trace electrically connects a first portion of the shunt to a first metal pillar (122A) of the metal pillars and electrically connects a second portion of the shunt to a second metal pillar (122B) of the metal pillars. The semiconductor package further includes a base layer opposite the second layer relative the first layer, the base layer forming exposed electrical contact pads (112A –112E) for the semiconductor package, the electrical contact pads providing electrical connections to the shunt, the metal pillars, and the semiconductor die.
H01L 23/52 - Arrangements for conducting electric current within the device in operation from one component to another
H01L 23/538 - Arrangements for conducting electric current within the device in operation from one component to another the interconnection structure between a plurality of semiconductor chips being formed on, or in, insulating substrates
H01L 23/48 - Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads or terminal arrangements
An apparatus is provided and includes a rotary encoder that comprises a stator (214), a rotor (212), and a controller (218). The stator (214) has an opening adapted to surround a first portion of a rotatable shaft (210), a transmit region, and a receive region. The rotor (212) has an opening adapted to surround a second portion of the rotatable shaft (210), an annular conductive region, and at least one conductor electrically coupled with the annular conductive region. The controller (218) has an input coupled to the receive region and has an output coupled to the transmit region. The controller (218) is configured to transmit a first signal on the output of the controller (218) and to the transmit region of the stator (214), receive a second signal on the input of the controller (218) and from the receive region of the stator (214), and determine, based on the second signal, a proximity of the at least one conductor to the receive region.
G01D 5/241 - Mechanical means for transferring the output of a sensing member; Means for converting the output of a sensing member to another variable where the form or nature of the sensing member does not constrain the means for converting; Transducers not specially adapted for a specific variable using electric or magnetic means influencing the magnitude of a current or voltage by varying capacitance by relative movement of capacitor electrodes
G01R 27/26 - Measuring inductance or capacitance; Measuring quality factor, e.g. by using the resonance method; Measuring loss factor; Measuring dielectric constants
In some examples, a circuit includes a resistor network (124), a filter (126), a current generator (128), and a capacitor (132). The resistor network has a resistor network output (164) and is adapted to be coupled between a switch terminal (162) of a power converter (104) and a ground terminal (154). The filter has a filter input and a filter output, the filter input coupled to the resistor network output. The current generator has a current generator output and first and second current generator inputs, the first current generator input configured to receive an input voltage and the second current generator input coupled to the filter output. The capacitor is coupled between the current generator output and the ground terminal.
A battery cell monitor circuit (106) includes a first serial transceiver (706), a second serial transceiver (708), and a command decoder (714). The command decoder (714) is configured to cause the first serial transceiver (706) or the second serial transceiver (708) to transmit a response to a battery monitoring command based on a response direction field included in the battery monitoring command.
A method (200) of fabricating a semiconductor device includes etching (205) a group of trenches in a semiconductor surface layer of a substrate. The group of trenches includes an outermost trench that has a first width and remaining trenches of the group of trenches have a second width that is less than the first width. The outermost trench is formed at an edge of the group of trenches. A dielectric liner is formed (210) in the group of trenches and the dielectric liner is etched (215) in an upper portion of the group of trenches to remove a partial thickness of the dielectric liner. A full thickness of the dielectric liner is maintained in a lower portion of the group of trenches. The group of trenches is filled (220) with a polysilicon layer.
H01L 29/78 - Field-effect transistors with field effect produced by an insulated gate
H01L 21/336 - Field-effect transistors with an insulated gate
H01L 27/088 - Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only the components being field-effect transistors with insulated gate
A semiconductor device (300), and methods of forming the same. In one example, the semiconductor device (300) includes a trench (305) in a substrate (310) having a top surface (302), and a shield (330) within the trench (305). The semiconductor device (300) also includes a shield liner (315) between a sidewall of the trench (305) and the shield (330), and a lateral insulator (345) over the shield (330) contacting the shield liner (315). The semiconductor device (300) also includes a gate dielectric layer (350) on an exposed sidewall of the trench (305) between the lateral insulator (345) and the top surface (302). The lateral insulator (345) may have a minimum thickness at least two times thicker than a maximum thickness of the gate dielectric layer (350).
A boost converter includes an input terminal (102), an output terminal (106), a switching terminal (112), a low-side transistor (108), and a down-mode detection circuit (302). The low-side transistor (108 ) is coupled to the switching terminal (112). The down-mode detection circuit (302) is coupled to the low-side transistor (108). The down-mode detection circuit (302) is configured to detect a voltage at the output terminal (106) greater than a voltage at the input terminal (102), and turn off the low-side transistor (108) based on the voltage at the output terminal (106) being greater than the voltage at the input terminal (102).
H02M 3/158 - Conversion of dc power input into dc power output without intermediate conversion into ac by static converters using discharge tubes with control electrode or semiconductor devices with control electrode using devices of a triode or transistor type requiring continuous application of a control signal using semiconductor devices only with automatic control of output voltage or current, e.g. switching regulators including plural semiconductor devices as final control devices for a single load
8.
CONTROL CIRCUIT WITH OVERCURRENT PREDICTION TO DRIVE CAPACITIVE LOAD
An apparatus (700) includes: an input (724) configured to receive an input voltage (714); an prediction circuit (706) coupled to the input (724) and configured to provide an overcurrent prediction (718) based on analysis of the input voltage (714); a delay circuit (704) coupled to the input (724); a gain control circuit (708) coupled to an output of the delay circuit (704) and configured to selectively adjust a gain applied to at least one frequency range of the input voltage (714) based on the overcurrent prediction (718); a driver (710) coupled to an output of the gain control circuit (708); and a capacitive load (712) coupled to an output of the driver (710).
A semiconductor device (100) includes an extended drain finFET (102). The drain drift region (128) of the finFET (102) extends between a drain contact region (132) and a body (124) of the finFET (102). The drain drift region (128) includes an enhanced portion (136) of the drain drift region (128) between the drain contact region (132) and the body (124). The drain drift region (128) also includes a first charge balance region and a second charge balance region laterally adjacent to, and on opposite sides of, the enhanced portion (136) of the drain drift region (128). The enhanced portion (136) of the drain drift region (128) and the drain contact region (132) have a first conductivity type; the body (124), the first charge balance region, and the second charge balance region have a second, opposite, conductivity type. The drain drift region (128) is wider than the body (124).
A semiconductor package (100) includes a semiconductor die (112) with an active surface (113) and an inactive surface (114), the active surface including metal pillars (116) providing electrical connections to functional circuitry of the semiconductor die, and a backside metal layer (118) on the inactive surface. The backside metal layer is attached to the inactive surface. The semiconductor package further includes a plurality of leads (122) with each of the leads including an internal leadfinger portion (125) and an exposed portion that includes a bonding portion (127). Distal ends of the metal pillars are in contact with and electrically coupled to the internal leadfinger portions. The backside metal layer is exposed on an outer surface of the semiconductor package. The bonding portions and the backside metal layer approximately planar to each other.
H01L 21/04 - Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer, carrier concentration layer
11.
ANALYTIC TECHNIQUES FOR IMPROVED SUPER TILING MACHINE LEARNING PROCESSING
Techniques for enhancing machine learning (ML) model execution. The technique includes determining an amount of memory (604) used to process layers (602) of a machine learning network having multiple layers, smoothing (652) the amount of memory used to process the layers of the machine learning network based on a number of layers, identifying change layers (654) where the smoothed amount of memory used changes more than a memory change threshold amount, grouping the layers of the machine learning network into a first layer grouping based on the identified change layers, and outputting the first layer grouping.
An electronic device (100) having a package structure (120) with conductive leads (102), first and second dies (106, 108) in the package structure (120), as well as first and second conductive plates (104, 105) electrically coupled to the respective first and second dies (106, 108) and having respective first and second sides (110, 114) spaced apart from and directly facing one another with a portion of the package structure (120) extending between the first side (110) of the first conductive plate (104) and the second side (114) of the second conductive plate (105) to form a capacitor (C1, C2). No other side of the first conductive plate (104) directly faces a side of the second conductive plate (105), and no other side of the second conductive plate (105) directly faces a side of the first conductive plate (104).
H01G 2/00 - CAPACITORS; CAPACITORS, RECTIFIERS, DETECTORS, SWITCHING DEVICES, LIGHT-SENSITIVE OR TEMPERATURE-SENSITIVE DEVICES OF THE ELECTROLYTIC TYPE - Details of capacitors not covered by a single one of groups
H01L 23/49 - Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads or terminal arrangements consisting of soldered or bonded constructions wire-like
H01L 21/58 - Mounting semiconductor devices on supports
H01L 21/60 - Attaching leads or other conductive members, to be used for carrying current to or from the device in operation
A power converter (200) including a piezoelectric resonator (210). The power converter includes a first transistor (220) coupled between an input terminal (IN) and a first plate (P1) of the piezoelectric resonator, and a second transistor (222) coupled between the first plate of the piezoelectric resonator and an output terminal (OUT). A load (235) may be coupled at the output terminal. Controller circuitry (240) has inputs coupled to the input node, the output node, and to the first plate of the piezoelectric resonator, and outputs coupled to control terminals of the first and second transistors. The controller circuitry operates to turn on the first transistor responsive to a comparison of voltages (Vsw1, Vin) at the first plate and the input terminal, turn on the second transistor responsive to a comparison of voltages (Vsw1, Vout) at the first plate and the output terminal, and turn off one of the first and second transistors responsive to an output level at the output terminal.
H01L 41/107 - Piezo-electric or electrostrictive elements with electrical input and electrical output
H02M 1/00 - APPARATUS FOR CONVERSION BETWEEN AC AND AC, BETWEEN AC AND DC, OR BETWEEN DC AND DC, AND FOR USE WITH MAINS OR SIMILAR POWER SUPPLY SYSTEMS; CONVERSION OF DC OR AC INPUT POWER INTO SURGE OUTPUT POWER; CONTROL OR REGULATION THEREOF - Details of apparatus for conversion
14.
AUTOMATED ANALOG AND MIXED-SIGNAL CIRCUIT DESIGN AND VALIDATION
A technique for designing circuits including receiving a data object (514) representing a circuit for a first process technology, the circuit including a first sub-circuit, the first sub-circuit including a first electrical component and a second electrical component arranged in a first topology; identifying the first sub-circuit in the data object (518) by comparing the first topology to a stored topology, the stored topology associated with the first process technology; identifying a first set of physical parameter values associated with first electrical component and the second electrical component of the first sub-circuit; determining a set of performance parameter values (520) for the first sub-circuit based on a first machine learning model of the first sub-circuit and the identified set of physical parameters; converting the identified first sub-circuit to a second sub-circuit (522) for the second process technology based on the determined set of performance parameter values; and outputting the second sub-circuit (526).
A method (200) includes attaching (204) semiconductor dies to die attach pads of first and second columns of the lead frame; enclosing (208) the semiconductor dies of the respective columns in respective first and second package structures; trimming (210) the lead frame to separate respective first and second lead portions of adjacent ones of the first and second columns of the lead frame; moving (214) the first columns along a column direction relative to the second columns; and separating (216) individual packaged electronic devices of the respective first and second columns from one another.
An integrated circuit device (100) and method comprising an IC chip (102) having metal interconnect levels (Ml-Mn) including a last copper interconnect level (Mn) and a chip-to-package interconnect (110) overlying and connected to the last copper interconnect level (Mn). The chip-to-package interconnect (110) having a via (112) connected to a first element of the last copper interconnect level (Mn) and a copper conductive structure (118) (e.g., bump copper). The via (112) includes a barrier material (112a) and a tungsten fill layer (112b), the via coupled between the copper conductive structure (118) and the first element.
A magnetic sensor circuit (100) includes a plurality of magnetic sensors (104A-C) having bias input and bias output terminals and first and second measurement terminals. The circuit includes a diagnostic sensor (108) having bias input and bias output terminals (110A-C, 112A-C) and first and second measurement terminals (122A-B). The circuit includes a first multiplexer (SI) configured to selectively couple a current source to the bias input terminals of the magnetic sensors or to the bias input terminal of the diagnostic sensor and includes a second multiplexer (S2) configured to selectively couple the bias output terminals of the magnetic sensors or the bias output terminal of the diagnostic sensor to a first terminal of a switch. The circuit includes a third multiplexer (S3) configured to selectively couple the measurement terminals of the magnetic sensors or the measurement terminals of the diagnostic sensor to differential input terminals of an amplifier.
For sensing pH of a fluid, a heating apparatus of a semiconductor die (102, 105, 107) controls a temperature of the fluid (114) to a first temperature. A first voltage of a gate (122) of a floating gate transistor (120) of the semiconductor die is measured while the temperature of the fluid is at the first temperature. Also, the heating apparatus controls the temperature of the fluid to a second temperature that is different than the first temperature. A second voltage of the gate is measured while the temperature of the fluid is at the second temperature. The pH of the fluid is determined based on the first and second voltages, the first temperature and the second temperature.
An equalization circuit (200) includes a feed-forward equalization (FEE) circuit (206) and a decision feedback equalization (DFE) circuit (220). The FFE circuit (206) includes a first FFE tap (208T), a second FFE tap (210T) coupled to the first FFE tap (208T), and a variable gain amplifier (218). The variable gain amplifier (218) includes an input and a programmable capacitor. The input is coupled to the first FFE tap (208T) and the second FFE tap (210T). The programmable capacitor is coupled to the input. The DFE circuit (220) includes an input and a DFE tap (224T). The input is coupled to the variable gain amplifier (218). The DFE tap (224T) is coupled to the input of the variable gain amplifier (218).
Techniques for updating a client device are provided that include receiving, by a client device, a software update (204) and a certificate (206) associated with the software update (204), verifying, by the client device, the certificate (206) associated with the software update (204) based on a stored public key of the client device (230), extracting an update scope value (216-224) from the certificate, comparing the update scope value (216-224) against a corresponding attribute of the update, and either applying the software update based on the comparing, or rejecting the software update based on the comparing.
A method includes rendering, by at least one processor, a first sub-frame (400) of an image, where the first sub-frame (400) includes a first subset of pixels (202) of the image. The method includes displaying the first sub-frame (400) on a display. The method also includes rendering, by the at least one processor, a second sub-frame of the image, where the second sub-frame includes a second subset of pixels (212) of the image, and where the second sub-frame is shifted a half-pixel diagonally from the first sub-frame (400). The method also includes displaying the second sub-frame on the display after displaying the first sub-frame (400), where the display is optically shifted a half-pixel diagonally to display the second sub-frame.
G09G 3/32 - Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED]
22.
MICROELECTROMECHANICAL DEVICE WITH BEAM STRUCTURE OVER SILICON NITRIDE UNDERCUT
In described examples, a microelectromechanical system (MEMS) (100) is located on a substrate (102). A silicon nitride (SiN) layer (104,134) is on a portion of the substrate. A mechanical structure (120, 132) has a first end (125) embedded in the SiN layer and a second end (124) cantilevered from the SiN layer.
B81B 7/02 - Microstructural systems containing distinct electrical or optical devices of particular relevance for their function, e.g. microelectro-mechanical systems (MEMS)
H01L 21/365 - Deposition of semiconductor materials on a substrate, e.g. epitaxial growth using reduction or decomposition of a gaseous compound yielding a solid condensate, i.e. chemical deposition
H01L 21/033 - Making masks on semiconductor bodies for further photolithographic processing, not provided for in group or comprising inorganic layers
23.
BANDGAP REFERENCE WITH INPUT AMPLIFIER FOR NOISE REDUCTION
A bandgap reference circuit (100) includes first through fourth bipolar junction transistors (BJTs) (M1-M4). The base and collector of the first BJT (M1) are shorted together. The second BJT (M2) is coupled to the first BJT (M1) via a first resistor (R1). The base of the third BJT (M3) is coupled to the base of the first BJT (M1). The base and collector of the fourth BJT (M4) are coupled together and also are coupled to the base of the second BJT (M2). A second resistor (R2) is coupled to the fourth emitter of the fourth BJT (M4). A third resistor (R3) is coupled to the second resistor (R2) and to the emitter of the second BJT (M2). An operational amplifier (OP1) has a first input coupled to the first resistor (R1) and the collector of the second BJT (M2), a second input coupled to the emitter of the third BJT (M3) and the collector of the fourth BJT (M4), and an output coupled to the collectors of the first and third BJTs (M1 and M3).
G05F 1/56 - Regulating voltage or current wherein the variable actually regulated by the final control device is dc using semiconductor devices in series with the load as final control devices
G05F 3/20 - Regulating voltage or current wherein the variable is dc using uncontrolled devices with non-linear characteristics being semiconductor devices using diode-transistor combinations
A device (102) includes an amplifier (306) having inverting and non-inverting inputs and an output. The device includes a capacitor (312) coupled to a first node (311) and to ground (309), a resistor (310) coupled to the first node and the amplifier output, and a first switch (320) coupled to the first node and a current sink (322), which is coupled to ground. The device includes AND gate (318) having inputs and an output coupled to control terminal of first switch. The device includes a first comparator (314) having non-inverting and inverting inputs and an output coupled to an AND gate input; a second comparator (324) having a non-inverting input coupled to the amplifier output, an inverting input coupled to a transistor stack (328), and an output coupled to an AND gate input; and a second switch (327) coupled to the transistor stack and to a current source (326), the second switch having a control terminal coupled to the first comparator output.
An integrated circuit (100) and method of making an integrated circuit (100) is provided. The integrated circuit (100) includes a substrate (102) having an electronic component (104). A substrate-based coil (110, 112) is on the substrate (102) and the substrate-based coil (110, 112) is electrically coupled to the electronic component (104). A magnetic mold compound (134) encapsulates the substrate-based coil (110, 112) and the electronic component (104).
H01L 27/02 - Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including integrated passive circuit elements with at least one potential-jump barrier or surface barrier
H01L 21/98 - Assembly of devices consisting of solid state components formed in or on a common substrate; Assembly of integrated circuit devices
An apparatus (200) includes a lens (202), a transducer and a driver, where the lens (202) has a first side (203), a second side (205), and a lens radius (224), and the transducer has a transducer outer radius (222). The transducer is coupled to the first side (203) of the lens (202), and the transducer outer radius (222) is less than the lens radius (224). The driver has output terminals coupled to the transducer and is configured to provide an oscillating drive signal (VDRV) at a non-zero frequency to vibrate the lens (202). An o-ring (208) is positioned between a clamp (201) and the second side (205) of the lens (202), where the o-ring (208) has a nominal radius (220) that is less than or equal to a nominal radius (223) of the transducer (102).
B08B 7/02 - Cleaning by methods not provided for in a single other subclass or a single group in this subclass by distortion, beating, or vibration of the surface to be cleaned
B08B 11/00 - Cleaning flexible or delicate articles by methods or apparatus specially adapted thereto
B60S 1/56 - Cleaning windscreens, windows, or optical devices specially adapted for cleaning other parts or devices than front windows or windscreens
Akondy Raja Raghupathi, Venkataratna, Subrahmanya Bharathi
Sabapathy, Sam, Gnana
Abstract
In described examples, a pulse width modulation (PWM) system (200) includes an initiator (202) and a receiver (204). The initiator (202) includes an initiator counter (228) and an initiator PWM signal generator (210). The initiator counter (228) advances an initiator count in response to an initiator clock signal. The initiator PWM signal generator (210) generates an initiator PWM signal in response to the initiator count. The receiver (204) includes a receiver counter (230), a receiver PWM signal generator (222), and circuitry configured to reset the receiver count. The receiver counter (230) advances a receiver count in response to a receiver clock signal. The receiver PWM signal generator (222) generates a receiver PWM signal in response to the receiver count. The circuitry resets the receiver count in response to a synchronization signal and based on an offset.
Adevice (e.g., an IoT device) includes a first radio (126), and a memory device (227) accessible to the first radio (126). The memory device is configured to store a fingerprinting feature (229) for a specific transmitter device. A second radio (122) and a processor (210) are also included. The processor (210) is coupled to the first and second radios (126, 122). The first radio (126) is configured to extract a fingerprinting feature of a first received wireless signal, determine that the extracted feature matches the fingerprinting feature stored in the storage device, and responsive to the determination that the extracted feature matches the feature stored in the storage device (227), cause the second radio (122) to transition from a lower power state to a higher power state of operation and continue to receive the incoming signal.
A system on a chip (SoC) (100) for smoke detection includes power regulator circuits coupled to respective pins (VLX, VBST, VINT, VCC, PLDO, VMCU) and analog sensor amplifier circuits (110, 112, 114) that are each coupled to a respective pin (e.g., VBST, VINT) of the pins coupled to the power regulator circuits. A first analog sensor amplifier circuit of the analog sensor amplifier circuits has a photoelectric amplifier (112) circuit, a first LED driver (114) and a second LED driver (116). The SoC also has a digital core (138) that includes a digital logic circuit, register bits (143), and an MCU communication circuit (142). The MCU communication circuit is coupled to a data pin (SDA), the register bits are coupled to control or modify operation of the power regulator circuits and the analog sensor amplifier circuits, and the register bits are operable to be written to by an MCU (102).
A device includes a hardware data processing node configured to execute a respective task, and a hardware thread scheduler including a hardware task scheduler (300). The hardware task scheduler (300) is coupled to the hardware data processing node and has a producer socket (304), a consumer socket (302), and a spare socket (306, 307). The spare socket is configured to provide data control signals also provided by a first socket of the producer and consumer sockets responsive to a memory-mapped register (224) being a first value. The spare socket is configured to provide data control signals also provided by a second socket of the producer and consumer sockets responsive to the memory-mapped register (224) being a second value.
Methods, apparatus, systems and articles of manufacture for an example event processor (308a-g) are described to retrieve an input event and an input event timestamp corresponding to the input event, generate an output event based on the input event and the input event timestamp, in response to determination that an input event threshold is exceeded within a threshold of time, and an anomaly detector (304) to retrieve the output event, determine whether the output event indicates threat to functional safety of a system on a chip (302), and in response to determining the output event indicates threat to functional safety of the system on a chip (302), adapt a process for the system on a chip (302) to preserve functional safety.
A sample-and-hold circuit (210) includes a first input resistor (RP), a first transistor (MINP), a first capacitor (C1), a second resistor (R1), and a first current source device (L1). A first current terminal of the first transistor (MINP) is coupled to the first input resistor (RP). A first terminal of the first capacitor (C1) is coupled to the second current terminal of the first transistor (MINP) at a first output node. A first terminal of the first resistor (R1) is coupled to the second terminal of the first transistor (MINP) at the first output node. The first current source device (L1) is coupled the first input resistor (RP) and to the first current terminal of the first transistor (MINP).
Methods and apparatus to extend local buffer of a hardware accelerator are described herein. In some examples, an apparatus, including a local memory (550), a first hardware accelerator (HWA) (210), a second HWA (215), the second HWA (215) and the first HWA (210) connected in a flexible data pipeline, and a spare scheduler (585) to manage, in response to the spare scheduler inserted in the flexible data pipeline, data movement between the first HWA (210) and the second HWA (215) through the local memory (550) and a memory (510). Local buffer extension may be performed by software to control data movement between local memory and other system memory. The other system memory may be on-chip memory (510) and/or external memory (515). The HWA sub-system (520) includes a set of spare schedulers to manage the data movement. Data aggregation may be performed in the other system memory. Additionally, the other system memory may be utilized for conversion between data line and data block.
G06F 9/38 - Concurrent instruction execution, e.g. pipeline, look ahead
G06F 13/28 - Handling requests for interconnection or transfer for access to input/output bus using burst mode transfer, e.g. direct memory access, cycle steal
34.
INTEGRATED SYSTEM-IN-PACKAGE WITH RADIATION SHIELDING
A system in a package (SIP) (195) includes carrier layer regions (107) that have a dielectric material with a metal post (109) therethrough, where adjacent carrier layer regions define a gap. A driver IC die (110) is positioned in the gap having nodes connected to bond pads (111) exposed by openings in a top side of a first passivation layer (113), with the bond pads facing up. A dielectric layer (116) is on the first passivation layer and carrier layer region (107) that includes filled through vias (116a) coupled to the bond pads and to the metal post (109). A light blocking layer (118) is on sidewalls and a bottom of the substrate. A first device (140) includes a light emitter that has first bondable features (151a). The light blocking layer blocks at least 90% of incident light. The first bondable features are flipchip mounted to a first portion of the bond pads.
H01L 21/60 - Attaching leads or other conductive members, to be used for carrying current to or from the device in operation
H01L 21/48 - Manufacture or treatment of parts, e.g. containers, prior to assembly of the devices, using processes not provided for in a single one of the groups
35.
CONSTANT RIPPLE INJECTION CIRCUIT FOR SWITCHING CONVERTER
H02M 3/158 - Conversion of dc power input into dc power output without intermediate conversion into ac by static converters using discharge tubes with control electrode or semiconductor devices with control electrode using devices of a triode or transistor type requiring continuous application of a control signal using semiconductor devices only with automatic control of output voltage or current, e.g. switching regulators including plural semiconductor devices as final control devices for a single load
In an example, an apparatus includes an error amplifier (202), a buffer (206), a transistor (208), and a current-mode feedforward ripple canceller (CFFRC) (106). The error amplifier has an amplifier output, a first input, and a second input, the error amplifier second input configured to receive a reference voltage (Vref). The buffer has a buffer input and a buffer output, the buffer input coupled to the error amplifier output. The transistor has a gate, a source, and a drain, the gate coupled to the buffer output, the drain coupled to the first input. The transistor is configured to receive an input voltage (VIN) at the source and provide an output voltage at the drain. The CFFRC has a CFFRC input and a CFFRC output, the CFFRC output coupled to the gate, and the CFFRC input configured to receive VIN.
An integrated circuit (100), comprising a plurality of pins (104, 106, 108), including a signal output pin (108). The integrated circuit also comprises a plurality of signal nodes (114N, 116N, 118N). Each node in the plurality of signal nodes is operable to store a respective internal data signal. The integrated circuit also comprises a plurality of testing circuits (120, 122, 124). Each testing circuit in the plurality of testing circuits configured to sample a respective internal data state and in response to concurrently couple a unique output signal to a same pin (104) in the plurality of pins, other than the signal output pin.
Systems, methods, and circuitries are provided that use an interleaved multi-level converter (101) to convert an input signal received at an input node (102) into an output signal at an output node (106). In one example, a power conversion system (100) includes a first multi-level switching circuit (110), a second multi-level switching circuit (150), and a control circuit (105). The first multi-level switching circuit and the second multi-level switching circuit are coupled to a switching node (103), the input node (102), and a reference node (104). The control circuit (105) is configured to generate, based on the output signal, switching control signals as pulse width modulated signals having a duty cycle to control the output signal and provide the switching control signals to the first multi-level switching circuit (110) and the second multi-level switching circuit (150).
H02M 3/158 - Conversion of dc power input into dc power output without intermediate conversion into ac by static converters using discharge tubes with control electrode or semiconductor devices with control electrode using devices of a triode or transistor type requiring continuous application of a control signal using semiconductor devices only with automatic control of output voltage or current, e.g. switching regulators including plural semiconductor devices as final control devices for a single load
H02M 7/483 - Converters with outputs that each can have more than two voltage levels
H02M 1/44 - Circuits or arrangements for compensating for electromagnetic interference in converters or inverters
39.
SWITCHING CONVERTER WITH ANALOG ON-TIME EXTENSION CONTROL
A system (600) includes: 1) a battery (640) configured to provide an input voltage (VIN); 2) switching converter circuitry (650) coupled to the battery (640), wherein the switching converter circuitry includes a power switch (S1); 3) a load (RLOAD) coupled to an output of the switching converter circuitry (650); and 4) a control circuit (660) coupled to power switch (S1). The control circuit (660) includes: 1) a switch driver circuit (630) coupled to the power switch (S1); 2) a summing comparator circuit (670) configured to output a first control signal (LOOPRAW) that indicates when to turn the power switch (S1) on; and 3) an analog on-time extension circuit (610) configured to extend an on-time of the power switch (S1) by gating a second control signal (SHOT) with the first control signal (LOOPRAW), wherein the second control signal (SHOT) indicates when to turn the power switch (S1) off.
H02M 3/158 - Conversion of dc power input into dc power output without intermediate conversion into ac by static converters using discharge tubes with control electrode or semiconductor devices with control electrode using devices of a triode or transistor type requiring continuous application of a control signal using semiconductor devices only with automatic control of output voltage or current, e.g. switching regulators including plural semiconductor devices as final control devices for a single load
H02M 1/08 - Circuits specially adapted for the generation of control voltages for semiconductor devices incorporated in static converters
40.
INTEGRATED CIRCUIT FOR SMOKE DETECTOR HAVING COMPATIBILITY WITH MULTIPLE POWER SUPPLIES
An AFE chip (101) for a smoke detector includes a DC/DC boost converter (102) having a boost input, a boost output, and a boost upper power supply input (110). The boost input is coupled to a first pin (PI) that is adapted for coupling to a battery through an inductor (L) and the boost output is coupled to a second pin (P2). The DC/DC boost converter (102) is configured to not switch when a voltage on the second pin (P2) is greater than a programmed boost voltage (VPGM). A set of power regulator circuits (113) have a power input, which is coupled to a third pin (P3), and a power output. The third pin is adapted for receiving an input voltage, the power output is coupled to provide an internal voltage (Vint), and the set of power regulator circuits (113) are further coupled to the boost upper power supply input (110).
In a described example, an apparatus (200) includes a package substrate with a split die pad having a slot (224) between a die mount portion and a wire bonding portion (226); a first end of the wire bonding portion coupled to the die mount portion at one end of the slot; a second end of the wire bonding portion coupled to a first lead (210) on the package substrate. At least one semiconductor die (202) is mounted on the die mount portion; a first end of a first wire bond (220) is bonded to a first bond pad on the at least one semiconductor die (202); a second end of the first wire bond (220) is bonded to the wire bonding portion (226); and mold compound (222) covers the at least one semiconductor die, the die mount portion, the wire bonding portion, and fills the slot (224).
Disclosed embodiments include an Ethernet PHY device comprising a serial communication interface (320) adapted to be coupled to a microcontroller (312), a register set (332) having registers, and a checksum generator circuit (360) coupled to the register set and configured to calculate a current checksum. The embodiment also includes a checksum register (338) that is coupled to the checksum generator (360) and is configured to store the current checksum. It further includes a checksum checker (334) that is coupled to the checksum generator (360), the checksum register (338) and the microcontroller (310), and is configured to compare a previous value of the checksum to the current checksum and, responsive to the previous value being different than the current checksum, send an error report to the microcontroller. The embodiment also includes a trigger circuit (336) coupled to the checksum generator configured to send a checksum start signal to the checksum generator.
H03K 19/177 - Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components using elementary logic circuits as components arranged in matrix form
G06F 9/38 - Concurrent instruction execution, e.g. pipeline, look ahead
43.
METHODS, APPARATUS, AND SYSTEMS TO DRIVE A TRANSISTOR
Methods, apparatus, and systems are described to drive a transistor. An example apparatus includes a regulator (505) including a first input terminal (522) adapted to be coupled to a control terminal (172) of a transistor (150), a first output terminal (524), and a second output terminal (528), a first stage (510) including a first input terminal (530) coupled to the first output terminal of the regulator and an output terminal (534) adapted to be coupled to the control terminal of the transistor, and a second stage (515) including an input terminal (536) coupled to the second output terminal of the regulator, and an output terminal (538) adapted to be coupled to the control terminal of the transistor.
H03K 17/687 - Electronic switching or gating, i.e. not by contact-making and -breaking characterised by the use of specified components by the use, as active elements, of semiconductor devices the devices being field-effect transistors
A multi-chip isolation (ISO) device package (100) includes a leadframe including leads (114, 124), an interposer substrate (122) including a top copper layer (122a) and a bottom metal layer (122c), with a dielectric layer (122b) in-between. A first IC die (110) and a second IC die (120) include circuitry (180a, 180b) including a transmitter or a receiver, and first and second bond pads (181a, 181b) are attached top side up in the package. A laminate transformer (130) is attached to the top copper layer positioned lateral to the IC die. Bondwires (141-145) wirebond the first bond pads to first pads on the laminate transformer and to the leads or the lead terminals, and bondwires wirebond the second bond pads to second pads on the laminate transformer and to leads or the lead terminals, and a mold compound (160) provides encapsulation.
H01L 23/50 - Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads or terminal arrangements for integrated circuit devices
H01L 23/538 - Arrangements for conducting electric current within the device in operation from one component to another the interconnection structure between a plurality of semiconductor chips being formed on, or in, insulating substrates
45.
HIGH VOLTAGE ISOLATION BARRIER WITH ELECTRIC OVERSTRESS INTEGRITY
An electronic device (100) comprises a multilevel metallization structure (103) over a semiconductor layer (101) and including a first region (196), a second region (198), a pre-metal level (110) on the semiconductor layer (101), and N metallization structure levels (120, 130, 140, 150, 160, 170, 180) over the pre-metal level (110), N being greater than 3. The electronic device (100) also comprises an isolation component (104) in the first region (196), the isolation component (104) including a first terminal (106) and a second terminal (108) in different respective metallization structure levels (130, 180), as well as a conductive shield (105) between the first region (196) and the second region (198) in the multilevel metallization structure (103), the conductive shield (105) including interconnected metal lines (126, 136, 146, 156, 166, 176, 186) and trench vias (118, 128, 138, 148, 158, 168, 178) in the respective metallization structure levels (120, 130, 140, 150, 160, 170, 180) that encircle the first region (196).
H01L 21/56 - Encapsulations, e.g. encapsulating layers, coatings
H01L 21/76 - Making of isolation regions between components
H01L 23/485 - Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads or terminal arrangements consisting of lead-in layers inseparably applied to the semiconductor body consisting of layered constructions comprising conductive layers and insulating layers, e.g. planar contacts
A current sense loop (100) includes an attenuator circuit (104), which has an embedded input chopper circuit (110), and an amplifier circuit (106), which has an output chopper circuit (112). The embedded input chopper (110) has a first chopper input (114) that is coupled to a first attenuator input (107), a first chopper output (116) that is coupled to a first attenuator output (118), a second chopper input (124) that is coupled to a second attenuator input (109), and a second chopper output (126) that is coupled to a second attenuator output (128). The amplifier circuit (106) has a first input (120) coupled to the first attenuator output (118) and a second input (130) coupled to the second attenuator output (128). An NFET (MN1) has a gate coupled to the amplifier output (136), a source coupled to a ground plane, and a drain coupled to the second attenuator input (109).
H03H 1/00 - Constructional details of impedance networks whose electrical mode of operation is not specified or applicable to more than one type of network
H03F 1/56 - Modifications of input or output impedances, not otherwise provided for
G01R 19/00 - Arrangements for measuring currents or voltages or for indicating presence or sign thereof
A receiver circuit includes a feedback loop (390, 391, 392) including a device. The receiver circuit also includes a register and a sequencer (340). The sequencer (340) is configured to, responsive to an error signal being below a threshold value, cause the register to store a value indicative of the state of the feedback loop. The sequencer (340) is also configured to cause the feedback loop to transition to a lower power state, and, responsive to a detected wake-up event, cause the previously stored value indicative of the state of the feedback loop (390, 391, 392) to be loaded from the register into the device and enable the feedback loop.
A receiver circuit includes an ADC (102), a processing channel (136), and an interference detection path (116). The processing channel (136) is configured to process data samples provided by the ADC (102), and includes a notch filter (110). The interference detection path (116) is configured to detect interference in the data samples, and includes a slicer, a slicer error circuit, and an interference detection circuit. The slicer is configured to slice input of the notch filter (110). The slicer error circuit is configured to compute an error of the slicer. The interference detection circuit configured to detect an interference signal in the error of the slicer, and set the notch filter (110) to attenuate the interference signal.
A method includes receiving an input signal (206) at a filter, where the filter includes a plurality of filter taps (209A-209N), and where each of a first filter tap (209A) and a second filter tap has a weighting coefficient (234). The method also includes shutting down the first filter tap (209A) based on the weighting coefficient (234) of the first filter tap (209 A) being below a threshold and the weighting coefficient (234) of the second filter tap being below the threshold, where the second filter tap is next to the first filter tap (209A).
H04B 3/23 - Reducing echo effects or singing; Opening or closing transmitting path; Conditioning for transmission in one direction or the other using a replica of transmitted signal in the time domain, e.g. echo cancellers
H04B 15/00 - Suppression or limitation of noise or interference
A method of regulating power supply to a speaker and a system for regulating power supply to a speaker comprising a generating (S310) of a low frequency signal output to the speaker, sensing (S330) a current and a voltage of the speaker after the low frequency signal is output to the speaker, measuring an impedance of the speaker based on the current and voltage, determining (S340) a temperature of the speaker and comparing with a threshold value, and lowering (S360) a power supply to the speaker where the temperature is above the threshold value.
A receiver circuit includes an interleaved ADC (106), a first delay circuit (112), a second delay circuit (114), a first processing channel, a second processing channel, and an interleaving ADC timing error detector circuit (206). The interleaved ADC(106) includes a first ADC (108) and a second ADC (110) in parallel. The first delay circuit (112) delays a first clock signal provided to the first ADC (108). The second delay circuit (114) delays a second clock signal provided to the second ADC (110). The first processing channel processes data samples provided by the first ADC (108), and includes a first sheer (138). The second processing channel processes data samples provided by the second ADC (110), and includes a second sheer (140). The interleaving ADC timing error detector circuit (206) controls delay of the first delay circuit (112) and the second delay circuit (114) based on an output signal of the first sheer (138), and an output signal or an input signal of the second sheer (140).
A projection system (100) includes: an illumination source (101) configured to output illumination light; a phase light modulator (PLM) (105) optically coupled to the illumination source, the PLM configured to: receive the illumination light; phase modulate the illumination light while displaying a phase hologram, to produce modulated light; and projection optics (106) coupled to the PLM, the projection optics configured to receive the modulated light and to project an image (107) responsive to the modulated light; wherein both a mean in intensity and a variance in intensity in bright regions of the projected image is greater than the mean intensity and the variance in intensity in dark regions of the projected image.
G03H 1/16 - Processes or apparatus for producing holograms using Fourier transform
B81B 7/02 - Microstructural systems containing distinct electrical or optical devices of particular relevance for their function, e.g. microelectro-mechanical systems (MEMS)
An example of a power supply system (100) includes a switching voltage regulator (102) comprising at least one switch (104) configured to conduct an input current to generate an output voltage responsive to a switching signal and based on an input voltage. The system (100) also includes a current regulator (106) configured to generate a current sample voltage based on an amplitude of the input current relative to a reference current defining a maximum average amplitude setpoint of the input current to set a switching time defining a switching period of the at least one switch (104). The system (100) also includes a switch controller (110) configured to provide the switching signal to control the at least one switch (104) based on an amplitude of the output voltage relative to a reference voltage and based on the switching time.
G05F 1/56 - Regulating voltage or current wherein the variable actually regulated by the final control device is dc using semiconductor devices in series with the load as final control devices
H02H 3/10 - Emergency protective circuit arrangements for automatic disconnection directly responsive to an undesired change from normal electric working condition, with or without subsequent reconnection responsive to excess current additionally responsive to some other abnormal electrical conditions
A method includes receiving first data at a controller (104) of an ADAS via a first virtual channel (212A) of a camera serial interface 2 (CSI-2) data interface (214). The method also includes receiving second data at the controller (104) of the ADAS via a second virtual channel (212B) of the CSI-2 data interface (214). The method includes storing the first data at a first address in a memory (208), the first address specified by the first virtual channel (212A). The method also includes storing the second data at a second address of a control register (204), the control register specified by the second data. The method includes performing a test using the first data and the second data.
An amplifier (700) comprises a common emitter stage coupled to a first (720) and a second (725) input, a common base stage coupled to the common emitter stage and to a first (730) and a second (735) output, and a cancellation path coupled to the common emitter stage and the common base stage and to the first and second outputs. The cancellation path generates a first cancellation signal that is 180 degrees out of phase with a first leakage signal at the first output and a second cancellation signal that is 180 degrees out of phase with a second leakage signal at the second output. The cancellation path comprises a first cancellation transistor (M6) coupled to the common emitter stage and the common base stage and to the first output and a second cancellation transistor (M5) coupled to the common emitter stage and the common base stage and to the second output.
A power converter (100) includes a watchdog circuit (104) having an input adapted to be coupled to a pause signal of a switching power supply. The watchdog circuit (104) is configured to provide a start signal at an output thereof based on the pause signal indicating that the power converter (100) has stopped switching for a threshold duration that is less than an audible range. A pulse generator circuit (110) has an input coupled to the output of the watchdog circuit and is configured to generate at least one pulse based on the start signal. A switch circuit (114) has an input terminal adapted to be coupled to an input voltage and at least one other terminal adapted to be coupled to an inductor (116). The switch circuit (114) is configured to provide negative current from an output (120) of the power converter through the at least one other terminal based on the at least one pulse.
H02M 3/335 - Conversion of dc power input into dc power output with intermediate conversion into ac by static converters using discharge tubes with control electrode or semiconductor devices with control electrode to produce the intermediate ac using devices of a triode or a transistor type requiring continuous application of a control signal using semiconductor devices only
A system (100) includes a red light emitting diode (LED) (108), a blue LED (104), and a green LED (106). The system (100) also includes a red laser (138), a first filter (128), a second filter (116), and a lens (118). The system (100) includes a first optical path (148) that includes the red LED (108), the red laser (138), the first filter (128), the second filter (116), and the lens (118), where the first filter (128) has a filter response to transmit red light from the red laser (138) and to reflect red light from the red LED (108). The system (100) also includes a second optical path (124) that includes the blue LED (104), the green LED (106), the second filter (116), and the lens (118), where the second filter (116) has a filter response to transmit blue light from the blue LED (104), to transmit green light from the green LED (106), to reflect red light from the red laser (138), and to reflect red light from the red LED (108).
A circuit (206) includes signal conditioner circuitry (208), level shifter circuitry (212), and state detector and controller circuitry (210) coupled between the signal conditioner circuitry (208) and the level shifter circuitry (212). The state detector and controller circuitry 208 includes receiver circuitry (228-238) and a finite state machine (222) coupled to the receiver circuitry (228-238). The finite state machine (222) is configured to detect a first data rate from signals, control operation of the signal conditioner circuitry (208) responsive to detecting the first data rate, and control operation of the level shifter circuitry (212) during a second data rate.
Aspects of the disclosure provide for a circuit (100) comprising a transmitter (108). In at least some examples, the transmitter is configured to receive an input signal and a loss of signal indication signal. The transmitter is further configured to dynamically modify processing of the input signal based on the loss of signal indication signal. The transmitter modifies processing of the input signal based on the loss of signal indication signal by processing the input signal via a limiting driver signal path (112) to generate an output signal when the loss of signal indication signal has a first value and processing the input signal via a linear driver signal path (114) to generate the output signal when the loss of signal indication signal has a second value.
A semiconductor package (100) includes a conductive pad (112), a semiconductor die (101) with an aluminum bond pad (102) over a dielectric layer of the semiconductor die, a gold bump (106) on the aluminum bond pad, a first intermetallic layer of gold and aluminum between the aluminum bond pad and the gold bump, a copper ball bond (104) on the gold bump, a second intermetallic layer of copper and gold between the copper ball bond and the gold bump, a copper wire (107) extending from the copper ball bond to the conductive pad, and a stitch bond (105) between the copper wire and the conductive pad.
A system (100) includes: a host processor (102); a transceiver (104) coupled to the host processor (102); and a power amplifier (126A-126N) coupled to an output of the transceiver (104). The transceiver (104) includes a transmit chain with digital pre-distortion (DPD) logic configured to: perform DPD correction operations on transmit data (107) received by the transmit chain; and output corrected transmit data (109A-109N) based on the performed DPD correction operations, wherein the output corrected transmit data (109A-109N) is provided to the power amplifier (126A-126N).
A system (100) includes an eUSB2 transmitter (104), wherein the eUSB2 transmitter (104) is configured to provide a data set comprising a data packet default sync bits and surplus sync bits. The system (100) also includes an eUSB2 to USB 2.0 repeater (120) coupled to the eUSB2 transmitter (104), wherein the eUSB2 to USB 2.0 repeater (120) is configured to remove the surplus sync bits and to output the data packet and the default sync bits.
A voltage supervisor (100) includes a first transistor (116) coupled between a first supply voltage (112) and a second supply voltage (124). The voltage supervisor (100) includes a second transistor (120) coupled between the first supply voltage (112) and the second supply voltage (124). The voltage supervisor (100) is configured to provide a first current (126) proportional to a difference in gate-to-source voltages of the first transistor (116) and the second transistor (120). The voltage supervisor (100) is also configured to provide a second current (146) proportional to a difference in the first supply voltage (112) and the difference in gate-to-source voltages of the first transistor (116) and the second transistor (120). The voltage supervisor (100) is configured to compare the first current (126) to the second current (146) to determine a voltage value that changes a state responsive to the first supply voltage (112) crossing a threshold.
Aspects of this description provide for a circuit (400). In at least some examples, the circuit includes an output node (420) at which a voltage for transmission via a differential conductor is present. The circuit further includes a first pull-up network coupled between a voltage supply node (418) and the output node and configured to include a first amount of resistance. The circuit further includes a second pull-up network (408) coupled between a voltage supply node and the output node and configured to include a second amount of resistance. The circuit further includes a comparator (416) having a first input terminal coupled to the output node, a second input terminal configured to receive a reference voltage, and an output terminal configured to output a comparison result.
An integrated circuit (100) is described herein that includes a semiconductor substrate (102). First and second piezoresistive sensors (108, 112) are on or in the substrate (102) where each piezoresistive sensor (108, 112) has a respective sensing axis (110, 114) extending in first and second directions respectively parallel with a surface (104) of the substrate (102), where the second direction is perpendicular to the first direction. A third piezoresistive sensor (116) is on or in the substrate (102) and has a respective sensing axis (118) extending in a third direction parallel with the surface (104) of the substrate (102) that is neither parallel nor perpendicular to the first and second directions.
H01L 27/20 - Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including magnetostrictive components
H01L 41/04 - SEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR - Details thereof - Details of piezo-electric or electrostrictive elements
66.
MICROELECTROMECHANICAL SYSTEM (MEMS) DEVICE WITH BACKSIDE PINHOLE RELEASE AND RE-SEAL
A device includes a substrate (110) having first and second layers (111, 113) and an insulator layer (112) between the first and second layers (111, 113). A microelectromechanical system (MEMS) structure (120) is provided on a portion (117) of the second layer (113). A trench (130) is formed in the second layer (113) and around at least a part of a periphery of the portion (117) of the second layer (113). An undercut (150) is formed in the insulator layer (112) and adjacent to the portion (117) of the second layer (113). The undercut (150) separates the portion (117) of the second layer (113) from the first layer (111). First and second pinholes (140) extend from a plane of the insulator layer and in the first layer (111). The first and second pinholes (140) are in fluid communication with the undercut (150) and the trench (130).
An oscillator (31) for use in pulse communication of pulse signals with a startup latency and a pulse oscillation signal (such as for use in a transmitter for OOK pulse communication with pulse modulation). The oscillator (31) includes an EC resonator (35) having a tank impedance, and including a high-side node (Vp), and a low-side node Vm, and having a tank voltage corresponding to [Vp-Vn], A pulse startup circuit (39 A), includes a PMOS transistor with a source connected to a supply voltage VDD, and a drain connected through a resistance R to the Vp node (where R is significantly larger than the tank impedance), and connected to an attenuation capacitance, in parallel with the resistance R. The PMOS control terminal is coupled to receive a kick start pulse to initiate a pulse signal, the oscillator (31) can include high-side (39 A) and low-side pulse (39B) startup circuits.
A phase light modulator includes a base plate (110), a mirror (102), a perforated hinge plate (106), and first second support posts (104). The perforated hinge plate (106) supports the mirror (102). The perforated hinge plate (106) has first and second flexural arms (107). The perforated hinge plate (106) is configured to move toward or away from the base plate (110) based on application of a potential difference between the base plate (110) and the perforated hinge plate (106). The first flexural arm (107) is connected to the first support posts (104), and the second flexural arm (107) is connected to the second support post (104).
A semiconductor device (150) includes a semiconductor surface having circuitry (180) with metal interconnect layers (122) over the semiconductor surface including a selected metal interconnect layer providing an interconnect trace (171) having a first and second end (171a, 171b). A top dielectric layer (119) is on the top metal interconnect layer. A redistribution layer (RDL) (123) is on the top dielectric layer. A corrosion interruption structure (CIS) (170) including the interconnect trace bridges an interrupting gap (123b) in a trace of the RDL.
H01L 21/50 - Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the groups
H01L 23/525 - Arrangements for conducting electric current within the device in operation from one component to another including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body with adaptable interconnections
70.
WIRELESS DEVICE WITH SUBSTRATE TO ANTENNA COUPLING
A device comprises an integrated circuit (IC) die (205), a substrate (210), a printed circuit board (PCB) (250), an antenna (260), and a waveguide stub (270A). The IC die is affixed to the substrate, which comprises a signal launch (220A) on a surface of the substrate that is configured to emit or receive a signal. The substrate and the antenna are affixed to the PCB, such that the signal launch and a waveguide opening of the antenna are aligned and comprise a signal channel (230A). The waveguide stub is arranged as a boundary around the signal channel. In some implementations, the waveguide stub has a height of λ/4, where λ represents a wavelength of the signal. In some implementations, the antenna includes the waveguide stub; in others, the substrate includes the waveguide stub.
H02M 3/158 - Conversion of dc power input into dc power output without intermediate conversion into ac by static converters using discharge tubes with control electrode or semiconductor devices with control electrode using devices of a triode or transistor type requiring continuous application of a control signal using semiconductor devices only with automatic control of output voltage or current, e.g. switching regulators including plural semiconductor devices as final control devices for a single load
Aspects of the disclosure provide for a circuit (112), in some examples, including a storage element (118), a co-processor (122), and a telemetry sequencer (120) coupled to the storage element and the co-processor. The telemetry sequencer is configured to implement a digital state machine to receive configuration information indicating a type of telemetry data for generation, retrieve operations and operands, where the operations and the operands define a sequential series of actions for execution to generate the telemetry data, drive the co-processor with the operations and the operands by passing some of the operations and some of the operands to the co-processor for processing by the co-processor, receive, from the co-processor, and store an intermediate output of the series of actions as the telemetry data in a first format, and receive, from the co-processor, and store a final output of the series of actions as the telemetry data in a second format.
A system (100) includes a platform (124) and a contactor (105). The platform (124) has a side configured to support a frame (122) with a carrier structure (120) and electronic devices (102) each having first and second sides (141, 142) and a terminal (103), the first side (141) positioned on the carrier structure (120), and the terminal (103) exposed in a first portion of the second side (142). The contactor (105) has first and second sides (151, 152), a contact (104) and a heater (106). The contact (104) is exposed on the first side (151) of the contactor (105) to contact the terminal (103) in a first portion of the second side of a selected one of the electronic devices (102), and the heater (106) is exposed on the first side (151) of the contactor to apply heat to a second portion of the second side (142) of the selected one of the electronic devices (102).
A microelectronic device (100) is formed by dispensing discrete amounts of a mixture (109) of photoresist resin and solvents from droplet-on-demand sites (108) onto a wafer (101) to form a first photoresist sublayer (112), while the wafer (101) is at a first temperature which allows the photoresist resin to attain less than 10 percent thickness non-uniformity. The wafer (101) moves under the droplet-on-demand sites (108) in a first direction to form the first photoresist sublayer (112). A portion of the solvents in the first photoresist sublayer (112) is removed. A second photoresist sublayer is formed on the first photoresist sublayer (112) using the droplet-on-demand sites (108) while the wafer (101) is at a second temperature to attain less than 10 percent thickness non-uniformity in the combined first (112) and second photoresist sublayers. The wafer (101) moves under the droplet-on-demand sites (108) in a second direction for the second photoresist sublayer, opposite from the first direction.
In described examples, a method of operating a transceiver (700) with a transmitter (702) and a receiver (706) includes generating a frequency reference (708). In the transmitter (704): A phase locked loop (PEL) (722) generates a first voltage controlled oscillator (VCO) control voltage responsive to the frequency reference (708). A VCO (714) in the transmitter generates a transmitter VCO signal responsive to the first VCO control voltage, and the PEL (722) is locked to the transmitter VCO signal. In the receiver (706): A signal is received. A receiver VCO (734) generates a receiver VCO signal responsive to the first or a second VCO control voltage. The receiver VCO signal is multiplied by the received signal to generate an I component, and by the received signal phase shifted by 90° to generate a Q component. The second VCO control signal is generated responsive to the I component and the Q component.
A peripheral proxy subsystem (306) is placed between multiple hosts (302, 304), each having a root controller (312, 316), and single root I/O virtualization (SR-IOV) peripheral devices (308) that are to be shared. The peripheral proxy subsystem (306) provides a root controller (318) for coupling to the endpoint (320) of the SR-IOV peripheral device (308) or devices and multiple endpoints (310, 314) for coupling to the root controllers (312, 316) of the hosts (302, 304). The peripheral proxy subsystem (306) maps the virtual functions of an SR-IOV peripheral device(308) to the multiple endpoints (310, 314) as desired to allow the virtual functions to be allocated to the hosts (302, 304). The virtual functions of the SR-IOV peripheral device (308) are then presented to the appropriate host (302, 304) as a physical function or a virtual function.
An image data frame is received (405) from an external source. An error concealment operation is performed on the received image data frame in response to determining (410) that a first frame size of the received image data frame is erroneous. The first frame size of the image data frame is determined to be erroneous based on at least one frame synchronization signal associated with the image data frame. An image processing operation is performed on the received image data frame on which the error concealment operation has been performed, thereby enabling an image processing module to perform the image processing operation without entering into a deadlock state and thereby prevent a host processor from having to execute hardware resets of deadlocked modules.
H04N 19/895 - Methods or arrangements for coding, decoding, compressing or decompressing digital video signals using pre-processing or post-processing specially adapted for video compression involving methods or arrangements for detection of transmission errors at the decoder in combination with error concealment
78.
DATA ADAPTATION IN HARDWARE ACCELERATION SUBSYSTEMS
Methods, apparatus, systems, and articles of manufacture are described herein to enable data aggregation and pattern adaptation in hardware acceleration subsystems. In some examples, a hardware acceleration subsystem (310) includes a first scheduler (382a), a first hardware accelerator (350a) coupled to the first scheduler (382a) to process at least a first data element and a second data element, and a first load store engine (352a) coupled to the first hardware accelerator (350a), the first load store engine (352a) configured to communicate with the first scheduler (382a) at a superblock level by sending a done signal to the first scheduler (382a) in response to determining that a block count is equal to a first BPR value and aggregate the first data element and the second data element based on the first BPR value to generate a first aggregated data element.
A converter system (100) includes a first switch (102) and a controller (110) configured to switch the first switch (102) between first and second states based on input and output voltages of the converter system (100), wherein the controller (110) includes: a timer unit (200) including a first timer (202) configured to determine a first duration based on a target switching frequency of the converter system (100), and a second timer (212) configured to determine a second duration based on a predetermined duration equal to or greater than a minimum duration of the first state of the first switch (102) and the input and output voltages; and a control logic unit (124), configured to switch the first switch (102) from the second state to the first state upon expiration of both the first and second durations.
G05F 1/40 - Regulating voltage or current wherein the variable is actually regulated by the final control device is ac using discharge tubes or semiconductor devices as final control devices
H02M 1/088 - Circuits specially adapted for the generation of control voltages for semiconductor devices incorporated in static converters for the simultaneous control of series or parallel connected semiconductor devices
A system includes a plurality of antennas (303, 304, 306, 308), an access control mechanism (320), and a computing resource (412). The computing resource (412) is configured to initiate each of multiple antennas (303, 304, 306, 308) to transmit a wireless signal and receive values indicative of signal strength of the wireless signals from the multiple antennas (303, 304, 306, 308). The computing resource (412) also is configured to calculate a position of a wireless electrical device (120) based on the received values and calculate an error value of the calculated position of the wireless electrical device (120). Further, the computing resource (412) is configured to determine that the error value is greater than an error threshold and to disable the access control mechanism (320).
In described examples, a method of operating a transmitter (302) includes generating a frequency reference signal having a reference frequency and outputting the frequency reference to a phase locked loop (PEL) (326) that includes a voltage controlled oscillator (VCO) (324). The VCO (324) output is locked to the frequency reference signal to form a carrier signal (327). The transmitter (302) receives an I input signal (304), a Q input signal (306), and a direct current (DC) leaky carrier signal (310). Either the I input signal (304) or the Q input signal (306) is added to the leaky carrier signal (310). The carrier signal (327) is modulated with the resulting two signals using an I-Q mixer (318) to generate a modulated signal (319) that includes an unmodulated carrier signal component. The modulated signal (319) is then transmitted.
H04B 1/38 - Transceivers, i.e. devices in which transmitter and receiver form a structural unit and in which at least one part is used for functions of transmitting and receiving
H04L 7/033 - Speed or phase control by the received code signals, the signals containing no special synchronisation information using the transitions of the received signal to control the phase of the synchronising-signal- generating means, e.g. using a phase-locked loop
A multi-hop mesh network (100) includes a root network device (102) and a first network device (104B). The first network device (104B) is configured to establish a first direct wireless connection with the root network device (102) and negotiate a first shared secret key with the root network device (102). The multi-hop network (100) further includes a second network device (142) configured to establish a second direct wireless connection with the first network device (104B) and negotiate a second shared secret key with the first network device (104B).
H04W 12/0431 - Key distribution or pre-distribution; Key agreement
H04L 9/28 - Arrangements for secret or secure communications; Network security protocols using particular encryption algorithm
H04W 84/02 - Hierarchically pre-organised networks, e.g. paging networks, cellular networks, WLAN [Wireless Local Area Network] or WLL [Wireless Local Loop]
83.
ALTERNATING FRAME PROCESSING OPERATION WITH PREDICTED FRAME COMPARISONS
Frames from an image stream or streams are processed by independently operating digital signal processors (DSPs) (404A, 404B), with only frame checking microprocessors (402A, 402B) operating in a lockstep mode. In one example, two DSP (404A, 404B) are operating on alternate frames. Each DSP (404A, 404B) processes the frames and produces prediction values for the next frame. The lockstep microprocessors (402A, 402B) develop their own next frame prediction. The lockstep processors (402A, 402B) compare issued frames and previously developed predicted frames for consistency. If the predictions are close enough, the issued frame passes the test. The lockstep processors (402A, 402B) then compare the issued frame to the preceding two frames for a similar consistency check. If the prior frames are also close enough, the issued frame is acceptable.
H04N 19/597 - Methods or arrangements for coding, decoding, compressing or decompressing digital video signals using predictive coding specially adapted for multi-view video sequence encoding
G06T 1/20 - Processor architectures; Processor configuration, e.g. pipelining
84.
BACKGROUND NOISE ESTIMATION AND VOICE ACTIVITY DETECTION SYSTEM
A method includes selecting (304) a frame of an audio signal. The method further includes determining (308) a first power spectral density (PSD) distribution of the frame. The method further includes generating (310) a first reference PSD distribution indicating an estimate of ( background noise in the frame based on a non-linear weight, a second reference PSD distribution of a previous frame of the audio signal, and a second PSD distribution of the previous frame. The method further includes determining (320) whether voice activity is detected in the frame based on the first PSD distribution of the frame and the first reference PSD distribution.
Aspects of this description provide for an integrated circuit (100). In at least some examples, the integrated circuit include an input pin (114) and an analog-to-digital converter (ADC) (104) comprising an input terminal coupled to the input pin and an output terminal. The circuit further includes a logic circuit (102) comprising an input terminal coupled to the output terminal of the ADC, a first output terminal, and a second output terminal, The circuit further includes a resistance circuit (103). In an example, the resistance circuit includes a resistor (106) coupled between the input pin and a first node (118), a first switch (108) coupled between the first node and a reference voltage pin (112), and a second switch (110) coupled between the first node and a ground pin (116).
H01L 27/02 - Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including integrated passive circuit elements with at least one potential-jump barrier or surface barrier
H03K 19/003 - Modifications for increasing the reliability
Described examples include an apparatus having a substrate (602) with a substrate surface (630). The apparatus also includes an element (600) with a planar surface (628) facing the substrate surface and with a nonplanar surface (626) opposite the planar surface facing away from the substrate surface.
G02B 26/08 - Optical devices or arrangements for the control of light using movable or deformable optical elements for controlling the direction of light
G03F 7/00 - Photomechanical, e.g. photolithographic, production of textured or patterned surfaces, e.g. printed surfaces; Materials therefor, e.g. comprising photoresists; Apparatus specially adapted therefor
Aspects of the present disclosure provide for a circuit (102). In at least some examples, the circuit includes a dual-role port (124) for transferring power to the circuit and from the circuit. The circuit also includes a micro-processing unit (114). The micro-processing unit is configured to control the circuit to operate as a sink device to receive power from a source device via the dual-role port when the power supply includes a first amount of stored energy, detect, at the dual-role port, a change in a termination resistance of the source device, and control the circuit to limit power transfer from the circuit to the power supply via the dual-role port when the power supply changes in status from a sourcing state to a sinking state.
A wireless station (STA) (103 A) in a wireless local area network (WLAN) (100) performs a method to avoid media access control (MAC) padding of a physical layer convergence protocol data unit (PPDU) (e.g., a trigger-based (TB) PPDU, etc.). The method can reduce current or power consumption by the STA (103 A), which can in turn optimize the STA (103 A) and, in certain instances, the WLAN (100) as whole. In one example, the method includes the STA (103 A) receiving a trigger frame from an access point (AP) (101). The trigger frame specifies a length of a PPDU. The method further includes the STA (103A) generating a TB PPDU based on the specifications in the trigger frame. In particular, the STA (103A) generates a PPDU that has a length that is less than the length specified by the trigger frame. The method also includes the STA (103 A) transmitting the generated PPDU to the AP (101).
A reconfigurable image processing pipeline (100) includes an image signal processor (ISP) (130), a control processor (110), and a local memory (150). ISP processes raw pixel data for a frame based on an image processing parameter and provides lines of processed pixel data to control processor via a first interface (175). For each region of interest (ROI) in the frame, ISP generates auto-exposure and auto-white balance (2A) statistics based on the lines for the ROI and writes them to the local memory via a second interface (185A). Control processor reads 2A statistics from the local memory, determines the image processing parameter based on them, and provides the image processing parameter to ISP. ISP also generates an integer N bin histogram for control processor, which sums a portion of the N total bins and compares the summed bin count to a lighting transition threshold. The image processing parameter is further based on the comparison.
An integrated circuit includes: a clock domain having a clock domain input; and clock management logic coupled to the clock domain. The clock management logic includes: a PLL having a reference clock input and a PLL clock output; a divider having a divider input and a divider output, the divider input coupled to the PLL clock output; and bypass logic having a first clock input, a second clock input, a bypass control input, and a bypass logic output, the first clock input coupled to divider output, the second clock input coupled to the reference clock input, and the bypass logic output coupled to the clock domain input. The bypass logic selectively bypasses the PLL and divider responsive to a bypass control signal triggered by a reset signal. The reset signal also triggers a reset control signal delayed relative to the bypass control signal.
H04L 27/144 - Demodulator circuits; Receiver circuits with demodulation using spectral properties of the received signal, e.g. by using frequency selective- or frequency sensitive elements
H03L 7/00 - Automatic control of frequency or phase; Synchronisation
A method for error handling in a geometric correction engine (GCE) is provided that includes receiving (800) configuration parameters by the GCE, generating (802), by the GCE in accordance with the configuration parameters, output blocks of an output frame based on corresponding blocks of an input frame, detecting (804), by the GCE, a run-time error during the generating, and reporting (806), by the GCE, an event corresponding to the run-time error.
In described examples, an SoC (200) includes at least two voltage domains (201, 202) interconnected with a communication bus (203). Detection logic (122, 236, 230) in a first voltage domain (201) determines when a voltage error occurs in a second voltage domain (202) and isolates communication (205) via the communication bus when a voltage error or a timing error is detected.
An integrated circuit (100) includes: a debugger (102); and an interface (104) coupled to the debugger (102). The interface (104) has: arbitration logic (106) coupled to the debugger (102); a power processor (108) coupled to the arbitration logic (106); and a power management network (112) coupled to the power processor (108). The integrated circuit (100) also includes subsystems (114A-114N) coupled to the interface (104). The debugger (102) is configured to perform debugging operations of the subsystems (114A-114N) via the interface (104).
Described herein is a technology for a wakeup pattern - data stream correlation by a detector to provide a trigger condition for a microcontroller in a wakeup receiver (WuRX). For example, the detector (118) includes a data packet layer (200) with a plurality of index registers (202) that are updated through sampling of data streams (208). A sample clock [204] is coupled to each of the plurality of index registers to independently activate each of the plurality of index registers. A shared comparator (212) will then compare the updated plurality of index registers to corresponding shift registers (210) that are initialized with rotating wakeup pattern bits (220). Based upon a number of matching results, the detector generates a triggering signal (228) that facilitates a low-power operating mode to a high-power operating mode change.
An example apparatus includes a processor (930) and a replacement generator (110) coupled to the processor (930) and configured to detect an access, by the processor (930), of a first instruction at a first address in a first memory (130), in response to the detected access, compare the first address to a set of trigger instruction address records in a second memory (135), wherein the set of trigger instruction address records includes a first trigger instruction address record (912) that is associated with a first replacement address record (914) and a first replacement value record (916), and based on the first address corresponding to the first trigger instruction address record (912), replace a first value at a second address in a third memory specified by the first replacement address record (912) with a second value specified by the first replacement value record (916).
Systems (800) and methods for sensorless trapezoidal control of brushless DC motors (802) provide effective high-torque start-up and low speed operation without the use of Hall effect sensors or encoders during motor operation. The systems and methods also provide the ability to boost signal-to-noise ratio for motor start-up and low speed operation via an augmenting supply voltage. Sampling architectures and current-dependent inductance modeling architectures for the control systems are also described.
A CNN (402) operates on the disparity or motion outputs of a block matching hardware module, such as a DMPAC module (522), to produce refined disparity or motion streams which improve operations in images having ambiguous regions. As the block matching hardware module (522) provides most of the processing, the CNN (402) can be small and thus able to operate in real time, in contrast to CNNs (402) which are performing all of the processing. In one example, the CNN (402) operation is performed only if the block hardware module (522) output confidence level is below a predetermined amount. The CNN (402) can have a number of different configurations and still be sufficiently small to operate in real time on conventional platforms.
A digital to analog converter (DAC) device (200) includes a thermometric DAC segment (202) responsive to a thermometric encoding of a first portion of a digital code, a binary scaled DAC segment (204) responsive to a second portion of the digital code, and a resistor ladder DAC segment (205) responsive to a third portion of the digital code. The thermometric DAC segment (202) includes a plurality of first resistors (212, 216, 220) connected to a reference voltage (201) in parallel and is configured to selectively connect the first plurality of resistors (212, 216, 220) to a current output node (277) based on the thermometric encoding. The binary scaled DAC segment (204) includes a plurality of second resistors (232, 236, 240, 244) connected to the reference voltage in parallel and having binary scaled resistances. The binary scaled DAC segment (204) is configured to selectively connect the plurality of second resistors (232, 236, 240, 244) to the current output node (277) based on the second portion.
In described examples an integrated circuit (IC) (100) has multiple layers of dielectric material (110) overlying at least a portion of a surface of a substrate (102). A trench (106) is etched through the layers of dielectric material to expose a portion the substrate to form a trench floor (105), the trench being surrounded by a trench wall formed by the layers of dielectric material. A metal perimeter band (321) surrounds the trench adjacent the trench wall, the perimeter band being embedded in one of the layers of the dielectric material.
In a described example, an integrated circuit (IC) includes a metal oxide semiconductor (MOS) transistor (100) formed in a semiconductor substrate (106). The transistor (100) includes a gate structure (104) formed over a surface of the substrate (106) and source and drain regions having a first conductivity type formed in the substrate on both sides of the gate structure (104). A well region (112) having a second opposite conductivity type is between the source and drain regions under the gate structure (104). The well region (112) includes a well dopant and a through-gate co-implant species. The well dopant and the co-implant species have a retrograde profile extending from the surface of the substrate (106) into the well region (112).
H01L 27/085 - Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only
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