A semiconductor device making it easy to detect disconnection in source wires and achieving a reduction in resistance and an inspection method for the semiconductor device are provided. A semiconductor device according to the present embodiment includes: a lead frame; a semiconductor chip on the lead frame; a source pad provided in the semiconductor chip; a plurality of source wires connected to the source pad; a disconnection detection wire connected to the source pad; source terminals connected to the plurality of source wires; and a disconnection detection terminal connected to the disconnection detection wire. One end of the disconnection detection wire is positioned in vicinity of a corner of the source pad closer to the disconnection detection terminal side.
A bonding region is specified by having a horizontal line partially constituting crosshairs displayed on a monitor of a wire bonding apparatus superimposed on a first line segment of a first marker, and having a vertical line partially constituting the crosshairs superimposed on a first line segment of a second marker.
H01L 25/065 - Assemblies consisting of a plurality of individual semiconductor or other solid state devices all the devices being of a type provided for in the same subgroup of groups , or in a single subclass of , , e.g. assemblies of rectifier diodes the devices not having separate containers the devices being of a type provided for in group
H01L 25/16 - Assemblies consisting of a plurality of individual semiconductor or other solid state devices the devices being of types provided for in two or more different main groups of groups , or in a single subclass of , , e.g. forming hybrid circuits
3.
SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING THE SAME
A semiconductor device including an oscillation circuit includes a MISFET having a halo region formed on a semiconductor substrate and a plurality of MISFETs having no halo regions formed on the semiconductor substrate. Gate electrodes of the plurality of MISFETs having no halo regions are electrically connected to each other. The plurality of MISFETs having no halo regions is used in a pair transistor included in the oscillation circuit.
H01L 27/06 - Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body including a plurality of individual components in a non-repetitive configuration
H01L 21/265 - Bombardment with wave or particle radiation with high-energy radiation producing ion implantation
H01L 21/266 - Bombardment with wave or particle radiation with high-energy radiation producing ion implantation using masks
H01L 29/08 - Semiconductor bodies characterised by the shapes, relative sizes, or dispositions of the semiconductor regions with semiconductor regions connected to an electrode carrying current to be rectified, amplified, or switched and such electrode being part of a semiconductor device which comprises three or more electrodes
H01L 29/423 - Electrodes characterised by their shape, relative sizes or dispositions not carrying the current to be rectified, amplified or switched
A common lead frame can be used for both a first package and a second package and has a planar shape according to specifications of each of a first chip used in the first package and a second chip used in the second package, and a thickness of at least a part of a lead portion through which any one of a first cutting line corresponding to an outer peripheral side of the first package and a second cutting line corresponding to an outer peripheral side of the second package passes is smaller than a thickness of a lead portion through which the first cutting line and the second cutting line do not pass.
H01L 21/48 - Manufacture or treatment of parts, e.g. containers, prior to assembly of the devices, using processes not provided for in a single one of the groups
A trench is formed in a semiconductor substrate. A first silicon oxide film is formed in an inside of the trench. A poly-crystalline silicon film is formed on the first silicon oxide film. A second silicon oxide film is formed from the poly-crystalline silicon film by performing a thermal oxidation treatment to the poly-crystalline silicon film. Thus, an insulating film including the first silicon oxide film and the second silicon oxide film is formed. A first conductive film is formed so as to embed the inside of the trench via the insulating film.
This invention provides a method of managing secret information that ensures that key information in the discard phase can be invalidated and that the system cannot be started. In method of managing secret information in a semiconductor device, the semiconductor device has an OTP (One Time Programmable) module, a security module and a processor. The OTP module further has an OTP memory for storing a secret information and a lifecycle flag for defining an operation phase and a discard phase, a sequencer for reading information stored in the OTP memory and a register for storing the information read by the sequencer. The security module performs a process by the secret information. The processor requests the process to the security module when changing the operation phase to the discard phase and sends a request to the security module to invalidate the secret information.
G06F 21/57 - Certifying or maintaining trusted computer platforms, e.g. secure boots or power-downs, version controls, system software checks, secure updates or assessing vulnerabilities
G06F 21/79 - Protecting specific internal or peripheral components, in which the protection of a component leads to protection of the entire computer to assure secure storage of data in semiconductor storage media, e.g. directly-addressable memories
A height of an upper surface of a control gate electrode is lower than a highest position of a lower surface of a silicide layer on a memory gate electrode adjacent to the control gate electrode via an ONO film. As a result, a structure in contact with the ONO film between the control gate electrode and the memory gate electrode is only the control gate electrode and the memory gate electrode made of polysilicon.
H01L 29/423 - Electrodes characterised by their shape, relative sizes or dispositions not carrying the current to be rectified, amplified or switched
H01L 27/11521 - Electrically programmable read-only memories; Multistep manufacturing processes therefor with floating gate characterised by the memory core region
H01L 27/11526 - Electrically programmable read-only memories; Multistep manufacturing processes therefor with floating gate characterised by the peripheral circuit region
H01L 27/11568 - Electrically programmable read-only memories; Multistep manufacturing processes therefor with charge-trapping gate insulators, e.g. MNOS or NROM characterised by the memory core region
H01L 27/11573 - Electrically programmable read-only memories; Multistep manufacturing processes therefor with charge-trapping gate insulators, e.g. MNOS or NROM characterised by the peripheral circuit region
H01L 29/788 - Field-effect transistors with field effect produced by an insulated gate with floating gate
H01L 29/792 - Field-effect transistors with field effect produced by an insulated gate with charge trapping gate insulator, e.g. MNOS-memory transistor
A semiconductor device includes an insulating substrate and an upper inductor that is formed on the insulating substrate and is a component of a transformer that performs contactless communication between different potentials. Here, the upper inductor is configured to be applied with a first potential. The upper inductor is formed so as to be magnetically coupled to a lower inductor that is configured to be applied with a second potential different from the first potential.
H01L 25/16 - Assemblies consisting of a plurality of individual semiconductor or other solid state devices the devices being of types provided for in two or more different main groups of groups , or in a single subclass of , , e.g. forming hybrid circuits
H01F 27/30 - Fastening or clamping coils, windings, or parts thereof together; Fastening or mounting coils or windings on core, casing, or other support
H01L 23/00 - SEMICONDUCTOR DEVICES NOT COVERED BY CLASS - Details of semiconductor or other solid state devices
A semiconductor device includes a logic circuit, a memory, and a storage device. The storage device has a first special information storage region into which special information is written before a solder reflow process, a second special information storage region into which special information for updating is written after the solder reflow process, and a data storage region. The first special information storage region is constituted by a memory cell having a high reflow resistance and in which data is retained even after the solder reflow process. The second special information storage region and the data storage region are constituted by memory cells having a low reflow resistance and in which data may not be retained during the solder reflow process.
Methods and systems for operating a voltage regulator are described. A integrated circuit can be configured to adjust at least one of a deadtime parameter and a drive strength parameter of a power stage based on at least one of an input voltage being provided to a power stage, a switch node voltage of the power stage, and an output current of the power stage. A controller of the power stage can be further configured to adjust a deadtime of the power stage based on adjustment of the deadtime parameter. The controller can be further configured to adjust a drive strength of the first driver and the second driver based on adjustment of the drive strength parameter.
H02M 1/38 - Means for preventing simultaneous conduction of switches
H02M 1/08 - Circuits specially adapted for the generation of control voltages for semiconductor devices incorporated in static converters
H02M 3/158 - Conversion of dc power input into dc power output without intermediate conversion into ac by static converters using discharge tubes with control electrode or semiconductor devices with control electrode using devices of a triode or transistor type requiring continuous application of a control signal using semiconductor devices only with automatic control of output voltage or current, e.g. switching regulators including plural semiconductor devices as final control devices for a single load
11.
SEMICONDUCTOR DEVICE AND SERIAL COMMUNICATION INTERFACE CONTROL METHOD
A semiconductor device includes a first clock; a second clock; a first baud rate generator generating the basic clock by using the first clock; a second baud rate generator generating the basic clock by using the second clock; and a control circuit correcting the first baud rate generator. The control circuit includes: a correction operation signal output circuit outputting a correction operation signal on the basis of the second clock of the second baud rate generator; and a correction value setting circuit outputting a correction value setting signal on the basis of the correction operation signal. The second baud rate generator counts a correction period in accordance with the correction operation signal by using the first clock on the basis of the correction value setting signal, and sets a baud rate correction value on the basis of a count result.
A semiconductor device includes a bus control circuit that controls access to a slave shared by a plurality of masters. The bus control circuit includes a plurality of priority determination circuits corresponding to the plurality of masters. The priority determination circuit is configured to, when receiving an urgent access from a corresponding master, change a priority level signal included in an access request from the corresponding master to allocate a high priority level for emergency and allocate a low priority level to a master other than the corresponding master.
G06F 13/372 - Handling requests for interconnection or transfer for access to common bus or bus system with decentralised access control using a time-dependent priority, e.g. individually loaded time counters or time slot
13.
INDUCTIVE CHARGER APPARATUS WITH MULTIPLE CHARGING PATHS AND METHOD FOR CHARGING THEREWITH
Exemplary embodiments may include a device with an input power component, a system supply component, an inductive charger component operatively coupled to the input component and the system component, and a direct charger component operatively coupled to the inductive charger and the system component. Exemplary embodiments may further include an input node of the inductive charger component and an input node of the direct charger component operatively coupled to an output node of the input power component at a first device node. Exemplary embodiments may also include a method of receiving an input power signal, obtaining a charging condition, entering a first charging state, in accordance with the obtained charging condition satisfying a first charging condition, and entering a second charging state, in accordance with the obtained charging condition satisfying a second charging condition.
A semiconductor device according to one embodiment, includes: a wiring substrate having a core insulating layer; a semiconductor chip mounted on an upper surface of the wiring substrate; a plurality of solder balls formed on a lower surface of the wiring substrate; and a heat sink having a first portion fixed to a back surface of the semiconductor chip via a first adhesive layer, and a second portion located around the first portion and fixed to the wiring substrate via a second adhesive layer. Here, a portion of the plurality of solder balls is arranged at a position overlapping with each of the second portion of the heat sink and the second adhesive layer. Also, a second thickness of the second adhesive layer is greater than two times a first thickness of the first adhesive layer.
It is related to improving a performance of a semiconductor device and suppressing yield deterioration. Using a resist pattern as a mask, an ion-implantation is performed from an upper surface of a semiconductor substrate to form an ion-implanted layer in the semiconductor substrate. By subsequently, another ion-implantation is performed. Then, another ion-implanted layer is formed in the semiconductor substrate so as to overlap with the ion-implanted layer. Next, a heat treatment is performed on the semiconductor substrate to diffuse impurities contained in the ion-implanted layers, thereby an p-type floating region is formed.
H01L 21/225 - Diffusion of impurity materials, e.g. doping materials, electrode materials, into, or out of, a semiconductor body, or between semiconductor regions; Redistribution of impurity materials, e.g. without introduction or removal of further dopant using diffusion into, or out of, a solid from or into a solid phase, e.g. a doped oxide layer
H01L 21/265 - Bombardment with wave or particle radiation with high-energy radiation producing ion implantation
H01L 21/266 - Bombardment with wave or particle radiation with high-energy radiation producing ion implantation using masks
H01L 21/28 - Manufacture of electrodes on semiconductor bodies using processes or apparatus not provided for in groups
16.
DUAL DIGITAL PHASE LOCK LOOP WITH UNMODULATION COUPLING
Semiconductor devices for synchronizing networks are described. A semiconductor device can include an analog phase-lock loop (APLL) configured to output a first signal. The semiconductor device can further include a first digital phase-lock loop (DPLL) configured to output a second signal. The semiconductor device can further include a second DPLL configured to output a third signal. A combination of the first signal and the second signal can be used to generate a first output clock signal. A difference resulting from a subtraction of the second signal from the third signal can be used to generate a second output clock signal.
H03L 7/07 - Automatic control of frequency or phase; Synchronisation using a reference signal applied to a frequency- or phase-locked loop using several loops, e.g. for redundant clock signal generation
H03L 7/107 - Automatic control of frequency or phase; Synchronisation using a reference signal applied to a frequency- or phase-locked loop - Details of the phase-locked loop for assuring initial synchronisation or for broadening the capture range using a variable transfer function for the loop, e.g. low pass filter having a variable bandwidth
H03L 7/23 - Indirect frequency synthesis, i.e. generating a desired one of a number of predetermined frequencies using a frequency- or phase-locked loop using more than one loop with pulse counters or frequency dividers
H04L 7/033 - Speed or phase control by the received code signals, the signals containing no special synchronisation information using the transitions of the received signal to control the phase of the synchronising-signal- generating means, e.g. using a phase-locked loop
17.
SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING THE SAME
A first trench extending in a Y direction is formed in each of a semiconductor substrate located in a cell region and the semiconductor substrate located in an outer peripheral region. A second trench is formed in the semiconductor substrate in the outer peripheral region so as to surround the cell region in a plan view. A p-type body region is formed in the semiconductor substrate in each region. A plurality of p-type floating regions is formed in the semiconductor substrate in the outer peripheral region. A field plate electrode is formed at a lower portion of each of the first trench and the second trench. A gate electrode is formed at an upper portion of the first trench located in the cell region. A floating gate electrode is formed at an upper portion of each of the first trench located in the outer peripheral region and the second trench.
The present disclosure relates technique capable of electrically monitoring a recess amount of a semiconductor substrate. That is, a semiconductor device includes the semiconductor substrate of a first conductivity type having a first main surface and a second main surface, a first area provided on the first main surface, and a second region provided on the first main surface between the first areas. The second area includes an evaluation element. The evaluation element includes: a first semiconductor region of a second conductivity type provided in the first main surface side; a second semiconductor region of the first conductivity type provided on the first main surface side of the first semiconductor region; a first electrode pad in contact with the first semiconductor region; and a second electrode pad in contact with the second semiconductor region.
An electrical test of a semiconductor device is conducted by electrically connecting a plurality of leads of the semiconductor device with a plurality of electrodes of a test board via a plurality of socket terminals of a socket of a test apparatus, respectively. At least a part of the socket is disposed inside a chamber of the test apparatus, and the test board is disposed outside the chamber. The semiconductor device is to be cooled by a cool air circulating in the chamber. The socket has a cavity portion through which the cool air circulating in the chamber can pass, and a part of each of the plurality of socket terminals is exposed in the cavity portion of the socket. The plurality of socket terminals is to be cooled by the cool air passing through the cavity portion of the socket.
A second memory has n banks accessible in parallel, and stores pixel data. An input DMA controller respectively transfers the pixel data stored in the second memory to n multiply-accumulate units by using n input channels. A sequence controller controls the input DMA controller so as to cause a first input channel to transfer the pixel data in a first pixel space of the input bank to a first multiply-accumulate unit and cause a second input channel to transfer the pixel data in a second pixel space of the same input bank to a second multiply-accumulate unit.
G06F 13/28 - Handling requests for interconnection or transfer for access to input/output bus using burst mode transfer, e.g. direct memory access, cycle steal
G06T 1/20 - Processor architectures; Processor configuration, e.g. pipelining
A second memory stores a plurality of input data sets DSi composed of a plurality of pieces of input data. N multiply-accumulate units are capable of performing parallel processings, and each performs a multiply-accumulate operation on any one of the plurality of weight parameter sets and any one of the plurality of input data sets. A second DMA controller transfers the input data set from the second memory to the n multiply-accumulate units. A measurement circuit measures a degree of matching/mismatching of logic levels among the plurality of pieces of input data contained in the input data set within the memory MEM2, the sequence controller controls the number of parallel processings by the n multiply-accumulate units based on a measurement result by the measurement circuit.
G06F 12/0831 - Cache consistency protocols using a bus scheme, e.g. with bus monitoring or watching means
G06F 13/28 - Handling requests for interconnection or transfer for access to input/output bus using burst mode transfer, e.g. direct memory access, cycle steal
A semiconductor chip includes a transformer that performs contactless communication between different potentials. The semiconductor chip includes a semiconductor substrate, a semiconductor region formed in an upper surface of the semiconductor substrate, and the transformer formed over the semiconductor substrate. Here, the transformer includes a lower inductor, a lead wiring portion electrically connected to the lower inductor, and an upper inductor 100 magnetically coupled to the lower inductor, and the lead wiring portion has a wiring facing the semiconductor region.
H01L 23/522 - Arrangements for conducting electric current within the device in operation from one component to another including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
In an embodiment, an apparatus is disclosed that includes a duty cycle controller. The duty cycle controller includes a tuning circuit comprising a first field-effect transistor. The first field-effect transistor is configured to implement a capacitor. The duty cycle controller further includes an edge delay circuit. The edge delay circuit includes a second field-effect transistor that, when activated by an input clock signal of the duty cycle controller, is configured to connect a voltage source to an output clock signal of the duty cycle controller. The edge delay circuit further includes a third field-effect transistor that, when activated, is configured to connect the first field-effect transistor of the tuning circuit to the output clock signal.
H03K 17/687 - Electronic switching or gating, i.e. not by contact-making and -breaking characterised by the use of specified components by the use, as active elements, of semiconductor devices the devices being field-effect transistors
24.
SPURIOUS EMISSIONS DETECTION AND CALIBRATION USING ENVELOPE DETECTOR
Methods and systems for operating a transceiver are described. A transceiver can include an upconverting mixer, a downconverting mixer, a controller, and an envelope detector. The upconverting mixer can mix an input signal with a local oscillator (LO) signal to generate a transmitter signal. The envelope detector can receive the transmitter signal outputted from the upconverting mixer and output an envelope of the transmitter signal to an output line of the downconverting mixer. The envelope can indicate at least one of a leaked LO signal and an image signal. The controller can receive a calibration parameter that is based on at least one of the leaked LO signal and image signal and calibrate the upconverting mixer based on the calibration parameter.
Systems and methods for wireless power transfer systems are described. A controller of a device can communicate with a power device by a first modulation mode. The controller can detect a failure condition between the controller and the power device. The controller can, in response to the detection of the failure condition, communicate with the power device by a second modulation mode. The first modulation mode can include capacitive modulation and the second modulation mode can include resistive modulation.
H02J 50/12 - Circuit arrangements or systems for wireless supply or distribution of electric power using inductive coupling of the resonant type
H02J 50/80 - Circuit arrangements or systems for wireless supply or distribution of electric power involving the exchange of data, concerning supply or distribution of electric power, between transmitting devices and receiving devices
H02M 7/219 - Conversion of ac power input into dc power output without possibility of reversal by static converters using discharge tubes with control electrode or semiconductor devices with control electrode using devices of a triode or transistor type requiring continuous application of a control signal using semiconductor devices only in a bridge configuration
A disconnection detector circuit that can favorably inspect a connection state of a wire without increase in parasitic capacitance is provided. A semiconductor device includes, in one package, a first integrated circuit including a transformer including a primary coil and a secondary coil, and a second integrated circuit connected to a midpoint and one end of the secondary coil. The second integrated circuit includes a reference line and a detector circuit. The reference line connects the midpoint of the secondary coil and a reference potential. On basis of a potential at a predetermined reference point of the first power supply line, the detector circuit detects whether a connection state between the second integrated circuit and the secondary coil is normal or abnormal.
Before a temperature characteristic of a band gap reference circuit is tested, temperature dependencies of a reference voltage and an absolute temperature proportional voltage for a plurality of samples are measured. When the temperature characteristic is tested, based on a difference ΔVref between the reference voltage of the band gap reference circuit at a predetermined temperature and a median value of the reference voltages of the plurality of samples, a difference ΔVptat between the absolute temperature proportional voltage of the band gap reference circuit at a predetermined temperature and a median value of the absolute temperature proportional voltages of the plurality of samples is calculated.
A battery simulator includes a circuit simulator that simulates an operation of an RC parallel circuit which is an equivalent circuit of a battery to be monitored and an RC parallel circuit optimization device that optimizes the RC parallel circuit based on a monitoring frequency of the battery, wherein the RC parallel circuit optimization device is configured to: delete a capacitance value of the RC parallel circuit when the monitoring frequency is determined to be a low frequency, and delete resistance and capacitance values of the RC parallel circuit when the monitoring frequency is determined to be a high frequency.
G01R 31/374 - Arrangements for testing, measuring or monitoring the electrical condition of accumulators or electric batteries, e.g. capacity or state of charge [SoC] with means for correcting the measurement for temperature or ageing
G01R 31/3835 - Arrangements for monitoring battery or accumulator variables, e.g. SoC involving only voltage measurements
H01M 10/42 - Methods or arrangements for servicing or maintenance of secondary cells or secondary half-cells
A semiconductor chip includes a lower wiring layer, a multilayer wiring layer formed on the lower wiring layer, and an upper wiring layer formed on the multilayer wiring layer. Here, a thickness of a wiring provided in the lower wiring layer is larger than a thickness of each of a plurality of wirings provided in the multilayer wiring layer, and a thickness of a wiring provided in the upper wiring layer is larger than the thickness of each of the plurality of wirings provided in the multilayer wiring layer. A lower inductor which is a component of a transformer is provided in the lower wiring layer, and an upper inductor which is a component of the transformer is provided in the upper wiring layer.
H01L 23/522 - Arrangements for conducting electric current within the device in operation from one component to another including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
H01L 23/528 - Layout of the interconnection structure
According to one embodiment, a semiconductor device includes a semiconductor substrate, wherein, when viewed from a front surface side, the semiconductor substrate includes: an IGBT region including a plurality of IGBTs; a diode region disposed to surround the IGBT region; a diode region including a plurality of diodes; and a peripheral region disposed to surround the diode region, wherein the IGBT includes: a drift layer; a barrier layer; a channel layer; an emitter layer; a pair of trench electrodes 60; a trench insulating film; a field stop layer; and a collector layer, and a diode includes a drift layer; a semiconductor layer; a channel layer; a pair of trench electrodes; a trench insulating film; a field stop layer; and a cathode layer.
In an embodiment, an apparatus an apparatus including a memory module is described. The memory module can include a plurality of memory ranks and a register clock driver (RCD) coupled to the plurality of memory ranks. The RCD can include a receiver configured to receive a chip select signal for selecting one or more memory ranks. The RCD can further include a logic circuit coupled to the receiver, and an output driver coupled to the logic circuit. The RCD can further include a loopback circuit configured to sample the chip select signal from one or more of a first sampling point between the receiver and the logic circuit and a second sampling point between the logic circuit and the output driver.
If the program stored in the external storage itself is replaced by a legitimate old version of the program by a malicious third party, the semiconductor device (for example, SoC) cannot recognize that it is an old version of the program, and the program can be easily rolled back. An OTP (One Time Programmable ROM) is installed in the chip to manage the latest software version. Specifically, the software version information is checked to see if it is older than the OTP version information by linking the electronic signature updated each time the software is updated with the control table containing the latest software version information stored in the OTP, and comparing the OTP management table with the software version information at system startup.
G06F 8/71 - Version control ; Configuration management
G06F 21/57 - Certifying or maintaining trusted computer platforms, e.g. secure boots or power-downs, version controls, system software checks, secure updates or assessing vulnerabilities
A semiconductor device includes a trench formed in an n-type semiconductor substrate, a p-type body region, an n-type source region, a field plate electrode formed at a lower portion of the trench, and a gate electrode formed at an upper portion of the trench. A gate potential is to be supplied to the gate electrode, a source potential is to be supplied to the source region and the body region, and a drain potential is to be supplied to the semiconductor substrate. A potential larger than the source potential and smaller than the drain potential is to be supplied to the field plate electrode.
A semiconductor device includes a semiconductor substrate, a first insulating film formed on an upper surface of the semiconductor substrate in an outer peripheral region so as to surround a cell region in plan view, and a resistive element formed on the first insulating film so as to surround the cell region in plan view. A second insulating film having a thickness thinner than that of the first insulating film is formed on the upper surface of the semiconductor substrate in the outer peripheral region. A dummy pattern is formed from a portion over the second insulating film to a portion over the first insulating film so as to cover a step occurring between the second insulating film and the first insulating film.
Techniques are provided for suppressing the accumulation of holes in floating region and improving the switching time of a semiconductor device such as an Insulated Gate Bipolar. The semiconductor device includes a trench gate and a trench emitter formed in a semiconductor substrate, and a floating region of a first conductivity type formed in the semiconductor substrate sandwiched between the trench gate and the trench emitter. The bottom of the floating region is located below the bottom of the trench gate and the trench emitter, and the floating region has a crystal defect region including crystal defects selectively formed at a position near an upper surface of the semiconductor substrate in the floating region.
When the external storage itself is replaced by a legitimate old key by a malicious third party, the security IP cannot recognize that it is the old key and can be easily rolled back, that is, the old key is regarded as the legitimate key and operates. An OTP is provided in the SoC, and the version of the key ring is managed in one control table area. Specifically, predetermined information that is updated in synchronization with the key update is written in the management table area of the OTP, and an authentication value is calculated by associating the predetermined information with a key ring including the update key. The calculated authentication value is added and registered when registering the key ring.
H04L 9/14 - Arrangements for secret or secure communications; Network security protocols using a plurality of keys or algorithms
H04L 9/32 - Arrangements for secret or secure communications; Network security protocols including means for verifying the identity or authority of a user of the system
37.
BATTERY STATUS DETECTION USING FORCED BATTERY MODE
Systems and methods for operating a battery charger are described. A controller of a battery charger can switch an operation mode of a battery charger to a forced battery mode. The controller can detect whether the operation mode successfully switched to the forced battery mode or failed to switch to the forced battery mode. The controller can, in response to the operation mode successfully switched to the forced battery mode, determine the battery charger is connected to a battery. The controller can, in response to the operation mode failed to switch to the forced battery mode, determine an occurrence of a failure condition associated with the battery charger.
Systems and methods for adaptive voltage regulation are described. According to an example, a method for operating a charger may include setting, by a charger controller of the charger, a maximum regulation voltage threshold and a minimum regulation voltage threshold, the minimum regulation voltage threshold being a predetermined percentage of the maximum regulation voltage threshold, the predetermined percentage ranging from between about 90% and about 98%; setting, by the charger controller, a charger regulation voltage to the maximum regulation voltage threshold; determining, by a battery monitor, a state of charge of a battery module; and operating the charger at the maximum regulation voltage threshold until the battery module is maximally charged.
A trench is formed in a semiconductor substrate. An insulating film is formed in the trench and on an upper surface of the semiconductor substrate. An ion implantation is performed to the insulating film. An etching treatment is performed to the insulating film, thereby a thickness of the insulating film is reduced. A conductive film is formed in the trench via the insulating film. In plan view, the trench extends in a Y-direction. The above-described ion implantation is performed from a direction inclined by a predetermined angle from an extending direction of a normal line with respect to the upper surface of the semiconductor substrate.
A control gate electrode is formed on a semiconductor substrate via a first gate dielectric film. A second gate dielectric film including a charge storage layer is formed on an upper surface of the semiconductor substrate and on one side surface of the control gate electrode. A memory gate electrode is formed on the second gate dielectric film. A cap film formed of a dielectric material is formed on an upper surface of the control gate electrode, and a silicide film is formed on an upper surface of the memory gate electrode. An upper surface of the cap film and an upper surface of the silicide film are exposed from a sidewall spacer SW and an interlayer dielectric film.
According to an example, a structure is generally described. The structure may include an inductor core having a plurality of surfaces; and at least one conductor integrated with at least one surface of the plurality of surfaces of the inductor core.
H05K 1/11 - Printed elements for providing electric connections to or between printed circuits
H01F 27/30 - Fastening or clamping coils, windings, or parts thereof together; Fastening or mounting coils or windings on core, casing, or other support
H05K 1/16 - Printed circuits incorporating printed electric components, e.g. printed resistor, capacitor, inductor
A message handler (61, 62) is described. The message handler is configured, in response to receiving a data package (131, 132) which is formatted according to a given communications protocol, such as CAN or Ethernet, and which comprises package-directing data (22; FIG. 4) and payload data (23; FIG. 4), to generate package (14) having a predetermined data format, for example a layer-2 or layer-3 package, which comprises a header (24; FIG. 4) and payload data (25; FIG. 4). The header comprises an address generated in dependence upon the package-directing data and wherein the payload comprises the data package. The package (14) having a predetermined data format may be an IEEE 1722 frame.
A jitter cancellation circuit includes a clock buffer and a current control unit. The clock buffer inputs a clock outputted from a clock propagation element driven by a power supply voltage. Further, the clock buffer decreases with respect to a power supply voltage according to an increase in an operating current, while giving a delay time increased according to a decrease in the operating current to output the clock. The current control unit is configured to increase/decrease the operating current of the clock buffer in an opposite phase of a fluctuation component of the power supply voltage.
H03K 5/133 - Arrangements having a single output and transforming input signals into pulses delivered at desired time intervals using a chain of active-delay devices
H03K 5/135 - Arrangements having a single output and transforming input signals into pulses delivered at desired time intervals by the use of time reference signals, e.g. clock signals
Systems and methods for wireless power transfer systems are described. A controller can be coupled to a power rectifier configured to rectify alternating current power into direct current power. The power rectifier can include a first high side transistor, a second high side transistor, a first low side transistor, and a second low side transistor. The controller can be configured to selectively switch on one or more of the first high side transistor, the second high side transistor, the first low side transistor, and the second low side transistor to operate a wireless power receiver under one of a full bridge rectifier mode and a voltage doubler mode.
H02M 7/25 - Conversion of ac power input into dc power output without possibility of reversal by static converters using discharge tubes with control electrode or semiconductor devices with control electrode using devices of a triode or transistor type requiring continuous application of a control signal using semiconductor devices only arranged for operation in series, e.g. for multiplication of voltage
H02J 50/12 - Circuit arrangements or systems for wireless supply or distribution of electric power using inductive coupling of the resonant type
H02M 1/00 - APPARATUS FOR CONVERSION BETWEEN AC AND AC, BETWEEN AC AND DC, OR BETWEEN DC AND DC, AND FOR USE WITH MAINS OR SIMILAR POWER SUPPLY SYSTEMS; CONVERSION OF DC OR AC INPUT POWER INTO SURGE OUTPUT POWER; CONTROL OR REGULATION THEREOF - Details of apparatus for conversion
H02M 7/219 - Conversion of ac power input into dc power output without possibility of reversal by static converters using discharge tubes with control electrode or semiconductor devices with control electrode using devices of a triode or transistor type requiring continuous application of a control signal using semiconductor devices only in a bridge configuration
Systems and methods for wireless power transfer systems are described. A controller can be coupled to a power rectifier configured to rectify alternating current power into direct current power. The power rectifier can include a first high side transistor, a second high side transistor, a first low side transistor, and a second low side transistor. The controller can be configured to operate the power rectifier in full bridge rectifier mode. The controller can be further configured to detect a misfire event between the wireless power receiver and a wireless power transmitter. The controller can be further configured to, in response to detection of the misfire event, switch an operation mode of the power rectifier from the full bridge rectifier mode to a diode mode.
H02M 7/219 - Conversion of ac power input into dc power output without possibility of reversal by static converters using discharge tubes with control electrode or semiconductor devices with control electrode using devices of a triode or transistor type requiring continuous application of a control signal using semiconductor devices only in a bridge configuration
G01R 19/00 - Arrangements for measuring currents or voltages or for indicating presence or sign thereof
H02M 1/32 - Means for protecting converters other than by automatic disconnection
In a case where a crack occurs in a dicing step, the crack can be suppressed from proceeding toward an element region. A first scribe region and a second scribe region that both define an element region are formed in a main surface of a semiconductor wafer. In the first scribe region, an evaluation-deep-trench group including an evaluation-deep-trench-first portion and an evaluation-deep-trench-second portion is formed. The evaluation-deep-trench-first portion is formed in a first region. The evaluation-deep-trench-second portion has a width in an X-axis direction, and is formed in a bar shape extending in a Y-axis direction, in a second region located between the first region and the element region.
H01L 21/784 - Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, each consisting of a single circuit element the substrate being a semiconductor body
H01L 29/06 - Semiconductor bodies characterised by the shapes, relative sizes, or dispositions of the semiconductor regions
A semiconductor device includes a cell region in which MISFETs are formed, and a peripheral region surrounding the cell region in plan view. In the cell region and the peripheral region, an n-type impurity region is formed in a semiconductor substrate. In the semiconductor substrate, an element isolation portion, a p-type impurity region, and an n-type impurity region are formed in the peripheral region so as to surround the cell region in plan view. A p-type impurity region and an n-type impurity region are formed in the semiconductor substrate in the cell region so as to contact the impurity region. The element isolation portion is located in the impurity region and is spaced apart from a junction interface between the impurity region and the impurity region.
H01L 27/088 - Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only the components being field-effect transistors with insulated gate
A semiconductor device capable of shortening processing time of a neural network is provided. The memory stores a compressed weight parameter. A plurality of multiply accumulators perform a multiply-accumulation operation to a plurality of pixel data and a plurality of weight parameters. A decompressor restores the compressed weight parameter stored in the memory to a plurality of weight parameters. A memory for weight parameter stores the plurality of weight parameters restored by the decompressor. The DMA controller transfers the plurality of weight parameters from the memory to the memory for weight parameter via the decompressor. A sequence controller writes down the plurality of weight parameters stored in the memory for weight parameter to a weight parameter buffer at write timing.
G06F 13/16 - Handling requests for interconnection or transfer for access to memory bus
G06F 13/28 - Handling requests for interconnection or transfer for access to input/output bus using burst mode transfer, e.g. direct memory access, cycle steal
G06F 7/544 - Methods or arrangements for performing computations using exclusively denominational number representation, e.g. using binary, ternary, decimal representation using unspecified devices for evaluating functions by calculation
When a counter circuit that repeatedly counts a loop variable, an accumulator variable, or the like is configured by a programmable device, a processing delay occurs. The processor comprises an array of programmable logic and at least one dedicated counter circuit for counting variables that are repeatedly modified.
An inductive sensor assembly including a printed circuit board (PCB) arrangement including at least one layer-stacked PCB, a sensor chip component element, a coil system comprising one or more sensor coils corresponding to the sensor chip component element, wherein the sensor chip component element and the coil system are arranged on opposite sides of the PCB arrangement.
G01D 5/20 - Mechanical means for transferring the output of a sensing member; Means for converting the output of a sensing member to another variable where the form or nature of the sensing member does not constrain the means for converting; Transducers not specially adapted for a specific variable using electric or magnetic means influencing the magnitude of a current or voltage by varying inductance, e.g. by a movable armature
51.
SEMICONDUCTOR DEVICE WITH IMPROVED BREAKDOWN VOLTAGE
A semiconductor device has an impurity region covering a bottom of a gate trench and a column region. A bottom of the column region is deeper than a bottom of the gate trench. The impurity region is arranged between the gate trench and the column region. This structure can improve the characteristics of the semiconductor device.
H01L 29/10 - Semiconductor bodies characterised by the shapes, relative sizes, or dispositions of the semiconductor regions with semiconductor regions connected to an electrode not carrying current to be rectified, amplified, or switched and such electrode being part of a semiconductor device which comprises three or more electrodes
52.
SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING THE SAME
The source region, drain region, buried insulating film, gate insulating film, and gate electrode of the semiconductor device are formed in a main surface of a semiconductor substrate. The buried insulating film is buried in a first trench formed between the source and drain regions. The first trench has a first side surface and a first bottom surface. The first side surface faces the source region in a first direction extending from one of the source and drain regions to the other. The first bottom surface is connected to the first side surface and is along the main surface of the semiconductor substrate. A crystal plane of a first surface of the semiconductor substrate, which is the first side surface of the first trench, is (111) plane. A crystal plane of a second surface of the semiconductor substrate, which is the bottom surface of the first trench, is (100) plane.
H01L 29/78 - Field-effect transistors with field effect produced by an insulated gate
H01L 29/04 - Semiconductor bodies characterised by their crystalline structure, e.g. polycrystalline, cubic or particular orientation of crystalline planes
A method of designing a semiconductor device. It can comprise interpreting a constraint defining a delay value from a timing constraint by inputting data defining a logic circuit and timing constraint data defining a timing constraint relating to the logic circuit, calculating the delay value that can applied to each path in the logic circuit, and verifying the logic circuit by detecting the delay value as a logic verification violation.
G06F 30/367 - Design verification, e.g. using simulation, simulation program with integrated circuit emphasis [SPICE], direct methods or relaxation methods
54.
SEMICONDUCTOR DEVICE, BATTERY PACK, METHOD OF CONTROLLING SEMICONDUCTOR DEVICE, AND CONTROL PROGRAMS
A semiconductor device, a battery pack, a method of controlling the semiconductor device, and a control program capable of accurately measuring a remaining capacity of a battery is provided. The semiconductor device includes: a current measurement circuit configured to measure a current value of a first current supplied from a battery to the semiconductor device that is a host device and a current value of a second current supplied from the battery to a load; and a computing circuit configured to calculate the remaining capacity of the battery, based on an accumulation value of the first current and an accumulation value of the second current in a period from start of discharging to end of discharging in the battery.
A semiconductor substrate includes an n-type substrate region, an n-type first semiconductor region and a second semiconductor region disposed at different positions on the n-type substrate region, an n-type buried layer formed on the n-type first semiconductor region and on the second semiconductor region, a p-type third semiconductor region and a p-type fourth semiconductor region formed on the n-type buried layer and spaced apart from each other, and an n-type fifth semiconductor region that reaches an upper surface of the semiconductor substrate from the n-type buried layer. The n-type buried layer, the n-type first semiconductor region, and the n-type substrate region are present under the p-type third semiconductor region and the n-type fifth semiconductor region. A first transistor is formed in an upper portion of the p-type third semiconductor region, and a second transistor is formed in an upper portion of the p-type fourth semiconductor region.
H01L 29/78 - Field-effect transistors with field effect produced by an insulated gate
H01L 27/088 - Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only the components being field-effect transistors with insulated gate
H01L 29/06 - Semiconductor bodies characterised by the shapes, relative sizes, or dispositions of the semiconductor regions
56.
CAN COMMUNICATION CONTROLLER AND METHOD OF OPERATING CAN COMMUNICATION CONTROLLER
A CAN communication controller and a method of operating a CAN communication controller are disclosed. The CAN communication controller is for transmitting first and second types of frames wherein the first type of frame is used to transmit event-triggered communication data and the second type of frame is used to transmit best effort traffic data, the CAN communication controller configured, in response to transmitting a frame of the second type having a given identifier, to delay arbitration of a following frame of the second type having the given identifier, and not to delay arbitration of a frame of the first type.
A differential amplifier includes a first differential amplifier circuit as a first stage, a second differential amplifier circuit having a common mode feedback circuit in a second stage, and a feedback differential circuit configured to multiply a differential signal between a differential output of the first differential amplifier circuit and a differential input of the second differential amplifier circuit by a magnitude of a differential output of the common mode feedback circuit.
The semiconductor device includes a control unit having redundant processors, a memory storing target data, a secure memory storing a key used for encryption or decryption processing, an cryptographic unit, a secure processor instructing cryptographic processing to the cryptographic unit in response to a request from the control unit, a first bus coupled to the control unit, the memory, the cryptographic unit, and the secure processor, and a second bus coupled to the secure memory, the cryptographic unit, and the secure processor. The control unit communicates with the memory via a predetermined error detection mechanism, the cryptographic unit includes a plurality of cryptographic processors that independently perform cryptographic processing on target data using a key based on an instruction, and each of the plurality of cryptographic processors includes a data transfer unit that performs data transfer with the memory via the error detection mechanism.
G06F 21/62 - Protecting access to data via a platform, e.g. using keys or access control rules
G06F 21/64 - Protecting data integrity, e.g. using checksums, certificates or signatures
G06F 21/79 - Protecting specific internal or peripheral components, in which the protection of a component leads to protection of the entire computer to assure secure storage of data in semiconductor storage media, e.g. directly-addressable memories
G06F 21/72 - Protecting specific internal or peripheral components, in which the protection of a component leads to protection of the entire computer to assure secure computing or processing of information in cryptographic circuits
59.
SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING THE SAME
A semiconductor device includes an n-type semiconductor substrate, a trench, and a gate electrode formed in the trench via a gate insulating film. An absolute value of a difference between a thickness of the gate insulating film formed on a corner portion of the trench and a thickness of the gate insulating film formed on the bottom portion of the trench is smaller than an absolute value of a difference between the thickness of the gate insulating film formed on the corner portion of the trench and a thickness of the gate insulating film formed on the sidewall portion of the trench.
An electric fuse including a fuse body and a fuse pad has a lamination structure of a polysilicon film and a cobalt silicide film. In the fuse body, a first portion having a first thickness and a second portion having a second thickness are formed. The first thickness is smaller than the second thickness. The polysilicon film is formed such that a thickness of the polysilicon film in the first portion becomes smaller than a thickness of the polysilicon film in the second portion.
H01L 23/525 - Arrangements for conducting electric current within the device in operation from one component to another including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body with adaptable interconnections
H01L 23/532 - Arrangements for conducting electric current within the device in operation from one component to another including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body characterised by the materials
61.
INTER-LAYER TWISTED COIL FOR WIRELESS POWER TRANSFER
Apparatuses including a coil and methods of forming the coil are described. The coil can include a first coil layer including at least an inner strand and an outer strand. The coil can further include a second coil layer including at least an inner strand and an outer strand. The inner strand of the first coil layer can be connected to the outer strand of the second coil layer. The outer strand of the first coil layer can be connected to the inner strand of the second coil layer.
A semiconductor device with improved reliability is provided. The semiconductor device is characterized by its embodiments in that sloped portions are formed on connection parts between a pad and a lead-out wiring portion, respectively. This feature suppresses crack formation in a coating area where a part of the pad is covered with a surface protective film.
H01L 23/00 - SEMICONDUCTOR DEVICES NOT COVERED BY CLASS - Details of semiconductor or other solid state devices
H01L 23/31 - Encapsulation, e.g. encapsulating layers, coatings characterised by the arrangement
H01L 21/48 - Manufacture or treatment of parts, e.g. containers, prior to assembly of the devices, using processes not provided for in a single one of the groups
H01L 21/56 - Encapsulations, e.g. encapsulating layers, coatings
H01L 21/78 - Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
H01L 21/66 - Testing or measuring during manufacture or treatment
This invention provides a placement area with an enlarged bump pitch while avoiding the risk of underfill void generation in the bump process.
This invention provides a placement area with an enlarged bump pitch while avoiding the risk of underfill void generation in the bump process.
The number of bumps is not changed, but the bump pitch at the center is arranged in parallel with the drying direction of the flip-chip process in the drying direction, and an arrangement area in which n rows are enlarged by +b(μm) bump pitch is made, and the chip area is finely adjusted.
This invention provides a placement area with an enlarged bump pitch while avoiding the risk of underfill void generation in the bump process.
The number of bumps is not changed, but the bump pitch at the center is arranged in parallel with the drying direction of the flip-chip process in the drying direction, and an arrangement area in which n rows are enlarged by +b(μm) bump pitch is made, and the chip area is finely adjusted.
According to the invention, with respect to the dry air direction after flux cleaning, the power of the dry air does not change for creating a minute bump enlarged area parallel to the air in the central portion.
A semiconductor device includes a crystal oscillator circuit, a first noise application circuit, and a second noise application circuit. The first noise application circuit is connected to the crystal oscillator circuit and is configured to drive a crystal resonator by selectively applying initial noises of opposite phases to a first external terminal and a second external terminal. The second noise application circuit applies a second noise to the first external terminal by amplifying a signal at the first external terminal and returning the amplified signal to the first external terminal, thereby driving an oscillation amplifier and a crystal resonator of the crystal oscillator circuit and shortening a start-up time of the crystal oscillator circuit.
H03B 5/36 - Generation of oscillations using amplifier with regenerative feedback from output to input with frequency-determining element being electromechanical resonator being a piezoelectric resonator active element in amplifier being semiconductor device
A semiconductor device according to an embodiment includes a level detection unit that validates a level detection signal LD when a value indicated by stream data exceeds a threshold condition value, a ring buffer that cyclically stores internal data generated from the stream data in a storage area that is set within a predetermined address range, a data processing unit that operates with a bus clock and performs data processing using the internal data acquired from the ring buffer, and an address adjustment unit that adjusts a read address indicating a read start position of the ring buffer to a position that becomes a predetermined difference from a write address of the ring buffer at that time in accordance with a start of generation of the bus clock, and generates a bus clock during a period in which the level detection signal LD is valid.
A semiconductor device having a semiconductor substrate, a BOX film on the semiconductor substrate, a semiconductor layer on the BOX film, a first trench penetrated through the semiconductor layer and reached to the first insulating film, a first insulating film covering a side surface of the first trench and in contact with an upper surface of the BOX film at a bottom of the first trench, a second trench formed at the bottom of the first trench such that the second trench penetrates through the first insulating film and reached in the BOX film, a second insulating film filled in the first trench and the second trench. A bottom surface of the second trench is located in the BOX film below an interface between the semiconductor layer and the BOX film, and a void is located in the second insulating film at the same height the interface.
H01L 27/12 - Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being other than a semiconductor body, e.g. an insulating body
67.
METHOD AND SYSTEM USING A BATTERY VOLTAGE LOOP UNDER HIGH-CURRENT CONDITIONS
Systems and methods for using a battery voltage loop under high-current conditions are described. A method for operating a charger, the method includes setting, by a charger controller, a battery voltage threshold; setting, by the charger controller, an on-the-go (OTG) voltage threshold; computing, by a first comparator, a battery voltage error based on a difference between a battery voltage and the battery voltage threshold; computing, by a second comparator, an OTG voltage error based on a difference between an OTG voltage and the OTG voltage threshold; and selecting, by a loop selector, a battery voltage loop when the battery voltage error is smaller than the OTG voltage error.
A visual inspection apparatus includes a stage on which a FCBGA type semiconductor package having a lid is placed, a camera located above the stage, a coaxial illumination device located between the camera and the stage, an oblique illumination device located between the camera and the stage, and a control device. The control device is configured to irradiate the FCBGA type semiconductor package with illumination lights by the coaxial illumination device and the oblique illumination device, capture the FCBGA type semiconductor package by the camera to obtain the captured image, integrate a number of pixels of a predetermined pixel value by a binarization process of the captured image to obtain a determination value, and compare the determination value with a predetermined value to determine a non-defective product or a defective product.
A semiconductor device includes a first metal film forming an uppermost layer wiring that has a bonding pad. A concentration of impurities at a crystal grain boundary of the first metal film is higher than a concentration of impurities in crystal grains in the first metal film. The maximum grain size of crystal grains included in the first metal film is less than 5 μm.
A semiconductor manufacturer generates a manufacturer encryption key and a manufacturer decryption key corresponding to the manufacturer decryption key, installs the manufacturer decryption key in a semiconductor device, and provides a customer with the manufacturer decryption key, the customer generates a customer encryption key and a customer decryption key corresponding to the customer decryption key, decrypts, by the customer decryption key, a customer key to be installed in the semiconductor device, and supplies the encrypted customer key to the semiconductor manufacturer, the semiconductor manufacturer encrypts the supplied customer key by the manufacturer encryption key without decryption, and supplies the encrypted customer key to the customer, the customer decrypts the customer key by the customer decryption key, and installs the decrypted customer key in the semiconductor device, and in the semiconductor device, the installed customer key is decrypted by the manufacturer decryption key installed by the semiconductor manufacturer.
A cryptographic key installation method of installing a customer key in a semiconductor device, wherein the semiconductor device includes a decryption functional unit that has a secret key installed therein in advance, and when the customer key encrypted by a public key corresponding to the secret key is installed, decrypts the encrypted customer key by the secret key installed in advance to generate a customer key, wherein an encryption device on a user side that uses the semiconductor device encrypts the customer key by the public key, and generates the encrypted customer key, and wherein a key installation device on the user side installs the encrypted customer key in the semiconductor device.
G06F 21/72 - Protecting specific internal or peripheral components, in which the protection of a component leads to protection of the entire computer to assure secure computing or processing of information in cryptographic circuits
72.
SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING THE SAME
A semiconductor device includes a chip mounting portion and a semiconductor chip provided on the chip mounting portion via a conductive adhesive material. Here, a planar shape of the semiconductor chip is a quadrangular shape. Also, in plan view, a plurality of thin portions is formed at a plurality of corner portions of the semiconductor chip, respectively. Also, the plurality of thin portions respectively formed at the plurality of corner portions of the semiconductor chip is spaced apart from each other. Further, thickness of each of the plurality of thin portions is smaller than a thickness of the semiconductor chip other than the plurality of the thin portions.
H01L 23/00 - SEMICONDUCTOR DEVICES NOT COVERED BY CLASS - Details of semiconductor or other solid state devices
H01L 23/58 - Structural electrical arrangements for semiconductor devices not otherwise provided for
H01L 29/78 - Field-effect transistors with field effect produced by an insulated gate
H01L 21/78 - Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
H01L 21/306 - Chemical or electrical treatment, e.g. electrolytic etching
73.
METHOD OF MANUFACTURING SEMICONDUCTOR DEVICE AND SEMICONDUCTOR DEVICE
A source pad electrically coupled with a source of a MOSFET of a semiconductor chip and located at a position below a lead in cross-sectional view is electrically connected with the lead for source via a conductive member bonded to the source pad and a wire bonded to the conductive member.
The semiconductor device has the main surface, the semiconductor substrate having the first impurity region formed on the main surface, the first electrode formed on the main surface having the first impurity region, the insulating film formed on the main surface such that surround the first electrode, the second electrode formed on the insulating film such that spaced apart from the first electrode and annularly surround the first electrode, and the semi-insulating film. The first electrode has the outer peripheral edge portion. The semi-insulating film is continuously formed from on the outer peripheral edge portion to on the second electrode. The outer peripheral edge portion includes the first corner portion. The second electrode has the second corner portion facing the first corner portion. The semi-insulating film on the insulating film is removed between the first corner and the second corner portion.
H01L 29/08 - Semiconductor bodies characterised by the shapes, relative sizes, or dispositions of the semiconductor regions with semiconductor regions connected to an electrode carrying current to be rectified, amplified, or switched and such electrode being part of a semiconductor device which comprises three or more electrodes
H01L 29/739 - Transistor-type devices, i.e. able to continuously respond to applied control signals controlled by field effect
In an embodiment, a semiconductor device is disclosed. The semiconductor device includes a plurality of output pins. Each of the output pins is electrically connected to an input pin of a buzzer and to a buzzer driver. The buzzer driver is configured to cause the buzzer to emit an audible sound. The semiconductor device further includes a plurality of ground switches. Each ground switch is configured to connect a corresponding output pin of the plurality of output pins to ground when closed. The semiconductor device further includes a current generator that is configured to supply a test current to a given output pin of the plurality of output pins and a clamp switch that is configured to connect the given output pin to an analog-to-digital converter.
G08B 29/00 - Checking or monitoring of signalling or alarm systems; Prevention or correction of operating errors, e.g. preventing unauthorised operation
An improved power MOSFET of a split gate structure including a gate electrode and a field plate electrode in a trench is disclosed. The improved power MOSFET includes a field plate electrode FP formed at a lower portion of a trench TR and a gate electrode GE formed an upper portion of the trench TR. The field plate electrode FP further includes a contact portion FPa which is formed at the upper portion of the trench TR to provide a source potential. The gate electrode GE further includes a connecting portion GEa at the both sides of the contact portion FPa in the trench TR. The connecting portion GEa electrically connects between one portion of the gate electrode GE at a region 2A side and the other portion of the gate electrode GE at a region 2A′ side.
A semiconductor device includes a trench emitter electrode located at a boundary between one end of an active cell region and an inactive cell region, a trench gate electrode located at a boundary between the other end of the active cell region and the inactive cell region, an end trench gate electrode connected to one end of the trench gate electrode, and an end trench emitter electrode connected to one end of the trench emitter electrode. A hole barrier region of a first conductivity type is provided under a body region of a second conductivity type between the end trench gate electrode and the end trench emitter electrode in a plan view. A body region in the active cell region and a body region in the inactive cell region are connected to each other by a body region between the end trench gate electrode and the end trench emitter electrode.
H01L 29/739 - Transistor-type devices, i.e. able to continuously respond to applied control signals controlled by field effect
H01L 29/06 - Semiconductor bodies characterised by the shapes, relative sizes, or dispositions of the semiconductor regions
H01L 29/10 - Semiconductor bodies characterised by the shapes, relative sizes, or dispositions of the semiconductor regions with semiconductor regions connected to an electrode not carrying current to be rectified, amplified, or switched and such electrode being part of a semiconductor device which comprises three or more electrodes
H01L 29/417 - Electrodes characterised by their shape, relative sizes or dispositions carrying the current to be rectified, amplified or switched
Methods and system for one-line synchronous interface are described. A timing device including a first buffer can be connected to a line card including a second buffer. The timing device can control the first buffer to output a synchronization pulse to the line card periodically at a time interval. For each output of the synchronization pulse, the timing device can switch the first buffer from a first output mode to a first input mode. Under the first input mode, the timing device listen for incoming data on the trace. The line card can receive the synchronization pulse periodically at the time interval. For each receipt of the synchronization pulse, the line card can switch the second buffer from a second input mode to a second output mode. Under the second output mode, the line card can transmit outgoing data on the trace.
H04L 7/06 - Speed or phase control by synchronisation signals the synchronisation signals differing from the information signals in amplitude, polarity, or frequency
79.
SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING THE SAME
A dielectric layer has a first opening exposing a surface of a first conductive layer and a second opening exposing a surface of a second conductive layer and having an opening area smaller than an opening area of the first opening. A material of the surface of the second conductive layer exposed from the second opening is different from a material of the surface of the first conductive layer exposed from the first opening, and includes aluminum.
An improved structure and a manufacturing method of a vertical type power MOSFET having a super junction configuration is disclosed. The improved structure and the manufacturing method of the vertical type power MOSFET comprising: a step of preparing a semiconductor substrate SB including an n-type semiconductor layer SL and a p-type epitaxial layer EP on the semiconductor layer SL; a step of forming a trench GT in the p-type epitaxial layer EP by using an etching mask with a predetermined opening width; and a step of introducing an n-type impurity into a bottom portion of the trench GT using the etching mask with the predetermined opening width, whereby forming an n-type column NC at the bottom of trench GT and reaching the semiconductor layer SL.
A method of manufacturing a semiconductor device includes: a grind step of forming a small thickness portion and a large thickness portion surrounding the small thickness portion in plan view by grinding a back surface of a semiconductor wafer; a preparation step of preparing a wafer holding member including a wafer placement surface and a back surface opposite to the wafer placement surface and having a larger thickness than a difference between a thickness of the large thickness portion and a thickness of the small thickness portion; and a placement step of placing the semiconductor wafer on the wafer holding member so that the small thickness portion of the semiconductor wafer and the wafer placement surface of the wafer holding member are in contact with each other on the back surface side of the semiconductor wafer.
H01L 21/683 - Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components for supporting or gripping
H01L 21/66 - Testing or measuring during manufacture or treatment
H01L 21/304 - Mechanical treatment, e.g. grinding, polishing, cutting
82.
SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING THE SAME
Wirings next to each other spaced apart by a first distance are formed in the uppermost layer of a multilayer wiring layer formed on a semiconductor substrate. A protective film covers upper surfaces and side surfaces of the wirings. The protective films formed on the side surfaces of the wirings are spaced apart from each other. The protective film is formed of an inorganic dielectric film. A thickness of the protective film formed on the upper surfaces of the wirings is larger than a thickness of the protective film formed on the side surfaces of the wirings.
A solid-state image sensor includes a buffer circuit, and an AD conversion circuit. The buffer circuit is connected to a first pixel and a second pixel of a plurality of pixels. The AD conversion circuit converts a voltage signal from the buffer circuit into a digital signal. The buffer circuit includes a voltage holding circuit connected to the first pixel, a voltage holding circuit connected to the second pixel, and a switch circuit. The switch circuit selectively switches the voltage holding circuit which outputs a voltage signal to the AD conversion circuit between the voltage holding circuits. The buffer circuit carries out an operation of holding a voltage signal of the first pixel in the voltage holding circuit and an operation of holding a voltage signal of the second pixel in the voltage holding circuit in parallel with each other.
An inductive position sensor for detecting a linear or angular movement of a conductive target, including: a transmitter coil; a first receiver coil and a second receiver coil, wherein the first receiver coil and the second receiver coil have a linear or angular shape and define the detection range of the inductive linear or arc position sensor; a first conductive target and a second conductive target; the first conductive target and the second conductive target each have a linear or angular shape extension of half the detection range of the inductive position sensor and are spaced from each other by half the detection range of the inductive position sensor.
G01D 5/20 - Mechanical means for transferring the output of a sensing member; Means for converting the output of a sensing member to another variable where the form or nature of the sensing member does not constrain the means for converting; Transducers not specially adapted for a specific variable using electric or magnetic means influencing the magnitude of a current or voltage by varying inductance, e.g. by a movable armature
85.
SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING THE SAME
A semiconductor device includes an n-type semiconductor substrate, a trench, a gate electrode formed in the trench via the gate insulating film, a p-type base region formed in the semiconductor substrate, and an n-type emitter region formed in the base region. The trench extends in a Y direction, in a plan view. Adjacent ones of a plurality of emitter regions are formed to be spaced apart from each other by a distance, along the Y direction. The distance is wider than ⅕ of a width of each of the emitter regions in the Y direction and narrower than the width.
In a memory region, a memory-region first portion in which no raised epitaxial layer is formed, a memory-region second portion in which a first raised epitaxial layer is formed, and a memory-region third portion in which a second raised epitaxial layer is formed are defined. In the memory-region first portion, a first-diffusion-layer first portion of a memory transistor and a second-diffusion-layer first portion of a select transistor are formed. A first-diffusion-layer second portion of the memory transistor is formed in the first raised epitaxial layer. A second-diffusion-layer second portion of the select transistor is formed in the second raised epitaxial layer.
A metal film, a manufacturing method of the metal film, semiconductor device, and a manufacturing method of semiconductor device are provided with high crack resistance (higher hardness) during wire bonding. The Metal film has first metal crystal grains, and the second metal crystal grains. Each of the first metal crystal grains has dislocations. Each of the second metal crystal grains has no dislocations. The number of the first metal crystal grains having the dislocations is larger than the number of the second metal crystal grains having no dislocations.
A first P-type transistor and a second P-type transistor are connected in series between a power supply terminal and an output terminal. A first N-type transistor and a second N-type transistor are connected between a ground terminal and a power supply terminal. The second N-type transistor and the second P-type transistor are complementarily turned on and off in accordance with an input signal. A gate voltage control circuit changes at least one of the gate voltage of the P-type transistor whose drain is electrically connected to the output terminal and the gate voltage of the N-type transistor by following the output voltage VOUT of the output terminal while keeping the P-type transistor or the N-type transistor on-states.
H03K 17/56 - Electronic switching or gating, i.e. not by contact-making and -breaking characterised by the use of specified components by the use, as active elements, of semiconductor devices
89.
SEMICONDUCTOR DEVICE INCLUDING A CIRCUIT FOR TRANSMITTING A SIGNAL
Reliability of a semiconductor device is improved. The semiconductor device includes a wiring substrate, a semiconductor chip and a capacitor mounted on the upper surface of the wiring substrate, and a lid formed of a metallic plate covering the semiconductor chip and the wire in substrate. The semiconductor chip is bonded to the lid via a conductive adhesive layer, and the capacitor, which is thicker than the thickness of the semiconductor chip, is disposed in the cut off portion provided in the lid, and is exposed from the lid.
H01L 25/16 - Assemblies consisting of a plurality of individual semiconductor or other solid state devices the devices being of types provided for in two or more different main groups of groups , or in a single subclass of , , e.g. forming hybrid circuits
H01L 23/367 - Cooling facilitated by shape of device
H01L 23/00 - SEMICONDUCTOR DEVICES NOT COVERED BY CLASS - Details of semiconductor or other solid state devices
An output driver is disclosed that can include a delay generator configured to produce a plurality of delay signals in response to an input signal; a pre-driver configured to produce a plurality of control signals based on the plurality of shifted delay signals; and a main driver configured to couple to a channel with an asymmetric termination and provide an output signal at a node of the main driver based in response to the plurality of control signals, wherein the plurality of control signals provides for an asymmetric response in the main driver in response to the asymmetric termination. In some embodiments, an asymmetric switching sequence can be included. In some embodiments, a pull-up diode can be engaged. In some embodiments, the output driver is arranged to operate with core voltages and core transistors.
A semiconductor device capable of increasing readout margin in a nonvolatile resistive random access memory is provided. A clamping circuit applies fixed potential to each of a memory element and a reference resistive element. A pre-charge circuit pre-charges first and second nodes to power-source potential. A sense amplifier amplifies the potential difference between the potential of the first node and the potential of the second node generated after a discharge period based on cell current and reference current after pre-charging made by the pre-charge circuit. A third node is coupled to the first and second nodes through a capacitor. An electric-charge supply circuit is connected to the third node, and supplies electric charge to the third node in the discharge period.
G11C 11/16 - Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using magnetic elements using elements in which the storage effect is based on magnetic spin effect
G11C 5/08 - Arrangements for interconnecting storage elements electrically, e.g. by wiring for interconnecting magnetic elements, e.g. toroidal cores
A semiconductor device includes a first regulator electrically connected to a first power supply line, a second regulator electrically connected to a second power supply line, a control circuit configured to control the first and second regulators, and at least two functional circuit modules electrically connectable to the first power supply line and the second power supply line. When all the functional circuit modules are set to a power-on state (active mode), the control circuit controls the first regulator to output a voltage to the first power supply line and the second regulator to output a voltage to the second power supply line, and when some functional circuit modules are set to a power-off state (standby mode), the control circuit controls the first regulator to output a voltage to the first power supply line and the second regulator not to output a voltage to the second power supply line.
H03K 19/00 - Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits
H01L 27/02 - Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including integrated passive circuit elements with at least one potential-jump barrier or surface barrier
H01L 27/092 - Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only the components being field-effect transistors with insulated gate complementary MIS field-effect transistors
93.
SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING THE SAME
A semiconductor device includes a wiring layer, a dielectric layer covering the wiring layer, a thin film resistor provided on the dielectric layer, and a plug electrode connecting the thin film resistor to the wiring layer. The plug electrode includes a barrier layer and a buried layer. The buried layer is configured by the filling portion filling a region surrounded by a first incline surface, and an extension portion extending from the filling portion along a second incline surface. The thin film resistor is in contact with the filling portion and the extension portion of the plug electrode. A second incline angle between the second incline surface and a main surface of a semiconductor substrate is smaller than a first incline angle between the first incline surface and the main surface of the semiconductor substrate.
H01L 29/00 - SEMICONDUCTOR DEVICES NOT COVERED BY CLASS - Details of semiconductor bodies or of electrodes thereof
H01C 7/00 - Non-adjustable resistors formed as one or more layers or coatings; Non-adjustable resistors made from powdered conducting material or powdered semi-conducting material with or without insulating material
H01L 21/768 - Applying interconnections to be used for carrying current between separate components within a device
H01L 23/522 - Arrangements for conducting electric current within the device in operation from one component to another including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
H01C 17/12 - Apparatus or processes specially adapted for manufacturing resistors adapted for coating resistive material on a base by thin-film techniques by sputtering
A semiconductor device includes: a first chip mounting portion; a second chip mounting portion; a first semiconductor chip mounted on the first chip mounting portion; second and third semiconductor chips mounted on the second chip mounting portion; and a sealing body for sealing them. Here, the third semiconductor chip includes a first coil and a second coil that are magnetically coupled to each other. Also, the first coil is electrically connected with a first circuit formed in the first semiconductor chip, and the second coil is electrically connected with a second circuit formed in the second semiconductor chip. Also, in cross-sectional view, the second coil is located closer to the second chip mounting portion than the first coil. Further, a power consumption during an operation of the second semiconductor chip is greater than a power consumption during an operation of the first semiconductor chip.
H01L 25/18 - Assemblies consisting of a plurality of individual semiconductor or other solid state devices the devices being of types provided for in two or more different subgroups of the same main group of groups , or in a single subclass of ,
H01L 25/00 - Assemblies consisting of a plurality of individual semiconductor or other solid state devices
H01L 23/00 - SEMICONDUCTOR DEVICES NOT COVERED BY CLASS - Details of semiconductor or other solid state devices
A clamp element 46 applies a fixed potential to a bit line BL at a time of a readout operation. A reference current source RCS generates a reference current Iref. An offset current source OCS1 is activated at a time of a readout operation for an OTP cell OTPC, and at a time of being activated, generates an offset current Iof1 to be subtracted from a cell current Icel. At the time of the readout operation for the OTP cell OTPC, the sense amplifier SA detects a magnitude relationship between the reference current Iref and a readout current Ird obtained by subtracting the offset current Iof1 from the cell current Icel.
G11C 11/16 - Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using magnetic elements using elements in which the storage effect is based on magnetic spin effect
In an embodiment, an apparatus is disclosed that includes a memory slot including a certificate chain corresponding to an entity and a memory block. The memory block has protection enabled. The apparatus includes a processing device. The processing device is configured to receive a request message to clear protection for the memory block from a computing device of the entity. The request message includes a signature generated based at least in part on a private key of the entity. The processing device is configured to determine a public key corresponding to the entity based at least in part on the certificate chain, determine that the signature is valid based at least in part on the public key, determine that the protection for the memory block corresponds to the certificate chain and clear the protection for the memory block.
A semiconductor device includes a wired input/output (204), a wireless input/output (206), and a battery (202). A wired charging path between the wired input/output (204) and the battery (202) includes a first transistor and a second transistor. A wireless charging path between the wireless input/output (206) and the battery (202) includes a third transistor and the second transistor.
According to one embodiment, an A/D converter includes a successive approximation algorithm setting register that stores a plurality of successive approximation algorithms, an algorithm selection unit that selects a predetermined successive approximation algorithm from the plurality of successive approximation algorithms, a control circuit that generates a comparison value based on the selected predetermined successive approximation algorithm, a DAC that generates a comparison voltage from the comparison value, and a comparator that compares an analog input voltage with the comparison voltage. The control circuit generates a comparison value from a result of the comparison made by the comparator based on the selected predetermined successive approximation algorithm, and converts an analog input voltage into a digital signal from the result of the comparison made by the comparator the number of times equal to the number of bits of the digital signal.
H03M 1/46 - Analogue value compared with reference values sequentially only, e.g. successive approximation type with digital/analogue converter for supplying reference values to converter
In an embodiment, a semiconductor device is disclosed that includes at least one processing device and firmware including a dynamic demodulation engine. The dynamic demodulation engine, when executed by the at least one processing device, is configured to obtain a digital signal waveform, dynamically select a bit detection method based at least in part on a characteristic of the digital signal waveform, perform demodulation of the digital signal waveform using the selected bit detection method and generate decoded packets based at least in part on the demodulation.
H02J 50/10 - Circuit arrangements or systems for wireless supply or distribution of electric power using inductive coupling
H02J 50/80 - Circuit arrangements or systems for wireless supply or distribution of electric power involving the exchange of data, concerning supply or distribution of electric power, between transmitting devices and receiving devices
100.
SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING THE SAME
A semiconductor device includes a lead, a semiconductor substrate, a back-surface electrode provided between the semiconductor substrate and the lead, and a solder layer configured to connect the back-surface electrode and the lead. The back-surface electrode includes a silicide layer formed on a back surface of the semiconductor substrate, a bonding layer formed on the lead, a barrier layer formed on the bonding layer, and a stress relaxation layer formed between the silicide layer and the barrier layer. The stress relaxation layer is made of a first metal film containing aluminum as a main component or a second metal film containing gold, silver, or copper as a main component.
H01L 23/485 - Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads or terminal arrangements consisting of lead-in layers inseparably applied to the semiconductor body consisting of layered constructions comprising conductive layers and insulating layers, e.g. planar contacts
