G06F 5/01 - Methods or arrangements for data conversion without changing the order or content of the data handled for shifting, e.g. justifying, scaling, normalising
G06F 7/537 - Reduction of the number of iteration steps or stages, e.g. using the Sweeny-Robertson-Tocher [SRT] algorithm
2.
N-GRAM BASED CLASSIFICATION WITH ASSOCIATIVE PROCESSING UNIT
A system for N-gram classification in a field of interest via hyperdimensional computing includes an associative memory array and a controller. The associative memory array stores hyperdimensional vectors in rows of the array. The hyperdimensional vectors represent symbols in the field of interest and the array includes bit-line processors along portions of bit-lines of the array. The controller activates rows of the array to perform XNOR, permute, and add operations on the hyperdimensional vectors with the bit-line processors, to encode N-grams, having N symbols therein, to generate fingerprints of a portion of the field of interest from the N-grams, to store the fingerprints within the associative memory array, and to match an input sequence to one of the stored fingerprints.
A system to generate true random numbers includes a RAM array, a null-read controller and a hash generator. The RAM array has memory cells and a sense amplifier. The memory cells store data therein, the cells are connected in rows to word lines and in columns to pairs of bit lines, and the sense amplifier senses a differential input signal. The null-read controller implements a null-read operation by the sense amplifier of a portion of the RAM array. The hash generator receives a null-read result from the null-read operation and outputs a partial true random number based on the null read result.
G11C 11/40 - Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors
G11C 11/406 - Management or control of the refreshing or charge-regeneration cycles
G11C 11/407 - Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing or timing for memory cells of the field-effect type
G11C 11/4072 - Circuits for initialization, powering up or down, clearing memory or presetting
4.
SYSTEM AND METHOD FOR PARALLEL COMBINATORIAL DESIGN
A system for parallel combinatorial design includes a processor, an in-memory vector processor and a storage unit. The processor includes a seed generator, a Cspan generator and a rule checker. The seed generator generates at least one seed to generate combinations of length N, defining a space of N choices of which M choices are to be selected. The Cspan generator generates at least one combination from the at least one seed and stores each combination in a separate column of the in-memory vector processor. The rule checker performs a parallel search at least in the in-memory vector processor for combinations which satisfy a rule and the storage unit receives search results of the rule checker from the in-memory vector processor.
H04L 9/00 - Arrangements for secret or secure communications; Network security protocols
G06F 7/58 - Random or pseudo-random number generators
H02H 3/05 - Emergency protective circuit arrangements for automatic disconnection directly responsive to an undesired change from normal electric working condition, with or without subsequent reconnection - Details with means for increasing reliability, e.g. redundancy arrangements
5.
FUNCTIONAL PROTEIN CLASSIFICATION FOR PANDEMIC RESEARCH
A protein searcher includes a pre-trained CNN, a feature extractor, a database and a KNN searcher. The pre-trained CNN, trained on a previously classified amino acid database, receives an unidentified amino acid sequence. The feature extractor extracts a feature vector of the unidentified amino acid sequence as a query feature vector. The database stores feature vectors of trained amino acid sequences and of at least one untrained amino acid sequence and stores associated classes of the trained amino acid sequences and associated tags of the at least one untrained amino acid sequence. The KNN searcher finds K feature vectors of the database which are close to the query feature vector and outputs the associated class or tag of each of the K feature vectors.
A system for training a neural-network-based floating-point-to-binary feature vector encoder preserves the locality relationships between samples in an input space over to an output space. The system includes a neural network under training and a probability distribution loss function generator. The neural network has floating-point inputs and floating-point pseudo-bipolar outputs. The generator compares an input probability distribution constructed from floating-point cosine similarities of an input space and an output probability distribution constructed from floating-point pseudo-bipolar pseudo-Hamming similarities of an output space. The system includes a proxy vector set generator to take a random sampling of vectors from training data for a proxy set, a sample vector selector to select sample vectors from the training data and a KNN vector set generator to find a set of k nearest neighbors closest to each sample vector from said proxy set for a reference set.
A method for multiplying a first sparse matrix by a second sparse matrix in an associative memory device includes storing multiplicand information related to each non-zero element of the second sparse matrix in a computation column of the associative memory device; the multiplicand information includes at least a multiplicand value. According to a first linear algebra rule, the method associates multiplier information related to a non-zero element of the first sparse matrix with each of its associated multiplicands, the multiplier information includes at least a multiplier value. The method concurrently stores the multiplier information in the computation columns of each associated multiplicand. The method, concurrently on all computation columns, multiplies a multiplier value by its associated multiplicand value to provide a product in the computation column, and adds together products from computation columns, associated according to a second linear algebra rule, to provide a resultant matrix.
A memory cell that may be used for computation and processing array using the memory cell are capable to performing a logic operation including a boolean AND, a boolean OR, a boolean NAND or a boolean NOR. The memory cell may have a read port that has isolation circuits that isolate the data stored in the storage cell of the memory cell from the read bit line.
G11C 8/08 - Word line control circuits, e.g. drivers, boosters, pull-up circuits, pull-down circuits, precharging circuits, for word lines
G11C 8/16 - Multiple access memory array, e.g. addressing one storage element via at least two independent addressing line groups
G11C 8/18 - Address timing or clocking circuits; Address control signal generation or management, e.g. for row address strobe [RAS] or column address strobe [CAS] signals
G11C 11/404 - Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming cells needing refreshing or charge regeneration, i.e. dynamic cells with charge regeneration common to a multiplicity of memory cells, i.e. external refresh with one charge-transfer gate, e.g. MOS transistor, per cell
9.
COMPUTATIONAL MEMORY CELL AND PROCESSING ARRAY DEVICE USING THE MEMORY CELLS FOR XOR AND XNOR COMPUTATIONS
A memory cell and processing array that has a plurality of memory are capable of performing logic functions, including an exclusive OR (XOR) or an exclusive NOR (XNOR) logic function. The memory cell may have a read port in which the digital data stored in the storage cell of the memory cell is isolated from the read bit line.
G11C 8/08 - Word line control circuits, e.g. drivers, boosters, pull-up circuits, pull-down circuits, precharging circuits, for word lines
G11C 8/16 - Multiple access memory array, e.g. addressing one storage element via at least two independent addressing line groups
G11C 8/18 - Address timing or clocking circuits; Address control signal generation or management, e.g. for row address strobe [RAS] or column address strobe [CAS] signals
G11C 11/404 - Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming cells needing refreshing or charge regeneration, i.e. dynamic cells with charge regeneration common to a multiplicity of memory cells, i.e. external refresh with one charge-transfer gate, e.g. MOS transistor, per cell
10.
FINDING K EXTREME VALUES IN CONSTANT PROCESSING TIME
A method includes determining a set of k extreme values of a dataset of elements in a constant time irrespective of the size of the dataset. A method creates a set of k indicators, each indicator associated with one multi-bit binary number in a large dataset of multi-bit binary numbers. The method includes arranging the multi-bit binary numbers such that each bit n of each said multi-bit binary number is located in a different row n of an associative memory array, starting from a row storing a most significant bit (MSB), adding an indicator to the set for each multi-bit binary number having a bit with an extreme value in the row and continuing the adding until said set contains k indicators.
A method for an associative memory array includes storing each column of a matrix in an associated column of the associative memory array, where each bit in row j of the matrix is stored in row R-matrix-row-j of the array, storing a vector in each associated column, where a bit j from the vector is stored in an R-vector-bit-j row of the array. The method includes simultaneously activating a vector-matrix pair of rows R- vector-bit-j and R-matrix-row-j to concurrently receive a result of a Boolean function on all associated columns, using the results to calculate a product between the vector- matrix pair of rows, and writing the product to an R-product-j row in the array.
G11C 15/04 - Digital stores in which information comprising one or more characteristic parts is written into the store and in which information is read-out by searching for one or more of these characteristic parts, i.e. associative or content-addressed stores using semiconductor elements
G06F 9/30 - Arrangements for executing machine instructions, e.g. instruction decode
G11C 7/00 - Arrangements for writing information into, or reading information out from, a digital store
G11C 7/10 - Input/output [I/O] data interface arrangements, e.g. I/O data control circuits, I/O data buffers
G11C 7/18 - Bit line organisation; Bit line lay-out
G11C 15/00 - Digital stores in which information comprising one or more characteristic parts is written into the store and in which information is read-out by searching for one or more of these characteristic parts, i.e. associative or content-addressed stores
A multi-memory cell operator includes a non-destructive memory array, an activation unit and a multiple column decoder. The non-destructive memory array has first and second bit lines per column. The activation unit activates at least two cells in a column of the memory array at the same time thereby to generate multiple Boolean function outputs of the data and of complementary data of the at least two cells on the first bit line and different multiple Boolean function outputs of the data and of the complementary data on the second bit line. The multiple column decoder at least activates the first and second bit lines of multiple selected columns for reading or writing. The multiple column decoder also includes a write unit to write the output of the first bit line, the second bit line or both bit lines of the selected columns into the memory array.
G11C 7/00 - Arrangements for writing information into, or reading information out from, a digital store
G11C 8/16 - Multiple access memory array, e.g. addressing one storage element via at least two independent addressing line groups
G11C 11/412 - Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming cells with positive feedback, i.e. cells not needing refreshing or charge regeneration, e.g. bistable multivibrator or Schmitt trigger using field-effect transistors only
Multi-bank, dual-pipe SRAM systems, methods, processes of operating such SRAMs, and/or methods of fabricating multi-bank, dual-pipe SRAM are disclosed. For example, one illustrative multi-bank, dual-pipe SRAM may comprise features for capturing read and write addresses, splitting and/or combining them via one or more splitting/combining processes, and/or bussing them to the SRAM memory banks, where they may be read and written to a particular bank. Illustrative multi-bank, dual-pipe SRAMs and methods herein may also comprise features for capturing two beats of write data, splitting and/or combining them via one or more splitting/combining processes, and bussing them to each SRAM bank, where they may be split/combined/recombined via one or more processes to write data to particular memory bank(s).
Multi-bank SRAM devices, systems, methods of operating multi-bank SRAMs, and/or methods of fabricating multi-bank SRAM systems are disclosed. For example, illustrative multi-bank SRAMs and methods may include or involve features for capturing read and write addresses at a particular frequency, splitting and/or combining them via one or more splitting/combining processes, and bussing them to each SRAM bank, where they may be split and/or combined via one or more splitting/combining processes to read and write to a particular bank. Some implementations herein may also involve features for capturing two beats of write data at a particular frequency, splitting and/or combining them via one or more splitting/combining processes, and bussing them to each SRAM bank, where they may be split and/or combined via one or more splitting/combining processes for writing to a particular bank. Reading and writing to banks may occur at less than or equal to half the frequency of capture.
Systems, methods and fabrication processes relating to dynamic random access memory (DRAM) devices involving data signals grouped into 10 bits are disclosed. According to one illustrative implementation a DRAM device may comprise a memory core, circuitry that receives a data bus inversion (DBI) bit associated with a data signal as input directly, without transmission through DBI logic associated with an input buffer, circuitry that stores the DBI bit into the memory core, reads the DBI bit from the memory core, and provides the DBI bit as output. In further implementations, DRAM devices herein may store and process the DBI bit on an internal data bus as a regular data bit.
G11C 7/12 - Bit line control circuits, e.g. drivers, boosters, pull-up circuits, pull-down circuits, precharging circuits, equalising circuits, for bit lines
16.
DATA BUS INVERSION MEMORY CIRCUITRY, CONFIGURATION AND OPERATION
Systems, methods and fabrication processes relating to memory devices involving data bus inversion are disclosed. According to one illustrative implementation, a memory device may comprise a memory core, circuitry that receives a data bus inversion (DBI) bit associated with a data signal as input directly, without transmission through DBI logic associated with an input buffer, and circuitry that stores the DBI bit into the memory core, reads the DBI bit from the memory core, and provides the DBI bit as output. In further implementations, memory devices herein may store and process the DBI bit on an internal data bus as a regular data bit.
F02B 51/04 - Other methods of operating engines involving pre-treating of, or adding substances to, combustion air, fuel, or fuel-air mixture of the engines involving electricity or magnetism
F02M 21/02 - Apparatus for supplying engines with non-liquid fuels, e.g. gaseous fuels stored in liquid form for gaseous fuels
C25B 9/00 - Cells or assemblies of cells; Constructional parts of cells; Assemblies of constructional parts, e.g. electrode-diaphragm assemblies; Process-related cell features
A sectioned bit line of an SRAM memory device, an SRAM memory device having a sectioned bit line, and associated systems and methods are described, including embodiments having sectioned bit lines with hierarchical aspects. In one illustrative implementation, each sectioned bit line may comprise a local bit line, a memory cell connected to the local bit line, and a pass gate coupled to the local bit line, wherein the pass gate is configured to be coupled to a global bit line. Further, in some embodiments, the sectioned bit lines are arranged in hierarchical arrays. In other implementations, SRAM memory devices may be configured involving sectioned bit lines (including hierarchical) and a global bit line wherein the pass gates are configured to connect and isolate the sectioned bit line and the global bit line.
Systems and methods are disclosed for increasing the performance of static random access memory (SRAM). Various systems herein, for example, may include or involve dual- or multi-pipe, multi-bank SRAMs, such as Quad-B2 SRAMs. In one illustrative implementation, there is provided an SRAM memory device including a memory array comprising a plurality of SRAM banks and pairs of separate and distinct pipes associated with each of the SRAM banks, wherein each pair of pipes may provide independent access to its associated SRAM bank.
patents
