Techniques for efficient execution of queries. A query plan generated for the query is optimized and rewritten as an enhanced query plan, which when executed, uses fewer CPU cycles and thus executes faster than the original query plan. The query for which the enhanced query plan is generated thus executes faster without compromising the results obtained or the data being queried. Optimization includes identifying a set of one or more fact scan operations in the original query plan and then, in the rewritten enhanced query plan, associating one or more dimension context predicate conditions with one or more of the set of fact scan operations. This reduces the overall cost of scanning and/or processing fact records in the enhanced query plan compared to the original query plan and makes the enhanced query plan execute faster than the original query plan.
The current document is directed to a query-as-a-service system ("QAAS system") that collects enormous volumes of data from network-connected entities, referred to as "Things" in the phrase "Internet of Things," persistently stores the collected data and provides a distributed-query-execution engine that allows remote clients to continuously execute queries against the collected data. In a described implementation, both the raw data and query results are persistently stored in the QAAS system, with the raw data stored for significantly longer periods of time. Query results generated by the query-processing engine are securely transmitted to QAAS remote clients for distribution to file systems, storage appliances, applications, and other data sinks within client systems.
In general, in one aspect, the invention relates to a service provider configured to perform a method. The method includes receiving a first request from a user network device for a public key, generating the public key and a private key, sending the public key to the user network device, sending the private key to a warehouse, receiving a second request for subscription information from the warehouse comprising a user identification, identifying the subscription information associated with the user identification, and sending the subscription information to the warehouse. The warehouse, in response to receiving the subscription information is configured to determine that a license corresponding to a application is associated with the user identification, generate an application package, wherein the application package is configured to deploy the application using a Java Runtime Environment (JRE) on the user network device, and send the application package to the user network device.
In general, in one aspect, the invention relates to a computer readable medium including software instructions for performing a method, the method including receiving, by a content server, a first request from a client for an application content file, wherein the application content file is associated with a first Java network launch protocol (JNLP) file, providing, in response to the first request, the application content file; receiving, from the client, a second request to edit the application content file, providing, in response to the second request, an application designer tool to the client; receiving, from the client, an altered application content file generated using the application designer tool, generating a second JNLP file associated with the altered application content file, and providing, to a webserver, the second JNLP file.
A system including a first physical network interface card (NIC) include a number of rings, where at least one of the rings is an active ring. The system further includes a host, operatively connected to the first NIC, and including Media Access Control (MAC) layer. The MAC layer is configured to obtain a power management policy, obtain a load associated with the active ring, determine, using the power management policy and the load, that the state associated with at least one of the rings must be changed, and change, in response to the determining, the state of at least one of the of rings.
The invention relates to a "jump gap" servo mode provided to position an optical tape medium relative to a pickup head so that tracking may be reestablished after gaps in the servo tracks which occur in the pre- and post-amble fields. These gaps arise periodically because of a seam in the drum used to emboss the servo track on the tape medium. Also disclosed herein are other aspects of optical tape technology, tape manufacturing, and tape usage including: configurations, formulations, markings, and structure of the optical tape; manufacturing methods, systems, and apparatus including curing processes, coating methods, embossing, drums, testing, tracking alignment stamper strip; pick up head adapted for the disclosed optical tape; and optical tape uses including optical storage media devices for multimedia applications.
G11B 7/003 - Recording, reproducing or erasing systems characterised by the shape of the carrier with webs, e.g. belts, spooled tapes or films of quasi-infinite extent
G11B 7/09 - Disposition or mounting of heads or light sources relatively to record carriers with provision for moving the light beam or focus plane for the purpose of maintaining alignment of the light beam relative to the record carrier during transducing operation, e.g. to compensate for surface irregularities of the latter or for track f
7.
DATA STORAGE SYSTEM AND METHOD FOR CALIBRATING SAME
Disclosed herein are aspects of optical tape technology. A segment (1210) on media (1110) includes tracks (1220) with length (1230). Segments (1210) may be separated by gaps/defects (1310). Within segment (1210), tracks (1220) each exhibit fields of modulated wobble indicative of a physical track address. Tracks (1220) may not line up across gaps (1310). While focused on a particular track and prior to encountering the first gap, servo system (1150) may record the specified physical address of the particular track. Once gap (1310) has passed the optical sensing element (1120), servo system (1150) may command sensing element (1120) to refocus and determine/record the physical track address of the post-gap track it is focused on. Servo system (1150) may then assign a single logical address to the recorded physical addresses.
G11B 27/24 - Indexing; Addressing; Timing or synchronising; Measuring tape travel by using information detectable on the record carrier by sensing features on the record carrier other than the transducing track
G11B 27/32 - Indexing; Addressing; Timing or synchronising; Measuring tape travel by using information detectable on the record carrier by using information signals recorded by the same method as the main recording on separate auxiliary tracks of the same or an auxiliary record carrier
G11B 7/003 - Recording, reproducing or erasing systems characterised by the shape of the carrier with webs, e.g. belts, spooled tapes or films of quasi-infinite extent
G11B 7/007 - Arrangement of the information on the record carrier, e.g. form of tracks
G11B 7/09 - Disposition or mounting of heads or light sources relatively to record carriers with provision for moving the light beam or focus plane for the purpose of maintaining alignment of the light beam relative to the record carrier during transducing operation, e.g. to compensate for surface irregularities of the latter or for track f
G11B 7/24 - Record carriers characterised by shape, structure or physical properties, or by the selection of the material
ORACLE AMERICA, INC. FORMERLY KNOWN AS SUN MICROSYSTEMS, INC. (USA)
Inventor
Drost, Robert J.
Mitchell, James G.
Douglas, David C.
Abstract
A chip package is described. This chip package includes a stack of semiconductor dies or chips that are offset from each other, thereby defining a terrace with exposed pads. A high-bandwidth ramp component, which is positioned approximately parallel to the terrace, electrically couples to the exposed pads. For example, the ramp component may be electrically coupled to the semiconductor dies using: microsprings, an anisotropic film, and/or solder. Consequently, the electrical contacts may have a conductive, a capacitive or, in general, a complex impedance. Furthermore, the chips and/or the ramp component may be positioned relative to each other using a ball-and-pit alignment technique. By removing the need for costly and area-consuming through-silicon vias (TSVs) in the semiconductor dies, the chip package facilitates chips to be stacked in a manner that provides high bandwidth and low cost.
H01L 25/065 - Assemblies consisting of a plurality of individual semiconductor or other solid state devices all the devices being of a type provided for in the same subgroup of groups , or in a single subclass of , , e.g. assemblies of rectifier diodes the devices not having separate containers the devices being of a type provided for in group
H01L 23/00 - SEMICONDUCTOR DEVICES NOT COVERED BY CLASS - Details of semiconductor or other solid state devices
H01L 23/28 - Encapsulation, e.g. encapsulating layers, coatings
9.
EXTENDED MAIN MEMORY HIERARCHY HAVING FLASH MEMORY FOR PAGE FAULT HANDLING
A computer system with flash memory in the main memory hierarchy is disclosed. In an embodiment, the computer system includes at least one processor, a memory management unit coupled to the at least one processor, and a random access memory (RAM) coupled to the memory management unit. The computer system may also include a flash memory coupled to the memory management unit, wherein the computer system is configured to store at least a subset of a plurality of pages in the flash memory during operation. Responsive to a page fault, the memory management unit may determine, without invoking an I/O driver, if a requested page associated with the page fault is stored in the flash memory and further configured to, if the page is stored in the flash memory, transfer the page into RAM.
A computer readable medium including computer readable code for causing a computer system to perform a method. The method includes receiving an application, receiving application information for the application, and determining an access privilege for the application based, in part, on the application information. The method also includes generating a deployment package for the application using the application and the access privilege, and publishing the application.
G06F 9/44 - Arrangements for executing specific programs
G06F 15/16 - Combinations of two or more digital computers each having at least an arithmetic unit, a program unit and a register, e.g. for a simultaneous processing of several programs
G06F 17/00 - Digital computing or data processing equipment or methods, specially adapted for specific functions
G06F 21/24 - by protecting data directly, e.g. by labelling
11.
CACHE COHERENT SUPPORT FOR FLASH IN A MEMORY HIERARCHY
System and method for using flash memory in a memory hierarchy. A computer system includes a processor coupled to a memory hierarchy via a memory controller. The memory hierarchy includes a cache memory, a first memory region of random access memory coupled to the memory controller via a first buffer, and an auxiliary memory region of flash memory coupled to the memory controller via a flash controller. The first buffer and the flash controller are coupled to the memory controller via a single interface. The memory controller receives a request to access a particular page in the first memory region. The processor detects a page fault corresponding to the request and in response, invalidates cache lines in the cache memory that correspond to the particular page, flushes the invalid cache lines, and swaps a page from the auxiliary memory region to the first memory region.
ORACLE AMERICA, INC. formerly known as SUN MICROSYSTEMS, INC. (USA)
Inventor
Chaudhry, Shailender
Tremblay, Marc
Abstract
A register file, in a processor, includes a first plurality of registers of a first size, n-bits. A decoder uses a mapping that divides the register file into a second plurality M of registers having a second size. Each of the registers having the second size is assigned a different name in a continuous name space. Each register of the second size includes a plurality N of registers of the first size, n-bits. Each register in the plurality N of registers is assigned the same name as the register of the second size that includes that plurality. State information is maintained in the register file for each n-bit register. The dependence of an instruction on other instructions is detected through the continuous name space. The state information allows the processor to determine when the information in any portion, or all, of a register is valid.
ORACLE AMERICA, INC. FORMERLY KNOWN AS SUN MICROSYSTEMS, INC. (USA)
Inventor
Cunningham, John, E.
Krishnamoorthy, Ashok V.
Shubin, Ivan
Li, Guoliang
Zheng, Xuezhe
Abstract
Embodiments of an optical device, an array of optical devices, and a technique for fabricating the optical device or the array are described. This optical device is implemented on a substrate (such as silicon), and includes a thermally tunable optical waveguide that has good thermal isolation from its surroundings. In particular, a portion of a semiconductor in the optical device, which includes the optical waveguide, is free standing above a gap between the semiconductor layer and the substrate. By reducing the thermal coupling between the optical waveguide and the external environment, the optical device can be thermally tuned with significantly less power consumption.
G02F 1/025 - Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour based on semiconductor elements with at least one potential jump barrier, e.g. PN, PIN junction in an optical waveguide structure
ORACLE AMERICA, INC. FORMERLY KNOWN AS SUN MICROSYSTEMS, INC. (USA)
Inventor
Li, Guoliang
Krishnamoorthy, Ashok, V.
Cunningham, John, E.
Shubin, Ivan
Zheng, Xuezhe
Abstract
Embodiments of an optical device, an array of optical devices, and a technique for fabricating the optical device or the array are described. This optical device is implemented on a substrate (such as silicon) (410), and includes a thermally tunable optical waveguide (414) with a high thermal resistance to the surrounding external environment and a low thermal resistance to a localized heater. In particular, the thermal resistances associated with thermal dissipation paths from a heater in the optical device to an external environment via electrodes (418) and via the substrate are increased, while the thermal resistance between the optical waveguide and the heater is decreased.
G02B 6/12 - Light guides; Structural details of arrangements comprising light guides and other optical elements, e.g. couplings of the optical waveguide type of the integrated circuit kind
G02F 1/01 - Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour
Embodiments of an optical device, an array of optical devices, and a technique for fabricating the optical device or the array are described. This optical device is implemented using two semiconductor layers (such as silicon), one of which includes a heater (710) and the other includes a thermally tunable optical waveguide (415). Spatially separating these two functions in the optical device results in more efficient heat transfer between the heater and the optical waveguide, reduced heat transfer to the surroundings, and reduced optical losses in the optical waveguide relative to existing silicon-based optical devices.
G02B 6/12 - Light guides; Structural details of arrangements comprising light guides and other optical elements, e.g. couplings of the optical waveguide type of the integrated circuit kind
G02F 1/01 - Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour
16.
DATA STORAGE SYSTEM AND METHOD OF PROCESSING A DATA ACCESS REQUEST
A data storage system includes a plurality of servers, a plurality of external interface providers each deployed on one of the servers, and a plurality of data storage controllers each deployed on one of the servers. Each of the providers is configured to receive a data access request, to identify one of the controllers that can satisfy the request, and to forward the request to the identified controller. The system further includes a plurality of data storage modules independent of the servers. The providers, controllers and modules are in communication with each other. Each of the controllers exclusively manages a portion of data content in at least one of the modules, and satisfies data access requests received from the providers by accessing the portion of data content in the at least one module.
A method for associating sounds with different keypresses, involving receiving an input of a first keypress from a keyboard including a plurality of keys, wherein the keyboard is associated with a computing device, determining whether a key corresponding to the first keypress is one of a plurality of significant elements, wherein the plurality of significant elements is a subset of the plurality of keys, determining a first sound event associated with the key, when the key is one of the plurality of significant elements, and outputting a first sound associated with the first sound event.
G06F 3/023 - Arrangements for converting discrete items of information into a coded form, e.g. arrangements for interpreting keyboard generated codes as alphanumeric codes, operand codes or instruction codes
G06F 9/44 - Arrangements for executing specific programs
A method for low-overhead data transfer. The method includes initiating, by a first application, TCP connection with a second application, establishing, in response to the initiation, the TCP connection between the first application and the second application, providing, by the first application, pre-post buffer information to the second application, where the pre-post buffer information corresponds to a location in a physical memory of the first computer and where the location in physical memory corresponds to a virtual memory address of the first application. The method further comprising transferring data, by the second application, to the first application using the pre-post buffer information, where transferring the data comprises writing the data directly into a location in the physical memory of the first computer.
A method for power management. The method includes gathering resource usage data for a first blade and a second blade on a blade chassis, migrating each virtual machine (VM) executing on the first blade to the second blade based on the resource usage data and a first migration policy, wherein the first migration policy defines when to condense the number of blades operating on the blade chassis, and powering down the first blade after each VM executing on the first blade is migrated from the first blade.
A method for power managing hardware. The method includes determining hardware to power manage, sending a tracing request from a power management control to a tracing framework to obtain usage data of the hardware, and identifying a first probe to obtain first tracing data corresponding to the usage data in a first hardware control software component, where the first hardware control software is configured to interact with the hardware. The method further includes enabling the first probe, obtaining the first tracing data from the first probe, where the first tracing data is obtained when the first probe is encountered during execution of the first hardware control software, and modifying operation of the hardware using the first tracing data.
The invention relates to a method for processing a packet. The method includes receiving the packet by a physical network interface, determining a target virtual network interface card (VNIC) using the destination address and a virtual switching table (VST), transferring the packet to a receive ring (RR) associated with the target VNIC, wherein the RR is located on the NEM, determining, by the target VNIC, that the packet is in the RR, determining, by the target VNIC, that the packet is to be processed using an offload engine, transferring the packet to offload memory located on an offload computer, wherein the offload computer is operatively connected to the NEM via the chassis interconnect and wherein the offload engine is executing on the offload computer, processing the packet by the offload engine to obtain a processed packet, and transferring the processed packet to a target computer memory using the chassis interconnect.
H04L 29/10 - Communication control; Communication processing characterised by an interface, e.g. the interface between the data link level and the physical level
G06F 15/16 - Combinations of two or more digital computers each having at least an arithmetic unit, a program unit and a register, e.g. for a simultaneous processing of several programs
patents
