In accordance with disclosed embodiments, there is a method of integrating and accessing passive components in three-dimensional fan-out wafer-level packages. One example is a microelectronic die package that includes a die, a package substrate attached to the die on one side of the die and configured to be connected to a system board, a plurality of passive devices over a second side of the die, and a plurality of passive device contacts over a respective passive die, the contacts being configured to be coupled to a second die mounted over the passive devices and over the second side of the die.
H01L 23/00 - SEMICONDUCTOR DEVICES NOT COVERED BY CLASS - Details of semiconductor or other solid state devices
H01L 21/48 - Manufacture or treatment of parts, e.g. containers, prior to assembly of the devices, using processes not provided for in a single one of the groups
H01L 21/56 - Encapsulations, e.g. encapsulating layers, coatings
H01L 21/683 - Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components for supporting or gripping
H01L 23/31 - Encapsulation, e.g. encapsulating layers, coatings characterised by the arrangement
H01L 23/538 - Arrangements for conducting electric current within the device in operation from one component to another the interconnection structure between a plurality of semiconductor chips being formed on, or in, insulating substrates
2.
Mechanism to accelerate graphics workloads in a multi-core computing architecture
A processing apparatus is described. The apparatus includes a plurality of processing cores, including a first processing core and a second processing core a first field programmable gate array (FPGA) coupled to the first processing core to accelerate execution of graphics workloads processed at the first processing core and a second FPGA coupled to the second processing core to accelerate execution of workloads processed at the second processing core.
Embodiments of the invention include a microelectronic device and methods of forming a microelectronic device. In an embodiment the microelectronic device includes a semiconductor die and an inductor that is electrically coupled to the semiconductor die. The inductor may include one or more conductive coils that extend away from a surface of the semiconductor die. In an embodiment each conductive coils may include a plurality of traces. For example, a first trace and a third trace may be formed over a first dielectric layer and a second trace may be formed over a second dielectric layer and over a core. A first via through the second dielectric layer may couple the first trace to the second trace, and a second via through the second dielectric layer may couple the second trace to the third trace.
H01F 41/04 - Apparatus or processes specially adapted for manufacturing or assembling magnets, inductances or transformers; Apparatus or processes specially adapted for manufacturing materials characterised by their magnetic properties for manufacturing cores, coils or magnets for manufacturing coils
H01L 23/522 - Arrangements for conducting electric current within the device in operation from one component to another including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
H01L 23/00 - SEMICONDUCTOR DEVICES NOT COVERED BY CLASS - Details of semiconductor or other solid state devices
4.
Mechanism to accelerate graphics workloads in a multi-core computing architecture
A processing apparatus is described. The apparatus includes a plurality of processing cores, including a first processing core and a second processing core a first field programmable gate array (FPGA) coupled to the first processing core to accelerate execution of graphics workloads processed at the first processing core and a second FPGA coupled to the second processing core to accelerate execution of workloads processed at the second processing core.
Radio frequency shielding within a semiconductor package is described. In one example, a multiple chip package has a digital chip, a radio frequency chip, and an isolation layer between the digital chip and the radio frequency chip. A cover encloses the digital chip and the radio frequency chip.
H01L 23/552 - Protection against radiation, e.g. light
H01L 23/31 - Encapsulation, e.g. encapsulating layers, coatings characterised by the arrangement
H01L 23/538 - Arrangements for conducting electric current within the device in operation from one component to another the interconnection structure between a plurality of semiconductor chips being formed on, or in, insulating substrates
H01L 23/00 - SEMICONDUCTOR DEVICES NOT COVERED BY CLASS - Details of semiconductor or other solid state devices
H01L 25/065 - Assemblies consisting of a plurality of individual semiconductor or other solid state devices all the devices being of a type provided for in the same subgroup of groups , or in a single subclass of , , e.g. assemblies of rectifier diodes the devices not having separate containers the devices being of a type provided for in group
H01L 25/18 - Assemblies consisting of a plurality of individual semiconductor or other solid state devices the devices being of types provided for in two or more different subgroups of the same main group of groups , or in a single subclass of ,
H01L 21/683 - Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components for supporting or gripping
H01L 23/04 - Containers; Seals characterised by the shape
H01L 23/48 - Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads or terminal arrangements
This disclosure describes systems, methods, and devices related to using enhanced high efficiency (HE) frames. A device may determine a high efficiency signal-B (HE-SIG-B) field for a high efficiency (HE) frame, the HE-SIG-B field comprising a common information field and a user information field. The device may determine a data portion of the HE frame, wherein the data portion includes one or more resource units (RUs) with a size equal to a number of tones. The device may determine a first resource allocation subfield and a second resource allocation subfield of the common information field based at least in part on the number of tones. The device may cause to send the HE frame.
Some embodiments include packages and methods of making the packages. One of the packages includes a ground layer (e.g., a ground plane) of metal formed over a chip of die, an antenna element of metal formed over the ground layer, and a dielectric lens formed over the antenna element. The dielectric lens includes a plurality of dielectric layers that have graded dielectric constants in a decreasing order along a direction from the antenna element toward a top surface of the package.
H01Q 19/06 - Combinations of primary active antenna elements and units with secondary devices, e.g. with quasi-optical devices, for giving the antenna a desired directional characteristic using refracting or diffracting devices, e.g. lens
H01Q 15/08 - Refracting or diffracting devices, e.g. lens, prism formed of solid dielectric material
H01L 23/522 - Arrangements for conducting electric current within the device in operation from one component to another including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
H01L 23/00 - SEMICONDUCTOR DEVICES NOT COVERED BY CLASS - Details of semiconductor or other solid state devices
H01L 21/56 - Encapsulations, e.g. encapsulating layers, coatings
H01L 21/3205 - Deposition of non-insulating-, e.g. conductive- or resistive-, layers, on insulating layers; After-treatment of these layers
H01L 21/48 - Manufacture or treatment of parts, e.g. containers, prior to assembly of the devices, using processes not provided for in a single one of the groups
H01L 21/768 - Applying interconnections to be used for carrying current between separate components within a device
H01L 23/13 - Mountings, e.g. non-detachable insulating substrates characterised by the shape
The disclosure relates to a method, apparatus and system to wirelessly charge a device without creating fire hazard or other risks to nearby sensitive objects. An exemplary embodiment includes a memory circuitry and a chipset. The chipset communicates with the memory circuitry and is configured to selectively communicate with one of a wireless charging module and an NFC module to detect presence of the sensitive device. The chipset can be further configured to: transmit a first polling signal at a first power level for a first duration and detect a response from the sensitive device; if no response is detected during the first duration, transmit a second polling signal at a second power level for a second duration; cease polling signal transmission if response is received to either the first or the second polling signals; and engage the wireless charging module to charge the proximally located wireless device if no response is detected from the sensitive device during the first or the second duration.
H02J 7/00 - Circuit arrangements for charging or depolarising batteries or for supplying loads from batteries
H02J 7/02 - Circuit arrangements for charging or depolarising batteries or for supplying loads from batteries for charging batteries from ac mains by converters
H02J 50/10 - Circuit arrangements or systems for wireless supply or distribution of electric power using inductive coupling
H02J 50/60 - Circuit arrangements or systems for wireless supply or distribution of electric power responsive to the presence of foreign objects, e.g. detection of living beings
9.
Transmitting magnetic field through metal chassis using fractal surfaces
Described herein are techniques related one or more systems, apparatuses, methods, etc. for reducing induced currents in a apparatus chassis. For example, a fractal slot is constructed in the apparatus chassis to reduce the induced currents, and enhance passage of magnetic fields through the apparatus chassis. In this example, the fractal slot may include a no-self loop fractal space filling curve shape to provide high impedance to the induced currents.
H04B 7/00 - Radio transmission systems, i.e. using radiation field
H04B 5/00 - Near-field transmission systems, e.g. inductive loop type
H01Q 1/22 - Supports; Mounting means by structural association with other equipment or articles
H01Q 1/52 - Means for reducing coupling between antennas; Means for reducing coupling between an antenna and another structure
H01Q 7/00 - Loop antennas with a substantially uniform current distribution around the loop and having a directional radiation pattern in a plane perpendicular to the plane of the loop
10.
Systems and methods for NFC access control in a secure element centric NFC architecture
This disclosure describes systems, methods, and computer-readable media related to near field communication (NFC) access control in a secure element centric NFC architecture. A secure element may receive a request for information and process the received request to identify a first access level associated with the request and a second access level associated with an originator of the request. The secure element may determine if the first access level matches the second access level. If the first access level does not match the second access level, the secure element may transmit a message to the originator of the request indicating a denial of the request. If the first access level does match the second access level, the secure element may transmit the request to a near field communication (NFC) controller, receive information from the NFC controller, and transmit the information from the NFC controller to the originator of the request.
G06F 21/62 - Protecting access to data via a platform, e.g. using keys or access control rules
H04L 29/06 - Communication control; Communication processing characterised by a protocol
H04W 4/80 - Services using short range communication, e.g. near-field communication [NFC], radio-frequency identification [RFID] or low energy communication
H04W 4/00 - Services specially adapted for wireless communication networks; Facilities therefor
Described herein are systems, methods and apparatus for decoding in-band on-channel signals and extracting audio and data signals. Memory requirements are reduced by selectively filtering a bit stream of data in the signal so that services of interest which are encoded therein are processed. A single pool of memory may be shared between physical layer and data link layer processing. Memory in this pool may be allocated dynamically between processing of data at the physical and data link layers. When the available memory is not sufficient to support the required services, the dynamic allocation allows for graceful degradation.
Two wireless communications devices in a wireless network may reserve a period of time for directional data communications between themselves during a Contention Access Period. The technique may include transmitting Clear-to-Send messages to each other, and to any other devices with which either has established a directional link, to prevent interfering transmissions from these other devices. Other devices that have not established a directional link with either of these two may overhear the CTS messages and also refrain from transmitting interfering signals during the reserved time period.
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