Avatar animation systems disclosed herein provide high quality, real-time avatar animation that is based on the varying countenance of a human face. In some example embodiments, the real-time provision of high quality avatar animation is enabled, at least in part, by a multi-frame regressor that is configured to map information descriptive of facial expressions depicted in two or more images to information descriptive of a single avatar blend shape. The two or more images may be temporally sequential images. This multi-frame regressor implements a machine learning component that generates the high quality avatar animation from information descriptive of a subject's face and/or information descriptive of avatar animation frames previously generated by the multi-frame regressor. The machine learning component may be trained using a set of training images that depict human facial expressions and avatar animation authored by professional animators to reflect facial expressions depicted in the set of training images.
Embodiments of the present disclosure are directed towards devices and methods for identifying preferred access networks based at least in part on access network information including access network assistance information, steering policies, or access commands. In some embodiments, conflicts between access network information and access network discovery and selection function (ANDSF) policies may be rectified in identifying a preferred access network.
H04W 8/02 - Processing of mobility data, e.g. registration information at HLR [Home Location Register] or VLR [Visitor Location Register]; Transfer of mobility data, e.g. between HLR, VLR or external networks
Method and apparatus for deriving a motion vector at a video decoder. A block-based motion vector may be produced at the video decoder by utilizing motion estimation among available pixels relative to blocks in one or more reference frames. The available pixels could be, for example, spatially neighboring blocks in the sequential scan coding order of a current frame, blocks in a previously decoded frame, or blocks in a downsampled frame in a lower pyramid when layered coding has been used.
The present invention relates to a helmet that includes an outer shell, a heads-up information system that comprises a display, and an attachment assembly. The heads-up information system is movable from a storage position within the outer shell to a use position in which the display of the heads-up information system is visible by a user, without obstructing the field of vision of the user, when the helmet is worn by the user. The attachment assembly is coupled to outer shell and the heads-up information system, and is operable to move the heads-up information system between the storage position and the use position.
Techniques to couple a high bandwidth memory device on a silicon substrate and a package substrate are disclosed. Examples include selectively activating input/out (I/O) or command and address (CA) contacts on a bottom side of a logic layer for the high bandwidth device based on a mode of operation. The I/O and CA contacts are for accessing one or more memory devices include in the high bandwidth memory device via one or more data channels.
Systems, apparatus, articles of manufacture and methods for face augmentation in video are disclosed. An example apparatus includes executable code to detect a face of a subject in the video, detect a gender of the subject based on the face, detect a skin tone of the subject based on the face, apply a first process to smooth skin on the face in the video, apply a second process to change the skin tone of the face, apply a third process to slim the face, apply a fourth process to adjust a size of eyes on the face, and apply a fifth process to remove an eye bag from the face. One or more of the first process, the second process, the third process, the fourth process, or the fifth process adjustable based on one or more of the gender or an age. The example apparatus also includes one or more processors to generate modified video with beauty effects, the beauty effects based on one or more of the first process, the second process, the third process, the fourth process, or the fifth process.
An array imaging apparatus having discrete camera modules is disclosed. In one embodiment, the apparatus comprises a substrate; and heterogeneous camera modules attached to the substrate and in a geometric relationship with each other, the heterogeneous camera modules having a substantially similar photometric response.
H04N 23/45 - Cameras or camera modules comprising electronic image sensors; Control thereof for generating image signals from two or more image sensors being of different type or operating in different modes, e.g. with a CMOS sensor for moving images in combination with a charge-coupled device [CCD] for still images
G03B 30/00 - Camera modules comprising integrated lens units and imaging units, specially adapted for being embedded in other devices, e.g. mobile phones or vehicles
H04N 5/073 - Arrangements or circuits at the transmitter end for mutually locking plural sources of synchronising signals, e.g. studios or relay stations
H04N 23/57 - Mechanical or electrical details of cameras or camera modules specially adapted for being embedded in other devices
Folding devices are disclosed. An example folding device includes a first frame; a second frame; an actuator including a first end coupled to the first frame and a second end hingably coupled to the second frame; and a display coupled to the first and second frames, when the folding device is in a folded position, the display wraps around ends of the first and second frames to cover a joint between the first and second frames, when the folding device rotates from the folded position toward an unfolded position, the actuator urges the ends of the first and second frames away from one another to encourage the display to unwrap from around the ends.
Computer-readable storage media, computing devices, and methods associated with an adaptive learning environment associated with an adaptive learning environment are disclosed. In embodiments, a computing device may include an instruction module and an adaptation module operatively coupled with the instruction module. The instruction module may selectively provide instructional content of one of a plurality of instructional content types to a user of the computing device via one or more output devices coupled with the computing device. The adaptation module may determine, in real-time, an engagement level associated with the user of the computing device and may cooperate with the instruction module to dynamically adapt the instructional content provided to the user based at least in part on the engagement level determined. Other embodiments may be described and/or claimed.
An electronic device may include a substrate, and the substrate may include one or more layers. The one or more layers may include a first dielectric material and one or more electrical traces. A cavity may be defined in the substrate, and the cavity may be adapted to receive one or more electrical components. One or more lateral traces may extend through a wall of the cavity. The lateral traces may provide electrical communication pathways between the substrate and the electrical components.
H01L 23/538 - Arrangements for conducting electric current within the device in operation from one component to another the interconnection structure between a plurality of semiconductor chips being formed on, or in, insulating substrates
Power management techniques are disclosed. For instance, an apparatus may include a bidirectional voltage converter circuit, and a control module that selectively operates the bidirectional voltage converter circuit in a charging mode and a delivery mode. The charging mode converts a voltage provided by an interface (e.g., a USB interface) into a charging voltage employed by an energy storage module (e.g., a rechargeable battery). Conversely, the delivery mode converts a voltage provided by the energy storage module into a voltage employed by the interface. Other embodiments are described and claimed.
Methods, systems, and storage media relating to a vehicle navigator system are disclosed herein. In an embodiment, vehicle operation data relating to one or more characteristics of operation of a motor vehicle may be received. An operation style by which an operator may operate the motor vehicle may be determined from the vehicle operation data. A vehicle location and a destination location may be received. A route may be determined from the vehicle location to the destination location according to the operation style by which an operator operates the motor vehicle. Other embodiments may be disclosed and/or claimed.
Embodiments that allow both high density and low density interconnection between microelectronic die and motherboard via. Direct Chip Attach (DCA) are described. In some embodiments, microelectronic die have a high density interconnect with a small bump pitch located along one edge and a lower density connection region with a larger bump pitch located in other regions of the die. The high density interconnect regions between die are interconnected using an interconnecting bridge made out of a material that can support high density interconnect manufactured into it, such as silicon. The lower density connection regions are used to attach interconnected die directly to a board using DCA. The high density interconnect can utilize current Controlled Collapsed Chip Connection (C4) spacing when interconnecting die with an interconnecting bridge, while allowing much larger spacing on circuit boards.
H01L 23/538 - Arrangements for conducting electric current within the device in operation from one component to another the interconnection structure between a plurality of semiconductor chips being formed on, or in, insulating substrates
H01L 23/00 - SEMICONDUCTOR DEVICES NOT COVERED BY CLASS - Details of semiconductor or other solid state devices
H01L 25/00 - Assemblies consisting of a plurality of individual semiconductor or other solid state devices
H01L 21/48 - Manufacture or treatment of parts, e.g. containers, prior to assembly of the devices, using processes not provided for in a single one of the groups
H01L 23/13 - Mountings, e.g. non-detachable insulating substrates characterised by the shape
H01L 25/065 - Assemblies consisting of a plurality of individual semiconductor or other solid state devices all the devices being of a type provided for in the same subgroup of groups , or in a single subclass of , , e.g. assemblies of rectifier diodes the devices not having separate containers the devices being of a type provided for in group
H01L 25/18 - Assemblies consisting of a plurality of individual semiconductor or other solid state devices the devices being of types provided for in two or more different subgroups of the same main group of groups , or in a single subclass of ,
16.
NON-PLANAR SEMICONDUCTOR DEVICE HAVING DOPED SUB-FIN REGION AND METHOD TO FABRICATE SAME
Non-planar semiconductor devices having doped sub-fin regions and methods of fabricating non-planar semiconductor devices having doped sub-fin regions are described. For example, a method of fabricating a semiconductor structure involves forming a plurality of semiconductor fins above a semiconductor substrate. A solid state dopant source layer is formed above the semiconductor substrate, conformal with the plurality of semiconductor fins. A dielectric layer is formed above the solid state dopant source layer. The dielectric layer and the solid state dopant source layer are recessed to approximately a same level below a top surface of the plurality of semiconductor fins, exposing protruding portions of each of the plurality of semiconductor fins above sub-fin regions of each of the plurality of semiconductor fins. The method also involves driving dopants from the solid state dopant source layer into the sub-fin regions of each of the plurality of semiconductor fins.
H01L 27/092 - Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only the components being field-effect transistors with insulated gate complementary MIS field-effect transistors
H01L 27/088 - Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only the components being field-effect transistors with insulated gate
H01L 21/225 - Diffusion of impurity materials, e.g. doping materials, electrode materials, into, or out of, a semiconductor body, or between semiconductor regions; Redistribution of impurity materials, e.g. without introduction or removal of further dopant using diffusion into, or out of, a solid from or into a solid phase, e.g. a doped oxide layer
H01L 29/08 - Semiconductor bodies characterised by the shapes, relative sizes, or dispositions of the semiconductor regions with semiconductor regions connected to an electrode carrying current to be rectified, amplified, or switched and such electrode being part of a semiconductor device which comprises three or more electrodes
H01L 21/8238 - Complementary field-effect transistors, e.g. CMOS
Power governance circuitry is provided to control a performance level of a processing unit of a processing platform. The power governance circuitry comprises measurement circuitry to measure a current utilization of the processing unit at a current operating frequency and to determine any change in utilization or power and frequency control circuitry is provided to update the current operating frequency to a new operating frequency by determining a new target quantified power expenditure to be applied in a subsequent processing cycle depending on the determination of any change in utilization or power. A new operating frequency is selected to satisfy the new target quantified power based on a scalability function specifying a variation of a given value of utilization or power with the operating frequency. A processing platform and machine readable instructions are provided to set a new quantified target power of a processing unit.
Embodiments of the invention include a microelectronic device that includes a substrate, at least one dielectric layer on the substrate and a plurality of conductive lines within the at least one dielectric layer. The microelectronic device also includes an air gap structure that is located below two or more of the plurality of conductive lines.
H01L 23/522 - Arrangements for conducting electric current within the device in operation from one component to another including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
H01L 21/768 - Applying interconnections to be used for carrying current between separate components within a device
H01L 29/06 - Semiconductor bodies characterised by the shapes, relative sizes, or dispositions of the semiconductor regions
H01L 23/532 - Arrangements for conducting electric current within the device in operation from one component to another including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body characterised by the materials
19.
Methods and apparatus for battery current monitoring
Methods and apparatus are disclosed for battery current monitoring. An example apparatus includes a haptic device, an isolation switch to deliver power from a battery to the haptic device, an integrator to integrate a signal based on a current from the battery to the haptic device to generate an integrator output, and control logic to control the isolation switch based on a comparison of the integrator output to a threshold.
H02H 3/093 - Emergency protective circuit arrangements for automatic disconnection directly responsive to an undesired change from normal electric working condition, with or without subsequent reconnection responsive to excess current with timing means
H02H 3/087 - Emergency protective circuit arrangements for automatic disconnection directly responsive to an undesired change from normal electric working condition, with or without subsequent reconnection responsive to excess current for dc applications
20.
GENERATION OF SYNTHETIC 3-DIMENSIONAL OBJECT IMAGES FOR RECOGNITION SYSTEMS
Techniques are provided for generation of synthetic 3-dimensional object image variations for training of recognition systems. An example system may include an image synthesizing circuit configured to synthesize a 3D image of the object (including color and depth image pairs) based on a 3D model. The system may also include a background scene generator circuit configured to generate a background for each of the rendered image variations. The system may further include an image pose adjustment circuit configured to adjust the orientation and translation of the object for each of the variations. The system may further include an illumination and visual effect adjustment circuit configured to adjust illumination of the object and the background for each of the variations, and to further adjust visual effects of the object and the background for each of the variations based on application of simulated camera parameters.
Examples are disclosed for access to a storage device maintained at a server. In some examples, a network input/output device coupled to the server may allocate, in a memory of the server, a buffer, a doorbell, and a queue pair accessible to a client remote to the server. For these examples, the network input/output device may assign an Non-Volatile Memory Express (NVMe) namespace context to the client. For these examples, indications of the allocated buffer, doorbell, queue pair, and namespace context may be transmitted to the client. Other examples are described and claimed.
G06F 21/79 - Protecting specific internal or peripheral components, in which the protection of a component leads to protection of the entire computer to assure secure storage of data in semiconductor storage media, e.g. directly-addressable memories
G06F 3/06 - Digital input from, or digital output to, record carriers
G06F 21/80 - Protecting specific internal or peripheral components, in which the protection of a component leads to protection of the entire computer to assure secure storage of data in storage media based on magnetic or optical technology, e.g. disks with sectors
G06F 15/167 - Interprocessor communication using a common memory, e.g. mailbox
H04L 67/1097 - Protocols in which an application is distributed across nodes in the network for distributed storage of data in networks, e.g. transport arrangements for network file system [NFS], storage area networks [SAN] or network attached storage [NAS]
G06F 13/42 - Bus transfer protocol, e.g. handshake; Synchronisation
22.
Processor Having Accelerated User Responsiveness In Constrained Environment
In one embodiment, a processor includes at least one core to execute instructions and a power controller coupled to the at least one core. The power controller may include a first logic to cause the at least one core to exit an idle state and enter into a maximum performance state for a first time duration, thereafter enter into an intermediate power state for a second time duration, and thereafter enter into a sustained performance state. Other embodiments are described and claimed.
A method and apparatus for monitoring an internet-of-things (IoT) battery device (IBD). An example IBD includes a radio transceiver to communicate with an IoT charging device (ICD), a battery, and a battery monitor to determine a state of charge for the battery. An alerter is included to send an alert message to the ICD, via the radio transceiver, to indicate that the SoCh is less than an alert threshold.
G01R 31/371 - Arrangements for testing, measuring or monitoring the electrical condition of accumulators or electric batteries, e.g. capacity or state of charge [SoC] with remote indication, e.g. on external chargers
G01R 31/382 - Arrangements for monitoring battery or accumulator variables, e.g. SoC
H02J 50/80 - Circuit arrangements or systems for wireless supply or distribution of electric power involving the exchange of data, concerning supply or distribution of electric power, between transmitting devices and receiving devices
H02J 50/10 - Circuit arrangements or systems for wireless supply or distribution of electric power using inductive coupling
H02J 7/00 - Circuit arrangements for charging or depolarising batteries or for supplying loads from batteries
A method, apparatus and system with an autonomic, self-healing polymer capable of slowing crack propagation within the polymer and slowing delamination at a material interface.
H01L 25/00 - Assemblies consisting of a plurality of individual semiconductor or other solid state devices
H01L 25/065 - Assemblies consisting of a plurality of individual semiconductor or other solid state devices all the devices being of a type provided for in the same subgroup of groups , or in a single subclass of , , e.g. assemblies of rectifier diodes the devices not having separate containers the devices being of a type provided for in group
H01L 25/16 - Assemblies consisting of a plurality of individual semiconductor or other solid state devices the devices being of types provided for in two or more different main groups of groups , or in a single subclass of , , e.g. forming hybrid circuits
H01Q 1/22 - Supports; Mounting means by structural association with other equipment or articles
H01Q 1/38 - Structural form of radiating elements, e.g. cone, spiral, umbrella formed by a conductive layer on an insulating support
Techniques related to coding video using adaptive quantization rounding offsets for use in transform coefficient quantization are discussed. Such techniques may include determining the value of a quantization rounding offset for a picture of a video sequence based on evaluating a maximum coding bit limit of the picture, a quantization parameter of the picture, and parameters corresponding to the video.
H04N 19/126 - Quantisation - Details of normalisation or weighting functions, e.g. normalisation matrices or variable uniform quantisers
H04N 19/146 - Data rate or code amount at the encoder output
H04N 19/172 - Methods or arrangements for coding, decoding, compressing or decompressing digital video signals using adaptive coding characterised by the coding unit, i.e. the structural portion or semantic portion of the video signal being the object or the subject of the adaptive coding the unit being an image region, e.g. an object the region being a picture, frame or field
H04N 19/159 - Prediction type, e.g. intra-frame, inter-frame or bidirectional frame prediction
H04N 19/142 - Detection of scene cut or scene change
26.
Techniques to couple high bandwidth memory device on silicon substrate and package substrate
Techniques to couple a high bandwidth memory device on a silicon substrate and a package substrate are disclosed. Examples include selectively activating input/out (I/O) or command and address (CA) contacts on a bottom side of a logic layer for the high bandwidth device based on a mode of operation. The I/O and CA contacts are for accessing one or more memory devices include in the high bandwidth memory device via one or more data channels.
Embodiments of a system and method for controlling a device charging on a wireless charger are generally described herein. A method may include disabling, in response to determining that the device is currently charging on the wireless charger, haptic feedback at the device, determining whether the device is in a night mode or a day mode, in response to determining that the device is in the night mode and currently charging on the wireless charger, disabling notifications of the device, and enabling, in response to determining that the device is in the day mode, the haptic feedback and the notifications when the device has been removed from the wireless charger.
An integrated circuit device with a substrate and a plurality of fins is provided where fin width is less than 11 nanometers, fin height is greater than 155 nanometers and spacing between any two neighboring fins is less than 30 nanometers and each fin is in non-collapsed state. An integrated circuit device with a substrate and a plurality of fins is provided where fin width is less than 15 nanometers, fin height is greater than 190 nanometers and spacing between any two neighboring fins is less than 30 nanometers and each fin is in non-collapsed state. A method for forming a fin-based transistor structure is provided where a plurality of fins on a substrate are pre-treated with at least one of a self-assembled monolayer, a non-polar solvent, and a surfactant. One or more of these treatments is to reduce adhesion and/or cohesive forces to prevent occurrence of fin collapse.
H01L 27/088 - Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only the components being field-effect transistors with insulated gate
H01L 21/02 - Manufacture or treatment of semiconductor devices or of parts thereof
H01L 27/02 - Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including integrated passive circuit elements with at least one potential-jump barrier or surface barrier
H01L 29/06 - Semiconductor bodies characterised by the shapes, relative sizes, or dispositions of the semiconductor regions
H01L 29/08 - Semiconductor bodies characterised by the shapes, relative sizes, or dispositions of the semiconductor regions with semiconductor regions connected to an electrode carrying current to be rectified, amplified, or switched and such electrode being part of a semiconductor device which comprises three or more electrodes
H01L 29/423 - Electrodes characterised by their shape, relative sizes or dispositions not carrying the current to be rectified, amplified or switched
Systems, methods, and circuitries are disclosed for a per-process memory encryption system. At least one translation lookaside buffer (TLB) is configured to encode key identifiers for keys in one or more bits of either the virtual memory address or the physical address. The process state memory configured to store a first process key table for a first process that maps key identifiers to unique keys and a second process key table that maps the key identifiers to different unique keys. The active process key table memory configured to store an active key table. In response to a request for data corresponding to a virtual memory address, the at least one TLB is configured to provide a key identifier for the data to the active process key table to cause the active process key table to return the unique key mapped to the key identifier.
The present disclosure is directed to a computer-assisted or autonomous driving (CA/AD) vehicle with a controller to control one or more light emitters to produce a light pattern that uniquely identify the vehicle. It may also be directed to a system to receive image data from one or more video cameras located in a location vicinity of the CA/AD vehicle emitting a pattern of light, and to analyze the received image data to determine a physical location of the vehicle.
G01C 21/28 - Navigation; Navigational instruments not provided for in groups specially adapted for navigation in a road network with correlation of data from several navigational instruments
G01S 19/14 - Receivers specially adapted for specific applications
G05D 1/02 - Control of position or course in two dimensions
G06T 7/70 - Determining position or orientation of objects or cameras
G08G 1/04 - Detecting movement of traffic to be counted or controlled using optical or ultrasonic detectors
B60Q 1/26 - Arrangement of optical signalling or lighting devices, the mounting or supporting thereof or circuits therefor the devices being primarily intended to indicate the vehicle, or parts thereof, or to give signals, to other traffic
H04N 7/18 - Closed-circuit television [CCTV] systems, i.e. systems in which the video signal is not broadcast
G08G 1/017 - Detecting movement of traffic to be counted or controlled identifying vehicles
31.
TECHNOLOGIES FOR PROVIDING INFORMATION TO A USER WHILE TRAVELING
Examples disclosed herein include a mobile computing device to determine network condition information associated with a route segment. The route segment may be one of a number of route segments defining at least one route from a starting location to a destination. The mobile computing device may determine a route from the starting location to the destination based on the network condition information. The mobile computing device may upload the network condition information to a crowdsourcing server. A mobile computing device may predict a future location of the device based on device context, determine a safety level for the predicted location, and notify the user if the safety level is below a threshold safety level. The device context may include location, time of day, and other data. The safety level may be determined based on predefined crime data.
Methods and apparatus relating to platform power consumption reduction via power state switching are described. In one embodiment, control logic causes a processor to enter a first low power consumption state (e.g., S0ix) instead of a second low power consumption state (e.g., S3) based on whether a threshold time period exists between a first wake event (e.g., corresponding to a first one of one or more awake requests) and a second wake event (e.g., corresponding to a second one of the one or more awake requests). Other embodiments are also claimed and disclosed.
An array imaging apparatus having discrete camera modules is disclosed. In one embodiment, the apparatus comprises a substrate; and heterogeneous camera modules attached to the substrate and in a geometric relationship with each other, the heterogeneous camera modules having a substantially similar photometric response.
H04N 23/45 - Cameras or camera modules comprising electronic image sensors; Control thereof for generating image signals from two or more image sensors being of different type or operating in different modes, e.g. with a CMOS sensor for moving images in combination with a charge-coupled device [CCD] for still images
H04N 23/57 - Mechanical or electrical details of cameras or camera modules specially adapted for being embedded in other devices
H04N 5/073 - Arrangements or circuits at the transmitter end for mutually locking plural sources of synchronising signals, e.g. studios or relay stations
34.
METHOD OF FORMING HIGH DENSITY, HIGH SHORTING MARGIN, AND LOW CAPACITANCE INTERCONNECTS BY ALTERNATING RECESSED TRENCHES
Embodiments of the invention describe low capacitance interconnect structures for semiconductor devices and methods for manufacturing such devices. According to an embodiment of the invention, a low capacitance interconnect structure comprises an interlayer dielectric (ILD). First and second interconnect lines are disposed in the ILD in an alternating pattern. The top surfaces of the first interconnect lines may be recessed below the top surfaces of the second interconnect lines. Increases in the recess of the first interconnect lines decreases the line-to-line capacitance between neighboring interconnects. Further embodiments include utilizing different dielectric materials as etching caps above the first and second interconnect lines. The different materials may have a high selectivity over each other during an etching process. Accordingly, the alignment budget for contacts to individual interconnect lines is increased.
H01L 23/528 - Layout of the interconnection structure
H01L 21/768 - Applying interconnections to be used for carrying current between separate components within a device
H01L 23/522 - Arrangements for conducting electric current within the device in operation from one component to another including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
H01L 23/532 - Arrangements for conducting electric current within the device in operation from one component to another including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body characterised by the materials
H01L 21/033 - Making masks on semiconductor bodies for further photolithographic processing, not provided for in group or comprising inorganic layers
H01L 21/02 - Manufacture or treatment of semiconductor devices or of parts thereof
Technologies for selectively augmenting communications transmitted by a communication device include a communication device configured to acquire new user environment information relating to the environment of the user if such new user environment information becomes available. The communication device is further configured to create one or more user environment indicators based on the new user environment information, to display the one or more created user environment indicators via a display of the communication device and include the created user environment indicator in a communication to be transmitted by the communication device if the created user environment indicator is selected for inclusion in the communication.
G06F 3/04817 - Interaction techniques based on graphical user interfaces [GUI] based on specific properties of the displayed interaction object or a metaphor-based environment, e.g. interaction with desktop elements like windows or icons, or assisted by a cursor's changing behaviour or appearance using icons
G06F 3/01 - Input arrangements or combined input and output arrangements for interaction between user and computer
H04M 1/72454 - User interfaces specially adapted for cordless or mobile telephones with means for adapting the functionality of the device according to specific conditions according to context-related or environment-related conditions
36.
Cobalt based interconnects and methods of fabrication thereof
An embodiment includes a metal interconnect structure, comprising: a dielectric layer disposed on a substrate; an opening in the dielectric layer, wherein the opening has sidewalls and exposes a conductive region of at least one of the substrate and an interconnect line; an adhesive layer, comprising manganese, disposed over the conductive region and on the sidewalls; and a fill material, comprising cobalt, within the opening and on a surface of the adhesion layer. Other embodiments are described herein.
H01L 23/532 - Arrangements for conducting electric current within the device in operation from one component to another including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body characterised by the materials
H01L 21/768 - Applying interconnections to be used for carrying current between separate components within a device
H01L 29/78 - Field-effect transistors with field effect produced by an insulated gate
H01L 23/522 - Arrangements for conducting electric current within the device in operation from one component to another including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
H01L 23/00 - SEMICONDUCTOR DEVICES NOT COVERED BY CLASS - Details of semiconductor or other solid state devices
37.
Electromigration resistant and profile consistent contact arrays
A package assembly includes a substrate and at least a first die having a first contact array and a second contact array. First and second via assemblies are respectively coupled with the first and second contact arrays. Each of the first and second via assemblies includes a base pad, a cap assembly, and a via therebetween. One or more of the cap assembly or the via includes an electromigration resistant material to isolate each of the base pad and the cap assembly. Each first cap assembly and via of the first via assemblies has a first assembly profile less than a second assembly profile of each second cap assembly and via of the second via assemblies. The first and second cap assemblies have a common applied thickness in an application configuration. The first and second cap assemblies have a thickness variation of ten microns or less in a reflowed configuration.
H01L 23/538 - Arrangements for conducting electric current within the device in operation from one component to another the interconnection structure between a plurality of semiconductor chips being formed on, or in, insulating substrates
H01L 25/18 - Assemblies consisting of a plurality of individual semiconductor or other solid state devices the devices being of types provided for in two or more different subgroups of the same main group of groups , or in a single subclass of ,
H01L 21/48 - Manufacture or treatment of parts, e.g. containers, prior to assembly of the devices, using processes not provided for in a single one of the groups
H01L 23/00 - SEMICONDUCTOR DEVICES NOT COVERED BY CLASS - Details of semiconductor or other solid state devices
H01L 25/00 - Assemblies consisting of a plurality of individual semiconductor or other solid state devices
In some examples, a transport agnostic source includes a streaming device to stream video on diverse transport topologies including isochronous and non-isochronous transports. In some examples, a transport agnostic sink includes a receiving device to receive streamed video from diverse transport topologies including isochronous and non-isochronous transports.
H04N 21/242 - Synchronization processes, e.g. processing of PCR [Program Clock References]
H04N 21/434 - Disassembling of a multiplex stream, e.g. demultiplexing audio and video streams or extraction of additional data from a video stream; Remultiplexing of multiplex streams; Extraction or processing of SI; Disassembling of packetised elementary stream
H04N 21/2343 - Processing of video elementary streams, e.g. splicing of video streams or manipulating MPEG-4 scene graphs involving reformatting operations of video signals for distribution or compliance with end-user requests or end-user device requirements
H04N 21/236 - Assembling of a multiplex stream, e.g. transport stream, by combining a video stream with other content or additional data, e.g. inserting a URL [Uniform Resource Locator ] into a video stream, multiplexing software data into a video stream; Remultiplexing of multiplex streams; Insertion of stuffing bits into the multiplex stream, e.g. to obtain a constant bit-rate; Assembling of a packetised elementary stream
39.
TEXTILE PATTERNING FOR SUBTRACTIVELY-PATTERNED SELF-ALIGNED INTERCONNECTS, PLUGS, AND VIAS
Embodiments of the invention include methods of forming a textile patterned hardmask. In an embodiment, a first hardmask and a second hardmask are formed over a top surface of an interconnect layer in an alternating pattern. A sacrificial cross-grating may then be formed over the first and second hardmasks. In an embodiment, portions of the first hardmask that are not covered by the sacrificial cross-grating are removed to form first openings and a third hardmask is disposed into the first openings. Embodiments may then include etching through portions of the second hardmask that are not covered by the sacrificial cross-grating to form second openings. The second openings may be filled with a fourth hardmask. According to an embodiment, the first, second, third, and fourth hardmasks are etch selective to each other. In an embodiment the sacrificial cross-grating may then be removed.
H01L 21/3213 - Physical or chemical etching of the layers, e.g. to produce a patterned layer from a pre-deposited extensive layer
H01L 21/768 - Applying interconnections to be used for carrying current between separate components within a device
H01L 21/033 - Making masks on semiconductor bodies for further photolithographic processing, not provided for in group or comprising inorganic layers
H01L 23/522 - Arrangements for conducting electric current within the device in operation from one component to another including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
40.
NON-PLANAR SEMICONDUCTOR DEVICE HAVING OMEGA-FIN WITH DOPED SUB-FIN REGION AND METHOD TO FABRICATE SAME
Non-planar semiconductor devices having omega-fins with doped sub-fin regions and methods of fabricating non-planar semiconductor devices having omega-fins with doped sub-fin regions are described. For example, a semiconductor device includes a plurality of semiconductor fins disposed above a semiconductor substrate, each semiconductor fin having a sub-fin portion below a protruding portion, the sub-fin portion narrower than the protruding portion. A solid state dopant source layer is disposed above the semiconductor substrate, conformal with the sub-fin region but not the protruding portion of each of the plurality of semiconductor fins. An isolation layer is disposed above the solid state dopant source layer and between the sub-fin regions of the plurality of semiconductor fins. A gate stack is disposed above the isolation layer and conformal with the protruding portions of each of the plurality of semiconductor fins.
H01L 27/088 - Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only the components being field-effect transistors with insulated gate
41.
Techniques for command validation for access to a storage device by a remote client
Examples are disclosed for access to a storage device maintained at a server. In some examples, a network input/output device coupled to the server may allocate, in a memory of the server, a buffer, a doorbell, and a queue pair accessible to a client remote to the server. For these examples, the network input/output device may assign an Non-Volatile Memory Express (NVMe) namespace context to the client. For these examples, indications of the allocated buffer, doorbell, queue pair, and namespace context may be transmitted to the client. Other examples are described and claimed.
G06F 21/79 - Protecting specific internal or peripheral components, in which the protection of a component leads to protection of the entire computer to assure secure storage of data in semiconductor storage media, e.g. directly-addressable memories
G06F 3/06 - Digital input from, or digital output to, record carriers
G06F 21/80 - Protecting specific internal or peripheral components, in which the protection of a component leads to protection of the entire computer to assure secure storage of data in storage media based on magnetic or optical technology, e.g. disks with sectors
G06F 15/167 - Interprocessor communication using a common memory, e.g. mailbox
H04L 67/1097 - Protocols in which an application is distributed across nodes in the network for distributed storage of data in networks, e.g. transport arrangements for network file system [NFS], storage area networks [SAN] or network attached storage [NAS]
G06F 13/42 - Bus transfer protocol, e.g. handshake; Synchronisation
42.
Dielectric and isolation lower fin material for fin-based electronics
A dielectric and isolation lower fin material is described that is useful for fin-based electronics. In some examples, a dielectric layer is on first and second sidewalls of a lower fin. The dielectric layer has a first upper end portion laterally adjacent to the first sidewall of the lower fin and a second upper end portion laterally adjacent to the second sidewall of the lower fin. An isolation material is laterally adjacent to the dielectric layer directly on the first and second sidewalls of the lower fin and a gate electrode is over a top of and laterally adjacent to sidewalls of an upper fin. The gate electrode is over the first and second upper end portions of the dielectric layer and the isolation material.
H01L 27/098 - Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only the components being PN junction gate field-effect transistors
43.
Aggregated analytics for intelligent transportation systems
Various systems and methods for collecting and generating analytics of data from motor vehicle safety and operation systems are disclosed herein. In one example, various minor vehicle incidents and events such as hard braking, swerving, deceleration, are tracked and correlated to geographic locations. Event data for these incidents may be collected, aggregated, anonymized, and electronically communicated to a processing system for further analysis and identification of problematic roadway and traffic conditions.
G06F 7/00 - Methods or arrangements for processing data by operating upon the order or content of the data handled
G06F 19/00 - Digital computing or data processing equipment or methods, specially adapted for specific applications (specially adapted for specific functions G06F 17/00;data processing systems or methods specially adapted for administrative, commercial, financial, managerial, supervisory or forecasting purposes G06Q;healthcare informatics G16H)
G08G 1/01 - Detecting movement of traffic to be counted or controlled
Power governance circuitry is provided to control a performance level of a processing unit of a processing platform. The power governance circuitry comprises measurement circuitry to measure a current utilization of the processing unit at a current operating frequency and to determine any change in utilization or power and frequency control circuitry is provided to update the current operating frequency to a new operating frequency by determining a new target quantified power expenditure to be applied in a subsequent processing cycle depending on the determination of any change in utilization or power. A new operating frequency is selected to satisfy the new target quantified power based on a scalability function specifying a variation of a given value of utilization or power with the operating frequency. A processing platform and machine readable instructions are provided to set a new quantified target power of a processing unit.
Embodiments that allow both high density and low density interconnection between microelectronic die and motherboard via. Direct Chip Attach (DCA) are described. In some embodiments, microelectronic die have a high density interconnect with a small bump pitch located along one edge and a lower density connection region with a larger bump pitch located in other regions of the die. The high density interconnect regions between die are interconnected using an interconnecting bridge made out of a material that can support high density interconnect manufactured into it, such as silicon. The lower density connection regions are used to attach interconnected die directly to a board using DCA. The high density interconnect can utilize current Controlled Collapsed Chip Connection (C4) spacing when interconnecting die with an interconnecting bridge, while allowing much larger spacing on circuit boards.
H01L 23/538 - Arrangements for conducting electric current within the device in operation from one component to another the interconnection structure between a plurality of semiconductor chips being formed on, or in, insulating substrates
H01L 23/00 - SEMICONDUCTOR DEVICES NOT COVERED BY CLASS - Details of semiconductor or other solid state devices
H01L 25/00 - Assemblies consisting of a plurality of individual semiconductor or other solid state devices
H01L 21/48 - Manufacture or treatment of parts, e.g. containers, prior to assembly of the devices, using processes not provided for in a single one of the groups
H01L 23/13 - Mountings, e.g. non-detachable insulating substrates characterised by the shape
H01L 25/065 - Assemblies consisting of a plurality of individual semiconductor or other solid state devices all the devices being of a type provided for in the same subgroup of groups , or in a single subclass of , , e.g. assemblies of rectifier diodes the devices not having separate containers the devices being of a type provided for in group
H01L 25/18 - Assemblies consisting of a plurality of individual semiconductor or other solid state devices the devices being of types provided for in two or more different subgroups of the same main group of groups , or in a single subclass of ,
H01L 23/14 - Mountings, e.g. non-detachable insulating substrates characterised by the material or its electrical properties
46.
SELF-ALIGNED 3-D EPITAXIAL STRUCTURES FOR MOS DEVICE FABRICATION
Techniques are disclosed for customization of fin-based transistor devices to provide a diverse range of channel configurations and/or material systems within the same integrated circuit die. In accordance with one example embodiment, sacrificial fins are removed and replaced with custom semiconductor material of arbitrary composition and strain suitable for a given application. In one such case, each of a first set of the sacrificial fins is recessed or otherwise removed and replaced with a p-type material, and each of a second set of the sacrificial fins is recessed or otherwise removed and replaced with an n-type material. The p-type material can be completely independent of the process for the n-type material, and vice-versa. Numerous other circuit configurations and device variations are enabled using the techniques provided herein.
H01L 21/8238 - Complementary field-effect transistors, e.g. CMOS
H01L 29/10 - Semiconductor bodies characterised by the shapes, relative sizes, or dispositions of the semiconductor regions with semiconductor regions connected to an electrode not carrying current to be rectified, amplified, or switched and such electrode being part of a semiconductor device which comprises three or more electrodes
H01L 21/8258 - Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using a combination of technologies covered by , , or
Systems, apparatus, articles of manufacture and methods for face augmentation in video are disclosed. An example apparatus includes executable code to detect a face of a subject in the video, detect a gender of the subject based on the face, detect a skin tone of the subject based on the face, apply a first process to smooth skin on the face in the video, apply a second process to change the skin tone of the face, apply a third process to slim the face, apply a fourth process to adjust a size of eyes on the face, and apply a fifth process to remove an eye bag from the face. One or more of the first process, the second process, the third process, the fourth process, or the fifth process adjustable based on one or more of the gender or an age. The example apparatus also includes one or more processors to generate modified video with beauty effects, the beauty effects based on one or more of the first process, the second process, the third process, the fourth process, or the fifth process.
In one embodiment, a processor includes a plurality of domains each to operate at an independently controllable voltage and frequency, a plurality of linear regulators each to receive a first voltage from an off-chip source and controllable to provide a regulated voltage to at least one of the plurality of domains, and a plurality of selectors each coupled to one of the domains, where each selector is configured to provide a regulated voltage from one of the linear regulators or a bypass voltage to a corresponding domain. Other embodiments are described and claimed.
Methods, systems, and storage media relating to a vehicle navigator system are disclosed herein. In an embodiment, vehicle operation data relating to one or more characteristics of operation of a motor vehicle may be received. An operation style by which an operator may operate the motor vehicle may be determined from the vehicle operation data. A vehicle location and a destination location may be received. A route may be determined from the vehicle location to the destination location according to the operation style by which an operator operates the motor vehicle. Other embodiments may be disclosed and/or claimed.
In one embodiment, a processor includes at least one core to execute instructions and a power controller coupled to the at least one core. The power controller may include a first logic to cause the at least one core to exit an idle state and enter into a maximum performance state for a first time duration, thereafter enter into an intermediate power state for a second time duration, and thereafter enter into a sustained performance state. Other embodiments are described and claimed.
An apparatus and method for performing multisampling anti-aliasing. For example, one embodiment of an apparatus samples multiple locations within each pixel of an image frame to generate a plurality of image slices. Each image slice comprises a different set of samples for each of the pixels of the image frame. Anti-aliasing is then performed on the image frame using the image slices by first subdividing the plurality of image slices into equal-sized pixel blocks and determining whether each pixel block has one or more different pixel values in different image slices. If so, then edge detection and simple shape detection is performed using pixel data from a pixel block in a single image slice; if not, then edge detection and simple shape detection is performed using the pixel block in multiple image slices.
Techniques to couple a high bandwidth memory device on a silicon substrate and a package substrate are disclosed. Examples include selectively activating input/out (I/O) or command and address (CA) contacts on a bottom side of a logic layer for the high bandwidth device based on a mode of operation. The I/O and CA contacts are for accessing one or more memory devices include in the high bandwidth memory device via one or more data channels.
A digital advertising system includes an advertisements module that provides a number of digital advertisements for display on a digital display device. A digital sign module including the digital display device displays digital advertisements provided by the advertisements module, and captures video analytics data relating to previous viewers of the digital advertisements displayed by the digital sign module. A data mining module retrieves the video analytics data from the digital sign module and generates trained advertising models based thereon using a data mining algorithm. A content management system module coupled to the advertisements module and the data mining module receives the digital advertisements and the trained advertising models and generates a subset of the advertisements for display based on the trained advertising models.
A method and apparatus for monitoring an internet-of-things (IoT) battery device (IBD). An example IBD includes a radio transceiver to communicate with an IoT charging device (ICD), a battery, and a battery monitor to determine a state of charge for the battery. An alerter is included to send an alert message to the ICD, via the radio transceiver, to indicate that the SoCh is less than an alert threshold.
G01R 31/371 - Arrangements for testing, measuring or monitoring the electrical condition of accumulators or electric batteries, e.g. capacity or state of charge [SoC] with remote indication, e.g. on external chargers
G01R 31/382 - Arrangements for monitoring battery or accumulator variables, e.g. SoC
H02J 50/80 - Circuit arrangements or systems for wireless supply or distribution of electric power involving the exchange of data, concerning supply or distribution of electric power, between transmitting devices and receiving devices
H02J 50/10 - Circuit arrangements or systems for wireless supply or distribution of electric power using inductive coupling
H02J 7/00 - Circuit arrangements for charging or depolarising batteries or for supplying loads from batteries
55.
FINFET transistor having a doped sub fin structure to reduce channel to substrate leakage
An apparatus is described. The apparatus includes a FINFET device having a channel. The channel is composed of a first semiconductor material that is epitaxially grown on a subfin structure beneath the channel. The subfin structure is composed of a second semiconductor material that is different than the first semiconductor material. The subfin structure is epitaxially grown on a substrate composed of a third semiconductor material that is different than the first and second semiconductor materials. The subfin structure has a doped region to substantially impede leakage currents between the channel and the substrate.
H01L 29/10 - Semiconductor bodies characterised by the shapes, relative sizes, or dispositions of the semiconductor regions with semiconductor regions connected to an electrode not carrying current to be rectified, amplified, or switched and such electrode being part of a semiconductor device which comprises three or more electrodes
Power management techniques are disclosed. For instance, an apparatus may include a bidirectional voltage converter circuit, and a control module that selectively operates the bidirectional voltage converter circuit in a charging mode and a delivery mode. The charging mode converts a voltage provided by an interface (e.g., a USB interface) into a charging voltage employed by an energy storage module (e.g., a rechargeable battery). Conversely, the delivery mode converts a voltage provided by the energy storage module into a voltage employed by the interface. Other embodiments are described and claimed.
H02J 7/00 - Circuit arrangements for charging or depolarising batteries or for supplying loads from batteries
H02J 7/14 - Circuit arrangements for charging or depolarising batteries or for supplying loads from batteries for charging batteries from dynamo-electric generators driven at varying speed, e.g. on vehicle
Power governance circuitry is provided to control a performance level of a processing unit of a processing platform. The power governance circuitry comprises measurement circuitry to measure a current utilization of the processing unit at a current operating frequency and to determine any change in utilization or power and frequency control circuitry is provided to update the current operating frequency to a new operating frequency by determining a new target quantified power expenditure to be applied in a subsequent processing cycle depending on the determination of any change in utilization or power. A new operating frequency is selected to satisfy the new target quantified power based on a scalability function specifying a variation of a given value of utilization or power with the operating frequency. A processing platform and machine readable instructions are provided to set a new quantified target power of a processing unit.
Folding devices are disclosed. An example folding device includes a first frame; a second frame; an actuator including a first end coupled to the first frame and a second end hingably coupled to the second frame; and a display coupled to the first and second frames, when the folding device is in a folded position, the display wraps around ends of the first and second frames to cover a joint between the first and second frames, when the folding device rotates from the folded position toward an unfolded position, the actuator urges the ends of the first and second frames away from one another to encourage the display to unwrap from around the ends.
Embodiments of the invention include a microelectronic device that includes a substrate, at least one dielectric layer on the substrate and a plurality of conductive lines within the at least one dielectric layer. The microelectronic device also includes an air gap structure that is located below two or more of the plurality of conductive lines.
H01L 23/48 - Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads or terminal arrangements
H01L 23/52 - Arrangements for conducting electric current within the device in operation from one component to another
H01L 23/522 - Arrangements for conducting electric current within the device in operation from one component to another including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
H01L 21/768 - Applying interconnections to be used for carrying current between separate components within a device
H01L 29/06 - Semiconductor bodies characterised by the shapes, relative sizes, or dispositions of the semiconductor regions
H01L 23/532 - Arrangements for conducting electric current within the device in operation from one component to another including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body characterised by the materials
61.
Semiconductor packaging with high density interconnects
Various embodiments disclosed relate to a semiconductor package. The present semiconductor package includes a substrate. The substrate is formed from alternating conducting layers and dielectric layers. A first active electronic component is disposed on an external surface of the substrate, and a second active electronic component is at least partially embedded within the substrate. A first interconnect region is formed from a plurality of interconnects between the first active electronic component and the second active electronic component. Between the first active electronic component and the substrate a second interconnect region is formed from a plurality of interconnects. Additionally, a third interconnect region is formed from a plurality of interconnects between the second active electronic component and the substrate.
H01L 23/538 - Arrangements for conducting electric current within the device in operation from one component to another the interconnection structure between a plurality of semiconductor chips being formed on, or in, insulating substrates
H01L 25/065 - Assemblies consisting of a plurality of individual semiconductor or other solid state devices all the devices being of a type provided for in the same subgroup of groups , or in a single subclass of , , e.g. assemblies of rectifier diodes the devices not having separate containers the devices being of a type provided for in group
H01L 25/18 - Assemblies consisting of a plurality of individual semiconductor or other solid state devices the devices being of types provided for in two or more different subgroups of the same main group of groups , or in a single subclass of ,
H01L 21/48 - Manufacture or treatment of parts, e.g. containers, prior to assembly of the devices, using processes not provided for in a single one of the groups
H01L 23/00 - SEMICONDUCTOR DEVICES NOT COVERED BY CLASS - Details of semiconductor or other solid state devices
H01L 25/00 - Assemblies consisting of a plurality of individual semiconductor or other solid state devices
H01L 25/03 - Assemblies consisting of a plurality of individual semiconductor or other solid state devices all the devices being of a type provided for in the same subgroup of groups , or in a single subclass of , , e.g. assemblies of rectifier diodes
62.
Dense memory arrays utilizing access transistors with back-side contacts
Described herein are memory arrays where some memory cells include access transistors with one front-side and one back-side source/drain (S/D) contacts. An example memory array further includes a bitline, coupled to the first S/D region of the access transistor of a first memory cell of the memory array, and a plateline, coupled to a first capacitor electrode of a storage capacitor of the first memory cell. Because the access transistor is a transistor with one front-side and one back-side S/D contacts, the bitline may be provided in a first layer, the channel material—in a second layer, and the plateline—in a third layer, where the second layer is between the first layer and the third layer, which may allow increasing the density of memory cells in a memory array, or, conversely, reducing the footprint area of a memory array with a given density of memory cells.
G11C 11/34 - Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices
H01L 27/108 - Dynamic random access memory structures
G11C 5/04 - Supports for storage elements; Mounting or fixing of storage elements on such supports
G11C 5/10 - Arrangements for interconnecting storage elements electrically, e.g. by wiring for interconnecting capacitors
G11C 11/402 - Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming cells needing refreshing or charge regeneration, i.e. dynamic cells with charge regeneration individual to each memory cell, i.e. internal refresh
Systems, apparatuses and methods to provide image data, augmented with related data, to be displayed on a mobile computing device are disclosed. An example mobile device includes a camera to provide images of a scene from different angles to a server, at least one sensor to sense a position and an orientation of the camera, and a screen to present augmented reality data over the scene based on the position and the orientation of the camera and on a three-dimensional representation of the scene based on the images.
A semiconductor package and a packaged electronic device are described. The semiconductor package has a foundation layer and a planar filtering circuit. The circuit is formed in the foundation layer to provide EMI/RFI mitigation. The circuit has one or more conductive traces that are patterned to form an equivalent circuit of inductors and capacitors. The one or more conductive traces include planar metal shapes, such as meanders, loops, inter-digital fingers, and patterned shapes, to reduce the z-height of the package. The packaged electronic device has a semiconductor die, a foundation layer, a motherboard, a package, and the circuit. The circuit removes undesirable interferences generated from the semiconductor die. The circuit has a z-height that is less than a z-height of solder balls used to attach the foundation layer to the motherboard. A method of forming a planar filtering circuit in a foundation layer is also described.
H01L 21/48 - Manufacture or treatment of parts, e.g. containers, prior to assembly of the devices, using processes not provided for in a single one of the groups
Examples disclosed herein include a mobile computing device to determine network condition information associated with a route segment. The route segment may be one of a number of route segments defining at least one route from a starting location to a destination. The mobile computing device may determine a route from the starting location to the destination based on the network condition information. The mobile computing device may upload the network condition information to a crowdsourcing server. A mobile computing device may predict a future location of the device based on device context, determine a safety level for the predicted location, and notify the user if the safety level is below a threshold safety level. The device context may include location, time of day, and other data. The safety level may be determined based on predefined crime data.
Methods of forming microelectronic package structures, and structures formed thereby, are described. Those methods/structures may include attaching a first die on a board, attaching an interposer on a top surface of the first die, and attaching a second die on the top surface of the first die that is adjacent the interposer, wherein the second die is offset from a center region of the first die. A first wire conductive structure may be attached to the second die that extends from the second die to a top surface of the interposer. A second wire conductive structure is attached to the interposer and extends from the interposer to the board.
H01L 25/065 - Assemblies consisting of a plurality of individual semiconductor or other solid state devices all the devices being of a type provided for in the same subgroup of groups , or in a single subclass of , , e.g. assemblies of rectifier diodes the devices not having separate containers the devices being of a type provided for in group
H01L 23/00 - SEMICONDUCTOR DEVICES NOT COVERED BY CLASS - Details of semiconductor or other solid state devices
H01L 25/18 - Assemblies consisting of a plurality of individual semiconductor or other solid state devices the devices being of types provided for in two or more different subgroups of the same main group of groups , or in a single subclass of ,
H01L 25/00 - Assemblies consisting of a plurality of individual semiconductor or other solid state devices
A BGA structure having larger solder balls in high stress regions of the array is disclosed. The larger solder balls have higher solder joint reliability (SJR) and as such may be designated critical to function (CTF), whereby the larger solder balls in high stress regions carry input/output signals between a circuit board and a package mounted thereon. The larger solder balls are accommodated by recessing each ball in the package substrate, the circuit board, or both the package substrate and the circuit board. Additionally, a ball attach method for mounting a plurality of solder balls having different average diameters is disclosed.
H05K 7/12 - Resilient or clamping means for holding component to structure
H05K 3/34 - Assembling printed circuits with electric components, e.g. with resistor electrically connecting electric components or wires to printed circuits by soldering
H05K 1/11 - Printed elements for providing electric connections to or between printed circuits
H01L 21/48 - Manufacture or treatment of parts, e.g. containers, prior to assembly of the devices, using processes not provided for in a single one of the groups
B23K 31/02 - Processes relevant to this subclass, specially adapted for particular articles or purposes, but not covered by any single one of main groups relating to soldering or welding
68.
Interface engine providing a continuous user interface
An interface engine provides animated views in a user interface. The interface engine directs the operation of a rendering environment to create an interface in a rendering area. The interface engine includes views, layouts, animators, and constraints. Views identify child views and resources for display in the rendering area. In response to events, such as user inputs, a view modifies itself by calling layouts, animators, and constraints. A layout manages the attributes of a view's child views, including child view position and size. An animator modifies the view's appearance over a specified period of time. A constraint imposes limits on view properties. In one implementation, an Internet site delivers an interface engine to a browser to supply content and a user interface. A presentation server compiles an interface engine description and specified resources into an interface engine. The presentation server delivers the interface engine to the browser, which executes the interface engine using a plug-in—eliminating excessive interface updates found in traditional HTML pages.
G06K 15/00 - Arrangements for producing a permanent visual presentation of the output data
G06F 3/0481 - Interaction techniques based on graphical user interfaces [GUI] based on specific properties of the displayed interaction object or a metaphor-based environment, e.g. interaction with desktop elements like windows or icons, or assisted by a cursor's changing behaviour or appearance
G06F 8/38 - Creation or generation of source code for implementing user interfaces
In some examples, a transport agnostic source includes a streaming device to stream video on diverse transport topologies including isochronous and non-isochronous transports. In some examples, a transport agnostic sink includes a receiving device to receive streamed video from diverse transport topologies including isochronous and non-isochronous transports.
H04N 21/242 - Synchronization processes, e.g. processing of PCR [Program Clock References]
H04N 21/434 - Disassembling of a multiplex stream, e.g. demultiplexing audio and video streams or extraction of additional data from a video stream; Remultiplexing of multiplex streams; Extraction or processing of SI; Disassembling of packetised elementary stream
H04N 21/2343 - Processing of video elementary streams, e.g. splicing of video streams or manipulating MPEG-4 scene graphs involving reformatting operations of video signals for distribution or compliance with end-user requests or end-user device requirements
H04N 21/236 - Assembling of a multiplex stream, e.g. transport stream, by combining a video stream with other content or additional data, e.g. inserting a URL [Uniform Resource Locator ] into a video stream, multiplexing software data into a video stream; Remultiplexing of multiplex streams; Insertion of stuffing bits into the multiplex stream, e.g. to obtain a constant bit-rate; Assembling of a packetised elementary stream
70.
Systems and method for selling content over a network
A method to generate revenue from supplied content is provided. Content is provided to a consumer via a network by providing a content service that allows the consumer to select and retrieve content as a package together with a clearing of the selectable content to an operator used by the consumer to select and retrieve the content via the network. Any content selected by the consumer is supplied directly to the consumer via the operator. The operator is charged for the supplied content.
Non-planar semiconductor devices having doped sub-fin regions and methods of fabricating non-planar semiconductor devices having doped sub-fin regions are described. For example, a method of fabricating a semiconductor structure involves forming a plurality of semiconductor fins above a semiconductor substrate. A solid state dopant source layer is formed above the semiconductor substrate, conformal with the plurality of semiconductor fins. A dielectric layer is formed above the solid state dopant source layer. The dielectric layer and the solid state dopant source layer are recessed to approximately a same level below a top surface of the plurality of semiconductor fins, exposing protruding portions of each of the plurality of semiconductor fins above sub-fin regions of each of the plurality of semiconductor fins. The method also involves driving dopants from the solid state dopant source layer into the sub-fin regions of each of the plurality of semiconductor fins.
H01L 27/092 - Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only the components being field-effect transistors with insulated gate complementary MIS field-effect transistors
H01L 21/8238 - Complementary field-effect transistors, e.g. CMOS
H01L 21/225 - Diffusion of impurity materials, e.g. doping materials, electrode materials, into, or out of, a semiconductor body, or between semiconductor regions; Redistribution of impurity materials, e.g. without introduction or removal of further dopant using diffusion into, or out of, a solid from or into a solid phase, e.g. a doped oxide layer
H01L 21/265 - Bombardment with wave or particle radiation with high-energy radiation producing ion implantation
H01L 27/088 - Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only the components being field-effect transistors with insulated gate
H01L 29/08 - Semiconductor bodies characterised by the shapes, relative sizes, or dispositions of the semiconductor regions with semiconductor regions connected to an electrode carrying current to be rectified, amplified, or switched and such electrode being part of a semiconductor device which comprises three or more electrodes
Systems, methods, and circuitries are disclosed for a per-process memory encryption system. At least one translation lookaside buffer (TLB) is configured to encode key identifiers for keys in one or more bits of either the virtual memory address or the physical address. The process state memory configured to store a first process key table for a first process that maps key identifiers to unique keys and a second process key table that maps the key identifiers to different unique keys. The active process key table memory configured to store an active key table. In response to a request for data corresponding to a virtual memory address, the at least one TLB is configured to provide a key identifier for the data to the active process key table to cause the active process key table to return the unique key mapped to the key identifier.
A method of fabricating a MOS transistor having a thinned channel region is described. The channel region is etched following removal of a dummy gate. The source and drain regions have relatively low resistance with the process.
H01L 29/06 - Semiconductor bodies characterised by the shapes, relative sizes, or dispositions of the semiconductor regions
H01L 29/08 - Semiconductor bodies characterised by the shapes, relative sizes, or dispositions of the semiconductor regions with semiconductor regions connected to an electrode carrying current to be rectified, amplified, or switched and such electrode being part of a semiconductor device which comprises three or more electrodes
H01L 29/10 - Semiconductor bodies characterised by the shapes, relative sizes, or dispositions of the semiconductor regions with semiconductor regions connected to an electrode not carrying current to be rectified, amplified, or switched and such electrode being part of a semiconductor device which comprises three or more electrodes
H01L 29/161 - Semiconductor bodies characterised by the materials of which they are formed including, apart from doping materials or other impurities, only elements of Group IV of the Periodic System in uncombined form including two or more of the elements provided for in group
H01L 29/165 - Semiconductor bodies characterised by the materials of which they are formed including, apart from doping materials or other impurities, only elements of Group IV of the Periodic System in uncombined form including two or more of the elements provided for in group in different semiconductor regions
H01L 29/24 - Semiconductor bodies characterised by the materials of which they are formed including, apart from doping materials or other impurities, only inorganic semiconductor materials not provided for in groups , , or
H01L 29/267 - Semiconductor bodies characterised by the materials of which they are formed including, apart from doping materials or other impurities, elements provided for in two or more of the groups , , , , in different semiconductor regions
Techniques related to coding video using adaptive quantization rounding offsets for use in transform coefficient quantization are discussed. Such techniques may include determining the value of a quantization rounding offset for a picture of a video sequence based on evaluating a maximum coding bit limit of the picture, a quantization parameter of the picture, and parameters corresponding to the video.
H04N 19/126 - Quantisation - Details of normalisation or weighting functions, e.g. normalisation matrices or variable uniform quantisers
H04N 19/146 - Data rate or code amount at the encoder output
H04N 19/172 - Methods or arrangements for coding, decoding, compressing or decompressing digital video signals using adaptive coding characterised by the coding unit, i.e. the structural portion or semantic portion of the video signal being the object or the subject of the adaptive coding the unit being an image region, e.g. an object the region being a picture, frame or field
H04N 19/159 - Prediction type, e.g. intra-frame, inter-frame or bidirectional frame prediction
H04N 19/142 - Detection of scene cut or scene change
76.
Distribution of tasks among asymmetric processing elements
Techniques to control power and processing among a plurality of asymmetric cores. In one embodiment, one or more asymmetric cores are power managed to migrate processes or threads among a plurality of cores according to the performance and power needs of the system.
G06F 1/3287 - Power saving characterised by the action undertaken by switching off individual functional units in the computer system
G06F 12/0875 - Addressing of a memory level in which the access to the desired data or data block requires associative addressing means, e.g. caches with dedicated cache, e.g. instruction or stack
Technology for a display controller is described. The display controller can detect a frame update when the display controller is in a dynamic sleep state. The display controller can wake up from the dynamic sleep state and enter a selective update state at a programmed vertical blanking interrupt (VBI) that precedes an actual VBI. The display controller can perform a scan-out with a display panel during the selective update state. The display controller can return to the dynamic sleep state in a same time frame after the scan-out is completed. The display controller can exclude timing logic to send a VBI at every time frame to the display panel to maintain time synchronization between the display controller and the display panel.
G09G 3/22 - Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix using controlled light sources
G06F 1/3237 - Power saving characterised by the action undertaken by disabling clock generation or distribution
G06F 1/3234 - Power saving characterised by the action undertaken
G06F 1/3206 - Monitoring of events, devices or parameters that trigger a change in power modality
G09G 3/20 - Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix
G06F 3/041 - Digitisers, e.g. for touch screens or touch pads, characterised by the transducing means
78.
Methods and systems for motion vector derivation at a video decoder
Method and apparatus for deriving a motion vector at a video decoder. A block-based motion vector may be produced at the video decoder by utilizing motion estimation among available pixels relative to blocks in one or more reference frames. The available pixels could be, for example, spatially neighboring blocks in the sequential scan coding order of a current frame, blocks in a previously decoded frame, or blocks in a downsampled frame in a lower pyramid when layered coding has been used.
A method, apparatus and system with an autonomic, self-healing polymer capable of slowing crack propagation within the polymer and slowing delamination at a material interface.
H01L 25/065 - Assemblies consisting of a plurality of individual semiconductor or other solid state devices all the devices being of a type provided for in the same subgroup of groups , or in a single subclass of , , e.g. assemblies of rectifier diodes the devices not having separate containers the devices being of a type provided for in group
H01L 25/16 - Assemblies consisting of a plurality of individual semiconductor or other solid state devices the devices being of types provided for in two or more different main groups of groups , or in a single subclass of , , e.g. forming hybrid circuits
Techniques are provided for generation of synthetic 3-dimensional object image variations for training of recognition systems. An example system may include an image synthesizing circuit configured to synthesize a 3D image of the object (including color and depth image pairs) based on a 3D model. The system may also include a background scene generator circuit configured to generate a background for each of the rendered image variations. The system may further include an image pose adjustment circuit configured to adjust the orientation and translation of the object for each of the variations. The system may further include an illumination and visual effect adjustment circuit configured to adjust illumination of the object and the background for each of the variations, and to further adjust visual effects of the object and the background for each of the variations based on application of simulated camera parameters.
Subtractive plug and tab patterning with photobuckets for back end of line (BEOL) spacer-based interconnects is described. In an example, a back end of line (BEOL) metallization layer for a semiconductor structure includes an inter-layer dielectric (ILD) layer disposed above a substrate. A plurality of conductive lines is disposed in the ILD layer along a first direction. A conductive tab is disposed in the ILD layer, the conductive tab coupling two of the plurality of conductive lines along a second direction orthogonal to the first direction. A conductive via is coupled to one of the plurality of conductive lines, the conductive via having a via hardmask thereon. An uppermost surface of each of the ILD layer, the plurality of conductive lines, the conductive tab, and the via hardmask is planar with one another.
H01L 21/768 - Applying interconnections to be used for carrying current between separate components within a device
H01L 23/522 - Arrangements for conducting electric current within the device in operation from one component to another including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
H01L 23/528 - Layout of the interconnection structure
82.
Techniques for multi-read and multi-write of memory circuit
Embodiments include apparatuses, methods, and systems to implement a multi-read and/or multi-write process with a set of memory cells. The set of memory cells may be multiplexed with a same sense amplifier. As part of a multi-read process, a memory controller coupled to a memory circuit may precharge the bit lines associated with the set of memory cells, provide a single assertion of a word line signal on the word line, and then sequentially read data from the set of memory cells (using the sense amplifier) based on the precharge and the single assertion of the word line signal. Additionally, or alternatively, a multi-write process may be performed to sequentially write data to the set of memory cells based on one precharge of the associated bit lines. Other embodiments may be described and claimed.
G11C 11/412 - Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming cells with positive feedback, i.e. cells not needing refreshing or charge regeneration, e.g. bistable multivibrator or Schmitt trigger using field-effect transistors only
G11C 7/12 - Bit line control circuits, e.g. drivers, boosters, pull-up circuits, pull-down circuits, precharging circuits, equalising circuits, for bit lines
G11C 7/10 - Input/output [I/O] data interface arrangements, e.g. I/O data control circuits, I/O data buffers
A package assembly includes a substrate and at least a first die having a first contact array and a second contact array. First and second via assemblies are respectively coupled with the first and second contact arrays. Each of the first and second via assemblies includes a base pad, a cap assembly, and a via therebetween. One or more of the cap assembly or the via includes an electromigration resistant material to isolate each of the base pad and the cap assembly. Each first cap assembly and via of the first via assemblies has a first assembly profile less than a second assembly profile of each second cap assembly and via of the second via assemblies. The first and second cap assemblies have a common applied thickness in an application configuration. The first and second cap assemblies have a thickness variation of ten microns or less in a reflowed configuration.
H01L 23/538 - Arrangements for conducting electric current within the device in operation from one component to another the interconnection structure between a plurality of semiconductor chips being formed on, or in, insulating substrates
H01L 25/18 - Assemblies consisting of a plurality of individual semiconductor or other solid state devices the devices being of types provided for in two or more different subgroups of the same main group of groups , or in a single subclass of ,
H01L 21/48 - Manufacture or treatment of parts, e.g. containers, prior to assembly of the devices, using processes not provided for in a single one of the groups
H01L 23/00 - SEMICONDUCTOR DEVICES NOT COVERED BY CLASS - Details of semiconductor or other solid state devices
H01L 25/00 - Assemblies consisting of a plurality of individual semiconductor or other solid state devices
An electronic device may include a substrate, and the substrate may include one or more layers. The one or more layers may include a first dielectric material and one or more electrical traces. A cavity may be defined in the substrate, and the cavity may be adapted to receive one or more electrical components. One or more lateral traces may extend through a wall of the cavity. The lateral traces may provide electrical communication pathways between the substrate and the electrical components.
H01L 23/538 - Arrangements for conducting electric current within the device in operation from one component to another the interconnection structure between a plurality of semiconductor chips being formed on, or in, insulating substrates
85.
Integrated circuit devices with non-collapsed fins and methods of treating the fins to prevent fin collapse
An integrated circuit device with a substrate and a plurality of fins is provided where fin width is less than 11 nanometers, fin height is greater than 155 nanometers and spacing between any two neighboring fins is less than 30 nanometers and each fin is in non-collapsed state. An integrated circuit device with a substrate and a plurality of fins is provided where fin width is less than 15 nanometers, fin height is greater than 190 nanometers and spacing between any two neighboring fins is less than 30 nanometers and each fin is in non-collapsed state. A method for forming a fin-based transistor structure is provided where a plurality of fins on a substrate are pre-treated with at least one of a self-assembled monolayer, a non-polar solvent, and a surfactant. One or more of these treatments is to reduce adhesion and/or cohesive forces to prevent occurrence of fin collapse.
H01L 29/06 - Semiconductor bodies characterised by the shapes, relative sizes, or dispositions of the semiconductor regions
H01L 27/088 - Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only the components being field-effect transistors with insulated gate
H01L 21/02 - Manufacture or treatment of semiconductor devices or of parts thereof
H01L 27/02 - Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including integrated passive circuit elements with at least one potential-jump barrier or surface barrier
H01L 29/08 - Semiconductor bodies characterised by the shapes, relative sizes, or dispositions of the semiconductor regions with semiconductor regions connected to an electrode carrying current to be rectified, amplified, or switched and such electrode being part of a semiconductor device which comprises three or more electrodes
H01L 29/423 - Electrodes characterised by their shape, relative sizes or dispositions not carrying the current to be rectified, amplified or switched
One embodiment provides an apparatus. The apparatus includes a first inverter comprising a first pull up transistor and a first pull down transistor; a second inverter cross coupled to the first inverter, the second inverter comprising a second pull up transistor and a second pull down transistor; a first access transistor coupled to the first inverter; and a second access transistor coupled to the second inverter. A gate electrode of one transistor of each inverter comprises a polarization layer.
G11C 11/00 - Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
G11C 11/412 - Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming cells with positive feedback, i.e. cells not needing refreshing or charge regeneration, e.g. bistable multivibrator or Schmitt trigger using field-effect transistors only
G11C 8/16 - Multiple access memory array, e.g. addressing one storage element via at least two independent addressing line groups
H01L 27/11 - Static random access memory structures
G11C 11/22 - Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using ferroelectric elements
Embodiments of a system and method for controlling a device charging on a wireless charger are generally described herein. A method may include disabling, in response to determining that the device is currently charging on the wireless charger, haptic feedback at the device, determining whether the device is in a night mode or a day mode, in response to determining that the device is in the night mode and currently charging on the wireless charger, disabling notifications of the device, and enabling, in response to determining that the device is in the day mode, the haptic feedback and the notifications when the device has been removed from the wireless charger.
Technologies for presenting an advertisement on a media consumption device includes receiving a request to seek past a commercial included in media content played on the media consumption device, determining an advertisement based on the commercial, and presenting the advertisement to a user of the media consumption device during performance of the requested seek function. The advertisement may be, for example, an extracted frame or image of the commercial and may include a logo or phrase associated with a product or service advertised in the commercial. Similar technologies related to a media content distribution system are also disclosed.
H04N 21/2387 - Stream processing in response to a playback request from an end-user, e.g. for trick-play
H04N 21/44 - Processing of video elementary streams, e.g. splicing a video clip retrieved from local storage with an incoming video stream or rendering scenes according to MPEG-4 scene graphs
H04N 21/8549 - Creating video summaries, e.g. movie trailer
H04N 21/433 - Content storage operation, e.g. storage operation in response to a pause request or caching operations
H04N 21/4402 - Processing of video elementary streams, e.g. splicing a video clip retrieved from local storage with an incoming video stream or rendering scenes according to MPEG-4 scene graphs involving reformatting operations of video signals for household redistribution, storage or real-time display
H04N 21/234 - Processing of video elementary streams, e.g. splicing of video streams or manipulating MPEG-4 scene graphs
H04N 21/242 - Synchronization processes, e.g. processing of PCR [Program Clock References]
H04N 21/43 - Processing of content or additional data, e.g. demultiplexing additional data from a digital video stream; Elementary client operations, e.g. monitoring of home network or synchronizing decoder's clock; Client middleware
H04N 21/6587 - Control parameters, e.g. trick play commands or viewpoint selection
89.
Stair-stacked dice device in a system in package, and methods of making same
A system in package includes a stair-stacked memory module that is stacked vertically with respect to a processor die. A spacer is used adjacent to the processor die to create a bridge for the stair-stacked memory module. Each memory die in the stair-stacked memory module includes a vertical bond wire that emerges from a matrix for connection. The matrix encloses the stair-stacked memory module and at least a portion of the processor die.
H01L 25/065 - Assemblies consisting of a plurality of individual semiconductor or other solid state devices all the devices being of a type provided for in the same subgroup of groups , or in a single subclass of , , e.g. assemblies of rectifier diodes the devices not having separate containers the devices being of a type provided for in group
H01L 25/18 - Assemblies consisting of a plurality of individual semiconductor or other solid state devices the devices being of types provided for in two or more different subgroups of the same main group of groups , or in a single subclass of ,
H01L 23/00 - SEMICONDUCTOR DEVICES NOT COVERED BY CLASS - Details of semiconductor or other solid state devices
H01L 21/66 - Testing or measuring during manufacture or treatment
H01L 25/00 - Assemblies consisting of a plurality of individual semiconductor or other solid state devices
H01L 23/31 - Encapsulation, e.g. encapsulating layers, coatings characterised by the arrangement
90.
Methods and arrangements for vehicle-to-vehicle communications
Logic may implement protocols and procedures for vehicle-to-vehicle communications for platooning. Logic may implement a communications topology to distinguish time-critical communications from non-time-critical communications. Logic may sign time-critical communications with a message authentication code (MAC) algorithm with a hash function such as Keccak MAC or a Cipher-based MAC. Logic may generate a MAC based on pairwise, symmetric keys to sign the time-critical communications. Logic may sign non-time-critical communications with a digital signature. Logic may encrypt non-time-critical communications. Logic may append a certificate to non-time-critical communications. Logic may append a header to messages to create data packets and may include a packet type to identify time-critical communications. Logic may decode and verify the time-critical messages with a pairwise symmetric key. And logic may prioritize time-critical communications to meet a specified latency.
H04L 29/06 - Communication control; Communication processing characterised by a protocol
H04L 9/32 - Arrangements for secret or secure communications; Network security protocols including means for verifying the identity or authority of a user of the system
G08G 1/00 - Traffic control systems for road vehicles
H04L 9/14 - Arrangements for secret or secure communications; Network security protocols using a plurality of keys or algorithms
H04L 9/30 - Public key, i.e. encryption algorithm being computationally infeasible to invert and users' encryption keys not requiring secrecy
H04L 9/06 - Arrangements for secret or secure communications; Network security protocols the encryption apparatus using shift registers or memories for blockwise coding, e.g. D.E.S. systems
H04L 9/12 - Transmitting and receiving encryption devices synchronised or initially set up in a particular manner
H04L 101/622 - Layer-2 addresses, e.g. medium access control [MAC] addresses
Herein is disclosed a virtual embodiment display system comprising one or more image sensors, configured to receive one or more images of a vehicle occupant; one or more processors, configured to determine a gaze direction of the vehicle occupant from the one or more images; select a display location corresponding to the determined gaze direction; and control an image display device to display a virtual embodiment of an intelligent agent at the display location; the image display device, configured to display the virtual embodiment of the intelligent agent at the selected display location according to the one or more processors.
A pre-packaged stair-stacked memory module is mounted on a board with at least one additional component. A stair-stacked memory module includes a plurality of memory dice that are stacked vertically with respect to a processor die. A spacer is used adjacent to the processor die to create a bridge for the stair-stacked memory module. Each memory die in the stair-stacked memory module includes a vertical bond wire that emerges from a matrix for connection. The matrix encloses the stair-stacked memory module and at least a portion of the processor die. The matrix might also enclose the at least one additional component.
H01L 25/065 - Assemblies consisting of a plurality of individual semiconductor or other solid state devices all the devices being of a type provided for in the same subgroup of groups , or in a single subclass of , , e.g. assemblies of rectifier diodes the devices not having separate containers the devices being of a type provided for in group
H01L 25/18 - Assemblies consisting of a plurality of individual semiconductor or other solid state devices the devices being of types provided for in two or more different subgroups of the same main group of groups , or in a single subclass of ,
H01L 25/00 - Assemblies consisting of a plurality of individual semiconductor or other solid state devices
H01L 21/66 - Testing or measuring during manufacture or treatment
G01R 31/28 - Testing of electronic circuits, e.g. by signal tracer
93.
Dielectric and isolation lower fin material for fin-based electronics
A dielectric and isolation lower fin material is described that is useful for fin-based electronics. In some examples, a dielectric layer is on first and second sidewalls of a lower fin. The dielectric layer has a first upper end portion laterally adjacent to the first sidewall of the lower fin and a second upper end portion laterally adjacent to the second sidewall of the lower fin. An isolation material is laterally adjacent to the dielectric layer directly on the first and second sidewalls of the lower fin and a gate electrode is over a top of and laterally adjacent to sidewalls of an upper fin. The gate electrode is over the first and second upper end portions of the dielectric layer and the isolation material.
H01L 29/06 - Semiconductor bodies characterised by the shapes, relative sizes, or dispositions of the semiconductor regions
H01L 27/098 - Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only the components being PN junction gate field-effect transistors
Methods and apparatus are disclosed for battery current monitoring. An example apparatus includes a haptic device, an isolation switch to deliver power from a battery to the haptic device, an integrator to integrate a signal based on a current from the battery to the haptic device to generate an integrator output, and control logic to control the isolation switch based on a comparison of the integrator output to a threshold.
H02H 3/093 - Emergency protective circuit arrangements for automatic disconnection directly responsive to an undesired change from normal electric working condition, with or without subsequent reconnection responsive to excess current with timing means
H02H 3/087 - Emergency protective circuit arrangements for automatic disconnection directly responsive to an undesired change from normal electric working condition, with or without subsequent reconnection responsive to excess current for dc applications
95.
Magnetic memory devices with enhanced tunnel magnetoresistance ratio (TMR) and methods of fabrication
A memory device includes a first electrode, a conductive layer including iridium above the first electrode, a magnetic junction on the conductive layer and a second electrode above the magnetic junction. The magnetic junction includes a magnetic structure including a first magnetic layer including cobalt, a non-magnetic layer including platinum or tungsten on the first magnetic layer and a second magnetic layer including cobalt on the non-magnetic layer. The magnetic junction further includes an anti-ferromagnetic layer on the magnet structure, a fixed magnet above the anti-ferromagnetic layer, a free magnet above the fixed magnet and a tunnel barrier between the fixed magnet and the free magnet.
H01L 27/22 - Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate using similar magnetic field effects
H01L 43/02 - Devices using galvano-magnetic or similar magnetic effects; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof - Details
H01L 43/12 - Processes or apparatus specially adapted for the manufacture or treatment of these devices or of parts thereof
H01F 10/32 - Spin-exchange-coupled multilayers, e.g. nanostructured superlattices
H01F 41/34 - Apparatus or processes specially adapted for manufacturing or assembling magnets, inductances or transformers; Apparatus or processes specially adapted for manufacturing materials characterised by their magnetic properties for applying conductive, insulating or magnetic material on a magnetic film in patterns, e.g. by lithography
G11C 11/16 - Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using magnetic elements using elements in which the storage effect is based on magnetic spin effect
96.
Array imaging system having discrete camera modules and method for manufacturing the same
An array imaging apparatus having discrete camera modules is disclosed. In one embodiment, the apparatus comprises a substrate; and heterogeneous camera modules attached to the substrate and in a geometric relationship with each other, the heterogeneous camera modules having a substantially similar photometric response.
H04N 5/073 - Arrangements or circuits at the transmitter end for mutually locking plural sources of synchronising signals, e.g. studios or relay stations
Systems, devices, and techniques are provided for occupancy assessment of a vehicle. For one or more occupants of the vehicle, the occupancy assessment establishes position and/or identity for some or all of the occupant(s).
B60N 2/00 - Seats specially adapted for vehicles; Arrangement or mounting of seats in vehicles
B60R 16/037 - Electric or fluid circuits specially adapted for vehicles and not otherwise provided for; Arrangement of elements of electric or fluid circuits specially adapted for vehicles and not otherwise provided for electric for occupant comfort
98.
Cobalt based interconnects and methods of fabrication thereof
An embodiment includes a metal interconnect structure, comprising: a dielectric layer disposed on a substrate; an opening in the dielectric layer, wherein the opening has sidewalls and exposes a conductive region of at least one of the substrate and an interconnect line; an adhesive layer, comprising manganese, disposed over the conductive region and on the sidewalls; and a fill material, comprising cobalt, within the opening and on a surface of the adhesion layer. Other embodiments are described herein.
H01L 23/532 - Arrangements for conducting electric current within the device in operation from one component to another including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body characterised by the materials
H01L 21/768 - Applying interconnections to be used for carrying current between separate components within a device
H01L 29/78 - Field-effect transistors with field effect produced by an insulated gate
H01L 23/522 - Arrangements for conducting electric current within the device in operation from one component to another including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
The present description relates the formation of a first level interlayer dielectric material layer within a non-planar transistor, which may be formed by a spin-on coating technique followed by oxidation and annealing. The first level interlayer dielectric material layer may be substantially void free and may exert a tensile strain on the source/drain regions of the non-planar transistor.
Methods and apparatus relating to platform power consumption reduction via power state switching are described. In one embodiment, control logic causes a processor to enter a first low power consumption state (e.g., S0ix) instead of a second low power consumption state (e.g., S3) based on whether a threshold time period exists between a first wake event (e.g., corresponding to a first one of one or more awake requests) and a second wake event (e.g., corresponding to a second one of the one or more awake requests). Other embodiments are also claimed and disclosed.
patents