A printed circuit board (PCB) includes a plurality of stacked layers, each layer having a major plane defining a major plane of the PCB, a plurality of signal pads disposed on a signal pad layer of the PCB that is parallel to the major plane of the PCB, and a plurality of signal vias, each signal via in the plurality of signal vias having a longitudinal axis perpendicular to the major plane of the PCB, each signal via extending through the plurality of layers along the longitudinal axis, each respective signal via being electrically coupled to a respective signal pad of the plurality of signal pads, wherein at least one signal via in the plurality of signal vias includes an added capacitive structure which, along with inductance of that via, forms a corrective filter to reduce insertion loss deviation of at least one broadband signal in that via.
A search engine of a network device performs a lookup based on packet information associated with a packet being processed using a plurality of packet processing applications. The lookup includes one or more accesses to a lookup table that includes a plurality of interleaved entries associated with different ones of the packet processing applications. For each access, the search engine generates a search key to include at least a search string generated based on the packet information and an application identifier indicating a packet processing application for which the lookup is being performed, identifies an entry based on the search key, determines whether the search key matches search information in the identified entry, and when the search key matches the search information in the identified entry, identifies an action to be performed by the packet processor in connection with processing the packet by the packet processing application.
H04L 47/2441 - Traffic characterised by specific attributes, e.g. priority or QoS relying on flow classification, e.g. using integrated services [IntServ]
A processor of a network device receives i) a timing message and ii) a control header corresponding to the timing message. The control header includes information that indicates a timestamping method for communicating timing information corresponding to transmission of the timing message by the network device. The timestamping method is selected from a set of multiple timestamping methods that includes: i) a one-step timestamping method, and ii) a two- step timestamping method. The processor determines whether the two-step timing timestamping method is to be performed based on analyzing the information in the control header. The network device transmits the timing message within a first packet and determines timing information corresponding to the transmission of the first packet. In response to determining that the timestamping method is the two-step method, the processor stores the timing information in a memory for subsequent inclusion in a second packet that is to be subsequently transmitted.
Timestamp circuitry of a network device modifies a packet by embedding a future timestamp in the packet to generate a timestamped packet. The future timestamp corresponds to a transmit time that occurs after the timestamp circuitry embeds the future timestamp in the packet. The timing information is added to the packet and the packet is then transferred to transmitter circuitry of the network device via a communication link, internal to the network device, that operates according to a media independent communication interface. Time gating circuitry of the transmitter circuitry i) holds the timestamped packet from proceeding to a network link coupled to the network device prior to a current time reaching the transmit time, and ii) releases the timestamped packet for transmission via the network link in response to the current time reaching the transmit time.
In a network switching system that comprises a plurality of interconnected network devices, a first network device transmits one or more first packets via a first network interface of the first network device, the one or more first packets belonging to a packet flow. The first network device receives a message that indicates congestion corresponding to the packet flow within the network switching system. In response to the message, the first network device selects a second network interface of the first network device for transmitting one or more second packets that belong to the packet flow. After receiving the message, the first network device transmits the one or more second packets via the second network interface of the first network device.
A network device includes a plurality of network interfaces configured to couple with a plurality of physical network links. A packet processor is configured to process packets received via the plurality of network interfaces. The packet processor includes a path selection engine that is configured to: for each of at least some packets processed by the packet processor, successively make path selection decisions that correspond to respective routing domains within a hierarchical communication network, the path selection decisions for forwarding the packet through the hierarchical communication network.
A network device transfers packets from a packet memory to one or more network interfaces for transmission by the one or more network interfaces. The transferring of packets includes transferring the packets via one or more respective transmit data paths that correspond to one or more respective network interfaces. The network device measures one or more respective amounts of time required to transmit respective packet data within the one or more respective transmit data paths. The network device uses the one or more respective measured amounts of time to determine when to start transfer of packets from the packet memory to the one or more network interfaces via the one or more respective transmit data paths.
G06F 5/06 - Methods or arrangements for data conversion without changing the order or content of the data handled for changing the speed of data flow, i.e. speed regularising
A network device includes a first queue for queueing express packets and a second queue for queueing preemptable packets that are to be transmitted via a network interface of the network device. The network device also includes a transmit controller that receives a packet directed to the first queue and determines whether the packet is a type of packet that requires transmission at a specific transmit time from the network interface of the network device. In response to determining that the packet is a type of packet that requires transmission at a specific transmit time, the transmit controller suspends an ongoing transmission of a preemptable packet from the second queue that would prevent transmission of the packet from the first queue at the specific transmit time via the network interface and causes the packet in the first queue to be transmitted at the specific transmit time via the network interface.
A packet is received via a first network interface of a first network device in an underlay network, the packet having been originated by a first endpoint device and including a first network address indicating a destination of the first packet. The first network device, without analyzing the first network address in the first packet, adds, to the first packet, a second network address corresponding to a cloud edge network device implemented at the cloud edge and information identifying the first network interface via which the first packet was received by the first network device. The first network device transmits the packet, via an overlay network layered over the underlay network, to the cloud edge network device to enable forwarding of the packet to the destination of the packet, based on the first network address included in the packet, by the cloud edge network device
A network device provides a search key corresponding to a packet to a TCAM. The TCAM determines that the search key matches one or more search patterns stored in the TCAM. The network device selects one search pattern among the one or more search patterns at least by analyzing respective priority information associated with the one or more search patterns. The respective priority information indicates one or more respective priority levels that are independent from one or more physical locations of the one or more search patterns within the TCAM. In connection with selecting the one search pattern, the network device determines one or more actions to be performed on the packet by the network device, the one or more actions corresponding to the selected one search pattern.
A packet processor of a network device repeatedly determines a fill level of a forwarding table that is populated with associations between network addresses and network interfaces of, or coupled to, the network device. The packet processor adjusts, based on the fill level of the forwarding table, a maximum rate according to which the packet processor is permitted to send messages to a central processing unit (CPU) coupled to the packet processor, the messages indicating network addresses that are to be stored in the forwarding table by the CPU. The packet processor of the network device receives packets via network links coupled to the network device; identifies new network addresses of the packets that are not in the forwarding table; and sends messages to the CPU at a rate that does not exceed the maximum rate, the messages indicating the new network addresses are to be added to the forwarding table.
A packet group processor of a network device defines groups of packets among packets that are being processed by the network device, each of at least some of the groups of packets defining a respective group of at least two different packets. Each group includes one or more packets to be transmitted via a respective same network interface. A transmit processor makes a single transmit decision that a particular group of at least two packets is to be transmitted via a corresponding network interface, and in response to the single transmit decision, transfers the particular group of at least two packets to the corresponding network interface for transmission.
An anomaly detection apparatus for detecting anomalies in network traffic includes a statistics generator that receives characteristics of packets in network traffic and to generate statistics for the network traffic. The statistics include distribution statistics regarding respective distributions of respective characteristics of packets in the network traffic over time. An anomaly detection processor detects deviations in the distribution statistics as compared to distribution statistics for normal network traffic and detects anomalies regarding the network traffic based on the deviations in the distribution statistics as compared to distribution statistics for the normal network traffic.
Schedules that indicate when time gates of a network device are to permit transfer of packet data are stored in a memory. Control circuitry repeatedly identifies initial positions in the schedules corresponding to times when the schedules are accessed in a background procedure. The control circuitry uses the identified initial positions to identify updated positions in the schedules that correspond to events when control of the time gates is needed, and uses scheduling information at the updated positions in the schedules to selectively transfer packet data to components of the network device using the time gates.
A network device includes a rate measurement circuit that is configured to measure respective egress rates at which respective data is being transmitted via respective ports associated with the network device. A marking ratio determination circuit is configured to select respective marking ratios based on respective measured egress rates, the marking ratios for marking packets to be transmitted via the respective ports to indicate respective levels of congestion corresponding to the respective ports. Different marking ratios correspond to different measured egress rates. A packet editor circuit is configured to mark selected packets to be transmitted via respective ports according to the respective selected marking ratios. The respective selected marking ratios indicate to other communication devices that respective network paths via which the selected packets travelled experienced congestion, and the respective marking ratios indicate respective levels of congestion.
A media access control (MAC) processor of a network device receives a timing packet to be transmitted by the network device. The MAC processor generates one or more indicators to be used by a PHY device of the network device for embedding timing information into the timing packet. The one or more indicators include at least an indicator indicating that the timing packet is a type of packet into which timing information is to be embedded, an indicator of a location of a field in the timing packet at which the timing information is to be embedded, and an indicator of whether timing information in the timing packet needs to be updated. The MAC processor transfers the timing packet and the one or more indicators to the PHY device for further processing of the timing packet and subsequent transmission of the timing packet from the network device.
Packets to be transmitted from a network device are buffered in queues in a first packet memory. In response to detecting congestion in a queue in the first packet memory, groups of multiple packets are transferred from the first packet memory to a second packet memory, the second packet memory configured to buffer a portion of traffic bandwidth supported by the network device. Prior to transmission of the packets among the one or more groups of multiple packets from the network device, packets among the one or more groups of multiple packets are transferred from the second packet memory back to the first packet memory. The packets transferred from the second packet memory back to the first packet memory are retrieved from the first packet memory and are forwarded to one or more network ports for transmission of the packets from the network device.
A packet processor of a network device includes a forwarding engine that is configured to determine egress network interfaces via which packets received by the network device are to be transmitted. The packet processor also includes a header parser configured to parse header information in the packets received by the network device. The header parser includes a first parsing circuit that is configured to parse a first portion of a header of a packet and to prompt a programmable second parsing circuit to parse a second portion of the header. The first portion of the header has a header structure known to the first parsing circuit. The programmable second parsing circuit includes configurable circuitry and a memory to store control information that controls operation of the configurable circuitry to parse the second portion of the header.
A printed circuit board (PCB) system includes a first printed circuit board (PCB), an integrated circuit (IC) package, and a memory module. The IC package includes i) a package substrate, ii) a main IC chip that is electrically coupled to a top surface of the package substrate, iii) first contact structures that are disposed on a bottom surface of the package substrate and that are electrically coupled to the first PCB, and iv) second contact structures that are disposed on a top surface of the package substrate. The memory module includes i) a second PCB, ii) one or more memory IC chips that are disposed on the second PCB, and iii) third contact structures that are disposed on a bottom surface of the second PCB. An interposer electrically couples the second contact structures of the IC package with the third contact structures of the memory module.
H05K 1/14 - Structural association of two or more printed circuits
H05K 1/18 - Printed circuits structurally associated with non-printed electric components
H05K 3/34 - Assembling printed circuits with electric components, e.g. with resistor electrically connecting electric components or wires to printed circuits by soldering
H05K 3/36 - Assembling printed circuits with other printed circuits
20.
EXACT MATCH AND TERNARY CONTENT ADDRESSABLE MEMORY (TCAM) HYBRID LOOKUP FOR NETWORK DEVICE
In a network device, a hash calculator generates a lookup hash value from data fields associated with a packet received by the network device. A compressed lookup key generator generates a compressed lookup key for the packet using the lookup hash value. A content addressable memory (CAM) stores compressed patterns corresponding to compressed lookup keys, uses the compressed lookup key received from the compressed lookup key generator to determine if the received compressed lookup key matches any stored compressed patterns, and outputs an index corresponding to a stored compressed pattern that matches the compressed lookup key. A memory stores uncompressed patterns corresponding to the compressed patterns stored in the CAM, and retrieves an uncompressed pattern using the index output by the CAM. A comparator generate a signal that indicates whether the uncompressed pattern retrieved from the memory matches the data fields associated with the packet.
A method for scan chain testing a multi-chip module including a plurality of integrated circuit dice, some of the integrated circuit dice being of a first type and some of the integrated circuit dice being of a second type, includes separately applying a first boundary scan test stream to each die of the first type, and a second boundary scan test stream to each die of the second type. Testing apparatus includes a test interface that couples to each respective test access port, and a controller configured to separately apply the first boundary scan test stream to each die of the first type, and the second boundary scan test stream to each die of the second type, A multi-chip module includes a plurality of integrated circuit dice, each having a boundary scan register chain with a test access port, and a test access port for the module as a whole.
A network device processes received packets at least to determine port or ports of the network device via which to transmit the packet. The network device also classifies the packets into packet flows, the packet flows being further categorized into traffic pattern categories characteristic of traffic pattern characteristics of the packet flows. The network device buffers, according to the traffic pattern categories of the packet flows, packets that belong to the packet flows in a first packet memory or in a second packet memory, the first packet memory having a memory access bandwidth different from a memory access bandwidth of the second packet memory. After processing the packets, the network device retrieves the packets from the first packet memory or the second packet memory in which the packets are buffered, and forwards the packets to the determined one or more ports for transmission of the packets.
A switching system comprises a controlling switch and a plurality of port extenders. One of the port extenders includes: at least one upstream port; multiple downstream ports; and a forwarding engine. A forwarding database is populated with entries indicating associations between i) respective network addresses corresponding to devices coupled to downstream ports, and ii) respective local downstream ports. The forwarding database excludes entries corresponding to network addresses corresponding to devices coupled to the at least one upstream port. The forwarding engine is configured to: for a first packet received via one of the local downstream ports, and having a destination network address in the forwarding database, forward the first packet to a different local downstream port indicated by the forwarding database. For a second packet received via one of the local downstream ports, and having a destination network address not in the forwarding database, forward the second packet to the at least one upstream port.
A first memory device stores (i) a head part of a FIFO queue structured as a linked list (LL) of LL elements arranged in an order in which the LL elements were added to the FIFO queue and (ii) a tail part of the FIFO queue. A second memory device stores a middle part of the FIFO queue, the middle part comprising a LL elements following, in an order, the head part and preceding, in the order, the tail part. A queue controller retrieves LL elements in the head part from the first memory device, moves LL elements in the middle part from the second memory device to the head part in the first memory device prior to the head part becoming empty, and updates LL parameters corresponding to the moved LL elements to indicate storage of the moved LL elements changing from the second memory device to the first memory device.
H04L 12/28 - Data switching networks characterised by path configuration, e.g. LAN [Local Area Networks] or WAN [Wide Area Networks]
H04L 12/861 - Packet buffering or queuing arrangements; Queue scheduling
G06F 3/06 - Digital input from, or digital output to, record carriers
G06F 5/10 - Methods or arrangements for data conversion without changing the order or content of the data handled for changing the speed of data flow, i.e. speed regularising having a sequence of storage locations each being individually accessible for both enqueue and dequeue operations, e.g. using random access memory
A first network device forwards a plurality of packets to the one or more network ports for transmission to a second network device, wherein ones of the packets include a field for indicating different, independent types of information. A field populator is configured to, for each of at least some packets among the plurality of packets: determine, from a set of different, independent types of information, a type of information to be included in the field of the packet according to a schedule known by the second network device, and populate the field in the packet only with data according to the type of information determined according to the schedule.
A network device comprises time measurement units configured to measure receipt times and transmit times of packets received/transmitted via network interfaces. One or more memories store configuration information that indicates certain network interface pairs and/or certain packet flows that are enabled for latency measurement. A packet processor includes a latency monitoring trigger unit configured to select, using the configuration information, packets that are forwarded between the certain network interface pairs and/or that belong to the certain packet flows for latency monitoring. One or more latency measurement units determine respective latencies for packets selected by the latency monitoring trigger unit using respective receipt times and respective transmit times for the packets selected by the latency monitoring trigger unit, calculates latency statistics for the certain network interface pairs and/or the certain packet flows using the respective latencies, and stores the latency statistics in the one or more memories.
A network device receives a packet is received from a network, and determines at least one port, among a plurality of ports of the network device, via which the packet is to be transmitted. The network device also determines an amount of free buffer space in a buffer memory of the network device, and dynamically determines, based at least in part on the amount of free buffer space, respective thresholds for triggering ones of multiple traffic management operations to be performed based on the packet. Using the respective thresholds, the network device determines whether or not to trigger ones of the multiple traffic management operations with respect to the packet. The network device performs one or more of the traffic management operations with respect to the packet determined to be triggered based on the corresponding one of the respective thresholds.
A packet received by a network device via a network. A first portion of the packet is stored in a packet memory, the first portion including at least a payload of the packet. The packet is processed based on information from a header of the packet. After the packet is processed, a second portion of the packet is stored in the packet memory, the second portion including at least a portion of the header of the packet. When the packet is to be transmitted the first portion of the packet and the second portion of the packet are retrieved from the packet memory, and the first portion and the second portion are combined to generate a transmit packet. The transmit packet is forwarded to a port of the network device for transmission of the transmit packet via port of the network device.
A packet is received by a network device. The packet is processed and at least one egress port via which the packet is to be transmitted is determined. A header of the packet is modified, based on information determined for the packet during processing of the packet, to generate a modified header. Egress classification is performed based at least in part on the modified header. Egress classification includes determining whether the packet is to be discarded by the network device. When it is determined that the packet is not to be discarded by the network device, a copy of the packet is generated for mirroring the packet to a destination other than the determined at least one egress port. The packet is then enqueued in an egress queue corresponding to the determined at least one egress port. The packet is subsequently transferred to the determined at least one egress port.
A switching system includes a port extender device coupled to a central switching device. Packets processed by the central switching device are forwarded to the port extender device and enqueued in ones of a plurality of egress queues in the port extender device for transmission of the packets via the front ports of the port extender device. Respective egress queues in the port extender device have a queue depth that is less than a queue depth of corresponding respective egress queues in the central switching device. A flow control message indicative of congestion in a particular egress queue of the port extender device is generated and transmitted to the central switch device to control transmission of packets from the central switching device to the particular egress queue of the port extender device.
A memory supports a write or multiple read operations in any given clock cycle. In a first clock cycle, new content data is written to a particular content memory bank among a set of content memory banks. Also in the first clock cycle, current content data is read from corresponding locations in one or more other content memory banks among the set of content memory banks. New parity data is generated based on the new content data written to the particular content memory bank and the current content data read from the one or more other content memory banks. The new parity data is written to a cache memory associated with the one or more parity banks. In a second clock cycle subsequent to the first clock cycle, the new parity data is transferred from the cache memory to one of the one or more parity memory banks.
A forwarding engine in a network device selects one or more groups of multiple egress interfaces of the network device for forwarding packets received by the network device. An egress interface selector in the network device selects individual egress interfaces within the one or more groups selected by the forwarding engine. The egress interface selector includes a table associated with a first group of multiple egress interfaces, wherein elements in the table include values indicate individual egress interfaces in the first group. When the forwarding engine selects the first group, a table element selector of selects an element in the table to identify the individual egress interface for forwarding the packet.
H04L 12/707 - Route fault prevention or recovery, e.g. rerouting, route redundancy, virtual router redundancy protocol [VRRP] or hot standby router protocol [HSRP] using path redundancy
H04L 12/709 - Route fault prevention or recovery, e.g. rerouting, route redundancy, virtual router redundancy protocol [VRRP] or hot standby router protocol [HSRP] using path redundancy using M+N parallel active paths
H04L 12/703 - Route fault prevention or recovery, e.g. rerouting, route redundancy, virtual router redundancy protocol [VRRP] or hot standby router protocol [HSRP]
H04L 12/939 - Provisions for redundant switching, e.g. using parallel switching planes
33.
SYSTEM AND METHOD FOR PERFORMING SIMULTANEOUS READ AND WRITE OPERATIONS IN MEMORY
A memory comprises a set of content memory banks, a parity memory bank, and a register corresponding to the parity memory bank. A first memory interface device is configured to, in response to receiving a write request to write to the set of content memory banks, perform a write operation over multiple clock cycles including temporarily storing parity information corresponding to the write request in the register before the parity information is written to the parity memory bank. A second memory interface device is configured to: in response to i) receiving a read request to read data from a memory bank in the set of content memory banks, and ii) determining that information responsive to the read request is to be reconstructed using parity information, and selectively use information from either i) the register or ii) the parity memory bank, to reconstruct information responsive to the read request.
Aspects of the disclosure provide a method for counting packets and bytes in a distributed packet-switched system. The method includes receiving a packet stream having at least one packet flow at a device of a packet-switched system having a plurality of distributed devices, statistically determining whether to update a designated device based on receipt of a packet belonging to the packet flow, and transmitting packet counting information to the designated device based on the statistical determination, where the designated device counts packets of the packet flow based on the packet counting information.
Header information is extracted from a received packet by a data path portion of a network device. The data path portion is configured to buffer a data portion of received packets until the received packets are ready for transmission from the network device. The data path portion determines a first classification identifier for the received packet based on the header information. The data path portion determines a congestion state of the data path portion. The congestion state indicates a received packet rate of the first data path portion that exceeds a packet handling rate of a control path portion of the network device. The data path portion discards the first packet if the congestion state meets a discard threshold associated with the first classification identifier.
Aspects of the disclosure provide an integrated circuit (IC) (120). The IC includes a clock generation and supply voltage monitoring circuit (221) configured to monitor a supply voltage to the IC and selectively modify an operating frequency of the IC in response to a sensed change in the supply voltage. The IC further includes a frequency comparing and compensating circuit (224) configured to output a control signal, based on the operating frequency, to a voltage supply to modify the supply voltage so as to compensate for changes in the operating frequency and return the operating frequency to a target operating frequency.
In a method for processing packets in a network device, a first packet is received at a first port of the network device. A first set of bits, corresponding to a first set of bit locations in a header of the first packet, is extracted from the header of the first packet. A first set of processing operations is performed to process the first packet using the first set of bits. A second packet is received at a second port of the network device. A second set of bits, corresponding to a second set of bit locations in a header of the second packet, is extracted from the header of the second packet. A second set of processing operations is performed to process the second packet using the second set of bits.
In a method for performing an exact match lookup in a network device, a network packet is received at the network device. A lookup key for the network packet is determined at least based on data included in a header of the received network packet. A hash function is selected, from among a plurality of possible hash functions, at least based on a size of the lookup key, and a hash operation is performed on the lookup key using the selected hash function to compute a hashed lookup key segment. A database is queried using the hashed lookup key segment to extract a value exactly corresponding to the lookup key.
A plurality of packets that belong to a data flow are received (402) and are distributed (404) to two or more packet processing elements, wherein a packet is sent to a first packet processing element. A first instance of the packet is queued (408) at a first packet processing element according to an order of the packet within the data flow. The first instance of the packet is caused to be transmitted when processing of the first instance is completed and the first instance of the packet is at a head of a queue at the first ordering unit. A second instance of the packet is queued at a second ordering unit. The second instance of the packet is caused to be transmitted when processing of the second instance is completed and the second instance of the packet is at a head of a queue (414) at the second ordering unit.
A plurality of packets are received by a packet processing device (402), and the packets are distributed among two or more packet processing node elements (404) for processing of the packets. The packets are assigned to respective packet classes (406), each class corresponding to a group of packets for which an order in which the packets were received is to be preserved. The packets are queued in respective queues (408) corresponding to the assigned packet classes and according to an order in which the packets were received by the packet processing device. The packet processing node elements issue (410) respective instructions indicative of processing actions to be performed with respect to the packets, and indications of at least some of the processing actions are stored (412). A processing action with respect to a packet is performed (414) when the packet has reached a head of a queue corresponding to the class associated with the packet.
Systems and methods are provided for a network device. A device includes a plurality of packet processing clients. The device further includes a plurality of memories, where a quantity of the memories is greater than a quantity of the packet processing clients, each of the memories storing a replica of data, the packet processing clients being configured to selectively read the control data from any of the memories. An arbiter is configured to select in a first clock cycle for the plurality of packet processing clients a first subset of memories from among the plurality of memories from which to read the conirol data, and in a second clock cycle, subsequent to the first clock cycle, to select for the plurality of packet processing clients a second subset of memories from among the plurality of -memories from which to read the control data.
A network device includes one or more ports coupled to a network, and a time synchronization module. The time synchronization module processes (i) respective path information, and (ii) respective time synchronization information included in each of at least some of a plurality of time synchronization packets received from a master clock device over two or more different communication paths and via at least one of the one or more ports, wherein the respective path information indicates a respective communication path in the network via which the respective time synchronization packet was received. The time synchronization module determines a system time clock responsive to the processing of the path information and the time synchronization information included in the at least some of the plurality of time synchronization packets.
In a network device communicatively coupled to a master clock via a plurality of different communication paths, a clock synchronization module is configured to determine a plurality of path time data sets corresponding to the plurality of different communication paths based on signals received from the master clock via the plurality of different communication paths between the network device and the master clock. A clock module is configured to determine a time of day as a function of the plurality of path time data sets.
There is provided a network device disposed at an interface between an access segment and an interconnecting layer of a data center. The network device includes an address resolution processor configured to receive an address request addressed to virtual machines in a transmission domain of the network device. The address request specifying a source layer 2 address, requesting a layer 2 address of a target virtual machine in the data center, and specifying a layer 3 address of the target virtual machine. The network device is further configured to transmit a local message over the first access segment requesting the respective layer 2 address of a virtual machine which has the specified layer 3 address. In response to receiving a reply, the network device transmits a message to the specified source layer 2 address to provide the layer 2 address of the network device and the specified layer 3 address.
A device in a server having a processor and a storage. The device has a downstream communication unit configured to receive a data packet. The device also has a protocol blind network path indication unit configured to obtain an indicator corresponding to a predetermined path to a data communication unit in the network using a destination address of the data packet. The device, furthermore, has an upstream communication unit configured to transmit a network protocol blind packet including the data packet and the indicator corresponding to the predetermined data path to the data communication unit in the network. The device also includes a combiner configured to bind the indicator to the data packet received by the downstream communication unit. The device also includes a protocol blind correlation storage unit configured to provide information related to target addresses and indicators corresponding to a plurality of predetermined data paths in the network. The protocol blind network path indication unit obtains the indicator corresponding to a predetermined path by accessing the protocol blind correlation structure.
In network device, a plurality of ports is configured to receive and to transmit packets on a network. A packet processing pipeline includes a plurality of hardware stages, wherein at least one hardware stage is configured to output a data structure comprising a field extracted from a received packet based on a first packet processing operation performed on the packet or the data structure, wherein the data structure is associated with the packet. Λ configurable processor is coupled to the at least one hardware stage of the packet processing pipeline. The configurable processor is configured to modify the field in the data structure to generate a modified data structure and to pass the modified data structure to a subsequent hardware stage that is configured to perform a second packet processing operation on the data structure using the field modified by the configurable processor.
In a memory device having a set of memory banks to store content data, at least two requests to perform respective memory operations in a first memory bank in the set of memory banks are received during a single clock cycle. It is determined that one or more of the at least two requests is blocked from accessing the first memory bank. In response to determining that the one or more of the at least two requests is blocked: redundancy data associated with the first memory bank and different from content data stored in the first memory bank is accessed, and, without accessing the first memory bank, at least a portion of the content data stored in the first memory bank is reconstructed based on the redundancy data associated with the first memory bank. A first requested memory operation is perfomied using the content data stored in the first memory bank, and a second requested memory operation is performed using content data reconstructed 1 ) without accessing the first memory bank and ii) based on the redundancy data associated with the first memory bank.
Systems and methods are provided for a first-in-first-out buffer. A buffer includes a first sub-buffer configured to store data received from a buffer input, and a second sub-buffer. The second sub-buffer is configured to store data received from either the buffer input or the first sub-buffer and to output data to a buffer output in a same order as that data is received at the buffer input. Buffer control logic is configured to selectively route data from the buffer input or the first sub-buffer to the second sub-buffer so that data received at the buffer input is available to be output from the second sub-buffer in a first-in-first-out manner.
G06F 5/16 - Multiplexed systems, i.e. using two or more similar devices which are alternately accessed for enqueue and dequeue operations, e.g. ping-pong buffers
Aspects of the disclosure provide a dongle device for providing services at a network device, such as a gateway device. The dongle device includes a connector configured to connect the dongle device to a network device that performs packet switching in and out of a network and/or within the network. The connector has a power pin configured to receive a power supply from the network device to power up the dongle device, and a data pin configured to enable the dongle device to communicate with the network device. The dongle device further includes a processor configured to provide a service in the network after the dongle device is powered up.
Methods and systems for implementing virtual processors are disclosed. For example, in an embodiment a processing apparatus configured to act as a plurality of virtual processors includes a first virtual program space that includes a first program execution memory, the first program execution memory including code to run a non-real-time operating system capable of supporting a one or more non-real-time applications, a second virtual program space that includes a second program execution memory, the second program execution memory including code to run one or more real-time processes, and a central processing unit (CPU) configured to operate in a first operating mode and a second operating mode, the CPU being configured to perform operating system and application activities using the first virtual program space for the first operating mode without using the second virtual program space and without appreciably interfering with the one or more real-time processes that are running in the second operating mode.
Aspects of the disclosure provide an integrated circuit (IC) that is configured to have an increased yield. The IC includes a memory element configured to store a specific value determined based on a characteristic of the IC, and a controller configured to control an input regulator based on the specific value of the IC. The input regulator is operative to provide a regulated input to the IC during operation, such that the IC performance satisfies performance requirement.
Aspects of the disclosure can provide a method and an apparatus to decode a data stream based on multiple transmissions with efficient usages of storage and power resources. The method for decoding can include receiving a first plurality of encoded code blocks corresponding to a first transmission of a transport block, decoding the first plurality of encoded code blocks into decoded code blocks, error detecting the decoded code blocks, and storing a decoding history of the decoded code blocks. Further, the method can include receiving a second plurality of encoded code blocks corresponding to a retransmission of the transport block. The second plurality of encoded code blocks can map the first plurality of encoded code blocks, respectively. The method can selectively decode a subset of the second plurality of encoded code blocks based on the decoding history. In addition, the method can include storing soft bits for code blocks that failed decoding. The soft bits can be a combination of soft bits from multiple transmissions. The memory size for storing the soft bits can be reduced by dynamically freeing memory space associated with successfully decoded code blocks.
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