A source switching device in a switching system receives information measured by a target switching device in the switching system. The information is indicative of an amount of data received in a given amount of time by the target switching device via each of two or more first links coupled to the target switching device. The source switching device determines, based at least in part on the information received from the target device, a path, from among multiple paths from the source switching device to the target switching device, for transmission of a packet flow directed to the target switching device. The source switching device transmits, via the determined path for transmission of the packet flow to the target device, one or more packets belonging to the packet flow.
A network device includes a receive processor configured to store, in a packet memory, a payload of a packet received from a communication network. The network device also includes a packet processor configured to modify one or more fields of a header of the packet to generate a modified header, perform egress classification of the packet based on the modified header, and store the modified header in the packet memory. The network device further includes a transmit processor configured to transmit the packet in accordance with the egress classification. The transmit processor is configured to, in response to a decision that the packet is to be transmitted from the network device, generate a transmit packet from the payload retrieved from the packet memory and the modified header retrieved from the packet memory and cause the transmit packet to be transmitted to a destination in the communication network.
H04L 47/2441 - Traffic characterised by specific attributes, e.g. priority or QoS relying on flow classification, e.g. using integrated services [IntServ]
H04L 47/32 - Flow control; Congestion control by discarding or delaying data units, e.g. packets or frames
A physical layer (PHY) processor of a network device receives: a timing packet that includes initial timing information, and one or more indicators of one or more parameters to be used by the PHY processor for embedding timing information into the timing packet, the one or more indicators including at least i) an indicator indicating that the timing packet is a type of packet into which timing information is to be embedded by the PHY device, ii) an indicator of a location of a field in the timing packet at which the timing information is to be embedded into the timing packet by the PHY device, and iii) an indicator of whether timing information in the timing packet needs to be updated by the PHY device. The PHY processor updates, based on the one or more indicators, the initial timing information in the timing packet.
An integrated circuit package, including a circuit board, signal pins extending orthogonally to the circuit board surface, and grouped into a plurality of differential signal pin pairs, each signal pin pair positioned at a vertex of an array of orthogonal rows and columns, wherein each signal pin pair includes a positive and a negative signal pin. The plurality of signal pin pairs includes a first subset of signal pin pairs wherein the positive and the negative signal pins are arranged in an orientation along a line parallel to rows of the array and a second subset of signal pin pairs in which the positive and the negative signal pins are arranged in an orientation along a line parallel to columns of the array. For each signal pin pair in one of the first and second subsets, each nearest signal pin pairs belong to another of the first and second subsets.
H05K 3/40 - Forming printed elements for providing electric connections to or between printed circuits
H01L 23/50 - Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads or terminal arrangements for integrated circuit devices
5.
PRINTED CIRCUIT BOARD VIA STRUCTURES WITH REDUCED INSERTION LOSS DISTORTION
A printed circuit board (PCB) includes a plurality of stacked layers, each layer having a major plane defining a major plane of the PCB, a plurality of signal pads disposed on a signal pad layer of the PCB that is parallel to the major plane of the PCB, and a plurality of signal vias, each signal via in the plurality of signal vias having a longitudinal axis perpendicular to the major plane of the PCB, each signal via extending through the plurality of layers along the longitudinal axis, each respective signal via being electrically coupled to a respective signal pad of the plurality of signal pads, wherein at least one signal via in the plurality of signal vias includes an added capacitive structure which, along with inductance of that via, forms a corrective filter to reduce insertion loss deviation of at least one broadband signal in that via.
A printed circuit board (PCB) includes a plurality of stacked layers, each layer having a major plane defining a major plane of the PCB, a plurality of signal pads disposed on a signal pad layer of the PCB that is parallel to the major plane of the PCB, and a plurality of signal vias, each signal via in the plurality of signal vias having a longitudinal axis perpendicular to the major plane of the PCB, each signal via extending through the plurality of layers along the longitudinal axis, each respective signal via being electrically coupled to a respective signal pad of the plurality of signal pads, wherein at least one signal via in the plurality of signal vias includes an added capacitive structure which, along with inductance of that via, forms a corrective filter to reduce insertion loss deviation of at least one broadband signal in that via.
A search engine of a network device performs a lookup based on packet information associated with a packet being processed using a plurality of packet processing applications. The lookup includes one or more accesses to a lookup table that includes a plurality of interleaved entries associated with different ones of the packet processing applications. For each access, the search engine generates a search key to include at least a search string generated based on the packet information and an application identifier indicating a packet processing application for which the lookup is being performed, identifies an entry based on the search key, determines whether the search key matches search information in the identified entry, and when the search key matches the search information in the identified entry, identifies an action to be performed by the packet processor in connection with processing the packet by the packet processing application.
A search engine of a network device performs a lookup based on packet information associated with a packet being processed using a plurality of packet processing applications. The lookup includes one or more accesses to a lookup table that includes a plurality of interleaved entries associated with different ones of the packet processing applications. For each access, the search engine generates a search key to include at least a search string generated based on the packet information and an application identifier indicating a packet processing application for which the lookup is being performed, identifies an entry based on the search key, determines whether the search key matches search information in the identified entry, and when the search key matches the search information in the identified entry, identifies an action to be performed by the packet processor in connection with processing the packet by the packet processing application.
H04L 47/2441 - Traffic characterised by specific attributes, e.g. priority or QoS relying on flow classification, e.g. using integrated services [IntServ]
An integrated circuit (IC) is manufactured and is mounted in an IC package. A processor of a measurement system determines a reference value of a physical layer (PHY) parameter at a second test point on a test fixture based on one or more model values, specified by an Ethernet communication standard, corresponding to a first test point on the test fixture corresponding to a contact on the IC package and one or more measured test fixture parameters characterizing a channel connecting the first test point to the second test point on the test fixture. The processor then determines whether the PHY parameter at the first test point on the IC package complies with the Ethernet communication standard based on i) the reference value of the PHY parameter and ii) a measured value of the PHY parameter obtained from a measurement of the PHY parameter at the second test point.
H01L 21/67 - Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components
G01R 31/28 - Testing of electronic circuits, e.g. by signal tracer
10.
DYNAMIC ONE-STEP/TWO-STEP TIMESTAMPING PER PACKET IN NETWORK DEVICES
A processor of a network device receives i) a timing message and ii) a control header corresponding to the timing message. The control header includes information that indicates a timestamping method for communicating timing information corresponding to transmission of the timing message by the network device. The timestamping method is selected from a set of multiple timestamping methods that includes: i) a one-step timestamping method, and ii) a two- step timestamping method. The processor determines whether the two-step timing timestamping method is to be performed based on analyzing the information in the control header. The network device transmits the timing message within a first packet and determines timing information corresponding to the transmission of the first packet. In response to determining that the timestamping method is the two-step method, the processor stores the timing information in a memory for subsequent inclusion in a second packet that is to be subsequently transmitted.
Timestamp circuitry of a network device modifies a packet by embedding a future timestamp in the packet to generate a timestamped packet. The future timestamp corresponds to a transmit time that occurs after the timestamp circuitry embeds the future timestamp in the packet. The timing information is added to the packet and the packet is then transferred to transmitter circuitry of the network device via a communication link, internal to the network device, that operates according to a media independent communication interface. Time gating circuitry of the transmitter circuitry i) holds the timestamped packet from proceeding to a network link coupled to the network device prior to a current time reaching the transmit time, and ii) releases the timestamped packet for transmission via the network link in response to the current time reaching the transmit time.
In a network switching system that comprises a plurality of interconnected network devices, a first network device transmits one or more first packets via a first network interface of the first network device, the one or more first packets belonging to a packet flow. The first network device receives a message that indicates congestion corresponding to the packet flow within the network switching system. In response to the message, the first network device selects a second network interface of the first network device for transmitting one or more second packets that belong to the packet flow. After receiving the message, the first network device transmits the one or more second packets via the second network interface of the first network device.
Electronic apparatus includes functional circuitry configured to respond to requests from a plurality of client devices, data storage circuitry configured as a plurality of client queues in which each respective client queue is configured to store pending requests from a respective client device, priority determination circuitry configured to assign a respective priority level to each respective client queue based at least in part on requests stored in the respective client queues, and arbiter circuitry configured to control access to the functional circuitry by the plurality of client devices. The arbiter circuitry is configured to monitor the priority level of each respective client queue, and control passage of requests from client queues to the functional circuitry based at least in part on a respective priority level assigned to each respective client queue. The priority determination circuitry includes fill level detector circuitry configured to determine a fill level of each client queue.
A network device determines whether a one-step timestamping method or a two-step timestamping method is to be used for transmission of a first packet. A first processor of the network device transfers to a second processor of the network device, i) a timing message to be included in the first packet, and ii) information that indicates the determined timestamping method. In response to the information from the first processor indicating that the one-step timestamping method is to be used, the second processor transmits the first packet with timing information embedded in the first packet. In response to the information from the first processor indicating that the two-step timestamping method is to be used, the second processor stores the timing information in a memory of the network device for subsequent inclusion in a second packet that is to be transmitted after transmitting the first packet, and transmits the first packet.
A processor of a network device receives i) a timing message and ii) a control header corresponding to the timing message. The control header includes information that indicates a timestamping method for communicating timing information corresponding to transmission of the timing message by the network device. The timestamping method is selected from a set of multiple timestamping methods that includes: i) a one-step timestamping method, and ii) a two-step timestamping method. The processor determines whether the two-step timing timestamping method is to be performed based on analyzing the information in the control header. The network device transmits the timing message within a first packet and determines timing information corresponding to the transmission of the first packet. In response to determining that the timestamping method is the two-step method, the processor stores the timing information in a memory for subsequent inclusion in a second packet that is to be subsequently transmitted.
A physical layer (PHY) processor of a network device receives a timing message via an external network and generates a first timestamp using a first local-domain clock used by the PHY processor. The PHY processor transfers the timing message and the first timestamp to a packet processor of the network device via an internal communication link. The packet processor generates a second timestamp for the timing message using a domain-specific clock. The packet processor determines a delay value using the first timestamp, the delay value accounting for a time delay corresponding to the transfer of the timing message within the network device from the PHY processor to the packet processor. The packet processor adjusts the second timestamp using the delay value to generate an adjusted domain-specific timestamp for the timing message.
In a network switching system that comprises a plurality of interconnected network devices, a first network device transmits one or more first packets via a first network interface of the first network device, the one or more first packets belonging to a packet flow. The first network device receives a message that indicates congestion corresponding to the packet flow within the network switching system. In response to the message, the first network device selects a second network interface of the first network device for transmitting one or more second packets that belong to the packet flow. After receiving the message, the first network device transmits the one or more second packets via the second network interface of the first network device.
Timestamp circuitry of a network device modifies a packet by embedding a future timestamp in the packet to generate a timestamped packet. The future timestamp corresponds to a transmit time that occurs after the timestamp circuitry embeds the future timestamp in the packet. The timing information is added to the packet and the packet is then transferred to transmitter circuitry of the network device via a communication link, internal to the network device, that operates according to a media independent communication interface. Time gating circuitry of the transmitter circuitry i) holds the timestamped packet from proceeding to a network link coupled to the network device prior to a current time reaching the transmit time, and ii) releases the timestamped packet for transmission via the network link in response to the current time reaching the transmit time.
A network device includes a plurality of network interfaces configured to couple with a plurality of physical network links. A packet processor is configured to process packets received via the plurality of network interfaces. The packet processor includes a path selection engine that is configured to: for each of at least some packets processed by the packet processor, successively make path selection decisions that correspond to respective routing domains within a hierarchical communication network, the path selection decisions for forwarding the packet through the hierarchical communication network.
A printed circuit board (PCB) system includes an integrated circuit (IC) package having a main IC chip that is electrically coupled to a top surface of a package substrate. A first printed circuit board (PCB) is electrically coupled to first contact structures on a bottom surface of the package substrate. A heat dissipation member is coupled to the main IC chip. A memory module is configured to electrically couple, via an interposer, with second contact structures on a top surface of the package substrate while the heat dissipation member dissipates heat from the main IC chip away from one or more memory IC chips on the memory module. The interposer is configured to electrically couple the second contact structures of the IC package with the memory module while the heat dissipation member dissipates heat from the main IC chip away from the one or more memory IC chips.
H01L 25/10 - Assemblies consisting of a plurality of individual semiconductor or other solid state devices all the devices being of a type provided for in the same subgroup of groups , or in a single subclass of , , e.g. assemblies of rectifier diodes the devices having separate containers
H01L 23/00 - SEMICONDUCTOR DEVICES NOT COVERED BY CLASS - Details of semiconductor or other solid state devices
H01L 25/00 - Assemblies consisting of a plurality of individual semiconductor or other solid state devices
H01L 25/18 - Assemblies consisting of a plurality of individual semiconductor or other solid state devices the devices being of types provided for in two or more different subgroups of the same main group of groups , or in a single subclass of ,
21.
HIERARCHICAL PATH SELECTION IN A COMMUNICATION NETWORK
A network device includes a plurality of network interfaces configured to couple with a plurality of physical network links. A packet processor is configured to process packets received via the plurality of network interfaces. The packet processor includes a path selection engine that is configured to: for each of at least some packets processed by the packet processor, successively make path selection decisions that correspond to respective routing domains within a hierarchical communication network, the path selection decisions for forwarding the packet through the hierarchical communication network.
A packet is received via a first network interface of a first network device in an underlay network, the packet having been originated by a first endpoint device and including a first network address indicating a destination of the first packet. The first network device, without analyzing the first network address in the first packet, adds, to the first packet, a second network address corresponding to a cloud edge network device implemented at the cloud edge and information identifying the first network interface via which the first packet was received by the first network device. The first network device transmits the packet, via an overlay network layered over the underlay network, to the cloud edge network device to enable forwarding of the packet to the destination of the packet, based on the first network address included in the packet, by the cloud edge network device
A network device transfers packets from a packet memory to one or more network interfaces for transmission by the one or more network interfaces. The transferring of packets includes transferring the packets via one or more respective transmit data paths that correspond to one or more respective network interfaces. The network device measures one or more respective amounts of time required to transmit respective packet data within the one or more respective transmit data paths. The network device uses the one or more respective measured amounts of time to determine when to start transfer of packets from the packet memory to the one or more network interfaces via the one or more respective transmit data paths.
G06F 5/06 - Methods or arrangements for data conversion without changing the order or content of the data handled for changing the speed of data flow, i.e. speed regularising
A network device transfers packets from a packet memory to one or more network interfaces for transmission by the one or more network interfaces. The transferring of packets includes transferring the packets via one or more respective transmit data paths that correspond to one or more respective network interfaces. The network device measures one or more respective amounts of time required to transmit respective packet data within the one or more respective transmit data paths. The network device uses the one or more respective measured amounts of time to determine when to start transfer of packets from the packet memory to the one or more network interfaces via the one or more respective transmit data paths.
A network device includes a first queue for queueing express packets and a second queue for queueing preemptable packets that are to be transmitted via a network interface of the network device. The network device also includes a transmit controller that receives a packet directed to the first queue and determines whether the packet is a type of packet that requires transmission at a specific transmit time from the network interface of the network device. In response to determining that the packet is a type of packet that requires transmission at a specific transmit time, the transmit controller suspends an ongoing transmission of a preemptable packet from the second queue that would prevent transmission of the packet from the first queue at the specific transmit time via the network interface and causes the packet in the first queue to be transmitted at the specific transmit time via the network interface.
A network device includes a first queue for queueing express packets and a second queue for queueing preemptable packets that are to be transmitted via a network interface of the network device. The network device also includes a transmit controller that receives a packet directed to the first queue and determines whether the packet is a type of packet that requires transmission at a specific transmit time from the network interface of the network device. In response to determining that the packet is a type of packet that requires transmission at a specific transmit time, the transmit controller suspends an ongoing transmission of a preemptable packet from the second queue that would prevent transmission of the packet from the first queue at the specific transmit time via the network interface and causes the packet in the first queue to be transmitted at the specific transmit time via the network interface.
A packet is received via a first network interface of a first network device in an underlay network, the packet having been originated by a first endpoint device and including a first network address indicating a destination of the first packet. The first network device, without analyzing the first network address in the first packet, adds, to the first packet, a second network address corresponding to a cloud edge network device implemented at the cloud edge and information identifying the first network interface via which the first packet was received by the first network device. The first network device transmits the packet, via an overlay network layered over the underlay network, to the cloud edge network device to enable forwarding of the packet to the destination of the packet, based on the first network address included in the packet, by the cloud edge network device
A network device provides a search key corresponding to a packet to a TCAM. The TCAM determines that the search key matches one or more search patterns stored in the TCAM. The network device selects one search pattern among the one or more search patterns at least by analyzing respective priority information associated with the one or more search patterns. The respective priority information indicates one or more respective priority levels that are independent from one or more physical locations of the one or more search patterns within the TCAM. In connection with selecting the one search pattern, the network device determines one or more actions to be performed on the packet by the network device, the one or more actions corresponding to the selected one search pattern.
A network device provides a search key corresponding to a packet to a TCAM. The TCAM determines that the search key matches one or more search patterns stored in the TCAM. The network device selects one search pattern among the one or more search patterns at least by analyzing respective priority information associated with the one or more search patterns. The respective priority information indicates one or more respective priority levels that are independent from one or more physical locations of the one or more search patterns within the TCAM. In connection with selecting the one search pattern, the network device determines one or more actions to be performed on the packet by the network device, the one or more actions corresponding to the selected one search pattern.
A packet processor of a network device repeatedly determines a fill level of a forwarding table that is populated with associations between network addresses and network interfaces of, or coupled to, the network device. The packet processor adjusts, based on the fill level of the forwarding table, a maximum rate according to which the packet processor is permitted to send messages to a central processing unit (CPU) coupled to the packet processor, the messages indicating network addresses that are to be stored in the forwarding table by the CPU. The packet processor of the network device receives packets via network links coupled to the network device; identifies new network addresses of the packets that are not in the forwarding table; and sends messages to the CPU at a rate that does not exceed the maximum rate, the messages indicating the new network addresses are to be added to the forwarding table.
A packet processor of a network device receives packets ingressing from a plurality of network links via a plurality of network ports of the network device. The packet processor buffers the packets in an internal packet memory in a plurality of queues, including a first queue. In response to the packet processor detecting congestion in the internal packet memory, the packet processor selectively forwards a group of multiple packets in the first queue from the internal packet memory to a first port, among one or more ports coupled to one or more external memories, to transfer the group of multiple packets to a first external memory that is coupled to the first port so that the first queue is stored across the internal packet memory and the first external packet memory.
H04L 47/122 - Avoiding congestion; Recovering from congestion by diverting traffic away from congested entities
H04L 47/33 - Flow control; Congestion control using forward notification
H04L 47/52 - Queue scheduling by attributing bandwidth to queues
H04L 47/722 - Admission control; Resource allocation using reservation actions during connection setup at the destination endpoint, e.g. reservation of terminal resources or buffer space
A packet processor of a network device repeatedly determines a fill level of a forwarding table that is populated with associations between network addresses and network interfaces of, or coupled to, the network device. The packet processor adjusts, based on the fill level of the forwarding table, a maximum rate according to which the packet processor is permitted to send messages to a central processing unit (CPU) coupled to the packet processor, the messages indicating network addresses that are to be stored in the forwarding table by the CPU. The packet processor of the network device receives packets via network links coupled to the network device; identifies new network addresses of the packets that are not in the forwarding table; and sends messages to the CPU at a rate that does not exceed the maximum rate, the messages indicating the new network addresses are to be added to the forwarding table.
H04L 49/9005 - Buffering arrangements using dynamic buffer space allocation
H04L 49/901 - Buffering arrangements using storage descriptor, e.g. read or write pointers
H04L 49/9015 - Buffering arrangements for supporting a linked list
33.
Congestion notification packet indicating specific packet flow experiencing congestion to facilitate individual packet flow based transmission rate control
A network device includes first, second, and third processors. The first processor detects congestion in a packet flow. The packet flow is i) one packet flow among a plurality of packet flows and ii) is formed of a plurality of packets of a same type received from a first device in a network via a first network connection. The packets in the packet flow are destined for a second device in the network. When congestion notification packet generation is enabled for the packet flow, the second processor generates a congestion notification packet by replicating a packet from the packet flow and sends the congestion notification packet to the first device via the first network connection. The congestion notification packet identifies the packet flow for which congestion is detected. The third processor forwards the plurality of packets in the packet flow to the second device via a second network connection.
A packet group processor of a network device defines groups of packets among packets that are being processed by the network device, each of at least some of the groups of packets defining a respective group of at least two different packets. Each group includes one or more packets to be transmitted via a respective same network interface. A transmit processor makes a single transmit decision that a particular group of at least two packets is to be transmitted via a corresponding network interface, and in response to the single transmit decision, transfers the particular group of at least two packets to the corresponding network interface for transmission.
A packet group processor of a network device defines groups of packets among packets that are being processed by the network device, each of at least some of the groups of packets defining a respective group of at least two different packets. Each group includes one or more packets to be transmitted via a respective same network interface. A transmit processor makes a single transmit decision that a particular group of at least two packets is to be transmitted via a corresponding network interface, and in response to the single transmit decision, transfers the particular group of at least two packets to the corresponding network interface for transmission.
At least a packet header of a packet received by a network device is provided to a programmable header alteration engine that includes a hardware input processor implemented in hardware and a programmable header alteration processor configured to execute computer readable instructions stored in a program memory. The hardware input processor determines whether the packet header is to be provided to a processing path coupled to the programmable header alteration processor or to be diverted to a bypass path that bypasses the programmable header alteration processor, and the packet header is provided to the processing path or to the bypass path based on the determination. The packet header is selectively i) processed by the programmable header alteration processor when the packet header is provided to the processing path and ii) not processed by the programmable header alteration processor when the packet header is provided to the bypass path.
H04L 47/2441 - Traffic characterised by specific attributes, e.g. priority or QoS relying on flow classification, e.g. using integrated services [IntServ]
An anomaly detection apparatus for detecting anomalies in network traffic includes a statistics generator that receives characteristics of packets in network traffic and to generate statistics for the network traffic. The statistics include distribution statistics regarding respective distributions of respective characteristics of packets in the network traffic over time. An anomaly detection processor detects deviations in the distribution statistics as compared to distribution statistics for normal network traffic and detects anomalies regarding the network traffic based on the deviations in the distribution statistics as compared to distribution statistics for the normal network traffic.
An anomaly detection apparatus for detecting anomalies in network traffic includes a statistics generator that receives characteristics of packets in network traffic and to generate statistics for the network traffic. The statistics include distribution statistics regarding respective distributions of respective characteristics of packets in the network traffic over time. An anomaly detection processor detects deviations in the distribution statistics as compared to distribution statistics for normal network traffic and detects anomalies regarding the network traffic based on the deviations in the distribution statistics as compared to distribution statistics for the normal network traffic.
Schedules that indicate when time gates of a network device are to permit transfer of packet data are stored in a memory. Control circuitry repeatedly identifies initial positions in the schedules corresponding to times when the schedules are accessed in a background procedure. The control circuitry uses the identified initial positions to identify updated positions in the schedules that correspond to events when control of the time gates is needed, and uses scheduling information at the updated positions in the schedules to selectively transfer packet data to components of the network device using the time gates.
Schedules that indicate when time gates of a network device are to permit transfer of packet data are stored in a memory. Control circuitry repeatedly identifies initial positions in the schedules corresponding to times when the schedules are accessed in a background procedure. The control circuitry uses the identified initial positions to identify updated positions in the schedules that correspond to events when control of the time gates is needed, and uses scheduling information at the updated positions in the schedules to selectively transfer packet data to components of the network device using the time gates.
A method for controlling the flow of data traffic on a destination device in a network involves (a) providing a table associated with the destination device; (b) reading each entry of the table from the start of the table to the end of the table; (c) for each port entry read, determining whether a buffer storage threshold for data received from a source port has been exceeded. When the buffer storage threshold for data received from the source port is determined to have been exceeded, an internal stop message is transmitted to a media access control unit on the destination device, otherwise an internal continue message is transmitted to the media access control unit. Operations (b) and (c) are repeated for each of a plurality of read cycles.
H04L 47/30 - Flow control; Congestion control in combination with information about buffer occupancy at either end or at transit nodes
H04L 47/2408 - Traffic characterised by specific attributes, e.g. priority or QoS for supporting different services, e.g. a differentiated services [DiffServ] type of service
H04L 69/324 - Intralayer communication protocols among peer entities or protocol data unit [PDU] definitions in the data link layer [OSI layer 2], e.g. HDLC
A network device includes queues for queuing packets, and functional circuitry to provide a processing resource to be shared by the queues. Further, the network device includes a first-in-first-out (FIFO) selection circuit that receives tokens respectively associated with the queues. The FIFO selection circuit buffers and outputs the tokens in a first-in-first-out manner. When a token is output by the FIFO selection circuit, a queue associated with the token is selected to provide a packet for the functional circuitry to process. When a queue associated with an output token having at least a second packet in the queue after the queue outputs a first packet, the FIFO selection circuit re-buffers the output token associated with the queue to permit the queue to output the second packet once the output token associated with the queue is again output by the FIFO selection circuit.
A first solid state drive (SSD) includes a built-in network interface device configured to communicate via a network fabric, and a second SSD includes a built-in network interface device configured to communicate via the network fabric. A connection is opened between the first SSD and the second SSD over the network fabric, where the first SSD is further communicatively coupled to the second SSD further over an interconnect associated with a host computer. The first SSD encapsulates a non-volatile memory over fabric (NVMe-oF) command to transfer data between the first SSD and the second SSD in a capsule and sends the capsule to the second SSD over the connection. The second SSD executes the NVMe command to transfer the data between the first SSD and the second SSD over the connection according to an NVMe-oF communication protocol and without transferring any of the data to the host computer.
A network device processes received packets to determine port or ports of the network device via which to transmit the packets. The network device classifies the packets into packet flows and selects, based at least in part on one or more characteristics of data being transmitted in the respective packet flows, a first packet memory having a first memory access bandwidth or a second packet memory having a second memory access bandwidth, and buffers the packets in the selected first or second packet memory which the packets are being processed by the network device. After processing the packets, the network device retrieves the packets from the first packet memory or the second packet memory in which the packets are buffered, and forwards the packets to the determined one or more ports for transmission of the packets.
H04L 47/52 - Queue scheduling by attributing bandwidth to queues
H04L 47/2441 - Traffic characterised by specific attributes, e.g. priority or QoS relying on flow classification, e.g. using integrated services [IntServ]
A network device includes a memory configured to store a plurality of entries in respective locations in the memory, the plurality of entries corresponding to a trie data structure for performing a longest prefix match search. The network device also includes: a memory access engine configured to retrieve from a location in the memory, in a single memory lookup operation, i) longest prefix match information for a node corresponding to a network address in a header of a packet, and ii) pointer information that indicates a child node in the trie data structure. The network device also includes: a child node address calculator configured to use i) the longest prefix match information, and ii) the pointer information, to calculate a memory address of another location in the memory corresponding to the child node.
A network device includes a packet processor that: determines at least one egress port via which a received packet is to be transmitted by the network device; modifies one or more fields in a header of the packet to generate a modified header; determines, based at least in part on the modified header, whether the packet a) is to be transmitted or b) is to be discarded; and stores the modified header in a packet memory. In response to the determination that the packet is to be transmitted, a transmit processor of the network device: retrieves a payload of the packet from the packet memory; retrieves the modified header from the packet memory; generates a transmit packet at least by combining the payload of the packet with the modified header; and transmits the transmit packet via the determined at least one egress port of the network device.
H04L 47/2441 - Traffic characterised by specific attributes, e.g. priority or QoS relying on flow classification, e.g. using integrated services [IntServ]
H04L 47/32 - Flow control; Congestion control by discarding or delaying data units, e.g. packets or frames
A network device includes a rate measurement circuit that is configured to measure respective egress rates at which respective data is being transmitted via respective ports associated with the network device. A marking ratio determination circuit is configured to select respective marking ratios based on respective measured egress rates, the marking ratios for marking packets to be transmitted via the respective ports to indicate respective levels of congestion corresponding to the respective ports. Different marking ratios correspond to different measured egress rates. A packet editor circuit is configured to mark selected packets to be transmitted via respective ports according to the respective selected marking ratios. The respective selected marking ratios indicate to other communication devices that respective network paths via which the selected packets travelled experienced congestion, and the respective marking ratios indicate respective levels of congestion.
A network device includes a rate measurement circuit that is configured to measure respective egress rates at which respective data is being transmitted via respective ports associated with the network device. A marking ratio determination circuit is configured to select respective marking ratios based on respective measured egress rates, the marking ratios for marking packets to be transmitted via the respective ports to indicate respective levels of congestion corresponding to the respective ports. Different marking ratios correspond to different measured egress rates. A packet editor circuit is configured to mark selected packets to be transmitted via respective ports according to the respective selected marking ratios. The respective selected marking ratios indicate to other communication devices that respective network paths via which the selected packets travelled experienced congestion, and the respective marking ratios indicate respective levels of congestion.
A first-in/first-out (FIFO) buffer includes at least one latch-based FIFO storage line, an input flip-flop stage upstream of the at least one latch-based storage line, an output flip-flop stage downstream of the at least one latch-based storage line. The output flip-flop stage functions as an additional storage line. Clock-gating circuitry separate from the device clock controls timing of the at least one latch-based FIFO storage line, the input flip-flop stage, and the output flip-flop stage. The input flip-flop stage functions as a second additional storage line, or as an input sampling stage. Optional bypass circuitry between the input flip-flop stage and the output flip-flop stage passes data for a storage line directly to the output flip-flop stage, without passing through the at least one latch-based storage line, when the buffer is empty.
This disclosure describes a programmable clock configuration block disposed at the SoC system, which manages clock frequency change flow in a single clock domain on a SoC system to provide dynamic clock frequency configuration while the SoC system is in operation. The programmable clock configuration block is configured to interact with the CPU of the SoC system to configure or change parameters relating to the clock signal frequency while the CPU is in an inactive state.
A media access control (MAC) processor of a network device receives a timing packet to be transmitted by the network device. The MAC processor generates one or more indicators to be used by a PHY device of the network device for embedding timing information into the timing packet. The one or more indicators include at least an indicator indicating that the timing packet is a type of packet into which timing information is to be embedded, an indicator of a location of a field in the timing packet at which the timing information is to be embedded, and an indicator of whether timing information in the timing packet needs to be updated. The MAC processor transfers the timing packet and the one or more indicators to the PHY device for further processing of the timing packet and subsequent transmission of the timing packet from the network device.
Packets to be transmitted from a network device are buffered in queues in a first packet memory. In response to detecting congestion in a queue in the first packet memory, groups of multiple packets are transferred from the first packet memory to a second packet memory, the second packet memory configured to buffer a portion of traffic bandwidth supported by the network device. Prior to transmission of the packets among the one or more groups of multiple packets from the network device, packets among the one or more groups of multiple packets are transferred from the second packet memory back to the first packet memory. The packets transferred from the second packet memory back to the first packet memory are retrieved from the first packet memory and are forwarded to one or more network ports for transmission of the packets from the network device.
H04L 47/122 - Avoiding congestion; Recovering from congestion by diverting traffic away from congested entities
H04L 47/33 - Flow control; Congestion control using forward notification
H04L 47/52 - Queue scheduling by attributing bandwidth to queues
H04L 47/722 - Admission control; Resource allocation using reservation actions during connection setup at the destination endpoint, e.g. reservation of terminal resources or buffer space
A media access control (MAC) processor of a network device receives a timing packet to be transmitted by the network device. The MAC processor generates one or more indicators to be used by a PHY device of the network device for embedding timing information into the timing packet. The one or more indicators include at least an indicator indicating that the timing packet is a type of packet into which timing information is to be embedded, an indicator of a location of a field in the timing packet at which the timing information is to be embedded, and an indicator of whether timing information in the timing packet needs to be updated. The MAC processor transfers the timing packet and the one or more indicators to the PHY device for further processing of the timing packet and subsequent transmission of the timing packet from the network device.
Packets to be transmitted from a network device are buffered in queues in a first packet memory. In response to detecting congestion in a queue in the first packet memory, groups of multiple packets are transferred from the first packet memory to a second packet memory, the second packet memory configured to buffer a portion of traffic bandwidth supported by the network device. Prior to transmission of the packets among the one or more groups of multiple packets from the network device, packets among the one or more groups of multiple packets are transferred from the second packet memory back to the first packet memory. The packets transferred from the second packet memory back to the first packet memory are retrieved from the first packet memory and are forwarded to one or more network ports for transmission of the packets from the network device.
Aspects of the disclosure provide an electronic device. The electronic device can include a first clock gating circuit that is configured to receive a clock signal and selectively transmit a clock pulse of the clock signal when triggered, access circuitry configured to launch configuration data in response to receiving a write request from a management module and trigger the first clock gating circuit to generate a first clock pulse that is delayed by a first predetermined amount of time after the launch of the configuration data by the access circuitry, and a first memory element configured to capture the configuration data in response to receiving the delayed first clock pulse generated by the first clock gating circuit.
Methods and systems are provided for processing a received packet based on associated state information. A packet processor of a network device receives a packet from a network. The received packet is classified as belonging to at least one respective identified flow from among a plurality of identified flows. For a respective received packet that belongs to an identified flow a current state value for the identified flow is ascertained based on a state table. The current state value is assigned to the respective received packet based on the current state value using the state table for the identified flow. A packet processing operation is subsequently performed on the respective received packet based in part on the state value of the identified flow to which the respective packet belongs.
H04L 47/2441 - Traffic characterised by specific attributes, e.g. priority or QoS relying on flow classification, e.g. using integrated services [IntServ]
Aspects of the disclosure provide a package system that includes a first integrated circuit (IC) package and a second IC package. The first IC package includes a first IC chip mounted on a first substrate-chip surface of a first package substrate. The first package substrate includes first near-conductive layers that are closer to the first substrate-chip surface than first far-conductive layers. The second IC package includes a second IC chip mounted on a second substrate-chip surface of a second package substrate. The second package substrate includes second near-conductive layers that are closer to the second substrate-chip surface than second far-conductive layers. A first contact structure on the first substrate-chip surface and a second contact structure on the second substrate-chip surface electrically couple the first IC chip with the second IC chip through electrical connections in the first and second near-conductive layers.
H01L 25/10 - Assemblies consisting of a plurality of individual semiconductor or other solid state devices all the devices being of a type provided for in the same subgroup of groups , or in a single subclass of , , e.g. assemblies of rectifier diodes the devices having separate containers
H01L 25/00 - Assemblies consisting of a plurality of individual semiconductor or other solid state devices
H01L 23/32 - Holders for supporting the complete device in operation, i.e. detachable fixtures
H01R 12/85 - Coupling devices connected with low or zero insertion force contact pressure producing means, contacts activated after insertion of printed circuits or like structures
58.
Managing addresses in a network device with a register-based buffer having an odd number of storage locations
Implementations described herein provide apparatus and methods for storing data in, and retrieving data from, storage buffer having an odd number of storage locations using minimal additional logic. A binary address symbol with a maximum value of one less than twice the number of storage locations is used to allow use of Gray code in transferring the storage location pointers between clock domains. An offset value is added to the binary address symbol to further facilitate use of Gray code. The Gray code is converted back to a binary symbol at the read side, the offset value is subtracted therefrom, and a pointer to a particular storage location is resolved.
Aspects of the disclosure provide a network device that includes a plurality of network ports, a power management controller and port controllers. The plurality of network ports is configured to respectively couple external devices with the network device via network cables, and provide power to the external devices via the network cables. The power management controller is configured to allocate power to the external devices following a power allocation order that is sorted according to power priorities of the external devices. A port controller detects an external device coupled to a particular network port having an operational error. In response to the error detection, the port controller assigns an error priority that is lower than regular power priorities to the external device. The regular priorities are assigned to external devices without the operational error. Further, the port controller provides the error priority to the power management controller for power allocation.
A network device receives a packet that conforms to a protocol that i) defines a time stamp field, ii) does not define a dedicated field for time correction information, and iii) defines a plurality of general purpose extension fields. The packet includes (i) a time stamp generated by a source node in the time stamp field, and (ii) a time correction value corresponding to multiple ones of the plurality of intermediate nodes, the time correction value being located in one of the general purpose extension fields. The network device identifies (i) a time specified by the time stamp, and (ii) time correction information specified in the one general purpose extension field, and uses the time correction information and the time specified by the time stamp to synchronize a clock maintained by the network device to a clock maintained by the source node.
A packet processor of a network device includes a forwarding engine that is configured to determine egress network interfaces via which packets received by the network device are to be transmitted. The packet processor also includes a header parser configured to parse header information in the packets received by the network device. The header parser includes a first parsing circuit that is configured to parse a first portion of a header of a packet and to prompt a programmable second parsing circuit to parse a second portion of the header. The first portion of the header has a header structure known to the first parsing circuit. The programmable second parsing circuit includes configurable circuitry and a memory to store control information that controls operation of the configurable circuitry to parse the second portion of the header.
A packet processor of a network device includes a forwarding engine that is configured to determine egress network interfaces via which packets received by the network device are to be transmitted. The packet processor also includes a header parser configured to parse header information in the packets received by the network device. The header parser includes a first parsing circuit that is configured to parse a first portion of a header of a packet and to prompt a programmable second parsing circuit to parse a second portion of the header. The first portion of the header has a header structure known to the first parsing circuit. The programmable second parsing circuit includes configurable circuitry and a memory to store control information that controls operation of the configurable circuitry to parse the second portion of the header.
Packets received by a network switch device from upstream network devices, coupled to respective ones of a plurality of ports of the network switch device, are temporarily stored in an internal memory of the network switch device. In response to detecting congestion in the internal memory of the network switch device, a flow control engine triggers, during respective timeslots of a timing schedule and while the flow control engine continues to monitor congestion in the internal memory of the network switch device, transmission of respective flow control messages via different subsets of ports, among the plurality of ports, to control flow of packets from different subsets of upstream network device, among the plurality of upstream network devices, to the network switch device so that flow control is distributed over time among upstream network devices of the plurality of upstream network devices.
Flow state information that is stored in a first memory among a plurality of memories for maintaining flow state information at a network device is updated based on packets ingressing the network device. The memories are arranged in a hierarchical arrangement in which memories at progressively higher levels of hierarchy are configured to maintain flow state information corresponding to progressively larger sets of flows processed by the network device. When it is determined that a fullness level of the first memory exceeds a first threshold, flow state information associated with at least one flow, among a first set of flows for which flow state information is currently being maintained in the first memory, is transferred from the first memory to a second memory, the second memory being at a higher hierarchical level than the first memory. A new flow is instantiated in space freed up in the first memory.
In a network device, a hash-based lookup system includes a hash generator configured to apply respective hash functions to a lookup key to generate respective hash values. Each hash function corresponds to a respective logical hash bank in a hash table. A number of hash values generated by the hash generator corresponds to the number of logical hash banks in the hash table, and the number of hash values generated by the hash generator is configurable. The hash-based lookup system also includes an address generator that is configured to generate respective addresses to a memory that stores the hash table, the respective addresses within respective address spaces of respective logical hash banks of the hash table. The address generator uses i) a parameter N that specifies the number of logical hash banks in the hash table, and ii) N hash values generated by the hash generator, to generate the respective addresses.
Implementations described herein provide apparatus and methods for storing data in, and retrieving data from, an asynchronous FIFO. Data is received at a write side receiving circuitry residing in a write-side clock domain of the FIFO and stored at a memory location in a data storage buffer having a plurality of locations. Each memory location in the data storage buffer has a binary pointer value corresponding to the respective location. The binary pointer value is converted to a corresponding Gray code symbol and transferred to the read side of the FIFO. At the read side the Gray code symbol is converted back to the corresponding binary pointer value. Read-side control circuitry, using the binary pointer value, transfers the data from the data storage buffer to a data output register residing in a read-side clock domain of the FIFO.
G06F 12/0804 - Addressing of a memory level in which the access to the desired data or data block requires associative addressing means, e.g. caches with main memory updating
G06F 12/0862 - Addressing of a memory level in which the access to the desired data or data block requires associative addressing means, e.g. caches with prefetch
A ball grid array (BGA) package for an integrated circuit device includes an integrated circuit device having a plurality of terminals, and two largest dimensions that define a major plane. A package substrate material encloses the integrated circuit device, and is formed, in a plane parallel to the major plane, into a polygon having at least five sides. An array of contacts on an exterior surface of the package substrate material is electrically coupled to the plurality of terminals. Contacts in the array of contacts are distributed in a pattern of contact positions, and the center of each contact position may be separated from the center of each nearest other position by a separation distance that is identical throughout the pattern. Each position may be occupied by a contact, or positions in a sub-pattern may lack a contact and may be available for insertion of at least one via.
This disclosure describes systems and methods for priority flow control in a network switching device having two or more egress queue managers for managing egress queues of ports of the network switching device. A first egress queue manager determines respective fill levels of packet data that is buffered in egress queues. The first egress queue manager generates a data structure that relates a port of the egress queue manager at which selected packets are ingressed and a port or an egress queue of the egress queue manager from which the selected packets are to be egressed. The first egress queue manager signals to one or more other egress managers the respective fill levels of egress queues along with other information to enable at least one of the other egress queue managers to make a priority flow control decision for one of the ports managed by the other egress queue manager.
A hardware queue for an integrated circuit device includes an internal queue memory and at least one external queue memory. The internal queue memory and the external queue memory are operated as a continuous hardware queue memory by monitoring occupancy of the internal queue memory and, based on that occupancy, controlling an internal tail pointer indicating a next write point for inserting new data into the internal queue memory, an internal head pointer indicating a next read point for extracting data from the internal queue memory based on order of insertion, at least one external tail pointer indicating a next write point for inserting new data into the external queue memory, at least one external head pointer indicating a next read point for extracting data from the external queue memory based on order of insertion, and wrap pointers indicating transitions between the internal queue memory and the external queue memory.
G06F 13/00 - Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
G06F 3/06 - Digital input from, or digital output to, record carriers
70.
Congestion notification packet indicating specific packet flow experiencing congestion to facilitate individual packet flow based transmission rate control
A system includes first, second, and third processors. The first processor is configured to detect congestion in a packet flow formed of a plurality of packets of a same type received from a first device in a network via a first network connection. The packets in the packet flow being destined for a second device in the network. The second processor is configured to send, when congestion notification packet generation is enabled for the packet flow, a congestion notification packet to the first device via the first network connection. The congestion notification packet identifies the packet flow for which congestion is detected. The third processor is configured to forward the plurality of packets in the packet flow to the second device via a second the network connection.
A network device includes a transmit buffer from which data is transmitted to a network, and a packet buffer from which data chunks are transmitted to the transmit buffer in response to read requests. The packet buffer has a maximum read latency from receipt of a read request to transmission of a responsive data chunk, and receives read requests including a read request for a first data chunk of a network packet and a plurality of additional read requests for additional data chunks of the network packet. A latency timer monitors elapsed time from receipt of the first read request, and outputs a latency signal when the elapsed time reaches the first maximum read latency. Transmission logic waits until the elapsed time equals the first maximum read latency, and then transmits the first data chunk from the transmit buffer, without regard to a fill level of the transmit buffer.
A source switching device in a switching system receives information measured by a target switching device in the switching system. The information is indicative of an amount of data received in a given amount of time by the target switching device via each of two or more first links coupled to the target switching device. The source switching device determines, based at least in part on the information received from the target device, a path, from among multiple paths from the source switching device to the target switching device, for transmission of a packet flow directed to the target switching device. The source switching device transmits, via the determined path for transmission of the packet flow to the target device, one or more packets belonging to the packet flow.
A printed circuit board (PCB) system includes a first printed circuit board (PCB), an integrated circuit (IC) package, and a memory module. The IC package includes i) a package substrate, ii) a main IC chip that is electrically coupled to a top surface of the package substrate, iii) first contact structures that are disposed on a bottom surface of the package substrate and that are electrically coupled to the first PCB, and iv) second contact structures that are disposed on a top surface of the package substrate. The memory module includes i) a second PCB, ii) one or more memory IC chips that are disposed on the second PCB, and iii) third contact structures that are disposed on a bottom surface of the second PCB. An interposer electrically couples the second contact structures of the IC package with the third contact structures of the memory module.
H05K 1/14 - Structural association of two or more printed circuits
H05K 1/18 - Printed circuits structurally associated with non-printed electric components
H05K 3/34 - Assembling printed circuits with electric components, e.g. with resistor electrically connecting electric components or wires to printed circuits by soldering
H05K 3/36 - Assembling printed circuits with other printed circuits
A printed circuit board (PCB) system includes a first printed circuit board (PCB), an integrated circuit (IC) package, and a memory module. The IC package includes i) a package substrate, ii) a main IC chip that is electrically coupled to a top surface of the package substrate, iii) first contact structures that are disposed on a bottom surface of the package substrate and that are electrically coupled to the first PCB, and iv) second contact structures that are disposed on a top surface of the package substrate. The memory module includes i) a second PCB, ii) one or more memory IC chips that are disposed on the second PCB, and iii) third contact structures that are disposed on a bottom surface of the second PCB. An interposer electrically couples the second contact structures of the IC package with the third contact structures of the memory module.
H01L 25/10 - Assemblies consisting of a plurality of individual semiconductor or other solid state devices all the devices being of a type provided for in the same subgroup of groups , or in a single subclass of , , e.g. assemblies of rectifier diodes the devices having separate containers
H01L 23/00 - SEMICONDUCTOR DEVICES NOT COVERED BY CLASS - Details of semiconductor or other solid state devices
H01L 25/18 - Assemblies consisting of a plurality of individual semiconductor or other solid state devices the devices being of types provided for in two or more different subgroups of the same main group of groups , or in a single subclass of ,
H01L 25/00 - Assemblies consisting of a plurality of individual semiconductor or other solid state devices
75.
Methods and apparatus for load balancing in a network switching system
A local network device of a network switching system determines, based on a first set of received packets that contain markings indicating congestion at one or more other network devices in the network switching system, one or more respective congestion levels of one or more network paths through the network switching system. The local network device selects, based on determined congestion levels, network paths via which a second set of received packets are to be forwarded for load balancing. The local network device alters header information in the second set of received packets, the altered header information to be used by other network devices in the network switching system to make network path selections so that the second set of received packets are subsequently forwarded responsively to the altered header information along the selected network paths within the network switching system.
Performance measuring circuitry, for determining relative operational performance attributes of different types of a class of semiconductor component disposed on a semiconductor die, includes a first oscillator circuit including a plurality of first circuit element modules having a first circuit topology. The first oscillator circuit provides a first performance indication indicative of a collective performance attribute of all types of components in the class. A second oscillator circuit separate from the first oscillator circuit includes a plurality of second circuit element modules having a second circuit topology, and provides a second performance indication responsive to different contributions from different types of components in the class. A comparison circuit receives outputs of the first and second oscillator circuits and determines the relative performance characteristic of the different types of components. Dice may be binned according to performance, for use in assembly of operational circuits with different performance characteristics.
A network device for a communications network includes a port configured to transmit data to the network at a maximum transmit data rate. The device also includes a transmit buffer configured to buffer data units that are ready for transmission to the network, and a packet buffer configured to buffer data units before the data units are ready for transmission. The packet buffer is configured to output data units at a maximum packet buffer transmission rate faster than the maximum transmit data rate. The device includes a rate controller configured to control a transmission rate of data from the packet buffer to the transmit buffer so that averaged over a period, the transmission rate from the packet buffer to the transmit buffer is at most equal to the maximum transmit data rate, while allowing the transmission rate, at one or more time intervals, to exceed the maximum transmit data rate.
In a switching system that comprises a central switching device an at least one port extender device, the central switching device includes at least one port configured to interface with the port extender device, and the port extender device includes a plurality of front ports for interfacing with one or more networks. The central switching device includes a processor that processes packets received from the at least one port extender device, and a plurality of egress queues for storing processed packets that are to be forwarded to the at least one port extender device for transmission via ones of the front ports. The central switching device also includes a flow control processor configured to, responsively to flow control messages received from the at least one port extender device, control transmission of packets to the at least one port extender device to prevent overflow of egress queues of the port extender device.
A local network device receives a plurality of packets via a plurality of network paths in a network system, and counts respective numbers of packets, per network path, that are marked, in Internet Protocol (IP) headers and/or headers corresponding to one or more protocols above an IP layer, to indicate congestion at one or more remote network devices in the network system. The local network device determines respective congestion levels of network paths among the plurality of paths based on the respective numbers of received packets that are marked to indicate congestion at one or more remote network devices in the network system, and performs load balancing operations using at least the respective determined congestion levels.
A method for operating a network device, having data storage with selectably modifiable capacity for storing instructional data for a packet processing operation, includes detecting a need for additional storage for the instructional data, allocating an additional memory block without interrupting operation of the network device, associating with the additional memory block an additional address hashing function, different from each of at least one respective previous address hashing function associated with any previously-allocated memory block. Each respective previous address hashing function transforms a look-up key into a respective addressable location in a previously-allocated memory block, and the additional address hashing function transforms the look-up key into an addressable location in the additional memory block. When a block is deallocated, each unit of instructional data is reprocessed through the hashing function of a different block to which the unit of the instructional data will be moved.
An upstream network device in a switching system processes packets an determines respective one or more egress ports of a downstream network device via which the packets are to be subsequently transmitted by the downstream network device. The upstream network device temporarily stores the packets in respective virtual output queues (VoQs) corresponding to the determined egress ports of the downstream network device. Responsively to receiving a flow control message indicating that particular one or more egress ports of the downstream network device are congested, the upstream network device modulates a flow of packets from particular one or more VoQs corresponding to the one or more particular congested egress ports of the downstream network device, to reduce congestion at the particular congested egress ports of the downstream network device, without modulating the flow of packets from other one or more VoQs corresponding to other egress ports of the downstream network device.
A network device comprises a network interface configured to transmit packets via a network link, and timestamp circuitry configured to modify a packet that is to be transmitted by the network interface circuitry by embedding a future timestamp in the packet. The future timestamp corresponds to a transmit time at which the packet is to be transmitted by the network interface circuitry, and the transmit time occurs after the timestamp circuitry embeds the timestamp in the packet. Time gating circuitry is configured to i) receive the packet, ii) determine when a current time indicated by a clock circuit reaches the transmit time, iii) hold the packet from proceeding to the network interface circuitry prior to the current time reaching the transmit time, and iv) release the packet in response to the current time reaching the transmit time.
At least a packet header of a packet received by a network device is provided to a programmable header alteration engine that includes a hardware input processor implemented in hardware and a programmable header alteration processor configured to execute computer readable instructions stored in a program memory. The hardware input processor determines whether the packet header is to be provided to a processing path coupled to the programmable header alteration processor or to be diverted to a bypass path that bypasses the programmable header alteration processor, and the packet header is provided to the processing path or to the bypass path based on the determination. The packet header is selectively i) processed by the programmable header alteration processor when the packet header is provided to the processing path and ii) not processed by the programmable header alteration processor when the packet header is provided to the bypass path.
H04L 47/2441 - Traffic characterised by specific attributes, e.g. priority or QoS relying on flow classification, e.g. using integrated services [IntServ]
In a network device, a hash calculator generates a lookup hash value from data fields associated with a packet received by the network device. A compressed lookup key generator generates a compressed lookup key for the packet using the lookup hash value. A content addressable memory (CAM) stores compressed patterns corresponding to compressed lookup keys, uses the compressed lookup key received from the compressed lookup key generator to determine if the received compressed lookup key matches any stored compressed patterns, and outputs an index corresponding to a stored compressed pattern that matches the compressed lookup key. A memory stores uncompressed patterns corresponding to the compressed patterns stored in the CAM, and retrieves an uncompressed pattern using the index output by the CAM. A comparator generate a signal that indicates whether the uncompressed pattern retrieved from the memory matches the data fields associated with the packet.
In a network device, a hash calculator generates a lookup hash value from data fields associated with a packet received by the network device. A compressed lookup key generator generates a compressed lookup key for the packet using the lookup hash value. A content addressable memory (CAM) stores compressed patterns corresponding to compressed lookup keys, uses the compressed lookup key received from the compressed lookup key generator to determine if the received compressed lookup key matches any stored compressed patterns, and outputs an index corresponding to a stored compressed pattern that matches the compressed lookup key. A memory stores uncompressed patterns corresponding to the compressed patterns stored in the CAM, and retrieves an uncompressed pattern using the index output by the CAM. A comparator generate a signal that indicates whether the uncompressed pattern retrieved from the memory matches the data fields associated with the packet.
At least a payload of a packet that is received by a network device is stored in a packet memory. The packet is processed at least to determine at least one egress port via which the packet is to be transmitted, modify a header of the packet to generate a modified header, and determine, based at least in part on the modified header, whether the packet is to be transmitted or to be discarded by the network device. In response to determining that the packet is to be transmitted, the at least the payload of the packet is retrieved from the packet memory, a transmit packet is generated at least by combining the at least the payload of the packet with the modified header, and the transmit packet is transmitted via the determined at least one egress port of the network device.
A packet processor of a network device determines an amount of free buffer space in a buffer memory currently available for buffering packets, and dynamically determines a value of a threshold for triggering a particular traffic management operation with respect to a packet, to dynamically adjust the value of the threshold based at least in part on a changing amount of free buffer space available for buffering packets in the buffer memory. The packet processor determines, based on a comparison between i) a current fill level of a particular transmit queue in which the packet is to be enqueued and ii) the dynamically adjusted value of the threshold, whether the particular traffic management operation is to be triggered with respect to the packet. When the particular traffic management operation is to be triggered, the packet processor performs the particular traffic management operation with respect to the packet.
Embodiments described herein provide a dual-line FIFO structure without the use of any multiplexer. Instead, the dual-line FIFO described herein uses a selectively transparent latch and a flip-flop serially connected to the latch, such that the combination of the serially connected latch and the flip-flop can temporarily store up to two data units at two clock cycles.
G06F 3/06 - Digital input from, or digital output to, record carriers
G06F 5/06 - Methods or arrangements for data conversion without changing the order or content of the data handled for changing the speed of data flow, i.e. speed regularising
G06F 13/16 - Handling requests for interconnection or transfer for access to memory bus
A packet received by a network device via a network. A first portion of the packet is stored in a packet memory, the first portion including at least a payload of the packet. The packet is processed based on information from a header of the packet. After the packet is processed, a second portion of the packet is stored in the packet memory, the second portion including at least a portion of the header of the packet. When the packet is to be transmitted the first portion of the packet and the second portion of the packet are retrieved from the packet memory, and the first portion and the second portion are combined to generate a transmit packet. The transmit packet is forwarded to a port of the network device for transmission of the transmit packet via port of the network device.
A method for scan chain testing a multi-chip module including a plurality of integrated circuit dice, some of the integrated circuit dice being of a first type and some of the integrated circuit dice being of a second type, includes separately applying a first boundary scan test stream to each die of the first type, and a second boundary scan test stream to each die of the second type. Testing apparatus includes a test interface that couples to each respective test access port, and a controller configured to separately apply the first boundary scan test stream to each die of the first type, and the second boundary scan test stream to each die of the second type, A multi-chip module includes a plurality of integrated circuit dice, each having a boundary scan register chain with a test access port, and a test access port for the module as a whole.
A method for scan chain testing a multi-chip module including a plurality of integrated circuit dice, some of the integrated circuit dice being of a first type and some of the integrated circuit dice being of a second type, includes separately applying a first boundary scan test stream to each die of the first type, and a second boundary scan test stream to each die of the second type. Testing apparatus includes a test interface that couples to each respective test access port, and a controller configured to separately apply the first boundary scan test stream to each die of the first type, and the second boundary scan test stream to each die of the second type. A multi-chip module includes a plurality of integrated circuit dice, each having a boundary scan register chain with a test access port, and a test access port for the module as a whole.
A downstream network device in a switching system receives, via an ingress port, packets from an upstream network device in the switching system, and forwards the packets to determined respective egress ports via which the packets are to be transmitted. The downstream network device monitors respective congestion states of ones of the respective egress ports, and in response to determining that a particular egress port is congested, generates a flow control message to include an indication of the particular congested egress port and transmits the flow control message via the ingress port to the upstream network device to cause the upstream network device to modulate a flow of packets directed to the particular congested egress port, to reduce congestion at the particular congested egress port, without causing the upstream network device to modulate the flow of packets directed to other ones of the egress ports of the downstream network device.
A method for processing network packets in a network device is described. A network packet is stored in a transient buffer as the network packet is being received at an ingress port of the network device. After at least a first portion of the network packet has been received and before the entire network packet has been received: the first portion is processed to identify an egress port of the network device from which the network packet is to be transmitted; a congestion state of the egress port is determined; and the network packet is selectively transferred from the transient buffer to the identified egress port for transmission from the network device or a different action is performed on the network packet, based on the congestion state.
Packets that are to be transmitted via a plurality of egress interfaces of a network device are stored in a memory of the network device. The packets are stored in a plurality of queues that respectively correspond to the egress interfaces. The network device determines a set of queues, from among the plurality of queues, for which packet dropping is enabled. The network device determines whether a utilization level of the memory meets a threshold. In response to determining that the utilization level of the memory meets the threshold: the network device randomly or pseudorandomly selects a first queue from the set of queues for which packet dropping is enabled, dequeues a first packet from the selected first queue, and deletes the first packet that was dequeued from the selected first queue.
In a method for managing a network device a current hash value is determined for a current key to be inserted into a lookup table. The current hash value associated with a current set of memory locations in the lookup table, wherein the current set of memory locations includes a memory location corresponding to the current hash value and one or more other memory locations. In response to determining that each memory location in the current set of memory location is occupied, one or multiple previously stored keys in the lookup table are iteratively moved to other memory locations in the lookup table to free up a memory location in the current set of memory locations, the current key is inserted into the freed up memory location.
A network device comprises time measurement units configured to measure receipt times and transmit times of packets received/transmitted via network interfaces. One or more memories store configuration information that indicates certain network interface pairs and/or certain packet flows that are enabled for latency measurement. A packet processor includes a latency monitoring trigger unit configured to select, using the configuration information, packets that are forwarded between the certain network interface pairs and/or that belong to the certain packet flows for latency monitoring. One or more latency measurement units determine respective latencies for packets selected by the latency monitoring trigger unit using respective receipt times and respective transmit times for the packets selected by the latency monitoring trigger unit, calculates latency statistics for the certain network interface pairs and/or the certain packet flows using the respective latencies, and stores the latency statistics in the one or more memories.
A FIFO memory device has a first number of data storage units and a second number of internal FIFO memories. Each internal FIFO memory has a third number of internal data storage units. The first number is a product of the second and third numbers. A fourth number of data inputs receives input data units in order. Input multiplexer circuitry connects each one of the data inputs to any one of the internal FIFO memories, for storage of input data units, in order, in a first layer of the FIFO memory device including corresponding storage locations in respective ones of the internal FIFO memories. The first layer may be physical, or may be logical and maintained by pointers. Output multiplexer circuitry coupled to the internal FIFO memories connects each of the internal FIFO memories to any one of the data outputs to read out the stored data units in order.
G06F 5/16 - Multiplexed systems, i.e. using two or more similar devices which are alternately accessed for enqueue and dequeue operations, e.g. ping-pong buffers
G06F 5/08 - Methods or arrangements for data conversion without changing the order or content of the data handled for changing the speed of data flow, i.e. speed regularising having a sequence of storage locations, the intermediate ones not being accessible for either enqueue or dequeue operations, e.g. using a shift register
G11C 7/10 - Input/output [I/O] data interface arrangements, e.g. I/O data control circuits, I/O data buffers
A network device receives a packet that conforms to a protocol that i) defines a time stamp field, ii) does not define a dedicated field for time correction information, and iii) defines a plurality of general purpose extension fields. The packet includes (i) a time stamp generated by a source node in the time stamp field, and (ii) a time correction value corresponding to multiple ones of the plurality of intermediate nodes, the time correction value being located in one of the general purpose extension fields. The network device identifies (i) a time specified by the time stamp, and (ii) time correction information specified in the one general purpose extension field, and uses the time correction information and the time specified by the time stamp to synchronize a clock maintained by the network device to a clock maintained by the source node.
In a network device, a flow classification hardware engine is configured to: store flow state information regarding known flows of packets in a flow information table in association with respective assigned flow identifiers (IDs). The assigned flow IDs are from an ordered set of M flow IDs, where M is a positive integer. In response to detecting new flows of packets, the flow classification hardware engine: i) assigns respective flow IDs, from the ordered set of M flow IDs, to the new flows, and ii) creates respective entries in the flow information table for the new flows. An embedded processor periodically, as part of a background process: i) identifies an oldest assigned flow ID, from the ordered set of M flow IDs, and ii) makes storage space in the flow information table corresponding to the oldest assigned flow ID available for a new flow.
Aspects of the disclosure provide a printed circuit board (PCB) system that includes an integrated circuit (IC) package, a first PCB and a PCB module. The IC package has a package substrate and an IC chip that is coupled to a top surface of the package substrate. The first PCB is configured to electrically couple with first contact structures that are disposed on a bottom surface of the package substrate. The PCB module includes a second PCB and one or more electronic components electrically coupled to the second PCB. The PCB module is configured to electrically couple with second contact structures that are disposed on the top surface of the package substrate.
H05K 7/00 - Constructional details common to different types of electric apparatus
H01L 23/538 - Arrangements for conducting electric current within the device in operation from one component to another the interconnection structure between a plurality of semiconductor chips being formed on, or in, insulating substrates
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