Abrégé

The invention concerns a process for testing an integrated circuit including a collection stage for a set of points (Wk,i,j) of a physical size while the integrated circuit executes a multiplication. The process includes steps consisting in dividing the set of points into a plurality of subsets of points (Ci,j), calculating an estimate (HWi,j) of the value of the physical size for each subset (Ci,j), and applying a transverse horizontal statistical treatment step to the subsets of lateral points (Ci,j) using the estimates of the value of the physical size to validate the hypothesis about variables manipulated by the integrated circuit.

Classes IPC  ?

• G01R 31/319 - Matériel de test, c. à d. circuits de traitement de signaux de sortie
• G01R 31/3173 - Tests marginaux
• G06K 19/07 - Supports d'enregistrement avec des marques conductrices, des circuits imprimés ou des éléments de circuit à semi-conducteurs, p.ex. cartes d'identité ou cartes de crédit avec des puces à circuit intégré

Abrégé

The invention relates to an integrated circuit (ClC2) comprising a multiplication function (SMT2) that is configured to execute a multiplication operation of two binary words x (a) and y (a, m) involving a plurality of basic multiplication steps of components xi (ai) of word x by components yj (aj, mj) of word y. According to the invention, the multiplication function of the integrated circuit is configured to execute two successive multiplications by modifying, in a random or pseudo-random manner, the order in which the basic multiplication steps of components xi by components yj are executed.

Classes IPC  ?

• G06F 21/75 - Protection de composants spécifiques internes ou périphériques, où la protection d'un composant mène à la protection de tout le calculateur pour assurer la sécurité du calcul ou du traitement de l’information par inhibition de l’analyse de circuit ou du fonctionnement, p.ex. pour empêcher l'ingénierie inverse
• G06F 7/523 - Multiplication uniquement