A memory device includes a plurality of pages arrayed in a column direction in a plan view, each page being constituted by a plurality of memory cells arrayed in a row direction on a substrate. Each of the memory cells included in each of the pages includes a semiconductor base material, first and second impurity regions positioned at respective ends of the semiconductor base material, first, second, and third gate conductor layers. The first and second impurity regions, the first, second, and third gate conductor layers are connected to a source line, a bit line, a first select gate line, a plate line, and a second select gate line, respectively. Upon operation end of page write operation and page read operation, voltage of the plate line is set to negative voltage lower than 0 V through capacitive coupling of the plate line and each of the first and second select gate lines to improve data retention characteristics of a write memory cell.
H10B 12/00 - Mémoires dynamiques à accès aléatoire [DRAM]
G11C 11/404 - Mémoires numériques caractérisées par l'utilisation d'éléments d'emmagasinage électriques ou magnétiques particuliers; Eléments d'emmagasinage correspondants utilisant des éléments électriques utilisant des dispositifs à semi-conducteurs utilisant des transistors formant des cellules nécessitant un rafraîchissement ou une régénération de la charge, c. à d. cellules dynamiques avec régénération de la charge commune à plusieurs cellules de mémoire, c. à d. rafraîchissement externe avec une porte à transfert de charges, p.ex. un transistor MOS, par cellule
G11C 11/4096 - Circuits de commande ou de gestion d'entrée/sortie [E/S, I/O] de données, p.ex. circuits pour la lecture ou l'écriture, circuits d'attaque d'entrée/sortie ou commutateurs de lignes de bits
A memory device including a semiconductor element includes two stacked memory cells including a first impurity region, first and second gate conductor layers, a second impurity region, third and fourth gate conductor layers, and a third impurity region on a P layer substrate in order from below in a vertical direction and configured to perform data write, read, and erase operation with voltage applied to each gate conductor layer. The first impurity region is connected to a first bit line. One of the first and second gate conductor layers and the other are connected to a word line and a plate line, respectively. The third and fourth gate conductor layers are each connected to the word line or plate line connected to the second or first gate conductor layer, respectively. The second and third impurity regions are connected to a source line and a second bit line, respectively.
G11C 11/4096 - Circuits de commande ou de gestion d'entrée/sortie [E/S, I/O] de données, p.ex. circuits pour la lecture ou l'écriture, circuits d'attaque d'entrée/sortie ou commutateurs de lignes de bits
G11C 11/4091 - Amplificateurs de lecture ou de lecture/rafraîchissement, ou circuits de lecture associés, p.ex. pour la précharge, la compensation ou l'isolation des lignes de bits couplées
G11C 11/4097 - Organisation de lignes de bits, p.ex. configuration de lignes de bits, lignes de bits repliées
H10B 12/00 - Mémoires dynamiques à accès aléatoire [DRAM]
A memory device includes pages in a column direction on a substrate and memory cells in each page in a row direction in plan view. Each memory cell includes a semiconductor base, first and second impurity regions, connected to a source line and a bit line, respectively, at both ends of the semiconductor base, and first and second gate conductor layers, one of which is connected to a word line and the other of which is connected to a plate line. Page erase, page write, and read operations are performed by controlling voltages applied to the source, bit, word, and plate lines. A first operation of outputting data of a first page to an input/output circuit via a sense amplifier circuit and a second operation of reading data of a second page of the same bank as the first page to the bit line are performed in parallel.
H10B 12/00 - Mémoires dynamiques à accès aléatoire [DRAM]
G11C 11/404 - Mémoires numériques caractérisées par l'utilisation d'éléments d'emmagasinage électriques ou magnétiques particuliers; Eléments d'emmagasinage correspondants utilisant des éléments électriques utilisant des dispositifs à semi-conducteurs utilisant des transistors formant des cellules nécessitant un rafraîchissement ou une régénération de la charge, c. à d. cellules dynamiques avec régénération de la charge commune à plusieurs cellules de mémoire, c. à d. rafraîchissement externe avec une porte à transfert de charges, p.ex. un transistor MOS, par cellule
G11C 11/4091 - Amplificateurs de lecture ou de lecture/rafraîchissement, ou circuits de lecture associés, p.ex. pour la précharge, la compensation ou l'isolation des lignes de bits couplées
G11C 11/4096 - Circuits de commande ou de gestion d'entrée/sortie [E/S, I/O] de données, p.ex. circuits pour la lecture ou l'écriture, circuits d'attaque d'entrée/sortie ou commutateurs de lignes de bits
A first N+ layer, a first P layer, a second N+ layer, a second P layer, and a third N+ layer are formed on a P layer substrate in order from below vertically, a first gate insulating layer surrounds the first P layer, a second gate insulating layer surrounds the second P layer, first and second gate conductor layers surround the first gate insulating layer, and third and fourth gate conductor layers surround the second gate insulating layer. A first wiring layer is connected to the first N+ layer, a second wiring layer is connected to the second N+ layer, and a third wiring layer is connected to the third N+ layer. The first and second gate conductor layers, the second wiring layer, and the third and fourth gate conductor layers have identical shapes in a plan view and are orthogonal to the first and third wiring layers.
H10B 12/00 - Mémoires dynamiques à accès aléatoire [DRAM]
G11C 11/404 - Mémoires numériques caractérisées par l'utilisation d'éléments d'emmagasinage électriques ou magnétiques particuliers; Eléments d'emmagasinage correspondants utilisant des éléments électriques utilisant des dispositifs à semi-conducteurs utilisant des transistors formant des cellules nécessitant un rafraîchissement ou une régénération de la charge, c. à d. cellules dynamiques avec régénération de la charge commune à plusieurs cellules de mémoire, c. à d. rafraîchissement externe avec une porte à transfert de charges, p.ex. un transistor MOS, par cellule
G11C 11/4096 - Circuits de commande ou de gestion d'entrée/sortie [E/S, I/O] de données, p.ex. circuits pour la lecture ou l'écriture, circuits d'attaque d'entrée/sortie ou commutateurs de lignes de bits
A memory device includes pages in a column direction on a substrate and memory cells in each page in a row direction in plan view. Each memory cell includes a semiconductor base, first and second impurity regions, connected to a source line and a bit line, respectively, at both ends of the semiconductor base, and first and second gate conductor layers, one of which is connected to a word line and the other of which is connected to a plate line. A continuous operation of a page erase operation and a page write operation is performed by controlling voltages applied to the source line, the bit line, the word line, and the plate line without performing a reset operation for returning the voltage applied to the plate line to a ground voltage.
H10B 12/00 - Mémoires dynamiques à accès aléatoire [DRAM]
G11C 11/404 - Mémoires numériques caractérisées par l'utilisation d'éléments d'emmagasinage électriques ou magnétiques particuliers; Eléments d'emmagasinage correspondants utilisant des éléments électriques utilisant des dispositifs à semi-conducteurs utilisant des transistors formant des cellules nécessitant un rafraîchissement ou une régénération de la charge, c. à d. cellules dynamiques avec régénération de la charge commune à plusieurs cellules de mémoire, c. à d. rafraîchissement externe avec une porte à transfert de charges, p.ex. un transistor MOS, par cellule
G11C 11/4091 - Amplificateurs de lecture ou de lecture/rafraîchissement, ou circuits de lecture associés, p.ex. pour la précharge, la compensation ou l'isolation des lignes de bits couplées
G11C 11/4096 - Circuits de commande ou de gestion d'entrée/sortie [E/S, I/O] de données, p.ex. circuits pour la lecture ou l'écriture, circuits d'attaque d'entrée/sortie ou commutateurs de lignes de bits
A memory device includes pages in a column direction on a substrate and memory cells in each page in a row direction in plan view. Each memory cell includes a semiconductor base, first and second impurity regions at both ends of the semiconductor base, and first and second gate conductor layers. A page erase operation, a page write operation, and a page read operation are performed by controlling voltages applied to the first and second impurity regions and the first and second gate conductor layers. In a first page group including at least one page, a refresh operation of increasing positive holes is performed in a memory cell storing logical data “1”. The refresh operation is performed continuously to an N-th page group.
H10B 12/00 - Mémoires dynamiques à accès aléatoire [DRAM]
G11C 11/404 - Mémoires numériques caractérisées par l'utilisation d'éléments d'emmagasinage électriques ou magnétiques particuliers; Eléments d'emmagasinage correspondants utilisant des éléments électriques utilisant des dispositifs à semi-conducteurs utilisant des transistors formant des cellules nécessitant un rafraîchissement ou une régénération de la charge, c. à d. cellules dynamiques avec régénération de la charge commune à plusieurs cellules de mémoire, c. à d. rafraîchissement externe avec une porte à transfert de charges, p.ex. un transistor MOS, par cellule
G11C 11/406 - Organisation ou commande des cycles de rafraîchissement ou de régénération de la charge
G11C 11/4091 - Amplificateurs de lecture ou de lecture/rafraîchissement, ou circuits de lecture associés, p.ex. pour la précharge, la compensation ou l'isolation des lignes de bits couplées
G11C 11/4096 - Circuits de commande ou de gestion d'entrée/sortie [E/S, I/O] de données, p.ex. circuits pour la lecture ou l'écriture, circuits d'attaque d'entrée/sortie ou commutateurs de lignes de bits
A dynamic flash memory includes a p layer as a semiconductor base material, first and second n+ layers on opposite sides thereof, first and second gate insulating layers in contact with each other and partially covering the p layer, and first and second gate conductor layers electrically isolated from each other and respectively provided on the first and second gate insulating layers. The first and second n+ layers and first and second gate conductor layers are respectively connected to source, bit, word, and plate lines. During writing, 1.0 V, 1.5 V, and 1.2 V are sequentially applied to the bit, plate, and word lines, respectively. During erasing, 2 V is applied to the plate line, and then, a voltage applied to each terminal is always set 0 V or greater (e.g., 0.6 V for the bit line). Further, during reading, voltages are sequentially applied to the bit, plate, and word lines.
H10B 12/00 - Mémoires dynamiques à accès aléatoire [DRAM]
G11C 11/404 - Mémoires numériques caractérisées par l'utilisation d'éléments d'emmagasinage électriques ou magnétiques particuliers; Eléments d'emmagasinage correspondants utilisant des éléments électriques utilisant des dispositifs à semi-conducteurs utilisant des transistors formant des cellules nécessitant un rafraîchissement ou une régénération de la charge, c. à d. cellules dynamiques avec régénération de la charge commune à plusieurs cellules de mémoire, c. à d. rafraîchissement externe avec une porte à transfert de charges, p.ex. un transistor MOS, par cellule
G11C 11/4096 - Circuits de commande ou de gestion d'entrée/sortie [E/S, I/O] de données, p.ex. circuits pour la lecture ou l'écriture, circuits d'attaque d'entrée/sortie ou commutateurs de lignes de bits
A memory device includes pages arranged in a column direction and each constituted by memory cells arranged in a row direction in plan view on a substrate, each memory cell includes a semiconductor body, first and second impurity regions, and first and second gate conductor layers, and in a page read operation, a first refresh operation of increasing by an impact ionization phenomenon, the number of positive holes in the semiconductor body of a memory cell for which page writing has been performed and a second refresh operation of decreasing the number of positive holes in the semiconductor body of a memory cell for which page writing has not been performed are performed and a third refresh operation for a memory cell, in a page, in which the logical “1” data is stored is performed by using latch data in a sense amplifier circuit.
G11C 11/403 - Mémoires numériques caractérisées par l'utilisation d'éléments d'emmagasinage électriques ou magnétiques particuliers; Eléments d'emmagasinage correspondants utilisant des éléments électriques utilisant des dispositifs à semi-conducteurs utilisant des transistors formant des cellules nécessitant un rafraîchissement ou une régénération de la charge, c. à d. cellules dynamiques avec régénération de la charge commune à plusieurs cellules de mémoire, c. à d. rafraîchissement externe
G11C 11/4096 - Circuits de commande ou de gestion d'entrée/sortie [E/S, I/O] de données, p.ex. circuits pour la lecture ou l'écriture, circuits d'attaque d'entrée/sortie ou commutateurs de lignes de bits
G11C 11/4097 - Organisation de lignes de bits, p.ex. configuration de lignes de bits, lignes de bits repliées
H10B 12/00 - Mémoires dynamiques à accès aléatoire [DRAM]
A semiconductor memory device includes a semiconductor base body (Si pillar) erected or horizontally laid on a substrate; first and second impurity regions located on opposite ends of the semiconductor base body; and gate insulating layer and first and second gate conductor layers located between the impurity regions, surrounding the semiconductor base body. By applying voltages to the impurity regions and gate conductor layers, a current is passed between the impurity regions, thereby causing impact ionization phenomenon in a semiconductor base body to generate electron groups and positive hole groups. A memory write operation is performed to remove the electron groups from the semiconductor base body and hold part of the positive hole groups in the semiconductor base body. A memory erase operation is performed by removing positive hole groups held in the semiconductor base body from the first and/or second impurity region(s). Two semiconductor elements make up one memory cell.
H10B 12/00 - Mémoires dynamiques à accès aléatoire [DRAM]
G11C 11/404 - Mémoires numériques caractérisées par l'utilisation d'éléments d'emmagasinage électriques ou magnétiques particuliers; Eléments d'emmagasinage correspondants utilisant des éléments électriques utilisant des dispositifs à semi-conducteurs utilisant des transistors formant des cellules nécessitant un rafraîchissement ou une régénération de la charge, c. à d. cellules dynamiques avec régénération de la charge commune à plusieurs cellules de mémoire, c. à d. rafraîchissement externe avec une porte à transfert de charges, p.ex. un transistor MOS, par cellule
G11C 11/4091 - Amplificateurs de lecture ou de lecture/rafraîchissement, ou circuits de lecture associés, p.ex. pour la précharge, la compensation ou l'isolation des lignes de bits couplées
G11C 11/4096 - Circuits de commande ou de gestion d'entrée/sortie [E/S, I/O] de données, p.ex. circuits pour la lecture ou l'écriture, circuits d'attaque d'entrée/sortie ou commutateurs de lignes de bits
A memory device includes pages arranged in a column direction and each constituted by memory cells arranged in a row direction on a substrate, each memory cell includes a semiconductor body, first and second impurity regions, and first and second gate conductor layers, the first and second impurity regions and first and second gate conductor layers are connected to source, bit, word, and plate lines respectively, and a page read operation includes a first refresh operation of increasing by an impact ionization phenomenon, a group of positive holes in the semiconductor body of a memory cell for which page writing has been performed and a subsequent second refresh operation of making some of a group of positive holes in the semiconductor body of a memory cell for which page writing has not been performed disappear and decreasing the number of positive holes.
H10B 12/00 - Mémoires dynamiques à accès aléatoire [DRAM]
G11C 11/404 - Mémoires numériques caractérisées par l'utilisation d'éléments d'emmagasinage électriques ou magnétiques particuliers; Eléments d'emmagasinage correspondants utilisant des éléments électriques utilisant des dispositifs à semi-conducteurs utilisant des transistors formant des cellules nécessitant un rafraîchissement ou une régénération de la charge, c. à d. cellules dynamiques avec régénération de la charge commune à plusieurs cellules de mémoire, c. à d. rafraîchissement externe avec une porte à transfert de charges, p.ex. un transistor MOS, par cellule
G11C 11/406 - Organisation ou commande des cycles de rafraîchissement ou de régénération de la charge
G11C 11/4091 - Amplificateurs de lecture ou de lecture/rafraîchissement, ou circuits de lecture associés, p.ex. pour la précharge, la compensation ou l'isolation des lignes de bits couplées
G11C 11/4096 - Circuits de commande ou de gestion d'entrée/sortie [E/S, I/O] de données, p.ex. circuits pour la lecture ou l'écriture, circuits d'attaque d'entrée/sortie ou commutateurs de lignes de bits
A memory device includes pages arranged in a column direction and each constituted by memory cells arranged in a row direction on a substrate, each memory cell includes a semiconductor body, first and second impurity regions, and first and second gate conductor layers, the first and second impurity regions and first and second gate conductor layers are connected to source, bit, word, and plate lines respectively, and voltages applied to these lines are controlled to perform an erase operation of collecting a group of positive holes in the semiconductor body of a selected memory cell in a part adjacent to the first gate conductor layer and making some of the group of positive holes disappear and a page write operation of increasing by an impact ionization phenomenon, the number of positive holes in the semiconductor body of a selected memory cell in a page.
H10B 12/00 - Mémoires dynamiques à accès aléatoire [DRAM]
G11C 11/404 - Mémoires numériques caractérisées par l'utilisation d'éléments d'emmagasinage électriques ou magnétiques particuliers; Eléments d'emmagasinage correspondants utilisant des éléments électriques utilisant des dispositifs à semi-conducteurs utilisant des transistors formant des cellules nécessitant un rafraîchissement ou une régénération de la charge, c. à d. cellules dynamiques avec régénération de la charge commune à plusieurs cellules de mémoire, c. à d. rafraîchissement externe avec une porte à transfert de charges, p.ex. un transistor MOS, par cellule
G11C 11/4091 - Amplificateurs de lecture ou de lecture/rafraîchissement, ou circuits de lecture associés, p.ex. pour la précharge, la compensation ou l'isolation des lignes de bits couplées
G11C 11/4096 - Circuits de commande ou de gestion d'entrée/sortie [E/S, I/O] de données, p.ex. circuits pour la lecture ou l'écriture, circuits d'attaque d'entrée/sortie ou commutateurs de lignes de bits
A memory apparatus includes a page including a plurality of memory cells arranged in a column on a substrate. Each of voltages applied to first and second gate conductor layers and first and second impurity layers in each memory cell included in the page is controlled to perform a page write operation of retaining holes, which have been formed through an impact ionization phenomenon or using a gate induced drain leakage current, in a semiconductor base material, or each of voltages applied to the first and second gate conductor layers, third and fourth gate conductor layers, and the first and second impurity layers is controlled to perform a page erase operation of removing the holes from the semiconductor base material, and further lowering a voltage of the semiconductor base material through capacitive coupling with the first gate conductor layer and the second gate conductor layer.
A semiconductor element memory device includes a first block including first memory cells arranged in a matrix, and/or a second block including second memory cells each formed of two memory cells. The memory device is configured to perform a data hold operation of controlling voltages to be applied to plate lines, word lines, a source line, odd-numbered bit lines, and even-numbered bit lines to hold, in a semiconductor base, a positive hole group generated by an impact ionization phenomenon or a gate-induced drain leakage current, and a data erase operation of controlling voltages to be applied to the plate lines, the word lines, the source line, the odd-numbered bit lines, and the even-numbered bit lines to discharge the positive hole group from the semiconductor base. The number of first blocks and the number of second blocks are variable in the memory device that is in operation.
G11C 11/4096 - Circuits de commande ou de gestion d'entrée/sortie [E/S, I/O] de données, p.ex. circuits pour la lecture ou l'écriture, circuits d'attaque d'entrée/sortie ou commutateurs de lignes de bits
G11C 11/4091 - Amplificateurs de lecture ou de lecture/rafraîchissement, ou circuits de lecture associés, p.ex. pour la précharge, la compensation ou l'isolation des lignes de bits couplées
G11C 11/4094 - Circuits de commande ou de gestion de lignes de bits
A memory device includes pages each constituted by a plurality of memory cells arranged in columns on a substrate, voltages applied to a first gate conductor layer, a second gate conductor layer, a first impurity region, and a second impurity region in each memory cell included in each page are controlled to perform a page write operation of retaining a group of positive holes, generated by an impact ionization phenomenon or a gate-induced drain leakage current, inside a semiconductor body, the voltages applied to the first gate conductor layer, the second gate conductor layer, the first impurity region, and the second impurity region are controlled to perform a page erase operation of discharging the group of positive holes from inside the semiconductor body and further lowering a voltage of the semiconductor body with capacitive coupling with the first gate conductor layer and with the second gate conductor layer, and in the page erase operation, at least two or more pages are simultaneously selected from among the pages and the page erase operation is performed.
G11C 11/4096 - Circuits de commande ou de gestion d'entrée/sortie [E/S, I/O] de données, p.ex. circuits pour la lecture ou l'écriture, circuits d'attaque d'entrée/sortie ou commutateurs de lignes de bits
H10B 12/00 - Mémoires dynamiques à accès aléatoire [DRAM]
G11C 11/4097 - Organisation de lignes de bits, p.ex. configuration de lignes de bits, lignes de bits repliées
A dynamic flash memory includes a p layer as a semiconductor base material; first and second n+ layers extending on opposite sides thereof; a first gate insulating layer partially covering the p layer; a first gate conductor layer provided thereon; a second gate insulating layer provided in contact with the first gate insulating layer and partially covering the p layer; and a second gate conductor layer provided on the second gate insulating layer and electrically isolated from the first gate conductor layer. The first and second n+ layers, and the first and second gate conductor layers are respectively connected to a source line, a bit line, a word line, and a plate line. A voltage applied to each terminal during memory erasing is always greater than or equal to 0 V such that 2 V and 0.6 V are respectively applied to the plate line and the bit line.
G11C 11/4096 - Circuits de commande ou de gestion d'entrée/sortie [E/S, I/O] de données, p.ex. circuits pour la lecture ou l'écriture, circuits d'attaque d'entrée/sortie ou commutateurs de lignes de bits
H10B 12/00 - Mémoires dynamiques à accès aléatoire [DRAM]
H01L 29/423 - Electrodes caractérisées par leur forme, leurs dimensions relatives ou leur disposition relative ne transportant pas le courant à redresser, à amplifier ou à commuter
A memory device includes pages each including memory cells arranged in columns in plan view on a substrate, and voltages applied to first and second gate conductor layers and first and second impurity regions in each memory cell are controlled to retain a group of positive holes, generated by an impact ionization phenomenon, inside a semiconductor body. The first and second impurity regions are connected to source and bit lines, the first and second gate conductor layers are connected to word and plate lines, and voltages applied to these lines are controlled to perform a page write operation, a page erase operation, and a page read operation. In the page write operation, the group of positive holes are retained inside the semiconductor body at a first time, and a page write post-processing operation of making a group of excess positive holes disappear is performed at a second time.
G11C 11/4096 - Circuits de commande ou de gestion d'entrée/sortie [E/S, I/O] de données, p.ex. circuits pour la lecture ou l'écriture, circuits d'attaque d'entrée/sortie ou commutateurs de lignes de bits
G11C 11/4091 - Amplificateurs de lecture ou de lecture/rafraîchissement, ou circuits de lecture associés, p.ex. pour la précharge, la compensation ou l'isolation des lignes de bits couplées
H10B 12/00 - Mémoires dynamiques à accès aléatoire [DRAM]
17.
METHOD FOR PRODUCING MEMORY DEVICE USING PILLAR-SHAPED SEMICONDUCTOR ELEMENTS
Provided is dynamic flash memory for performing data write, read, and erase operations by controlling a voltage applied to each of a source line, a plate line, word lines, and bit lines. The memory is formed by forming on a substrate a first N+ layer, which connects to the source line, and second N+ layers, which connect to the bit lines, at opposite ends of Si pillars standing is the upright position along the vertical direction; and forming a SiO2 layer, which is located between a first TiN layer surrounding a first gate HfO2 layer surrounding the lower portion of the Si pillars, is continuous around the Si pillars, and connects to the plate line, and second TiN layers surrounding a second gate HfO2 layer surrounding the upper portion of the Si pillars and respectively connecting to the word lines, by oxidizing a doped semiconductor layer or conductor layer.
H10B 12/00 - Mémoires dynamiques à accès aléatoire [DRAM]
G11C 11/404 - Mémoires numériques caractérisées par l'utilisation d'éléments d'emmagasinage électriques ou magnétiques particuliers; Eléments d'emmagasinage correspondants utilisant des éléments électriques utilisant des dispositifs à semi-conducteurs utilisant des transistors formant des cellules nécessitant un rafraîchissement ou une régénération de la charge, c. à d. cellules dynamiques avec régénération de la charge commune à plusieurs cellules de mémoire, c. à d. rafraîchissement externe avec une porte à transfert de charges, p.ex. un transistor MOS, par cellule
G11C 11/4096 - Circuits de commande ou de gestion d'entrée/sortie [E/S, I/O] de données, p.ex. circuits pour la lecture ou l'écriture, circuits d'attaque d'entrée/sortie ou commutateurs de lignes de bits
A first Si pillar and a second Si pillar are disposed above a substrate. The first Si pillar stands in a perpendicular direction. In plan view, the outer periphery line of the second Si pillar is located inside the outer periphery line of the first Si pillar. An N+ layer connected to a source line and an N+ layer connected to a bit line are disposed at both ends of the first and second Si pillars. A first gate insulating layer surrounds the first Si pillar. A first gate conductor layer surrounds the first gate insulating layer and is connected to a plate line. A second gate conductor layer surrounds a gate HfO2 layer surrounding the second Si pillar and is connected to a word line. Voltages applied to the source line, the plate line, the word line, and the bit line are controlled to perform a data hold operation of holding a group of holes generated by an impact ionization phenomenon or a gateinduced drain leakage current in a channel region of the Si pillar and a data erase operation of discharging the group of holes from the channel region.
H10B 12/00 - Mémoires dynamiques à accès aléatoire [DRAM]
G11C 11/4096 - Circuits de commande ou de gestion d'entrée/sortie [E/S, I/O] de données, p.ex. circuits pour la lecture ou l'écriture, circuits d'attaque d'entrée/sortie ou commutateurs de lignes de bits
H01L 29/10 - Corps semi-conducteurs caractérisés par les formes, les dimensions relatives, ou les dispositions des régions semi-conductrices avec des régions semi-conductrices connectées à une électrode ne transportant pas le courant à redresser, amplifier ou commuter, cette électrode faisant partie d'un dispositif à semi-conducteur qui comporte trois électrodes ou plus
H01L 29/423 - Electrodes caractérisées par leur forme, leurs dimensions relatives ou leur disposition relative ne transportant pas le courant à redresser, à amplifier ou à commuter
H01L 29/78 - Transistors à effet de champ l'effet de champ étant produit par une porte isolée
A memory device according to the present invention includes memory cells each of which is formed of a semiconductor body that stands on a substrate in a vertical direction relative to the substrate, voltages applied to a first gate conductor layer, a second gate conductor layer, a first impurity region, and a second impurity region of the memory cell are controlled to perform a write operation of retaining a group of positive holes, generated by an impact ionization phenomenon or a gate-induced drain leakage current, inside a semiconductor body, and the voltages applied to the first gate conductor layer, the second gate conductor layer, the first impurity region, and the second impurity region are controlled to perform an erase operation of discharging the group of positive holes from inside the semiconductor body. The first impurity region of the memory cell is connected to a source line wiring layer, the second impurity region thereof is connected to a bit line wiring layer, one of the first gate conductor layer or the second gate conductor layer thereof is connected to a word line wiring layer, and the other of the first gate conductor layer or the second gate conductor layer is connected to a first driving control line wiring layer, and in the vertical direction relative to the substrate, the source line wiring layer is connected to the first impurity region at a position lower than the first driving control line wiring layer and the word line wiring layer.
H10B 12/00 - Mémoires dynamiques à accès aléatoire [DRAM]
G11C 11/404 - Mémoires numériques caractérisées par l'utilisation d'éléments d'emmagasinage électriques ou magnétiques particuliers; Eléments d'emmagasinage correspondants utilisant des éléments électriques utilisant des dispositifs à semi-conducteurs utilisant des transistors formant des cellules nécessitant un rafraîchissement ou une régénération de la charge, c. à d. cellules dynamiques avec régénération de la charge commune à plusieurs cellules de mémoire, c. à d. rafraîchissement externe avec une porte à transfert de charges, p.ex. un transistor MOS, par cellule
G11C 11/4096 - Circuits de commande ou de gestion d'entrée/sortie [E/S, I/O] de données, p.ex. circuits pour la lecture ou l'écriture, circuits d'attaque d'entrée/sortie ou commutateurs de lignes de bits
A semiconductor element memory device is configured to perform a data hold operation of controlling voltages to be applied to a plate line, a word line, a source line, and a bit line to hold, in a semiconductor base, a positive hole group formed by an impact ionization phenomenon or a gate-induced drain leakage current, and a data erase operation of controlling voltages to be applied to the plate line, the word line, the source line, and the bit line to discharge the positive hole group from the semiconductor base. The semiconductor element memory device includes a plurality of memory cells arranged in a matrix within a block, and constantly manages, using a controller circuit and a logical/physical conversion table, which physical block address of a dynamic flash memory corresponds to data stored in a logical block address.
H10B 12/00 - Mémoires dynamiques à accès aléatoire [DRAM]
G11C 11/404 - Mémoires numériques caractérisées par l'utilisation d'éléments d'emmagasinage électriques ou magnétiques particuliers; Eléments d'emmagasinage correspondants utilisant des éléments électriques utilisant des dispositifs à semi-conducteurs utilisant des transistors formant des cellules nécessitant un rafraîchissement ou une régénération de la charge, c. à d. cellules dynamiques avec régénération de la charge commune à plusieurs cellules de mémoire, c. à d. rafraîchissement externe avec une porte à transfert de charges, p.ex. un transistor MOS, par cellule
G11C 11/4096 - Circuits de commande ou de gestion d'entrée/sortie [E/S, I/O] de données, p.ex. circuits pour la lecture ou l'écriture, circuits d'attaque d'entrée/sortie ou commutateurs de lignes de bits
G06F 12/02 - Adressage ou affectation; Réadressage
A memory device includes pages arranged in columns and each constituted by a plurality of memory cells on a substrate, voltages applied to a first gate conductor layer, a second gate conductor layer, a first impurity region, and a second impurity region in each memory cell included in each of the pages are controlled to perform a page write operation of retaining, inside a channel semiconductor layer, a group of positive holes generated by an impact ionization phenomenon or by a gate-induced drain leakage current, and the voltages applied to the first gate conductor layer, the second gate conductor layer, the third gate conductor layer, the fourth gate conductor layer, the first impurity region, and the second impurity region are controlled to perform a page erase operation of discharging the group of positive holes from inside the channel semiconductor layer. The first impurity layer of the memory cell is connected to a source line, the second impurity layer thereof is connected to a bit line, one of the first gate conductor layer or the second gate conductor layer thereof is connected to a word line, and the other of the first gate conductor layer or the second gate conductor layer thereof is connected to a first driving control line. In a page read operation, page data in a group of memory cells selected by the word line is read to sense amplifier circuits, and in at least one operation among the page write operation, the page erase operation, and the page read operation, a voltage applied to at least one of the source line, the bit line, the word line, or the first driving control line is controlled by a reference voltage generating circuit combined with a temperature-compensating circuit.
There is provided a columnar semiconductor memory device in which a data retention operation is performed in which voltages applied to a first gate conductor layer, a second gate conductor layer, a first impurity region, and a second impurity region are controlled to retain a group of positive holes, generated by an impact ionization phenomenon or a gate-induced drain leakage current, inside a semiconductor body, and a data erase operation is performed in which the voltages applied to the first gate conductor layer, the second gate conductor layer, the first impurity region, and the second impurity region are controlled to discharge the group of positive holes from inside the semiconductor body and the voltage of the semiconductor body is lowered with capacitive coupling with the first gate conductor layer and capacitive coupling with the second gate conductor layer.
G11C 11/4096 - Circuits de commande ou de gestion d'entrée/sortie [E/S, I/O] de données, p.ex. circuits pour la lecture ou l'écriture, circuits d'attaque d'entrée/sortie ou commutateurs de lignes de bits
A data retention operation of holding positive hole groups generated by an impact ionization phenomenon or by a gate-induced drain leakage current in a semiconductor base body is performed by controlling voltages applied to plate lines, word lines, a source line, odd-numbered bit lines, and even-numbered bit lines; and a data erase operation is performed by removing positive hole groups from inside the semiconductor base body by controlling the voltages applied to plate lines, word lines, source line, odd-numbered bit lines, and even-numbered bit lines and lowering a voltage of The semiconductor base body by means of capacitive coupling between the plate lines and word lines. A block is made up of memory cells arrayed in a matrix, and storage data is read from the memory cells in the block alternately to the odd-numbered bit lines and even-numbered bit line.
H10B 12/00 - Mémoires dynamiques à accès aléatoire [DRAM]
G11C 11/404 - Mémoires numériques caractérisées par l'utilisation d'éléments d'emmagasinage électriques ou magnétiques particuliers; Eléments d'emmagasinage correspondants utilisant des éléments électriques utilisant des dispositifs à semi-conducteurs utilisant des transistors formant des cellules nécessitant un rafraîchissement ou une régénération de la charge, c. à d. cellules dynamiques avec régénération de la charge commune à plusieurs cellules de mémoire, c. à d. rafraîchissement externe avec une porte à transfert de charges, p.ex. un transistor MOS, par cellule
G11C 11/4091 - Amplificateurs de lecture ou de lecture/rafraîchissement, ou circuits de lecture associés, p.ex. pour la précharge, la compensation ou l'isolation des lignes de bits couplées
G11C 11/4096 - Circuits de commande ou de gestion d'entrée/sortie [E/S, I/O] de données, p.ex. circuits pour la lecture ou l'écriture, circuits d'attaque d'entrée/sortie ou commutateurs de lignes de bits
A semiconductor-element-including semiconductor memory device includes a block in which a plurality of memory cells CL00 to CL13 are arranged in a matrix, in which a data retention operation is performed in which voltages applied to plate lines PL0 and PL1, word lines WL0 and WL1, a source line SL, and bit lines BL0 to BL3 are controlled to retain a group of positive holes, generated by an impact ionization phenomenon or a gate-induced drain leakage current, inside a semiconductor body, and a data erase operation is performed in which the voltages applied to the plate lines PL0 and PL1, the word lines WL0 and WL1, the source line SL, and the bit lines BL0 to BL3 are controlled to discharge the group of positive holes from inside the semiconductor body and the voltage of the semiconductor body is lowered with capacitive coupling with the plate lines PL0 and PL1 and capacitive coupling with the word lines WL0 and WL1. For the memory cells in the block, one or both of a memory re-write operation for the memory cells CL00, CL02, CL03, CL11, and CL13 that are in a state of the data retention operation and a memory re-erase operation for the memory cells CL01, CL10, and CL12 in a state of the data erase operation are performed for all of the memory cells in the block simultaneously.
G11C 16/16 - Circuits pour effacer électriquement, p.ex. circuits de commutation de la tension d'effacement pour effacer des blocs, p.ex. des réseaux, des mots, des groupes
G11C 16/12 - Circuits de commutation de la tension de programmation
G11C 16/10 - Circuits de programmation ou d'entrée de données
A memory device uses semiconductor elements. By controlling voltages applied to plate lines, word lines, source lines, and bit lines, the memory device performs a data write operation of holding positive hole groups formed by an impact ionization phenomenon or by a gate-induced drain leakage current in a semiconductor base material, and a data erase operation of removing positive hole groups from inside the semiconductor base material. The memory device includes a block made up of memory cells, which are arrayed in a matrix. Storage data of memory cells connected with a first word line, i.e., a selected one of the word lines, in the block is read to the bit lines by applying a first voltage to the first word line, and a second voltage to a second word line adjacent to the first word line.
G11C 11/4096 - Circuits de commande ou de gestion d'entrée/sortie [E/S, I/O] de données, p.ex. circuits pour la lecture ou l'écriture, circuits d'attaque d'entrée/sortie ou commutateurs de lignes de bits
G11C 11/4094 - Circuits de commande ou de gestion de lignes de bits
G11C 11/4091 - Amplificateurs de lecture ou de lecture/rafraîchissement, ou circuits de lecture associés, p.ex. pour la précharge, la compensation ou l'isolation des lignes de bits couplées
26.
SEMICONDUCTOR ELEMENT MEMORY CELL AND SEMICONDUCTOR ELEMENT MEMORY DEVICE
By controlling voltages applied to plate lines, word lines, source lines, and bit lines, a memory device that uses semiconductor elements performs a data retention operation of holding positive hole groups formed by an impact ionization phenomenon or by a gate-induced drain leakage current in a semiconductor base material, and a memory erase operation of removing positive hole groups from inside the semiconductor base material. The memory device also performs a data erase operation during the memory erase operation to remove positive hole groups from inside the semiconductor base material of all the memory cells in a block made up of the memory cells, which are arrayed in a matrix.
G11C 11/4096 - Circuits de commande ou de gestion d'entrée/sortie [E/S, I/O] de données, p.ex. circuits pour la lecture ou l'écriture, circuits d'attaque d'entrée/sortie ou commutateurs de lignes de bits
H10B 12/00 - Mémoires dynamiques à accès aléatoire [DRAM]
A memory apparatus includes a page including a plurality of memory cells arranged in a column on a substrate. Each of voltages applied to first and second gate conductor layers and first and second impurity layers in each memory cell included in the page is controlled to perform a page write operation of retaining holes, which have been formed through an impact ionization phenomenon or using a gate induced drain leakage current, in a semiconductor base material, or each of voltages applied to the first and second gate conductor layers, third and fourth gate conductor layers, and the first and second impurity layers is controlled to perform a page erase operation of removing the holes from the semiconductor base material, and to input page data for the page write operation to a sense amplifier circuit during the page erase operation.
H10B 12/00 - Mémoires dynamiques à accès aléatoire [DRAM]
G11C 11/404 - Mémoires numériques caractérisées par l'utilisation d'éléments d'emmagasinage électriques ou magnétiques particuliers; Eléments d'emmagasinage correspondants utilisant des éléments électriques utilisant des dispositifs à semi-conducteurs utilisant des transistors formant des cellules nécessitant un rafraîchissement ou une régénération de la charge, c. à d. cellules dynamiques avec régénération de la charge commune à plusieurs cellules de mémoire, c. à d. rafraîchissement externe avec une porte à transfert de charges, p.ex. un transistor MOS, par cellule
G11C 11/4096 - Circuits de commande ou de gestion d'entrée/sortie [E/S, I/O] de données, p.ex. circuits pour la lecture ou l'écriture, circuits d'attaque d'entrée/sortie ou commutateurs de lignes de bits
A memory device includes pages including memory cells arranged on a substrate. Voltages applied to first and second gate conductor layers and first and second impurity regions in each memory cell are controlled to retain a group of positive holes. The first and second impurity regions and first and second gate conductor layers are connected to source, bit, plate, and word lines. In a page write operation, a channel semiconductor layer is at a first data retention voltage. In a page erase operation, the group of positive holes are discharged by controlling the voltages, the channel semiconductor layer is at a second data retention voltage, a positive voltage pulse is applied to at least one of the word and plate lines of a selected page, and a ground voltage is applied to the word and plate lines of a non-selected page and to all of the source and bit lines.
G11C 11/4097 - Organisation de lignes de bits, p.ex. configuration de lignes de bits, lignes de bits repliées
H10B 12/00 - Mémoires dynamiques à accès aléatoire [DRAM]
G11C 11/4091 - Amplificateurs de lecture ou de lecture/rafraîchissement, ou circuits de lecture associés, p.ex. pour la précharge, la compensation ou l'isolation des lignes de bits couplées
G11C 11/4096 - Circuits de commande ou de gestion d'entrée/sortie [E/S, I/O] de données, p.ex. circuits pour la lecture ou l'écriture, circuits d'attaque d'entrée/sortie ou commutateurs de lignes de bits
29.
PILLAR-SHAPED SEMICONDUCTOR MEMORY DEVICE AND MANUFACTURING METHOD THEREOF
A contact hole is formed on a boundary region between an N+ layer connected to a bottom part of a Si pillar forming a select transistor SGT and a P+ layer connected to a bottom part of a Si pillar forming a load transistor SGT on an X-X′ line and on a gate TiN layer surrounding a Si pillar forming a load transistor SGT on an XX-XX′ line in an SRAM cell. A conductor W layer is formed in a bottom part of the contact hole. A SiO2 layer including a hole is formed inside the contact hole on the W layer.
H10B 10/00 - Mémoires statiques à accès aléatoire [SRAM]
H01L 29/423 - Electrodes caractérisées par leur forme, leurs dimensions relatives ou leur disposition relative ne transportant pas le courant à redresser, à amplifier ou à commuter
30.
MANUFACTURING METHOD OF PILLAR-SHAPED SEMICONDUCTOR DEVICE
P+ layers which entirely cover top parts of Si pillars and which surround the Si pillars at equal widths in a plan view are formed by self-alignment with the Si pillars, W layers are formed on the P+ layers, a band-shaped contact hole which is in contact with respective partial regions of the W layers and which extends in the Y direction is formed, and a supply wiring metal layer is formed by filling the band-shaped contact hole. The partial regions of the W layers are shaped so as to protrude to outside of the band-shaped contact hole in a plan view.
H01L 29/423 - Electrodes caractérisées par leur forme, leurs dimensions relatives ou leur disposition relative ne transportant pas le courant à redresser, à amplifier ou à commuter
H10B 10/00 - Mémoires statiques à accès aléatoire [SRAM]
H01L 29/66 - Types de dispositifs semi-conducteurs
31.
PILLAR-SHAPED SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD THEREOF
In a method of forming a gate conductor layer which surrounds a semiconductor pillar, a first impurity region and a first mask material layer having oxidation resistance are respectively formed in a top part of a semiconductor pillar and on a side wall of the semiconductor pillar, thermal or chemical oxidation is performed on the entire stack, a first insulation layer is formed on the exposed surface of the first impurity region, the first mask material layer is removed, and a gate conductor layer is formed in an upper part of the first insulation layer.
H10B 10/00 - Mémoires statiques à accès aléatoire [SRAM]
H01L 29/423 - Electrodes caractérisées par leur forme, leurs dimensions relatives ou leur disposition relative ne transportant pas le courant à redresser, à amplifier ou à commuter
H01L 29/36 - Corps semi-conducteurs caractérisés par la concentration ou la distribution des impuretés
A p layer extending in a direction horizontal to a substrate is provided separately from the substrate. An n+ layer and an n layer are provided on respective sides of the layer. A gate insulating layer partially covers the layers. A gate conductor layer partially covers the layer. A gate insulating layer partially covering the layer is provided separately from the layer. A gate conductor layer partially covers the layer. An n+ layer is provided at part of the p layer between the layers. The layers are connected to a bit line, a control line, a word line, a plate line, and a source line, respectively. Memory operation of a dynamic flash memory cell is performed by manipulating voltage of each line.
H10B 12/00 - Mémoires dynamiques à accès aléatoire [DRAM]
G11C 11/404 - Mémoires numériques caractérisées par l'utilisation d'éléments d'emmagasinage électriques ou magnétiques particuliers; Eléments d'emmagasinage correspondants utilisant des éléments électriques utilisant des dispositifs à semi-conducteurs utilisant des transistors formant des cellules nécessitant un rafraîchissement ou une régénération de la charge, c. à d. cellules dynamiques avec régénération de la charge commune à plusieurs cellules de mémoire, c. à d. rafraîchissement externe avec une porte à transfert de charges, p.ex. un transistor MOS, par cellule
G11C 11/4096 - Circuits de commande ou de gestion d'entrée/sortie [E/S, I/O] de données, p.ex. circuits pour la lecture ou l'écriture, circuits d'attaque d'entrée/sortie ou commutateurs de lignes de bits
A p layer is a semiconductor base material. An n+ layer is disposed on one extension side. An n+ layer is disposed on the opposite side in contact with the p layer. A gate insulating layer partially covers the p layer. A first gate conductor layer contacts the insulating layer. A second gate conductor layer is electrically separated from the first gate conductor layer. Memory operation is performed by applying voltage to each of the layers. In the operation, the quotient of the impurity concentration of a region and the gate capacitance of a MOS structure constituted by the layers per unit area is larger than the quotient of the impurity concentration of a region and the gate capacitance of a MOS structure constituted by the layers per unit area.
A p layer is a semiconductor base material. An n+ layer is disposed on one extension side of the layer. An n+ layer is disposed on the opposite side in contact with the layer. A gate insulating layer partially covers the layers. A gate conductor layer is disposed in contact with the layer. A gate insulating layer partially covers the layers. A gate conductor layer is disposed in electrical separation from the layer. Memory operation is performed by applying voltage to each of the layers. In this case, the gate capacitance of a MOS structure constituted by the layers per unit area is smaller than that of a MOS structure constituted by the layers.
H10B 12/00 - Mémoires dynamiques à accès aléatoire [DRAM]
G11C 11/404 - Mémoires numériques caractérisées par l'utilisation d'éléments d'emmagasinage électriques ou magnétiques particuliers; Eléments d'emmagasinage correspondants utilisant des éléments électriques utilisant des dispositifs à semi-conducteurs utilisant des transistors formant des cellules nécessitant un rafraîchissement ou une régénération de la charge, c. à d. cellules dynamiques avec régénération de la charge commune à plusieurs cellules de mémoire, c. à d. rafraîchissement externe avec une porte à transfert de charges, p.ex. un transistor MOS, par cellule
G11C 11/4096 - Circuits de commande ou de gestion d'entrée/sortie [E/S, I/O] de données, p.ex. circuits pour la lecture ou l'écriture, circuits d'attaque d'entrée/sortie ou commutateurs de lignes de bits
On a substrate Sub, a semiconductor base material (Si pillar) that stands on the substrate in a vertical direction or that extends along the substrate in a horizontal direction a first impurity layer and a second impurity layer that are disposed on respective ends of the semiconductor base material, a first gate conductor layer, and a second gate conductor layer that surround the semiconductor base material between the first impurity layer and the second impurity layer, and a channel semiconductor layer are disposed. Voltages are applied to perform a memory write operation of discharging a group of electrons from the channel semiconductor layer and retaining some of a group of positive holes in the channel semiconductor layer generated inside the channel semiconductor layer by a gate-induced drain leakage current, and a memory erase operation of discharging the group of positive holes retained in the channel semiconductor layer.
H10B 12/00 - Mémoires dynamiques à accès aléatoire [DRAM]
G11C 11/404 - Mémoires numériques caractérisées par l'utilisation d'éléments d'emmagasinage électriques ou magnétiques particuliers; Eléments d'emmagasinage correspondants utilisant des éléments électriques utilisant des dispositifs à semi-conducteurs utilisant des transistors formant des cellules nécessitant un rafraîchissement ou une régénération de la charge, c. à d. cellules dynamiques avec régénération de la charge commune à plusieurs cellules de mémoire, c. à d. rafraîchissement externe avec une porte à transfert de charges, p.ex. un transistor MOS, par cellule
G11C 11/4096 - Circuits de commande ou de gestion d'entrée/sortie [E/S, I/O] de données, p.ex. circuits pour la lecture ou l'écriture, circuits d'attaque d'entrée/sortie ou commutateurs de lignes de bits
A p layer extending in a direction horizontal to a substrate is provided separately from the substrate. An n+ layer is provided on one side of the layer. A gate insulating layer partially covers the layers. A gate conductor layer partially covers the layer. A gate insulating layer partially covering the layer is provided separately from the layer. A gate conductor layer partially covers the layer. An n+ layer is provided at part of the p layer between the layers. The layers are connected to a bit line, a source line, a word line, and a plate line, respectively. Memory operation of a dynamic flash memory cell is performed by manipulating voltage of each line.
An N+ layer 11a connected to a source line SL, N+ layers 13a and 13c connected to a bit line BL1, and N+ layers 13b and 13d connected to a bit line BL2 are formed at both ends of Si pillars 12a to 12d standing on a substrate 10 in a perpendicular direction. Also formed are a TiN layer 18 surrounding a gate HfO2 layer surrounding the Si pillars 12a to 12d, the TiN layer 18 extending between the Si pillars 12a to 12d and connected to a plate line PL, and TiN layers 26a and 26b surrounding a gate HfO2 layer 17b surrounding the Si pillars 12a to 12d, the TiN layer 26a extending between the Si pillars 12a and 12b and connected to a word line WL1, the TiN layer 26b extending between the Si pillars 12c and 12d and connected to a word line WL2. The voltages applied to the source line SL, the plate line PL, the word lines WL1 and WL2, and the bit lines BL1 and BL2 are controlled to perform a data holding operation of holding a group of holes generated by an impact ionization phenomenon or a gate-induced drain leakage current in any or all of the Si pillars 12a to 12d and a data erase operation of removing the group of holes from the Si pillars 12a to 12d.
H10B 12/00 - Mémoires dynamiques à accès aléatoire [DRAM]
G11C 5/06 - Dispositions pour interconnecter électriquement des éléments d'emmagasinage
G11C 11/4096 - Circuits de commande ou de gestion d'entrée/sortie [E/S, I/O] de données, p.ex. circuits pour la lecture ou l'écriture, circuits d'attaque d'entrée/sortie ou commutateurs de lignes de bits
H01L 29/78 - Transistors à effet de champ l'effet de champ étant produit par une porte isolée
H01L 29/49 - Electrodes du type métal-isolant-semi-conducteur
H01L 29/51 - Matériaux isolants associés à ces électrodes
A first insulating layer 21 is disposed on a substrate 20. N+ layers 2 are separated from the insulating layer and in directions horizontal and vertical to the substrate. P layers 1 contact the n+ layers 2 and extend in the horizontal direction. N+ layers 3 contact the p layers 1. Gate insulating layers 4 cover the p layers 1 and part of the n+ layers 2 and 3. Second gate conductor layers 6 are electrically separated from a first gate conductor layer 5 contacting the gate insulating layers 4. A conductor layer 12 contacts the n+ layers 2. A conductor layer 13 contacts the n+ layers 3. A second insulating layer 22 contacts the first gate conductor layer 5, the n+ layers 2, and the conductor layer 12. A third insulating layer 23 contacts the second gate conductor layers 6, the n+ layers 3, and the conductor layer 13.
A memory device includes pages each including memory cells arranged on a substrate. Voltages applied to first and second gate conductor layers and first and second impurity layers in each memory cell are controlled to retain a group of positive holes. In a page write operation, a voltage of the channel semiconductor layer is made equal to a first data retention voltage. In a page erase operation, the group of positive holes are discharged by controlling the voltages, the voltage of the channel semiconductor layer is made equal to a second data retention voltage, and erase and ground voltages are applied to selected and non-selected pages respectively. The first and second impurity layers and first and second gate conductor layers are connected to source, bit, plate, and word lines. The source, word, and plate lines are disposed parallel to the pages. The bit line is disposed perpendicular to the pages.
H10B 12/00 - Mémoires dynamiques à accès aléatoire [DRAM]
G11C 11/404 - Mémoires numériques caractérisées par l'utilisation d'éléments d'emmagasinage électriques ou magnétiques particuliers; Eléments d'emmagasinage correspondants utilisant des éléments électriques utilisant des dispositifs à semi-conducteurs utilisant des transistors formant des cellules nécessitant un rafraîchissement ou une régénération de la charge, c. à d. cellules dynamiques avec régénération de la charge commune à plusieurs cellules de mémoire, c. à d. rafraîchissement externe avec une porte à transfert de charges, p.ex. un transistor MOS, par cellule
G11C 11/4091 - Amplificateurs de lecture ou de lecture/rafraîchissement, ou circuits de lecture associés, p.ex. pour la précharge, la compensation ou l'isolation des lignes de bits couplées
G11C 11/4096 - Circuits de commande ou de gestion d'entrée/sortie [E/S, I/O] de données, p.ex. circuits pour la lecture ou l'écriture, circuits d'attaque d'entrée/sortie ou commutateurs de lignes de bits
Si bodies 24aa to 24ad, 24ba to 24bd, and 45a to 45d are disposed parallel to a substrate 20 and are adjacent to each other in a horizontal direction at regular intervals. A HfO2 layer 27b surrounds the Si bodies 24aa to 45d. TiN layers 34a to 34d surround the HfO2 layer 27b, are isolated from each other, and are each formed of portions contiguous in the horizontal direction. The Si bodies 45a to 45d are formed stepwise in cross-sectional view in the terminating end in the horizontal direction. Metal wiring layers 52a to 52d are connected to the TiN layers 34a to 34d and extend up to above an insulating layer 50 through contact holes 51a to 51d extending in a vertical direction from the terminating ends of the TiN layers 34a to 34d. The metal wiring layers 52a to 52d are connected to word lines WL1 to WL4.
On P layer bases extending in a band shape in a first direction in plan view, N+ layers also extending in a band shape in the first direction and Si pillars are formed. Subsequently, a gate insulating layer and gate conductor layers are formed so as to surround the Si pillars. Subsequently, contact holes whose bottom portions are in contact with the N+ layers are formed in an insulating layer, and first conductor W layers are formed at the bottom portions of the contact holes. Subsequently, insulating layers each having a hole are formed in the contact holes. Subsequently, a second conductor W layer is formed in a second direction perpendicular to the first direction so as to be connected to the gate conductor layers.
On a semiconductor base that extends in a band shape in a direction (first direction) perpendicular to a line X-X′ direction (second direction) in plan view, an N+ layer, a P+ layer, and Si pillars that also extend in a band shape in the first direction are formed. Subsequently, a gate insulating layer and gate conductor layers are formed so as to surround the Si pillars. Subsequently, a contact hole whose bottom portion is in contact with the N+ layer and the P+ layer is formed in an insulating layer, and a first conductor W layer is formed at the bottom portion of the contact hole. Subsequently, an insulating layer that has a hole is formed in the contact hole. Subsequently, a second conductor W layer is formed in the line X-X′ direction so as to be connected to the gate conductor layers.
H01L 29/423 - Electrodes caractérisées par leur forme, leurs dimensions relatives ou leur disposition relative ne transportant pas le courant à redresser, à amplifier ou à commuter
H01L 27/088 - Dispositifs consistant en une pluralité de composants semi-conducteurs ou d'autres composants à l'état solide formés dans ou sur un substrat commun comprenant des éléments de circuit passif intégrés avec au moins une barrière de potentiel ou une barrière de surface le substrat étant un corps semi-conducteur comprenant uniquement des composants semi-conducteurs d'un seul type comprenant uniquement des composants à effet de champ les composants étant des transistors à effet de champ à porte isolée
H01L 29/06 - Corps semi-conducteurs caractérisés par les formes, les dimensions relatives, ou les dispositions des régions semi-conductrices
A dynamic flash memory cell and a fin transistor are formed on a P layer substrate 10a. The dynamic flash memory cell includes a first insulating layer 11a, a fin P layer 25, N+ layers 35ba and 35bb, a gate insulating layer 27b, and gate conductor layers 30ba and 30bb; the fin transistor includes a fin P layer 22 including fin P layers 15a and 15b, N+ layers 35aa and 35ab, a gate insulating layer 27a, and a gate conductor layer 30a; in a perpendicular direction, a top portion of the fin P layer 25 is positioned close to or higher than a top portion of the fin P layer 15a, bottom portions of the gate insulating layers 27a and 27b are positioned close to each other, and a bottom portion of the fin semiconductor layer 15b is positioned within the P layer substrate 10a.
Provided on a substrate are a first insulating layer; a first metal wire layer embedded therein; a second metal wire layer extending vertically on the first metal wire layer; a first n+ layer on the second metal wire layer, a semiconductor p layer on the first n+ layer, and a second n+ layer on the semiconductor p layer, each extending vertically; a gate insulating layer partially covering them; first and second electrically isolated gate conductor layers around the gate insulating layer; a second insulating layer partially covering the first and second n+ layers and the first and second gate conductor layers; a third insulating layer on the second insulating layer, partially covering the second n+ layer and the second gate conductor layer; and a fourth metal wire layer connecting to the second n+ layer via a contact hole. A fifth metal wire layer connects to the second gate conductor layer.
H10B 12/00 - Mémoires dynamiques à accès aléatoire [DRAM]
G11C 11/404 - Mémoires numériques caractérisées par l'utilisation d'éléments d'emmagasinage électriques ou magnétiques particuliers; Eléments d'emmagasinage correspondants utilisant des éléments électriques utilisant des dispositifs à semi-conducteurs utilisant des transistors formant des cellules nécessitant un rafraîchissement ou une régénération de la charge, c. à d. cellules dynamiques avec régénération de la charge commune à plusieurs cellules de mémoire, c. à d. rafraîchissement externe avec une porte à transfert de charges, p.ex. un transistor MOS, par cellule
G11C 11/4096 - Circuits de commande ou de gestion d'entrée/sortie [E/S, I/O] de données, p.ex. circuits pour la lecture ou l'écriture, circuits d'attaque d'entrée/sortie ou commutateurs de lignes de bits
45.
METHOD FOR MANUFACTURING MEMORY DEVICE INCLUDING PILLAR-SHAPED SEMICONDUCTOR ELEMENT
An N+ layer connected to a source line SL at both ends of individual Si pillars standing in a vertical direction; N+ layers connected to a bit line BL1; N+ layers connected to a bit line BL2; a TiN layer surrounding gate HfO2 layers surrounding the individual Si pillars, being continuous between the individual Si pillars, and connected to a plate line PL; a TiN layer surrounding gate HfO2 layers surrounding the four Si pillars, being continuous between the individual Si pillars, and connected to a word line WL1; and a TiN layer connected to a word line WL2 are formed on a substrate. Voltages to be applied to the source line SL, the plate line PL, the word lines WL1 and WL2, and the bit lines BL1 and BL2 are controlled to perform a data hold operation of holding, in any or all of the Si pillars, a positive hole group generated by an impact ionization phenomenon or a gate-induced drain-leakage current, and a data erase operation of discharging the positive hole group from the Si pillars.
An N+ layer and a P+ layer that are impurity regions at a bottom portion are formed using as etching masks top first mask material layers and SiN layers surrounding Si pillars and formed in a self-aligned manner with respect to the Si pillars and a SiO2 layer. Then, a SiO2 layer is formed that has an upper surface located at the level of the bottom portions of the N+ layer and the P+ layer. Then, a W layer is selectively formed on exposed side faces of the N+ layer and the P+ layer. Then, a contact hole for connection to a wire metal layer is formed above the W layer as seen in plan view.
H01L 27/088 - Dispositifs consistant en une pluralité de composants semi-conducteurs ou d'autres composants à l'état solide formés dans ou sur un substrat commun comprenant des éléments de circuit passif intégrés avec au moins une barrière de potentiel ou une barrière de surface le substrat étant un corps semi-conducteur comprenant uniquement des composants semi-conducteurs d'un seul type comprenant uniquement des composants à effet de champ les composants étant des transistors à effet de champ à porte isolée
H01L 29/423 - Electrodes caractérisées par leur forme, leurs dimensions relatives ou leur disposition relative ne transportant pas le courant à redresser, à amplifier ou à commuter
H01L 29/06 - Corps semi-conducteurs caractérisés par les formes, les dimensions relatives, ou les dispositions des régions semi-conductrices
H01L 29/775 - Transistors à effet de champ avec un canal à gaz de porteurs de charge à une dimension, p.ex. FET à fil quantique
On a substrate, a first semiconductor layer 1 is formed; from a portion of the layer 1, a first impurity layer 3 extends vertically, and a second semiconductor layer 4 is disposed on the layer 3; side walls of the layers 3 and 4 and the layer 1 are covered with a first gate insulating layer 2; in the resultant grooves, a first gate conductor layer 22 and a second insulating layer 6 are disposed; over the second semiconductor layer 4, layers are disposed that are a third semiconductor layer 8, an n+ layer 7a connecting to a source line SL and an n+ layer 7b connecting to a bit line BL that are disposed on both sides of the layer 8, a second gate insulating layer 9 formed so as to cover the layer 8, and a second gate conductor layer 10 connecting to a word line WL.
An N+ layer 21 connected to a source line SL at both ends of Si pillars 23a to 23d standing in a vertical direction; N+ layers 30a and 30b connected to a bit line BL1; N+ layers 30c and 30d connected to a bit line BL2; the Si pillars 23a to 23d connected to the N+ layer 21; gate insulating layers 27a to 27d surrounding the Si pillars 23a to 23d; first gate conductor layers 28a and 28b surrounding the gate insulating layers 27a t 27d and connected to plate lines PL1 and PL2; and second gate conductor layers 29a and 29b connected to word lines WL1 and WL2 are disposed on a substrate 1. The Si pillars 23a and 23c have sections partially overlap each other in perspective view of the sections along line X1-X1′ and line X2-X2′, and the same applies to the Si pillars 23b and 23d.
A memory device includes pages each composed of memory cells arrayed in columns on a substrate. A page write operation of retaining a hole group formed by impact ionization inside a channel semiconductor layer, and a page erase operation of discharging the hole group from the channel semiconductor layer are performed. A first impurity layer is connected to a source line, a second impurity layer to a bit line, a first gate conductor layer to a first selection gate line, a second gate conductor layer to a drive control line, a third gate conductor layer to a second selection gate line, and a bit line to a sense amplifier circuit. Page data of a memory cell group selected in at least one page is read to the bit line. Zero volts or less is applied to the drive control line of the memory cell connected to an unselected page.
G11C 11/404 - Mémoires numériques caractérisées par l'utilisation d'éléments d'emmagasinage électriques ou magnétiques particuliers; Eléments d'emmagasinage correspondants utilisant des éléments électriques utilisant des dispositifs à semi-conducteurs utilisant des transistors formant des cellules nécessitant un rafraîchissement ou une régénération de la charge, c. à d. cellules dynamiques avec régénération de la charge commune à plusieurs cellules de mémoire, c. à d. rafraîchissement externe avec une porte à transfert de charges, p.ex. un transistor MOS, par cellule
H10B 12/00 - Mémoires dynamiques à accès aléatoire [DRAM]
G11C 11/406 - Organisation ou commande des cycles de rafraîchissement ou de régénération de la charge
G11C 11/4096 - Circuits de commande ou de gestion d'entrée/sortie [E/S, I/O] de données, p.ex. circuits pour la lecture ou l'écriture, circuits d'attaque d'entrée/sortie ou commutateurs de lignes de bits
A memory device includes pages each constituted by memory cells, and a page write operation and a page erase operation are performed. First and second impurity layers and first and second gate conductor layers in each memory cell is connected to a source line, a bit line, a word line, and a driving control line. In a page read operation, page data is read. In the page write and read operations, a selected driving control line is lowered to zero volt at a first reset time, the driving control line is isolated from a driving circuit at a second reset time, thereby putting the driving control line in a zero-volt floating state, and a selected word line is set at zero volt at a third reset time, thereby putting the driving control line in a negative-voltage floating state by capacitive coupling between the word line and the driving control line.
G11C 11/4096 - Circuits de commande ou de gestion d'entrée/sortie [E/S, I/O] de données, p.ex. circuits pour la lecture ou l'écriture, circuits d'attaque d'entrée/sortie ou commutateurs de lignes de bits
H10B 12/00 - Mémoires dynamiques à accès aléatoire [DRAM]
G11C 11/4094 - Circuits de commande ou de gestion de lignes de bits
G11C 16/24 - Circuits de commande de lignes de bits
A memory device includes pages each constituted by memory cells, and a page write operation of retaining a group of positive holes, inside a channel semiconductor layer, generated by an impact ionization phenomenon by controlling voltages applied to first and second gate conductor layers and first and second impurity layers in each memory cell and a page erase operation of discharging the group of positive holes by controlling the voltages are performed. The first and second impurity layers and the first and second gate conductor layers of each memory cell is connected to a source line, a bit line connected to a sense amplifier circuit, a word line, and a driving control line respectively. In a page read operation, page data in a selected page is read to the bit lines. To the driving control line connected to a non-selected page, a voltage of zero volt or lower is applied.
G11C 11/4096 - Circuits de commande ou de gestion d'entrée/sortie [E/S, I/O] de données, p.ex. circuits pour la lecture ou l'écriture, circuits d'attaque d'entrée/sortie ou commutateurs de lignes de bits
H10B 12/00 - Mémoires dynamiques à accès aléatoire [DRAM]
G11C 11/4094 - Circuits de commande ou de gestion de lignes de bits
G11C 16/24 - Circuits de commande de lignes de bits
52.
SEMICONDUCTOR MEMORY DEVICE AND MANUFACTURING METHOD OF SEMICONDUCTOR MEMORY DEVICE
A Si pillar is formed in a memory region. A TiN layer to be connected to a plate line and a TiN layer to be connected to a word line are formed to extend in a horizontal direction, bend upward from the horizontal direction to a vertical direction in a memory region peripheral portion, and have upper surfaces on a same plane. The TiN layers are connected to metal wiring layers via contact holes formed on the upper surfaces thereof. A memory operation is performed by storing or not storing a group of holes generated by an impact ionization phenomenon in the Si pillar by controlling voltages to be applied to a source line, the plate line, the word line, and a bit line.
A dynamic flash memory is formed by stacking, on a first impurity layer on a P-layer substrate, a first insulating layer, a first material layer, a second insulating layer, a second material layer, a third insulating layer, a third material layer, and a fourth material layer, forming a first hole penetrating these layers on the P-layer substrate, forming a semiconductor pillar by embedding the first hole with a semiconductor, removing the first, second, and third material layers to form second, third, and fourth holes, by oxidizing an outermost surface of the semiconductor pillar exposing in the second, third, and fourth holes to form first, second, and third gate insulating layers, and forming first, second, and third gate conductor layers embedded in the second, third, and fourth holes.
A dynamic flash memory cell is formed by: stacking a first insulating layer, a first material layer, a second insulating layer, a second material layer, a third insulating layer, and a third material layer on a first impurity layer on a P-layer substrate; making a first hole that extends through the insulating layers and the material layers formed on the P-layer substrate; forming a semiconductor pillar by filling the first hole; making a second hole and a third hole by removing the first material layer and the second material layer; forming a first gate insulating layer and a second gate insulating layer by oxidizing a surface layer of the semiconductor pillar exposed inside the second hole and inside the third hole; and forming a first gate conductor layer and a second gate conductor layer by filling the second hole and the third hole.
A memory device includes pages each constituted by memory cells on a substrate. Voltages applied to first and second gate conductor layers and impurity layers in each memory cell are controlled to retain positive holes inside a channel semiconductor layer. In a page write operation, the voltage of the channel semiconductor layer is set to a first data retention voltage. In a page erase operation, the applied voltages are controlled to discharge the positive holes, and the voltage of the channel semiconductor layer is set to a second data retention voltage. At a second time after a first time, a memory re-erase operation is performed for the channel semiconductor layers at the second data retention voltage at the first time. At a third time after the second time, a memory re-write operation is performed for the channel semiconductor layers at the first data retention voltage at the first time.
G11C 11/4096 - Circuits de commande ou de gestion d'entrée/sortie [E/S, I/O] de données, p.ex. circuits pour la lecture ou l'écriture, circuits d'attaque d'entrée/sortie ou commutateurs de lignes de bits
G11C 16/24 - Circuits de commande de lignes de bits
H01L 27/108 - Structures de mémoires dynamiques à accès aléatoire
H01L 29/78 - Transistors à effet de champ l'effet de champ étant produit par une porte isolée
G11C 11/4094 - Circuits de commande ou de gestion de lignes de bits
A groove is formed in a first semiconductor layer 1, a sidewall of the groove is coated with a first insulating film 2, a first impurity layer 3 and a second impurity layer 4 thereon are disposed in the groove, a second semiconductor layer 7 is disposed on the second impurity layer, a first semiconductor is disposed at the other part, an n+ layer 6a and an n+ layer 6c are positioned at respective ends of the second semiconductor layer 7 and connected to a source line SL and a bit line BL, respectively, a first gate insulating layer 8 is formed on the second semiconductor layer 7, and a first gate conductor layer 9 is connected to a word line WL. Voltage applied to the source line SL, a plate line PL connected to the first semiconductor layer 1, the word line WL, and the bit line BL is controlled to perform data holding operation of holding, near the gate insulating layer, holes generated by an impact ionization phenomenon in a channel region 12 of the second semiconductor layer or by gate-induced drain leakage current, and data erase operation of removing the holes from the channel region 12.
A memory device includes a page constituted by multiple memory cells arranged in a row form on a substrate, and performs a page write operation of controlling voltages to be applied to first and second gate conductor layers and first and second impurity layers of each memory cell included in the page to hold a positive hole group formed by an impact ionization phenomenon inside a channel semiconductor layer; During a page read operation, page data of a memory cell group selected with the word line is read to the sense amplifier circuit, and a refresh operation is performed at least once before the page read operation to hold a positive hole group formed by an impact ionization phenomenon inside a channel semiconductor layer.
H01L 27/108 - Structures de mémoires dynamiques à accès aléatoire
G11C 11/404 - Mémoires numériques caractérisées par l'utilisation d'éléments d'emmagasinage électriques ou magnétiques particuliers; Eléments d'emmagasinage correspondants utilisant des éléments électriques utilisant des dispositifs à semi-conducteurs utilisant des transistors formant des cellules nécessitant un rafraîchissement ou une régénération de la charge, c. à d. cellules dynamiques avec régénération de la charge commune à plusieurs cellules de mémoire, c. à d. rafraîchissement externe avec une porte à transfert de charges, p.ex. un transistor MOS, par cellule
G11C 11/4091 - Amplificateurs de lecture ou de lecture/rafraîchissement, ou circuits de lecture associés, p.ex. pour la précharge, la compensation ou l'isolation des lignes de bits couplées
G11C 11/4096 - Circuits de commande ou de gestion d'entrée/sortie [E/S, I/O] de données, p.ex. circuits pour la lecture ou l'écriture, circuits d'attaque d'entrée/sortie ou commutateurs de lignes de bits
First and second impurity layers are formed on a first semiconductor layer on a substrate. A third gate insulating layer covers side walls of the impurity layers and the first semiconductor layer. First and second gate conductor layers and a second insulating layer are formed in a groove, and n+-layers connected to source and bit lines are formed at ends of a second semiconductor layer formed on the second impurity layer and covered with a second gate insulating layer, on which a third gate conductor layer connected to a word line is formed. An operation of maintaining holes generated in a channel region of the second semiconductor layer by impact ionization or a GIDL current near the gate insulating layer and an operation of discharging the holes from the channel region are performed by controlling voltages applied to the source, bit, and word lines and first and second plate lines.
H01L 27/108 - Structures de mémoires dynamiques à accès aléatoire
G11C 11/404 - Mémoires numériques caractérisées par l'utilisation d'éléments d'emmagasinage électriques ou magnétiques particuliers; Eléments d'emmagasinage correspondants utilisant des éléments électriques utilisant des dispositifs à semi-conducteurs utilisant des transistors formant des cellules nécessitant un rafraîchissement ou une régénération de la charge, c. à d. cellules dynamiques avec régénération de la charge commune à plusieurs cellules de mémoire, c. à d. rafraîchissement externe avec une porte à transfert de charges, p.ex. un transistor MOS, par cellule
G11C 11/4096 - Circuits de commande ou de gestion d'entrée/sortie [E/S, I/O] de données, p.ex. circuits pour la lecture ou l'écriture, circuits d'attaque d'entrée/sortie ou commutateurs de lignes de bits
59.
METHOD FOR MANUFACTURING SEMICONDUCTOR ELEMENT-INCLUDING MEMORY DEVICE
An N+ layer 11a and N+ layers 13a to 13d that are disposed on both ends of Si pillars 12a to 12d standing on a substrate 10 in a vertical direction, a TiN layer 18a that surrounds a gate HfO2 layer 17a surrounding the Si pillars 12a to 12d and that extends between the Si pillars 12a and 12b, a TiN layer 18b that surrounds the gate HfO2 layer 17a and that extends between the Si pillars 12c and 12d, a TiN layer 26a that surrounds a gate HfO2 layer 17b surrounding the Si pillars 12a to 12d and that extends between the Si pillars 12a and 12b, and a TiN layer 26b that surrounds the gate HfO2 layer 17b and that extends between the Si pillars 12c and 12d are formed. Voltages applied to the N+ layers 11a and 13a to 13d and the TiN layers 18a, 18b, 26a, and 26b are controlled to perform a data write operation of retaining, inside the Si pillars 12a to 12d, a group of positive holes generated by an impact ionization phenomenon and a data erase operation of discharging the group of positive holes from the inside of the Si pillars 12a to 12d.
c positioned at respective ends of the layer 7 and connected to a source line SL and a bit line BL, respectively, a second gate insulating layer 8 formed to cover the second semiconductor layer 7, and a second gate conductor layer 9 connected to a word line WL are disposed on the second impurity layer. Voltage applied to the source line SL, a plate line PL connected to the first gate conductor layer 22, the word line WL, and the bit line BL is controlled to perform data holding operation of holding, near the gate insulating layer, holes generated by an impact ionization phenomenon in a channel region of the second semiconductor layer or by gate-induced drain leakage current, and data erase operation of removing the holes in the channel region 12.
H01L 23/00 - DISPOSITIFS À SEMI-CONDUCTEURS NON COUVERTS PAR LA CLASSE - Détails de dispositifs à semi-conducteurs ou d'autres dispositifs à l'état solide
G11C 11/39 - Mémoires numériques caractérisées par l'utilisation d'éléments d'emmagasinage électriques ou magnétiques particuliers; Eléments d'emmagasinage correspondants utilisant des éléments électriques utilisant des dispositifs à semi-conducteurs utilisant des thyristors
H10B 12/00 - Mémoires dynamiques à accès aléatoire [DRAM]
61.
PILLAR-SHAPED SEMICONDUCTOR DEVICE AND METHOD FOR PRODUCING THE SAME
A method for forming a first impurity region 3 connected to lower portions of first semiconductor pillars and second impurity regions 4a and 4b connected to lower portions of second semiconductor pillars includes forming a semiconductor layer 100 having an impurity concentration lower than an impurity concentration of each of the first impurity region 3 and the second impurity regions 4a and 4b in impurity boundary regions of the first impurity region 3 and the second impurity regions 4a and 4b in a vertical direction and a horizontal direction.
A memory device includes a page made up of plural memory cells arranged in a column on a substrate, and a page write operation is performed to hold positive hole groups generated by an impact ionization phenomenon, in a channel semiconductor layer by controlling voltages applied to a first gate conductor layer, a second gate conductor layer, a first impurity region, and a second impurity region of each memory cell contained in the page and a page erase operation is performed to remove the positive hole groups out of the channel semiconductor layer by controlling voltages applied to the first gate conductor layer, the second gate conductor layer, the first impurity region, and the second impurity region. The first impurity layer of the memory cell is connected with a source line, the second impurity layer is connected with a bit line, one of the first gate conductor layer and the second gate conductor layer is connected with a word line, and another is connected with a drive control line; during the write operation after the page erase operation, the positive hole group is formed in the channel semiconductor layer by an impact ionization phenomenon by controlling voltages applied to the word line, the drive control line, the source line, and the bit line; and an applied voltage/applied voltages of one or both of the word line and the drive control line is/are lowered with drops in a first threshold voltage of the first gate conductor layer and a second threshold voltage of the second gate conductor layer.
G11C 5/06 - Dispositions pour interconnecter électriquement des éléments d'emmagasinage
H10B 12/00 - Mémoires dynamiques à accès aléatoire [DRAM]
G11C 11/4096 - Circuits de commande ou de gestion d'entrée/sortie [E/S, I/O] de données, p.ex. circuits pour la lecture ou l'écriture, circuits d'attaque d'entrée/sortie ou commutateurs de lignes de bits
H01L 29/78 - Transistors à effet de champ l'effet de champ étant produit par une porte isolée
63.
METHOD OF PRODUCING SEMICONDUCTOR DEVICE INCLUDING MEMORY ELEMENT
Material layers including first and second poly-Si layer are formed on a P-layer substrate. Holes which are parallel to each other and each of which is continuous in a first direction are formed in the material layers. The first and second poly-Si layers are each divided by the holes in a second direction orthogonal to the first direction in plan view. Gate insulating layers and P-layer Si pillars are formed in the holes. The P-layer Si pillars are isolated from one another by the gate insulating layers. A dynamic flash memory is formed in which a first gate conductor layer is connected to a plate line, a second gate conductor layer is connected to a word line, the P-layer Si pillars serve as channels, and one of the N+ layers below and above the P-layer Si pillars is connected to a source line.
An n+ layer 3a connected to a source line SL at both ends, an n+ layer 3b connected to a bit line BL, a first gate insulating layer 4a formed on a semiconductor substrate 1 existing on an insulating film 2, a gate conductor layer 16a connected to a plate line PL, a gate insulating layer 4b formed on the semiconductor substrate, and a second gate conductor layer 5b connected to a word line WL and having a work function different from a work function of the gate conductor layer 16a are disposed on the semiconductor substrate, and data hold operation of holding, near a gate insulating film, holes generated by an impact ionization phenomenon or gate-induced drain leakage current inside a channel region 12 of the semiconductor substrate 1 and data erase operation of removing the holes from inside the substrate 1 and the channel region 12 are performed by controlling voltage applied to the source line SL, the plate line PL, the word line WL, and the bit line BL.
H01L 27/108 - Structures de mémoires dynamiques à accès aléatoire
H01L 29/78 - Transistors à effet de champ l'effet de champ étant produit par une porte isolée
G11C 11/4096 - Circuits de commande ou de gestion d'entrée/sortie [E/S, I/O] de données, p.ex. circuits pour la lecture ou l'écriture, circuits d'attaque d'entrée/sortie ou commutateurs de lignes de bits
G11C 5/06 - Dispositions pour interconnecter électriquement des éléments d'emmagasinage
H01L 29/06 - Corps semi-conducteurs caractérisés par les formes, les dimensions relatives, ou les dispositions des régions semi-conductrices
A memory device includes pages containing memory cells arranged in an array on a substrate. In each memory cell, a voltage applied to a first gate conductor layer, second gate conductor layer, third gate conductor layer, first impurity layer, and second impurity layer is controlled to form a hole group by impact ionization inside a channel semiconductor layer, and a page write operation of holding the hole group and a page erase operation of removing the hole group are performed. The first impurity layer is connected to a source line, the second impurity layer to a bit line, the first gate conductor layer to a first plate line, the second gate conductor layer to a second plate line, and the third gate conductor layer to a word line. A page erase operation is performed without inputting a positive or negative bias pulse to the bit line and the source line.
H01L 27/108 - Structures de mémoires dynamiques à accès aléatoire
G11C 11/4096 - Circuits de commande ou de gestion d'entrée/sortie [E/S, I/O] de données, p.ex. circuits pour la lecture ou l'écriture, circuits d'attaque d'entrée/sortie ou commutateurs de lignes de bits
G11C 11/404 - Mémoires numériques caractérisées par l'utilisation d'éléments d'emmagasinage électriques ou magnétiques particuliers; Eléments d'emmagasinage correspondants utilisant des éléments électriques utilisant des dispositifs à semi-conducteurs utilisant des transistors formant des cellules nécessitant un rafraîchissement ou une régénération de la charge, c. à d. cellules dynamiques avec régénération de la charge commune à plusieurs cellules de mémoire, c. à d. rafraîchissement externe avec une porte à transfert de charges, p.ex. un transistor MOS, par cellule
G11C 11/4097 - Organisation de lignes de bits, p.ex. configuration de lignes de bits, lignes de bits repliées
b that is connected to a first bit line BL1, are stacked on top of one another on a P-layer substrate 20 to form a dynamic flash memory. In plan view, a first plate line PL1, a first word line WL1, a second word line WL2, and a second plate line PL2 extend in the same direction and are formed to be perpendicular to a direction in which the first bit line BL1 extends.
G11C 11/4096 - Circuits de commande ou de gestion d'entrée/sortie [E/S, I/O] de données, p.ex. circuits pour la lecture ou l'écriture, circuits d'attaque d'entrée/sortie ou commutateurs de lignes de bits
G11C 11/404 - Mémoires numériques caractérisées par l'utilisation d'éléments d'emmagasinage électriques ou magnétiques particuliers; Eléments d'emmagasinage correspondants utilisant des éléments électriques utilisant des dispositifs à semi-conducteurs utilisant des transistors formant des cellules nécessitant un rafraîchissement ou une régénération de la charge, c. à d. cellules dynamiques avec régénération de la charge commune à plusieurs cellules de mémoire, c. à d. rafraîchissement externe avec une porte à transfert de charges, p.ex. un transistor MOS, par cellule
H10B 12/00 - Mémoires dynamiques à accès aléatoire [DRAM]
A memory device includes a page made up of plural memory cells arranged in a column on a substrate. A page write operation is performed to hold positive hole groups generated by an impact ionization phenomenon, in a channel semiconductor layer by controlling voltages applied to a first gate conductor layer, a second gate conductor layer, a first impurity layer, and a second impurity layer of each memory cell contained in the page and a page erase operation is performed to remove the positive hole groups out of the channel semiconductor layer by controlling voltages applied to the first gate conductor layer, the second gate conductor layer, the first impurity layer, and the second impurity layer. The first impurity layer of the memory cell is connected with a source line, the second impurity layer is connected with a bit line, one of the first gate conductor layer and the second gate conductor layer is connected with a word line, and another is connected with a drive control line. The bit line is connected to a sense amplifier circuit via a switch circuit. At least one of word lines is selected and a refresh operation is performed to return the voltage of the channel semiconductor layer of the selected word line to the first data retention voltage by controlling voltages applied to the selected word line, the drive control line, the source line, and the bit line and thereby forming the positive hole groups by an impact ionization phenomenon in the channel semiconductor layer of the memory cell in which the voltage of the channel semiconductor layer is set to the first data retention voltage using the page write operation. The refresh operation is performed, with the switch circuit kept in a nonconducting state, concurrently with a page read operation of reading page data of a first memory cell group belonging to a first page into the sense amplifier circuit.
A P layer 2 having a band shape is on an insulating substrate 1. An N+ layer 3a connected to a first source line SL1 and an N+ layer 3b connected to a first bit line are on respective sides of the P layer 2 in a first direction parallel to the insulating substrate. A first gate insulating layer 4a surrounds a portion of the P layer 2 connected to the N+ layer 3a, and a second gate insulating layer 4b surrounds the P layer 2 connected to the N+ layer 3b. A first gate conductor layer 5a connected to a first plate line and a second gate conductor layer 5b connected to a second plate line are isolated from each other and cover two respective side surfaces of the first gate insulating layer 4a in a second direction perpendicular to the first direction. A third gate conductor layer 5c connected to a first word line surrounds the second gate insulating layer 4b. These components constitute a dynamic flash memory.
Provided is a step of forming, on a P-layer substrate 20, an N+ layer 21A to be connected to a source line SL, Si pillars 25a to 25d, N+ layers 23A to 23D to be connected to bit lines BL1 and BL2, HfO2 layers 30a and 32 surrounding lower and upper portions of the Si pillars 25a to 25d, a TiN layer 31a to be connected to a plate line PL, and TiN layers 33a and 33b to be connected to word lines WL1 and WL2. P layers 27a to 27d are formed so as to surround the Si pillars 25a to 25d and so as to be deposited on them to form a plurality of dynamic flash memory cells arranged in rows and columns.
A first mask material layer on a Si pillar 7a and a first material layer around a side surface of a top portion of the Si pillar 7a are formed. A second material layer is then formed on an outer periphery of the first material layer. The first mask material layer and the first material layer are then etched by using the second material layer as a mask. A thin SiGe layer, a p+ layer 23a, and a SiO2 layer 24a are then formed in a recessed portion formed around the Si pillar 7a. The exposed side surface of the thin SiGe layer is oxidized to form a SiO2 layer 26a. A TiN layer and a W layer, which are gate conductor layers, are etched by using the SiO2 layers 24a and 26a as masks to form a TiN layer 29a and a W layer 30a. In plan view, the Si pillar 7a, the p+ layer 23a with a small diode junction resistance, and the TiN layer 29a and the W layer 30a, which are gate line conductor layers, thus have a self-alignment relationship, and the p+ layer 23a and the TiN layer 29a are self-aligned with each other with the HfO2 layer 28 and the SiO2 layer 26a therebetween in the vertical direction.
A memory device includes a page made up of plural memory cells arranged in a column on a substrate, and a page write operation is performed to hold positive hole groups generated by an impact ionization phenomenon, in a channel semiconductor layer by controlling voltages applied to a first gate conductor layer, a second gate conductor layer, a first impurity region, and a second impurity region of each memory cell contained in the page and a page erase operation is performed to remove the positive hole groups out of the channel semiconductor layer by controlling voltages applied to the first gate conductor layer, the second gate conductor layer, the first impurity region, and the second impurity region. The first impurity layer of the memory cell is connected with a source line, the second impurity layer is connected with a bit line, one of the first gate conductor layer and the second gate conductor layer is connected with a word line, and another is connected with a drive control line, and the bit line is connected to a sense amplifier circuit via a switch circuit. During a page read operation, page data of a memory cell group selected by the word line is read into a sense amplifier circuit concurrently with a memory cell refresh operation for forming positive hole groups.
H01L 27/108 - Structures de mémoires dynamiques à accès aléatoire
G11C 11/4091 - Amplificateurs de lecture ou de lecture/rafraîchissement, ou circuits de lecture associés, p.ex. pour la précharge, la compensation ou l'isolation des lignes de bits couplées
G11C 11/4097 - Organisation de lignes de bits, p.ex. configuration de lignes de bits, lignes de bits repliées
A memory device includes a page made up of plural memory cells arranged in a column on a substrate, and a page write operation is performed to hold positive hole groups generated by an impact ionization phenomenon, in a channel semiconductor layer by controlling voltages applied to a first gate conductor layer, a second gate conductor layer, a first impurity region, and a second impurity region of each memory cell contained in the page and a page erase operation is performed to remove the positive hole groups out of the channel semiconductor layer by controlling voltages applied to the first gate conductor layer, the second gate conductor layer, the first impurity region, and the second impurity region. The first impurity layer of the memory cell is connected with a source line, the second impurity layer is connected with a bit line, one of the first gate conductor layer and the second gate conductor layer is connected with a word line, and another is connected with a drive control line. During a refresh operation, at least one of word lines is selected and a voltage of the channel semiconductor layer of the selected word line is returned to a voltage in a state in which a page is written by controlling voltages applied to the selected word line, the drive control line, the source line, and the bit line and thereby forming the positive hole groups by an impact ionization phenomenon in the channel semiconductor layer.
There are an N+ layer connected to a source line SL and an N+ layer connected to a bit line BL at both ends of a Si pillar standing on a substrate in a perpendicular direction, a P+ layer connected to the N+ layer, a first gate insulating layer surrounding the Si pillar, a first gate conductor layer surrounding the first gate insulating layer and connected to a plate line PL, and a second gate conductor layer surrounding a gate HfO2 layer surrounding the Si pillar and connected to a word line WL. The voltages applied to the source line SL, the plate line PL, the word line WL, and the bit line BL are controlled to perform a data hold operation of holding a group of holes generated by an impact ionization phenomenon or a gate-induced drain leakage current inside a channel region of the Si pillar and a data erase operation of removing the group of holes from the channel region.
H01L 27/108 - Structures de mémoires dynamiques à accès aléatoire
G11C 11/404 - Mémoires numériques caractérisées par l'utilisation d'éléments d'emmagasinage électriques ou magnétiques particuliers; Eléments d'emmagasinage correspondants utilisant des éléments électriques utilisant des dispositifs à semi-conducteurs utilisant des transistors formant des cellules nécessitant un rafraîchissement ou une régénération de la charge, c. à d. cellules dynamiques avec régénération de la charge commune à plusieurs cellules de mémoire, c. à d. rafraîchissement externe avec une porte à transfert de charges, p.ex. un transistor MOS, par cellule
G11C 11/4096 - Circuits de commande ou de gestion d'entrée/sortie [E/S, I/O] de données, p.ex. circuits pour la lecture ou l'écriture, circuits d'attaque d'entrée/sortie ou commutateurs de lignes de bits
74.
METHOD FOR MANUFACTURING MEMORY DEVICE USING SEMICONDUCTOR ELEMENT
A first impurity layer 101a and a second impurity layer 101b are formed on a substrate Sub at both ends of a Si pillar 100 standing in a vertical direction and having a circular or rectangular horizontal cross-section. Then, a first gate insulating layer 103a and a second gate insulating layer 103b surrounding the Si pillar 100, a first gate conductor layer 104a surrounding the first gate insulating layer 103a, and a second gate conductor layer 104b surrounding the second gate insulating layer 103b are formed. Then, a voltage is applied to the first impurity layer 101a, the second impurity layer 101b, the first gate conductor layer 104a, and the second gate conductor layer 104b to generate an impact ionization phenomenon in a channel region 102 by current flowing between the first impurity layer 101a and the second impurity layer 101b. Of generated electrons and positive holes, the electrons are discharged from the channel region 102 to perform a memory write operation for holding some of the positive holes in the channel region 102, and the positive holes held in the channel region 102 are discharged from one or both of the first impurity layer 101a and the second impurity layer 101b to perform a memory erase operation.
A memory device includes pages arranged in columns and each constituted by a plurality of memory cells on a substrate, voltages applied to a first gate conductor layer, a second gate conductor layer, a first impurity layer, and a second impurity layer in each memory cell included in each of the pages are controlled to perform a page write operation of retaining, inside a channel semiconductor layer, a group of positive holes generated by an impact ionization phenomenon or by a gate-induced drain leakage current, and the voltages applied to the first gate conductor layer, the second gate conductor layer, the first impurity layer, and the second impurity layer are controlled to perform a page erase operation of discharging the group of positive holes from inside the channel semiconductor layer. The first impurity layer of the memory cell is connected to a source line, the second impurity layer thereof is connected to a bit line, one of the first gate conductor layer or the second gate conductor layer thereof is connected to a word line, and the other of the first gate conductor layer or the second gate conductor layer thereof is connected to a first driving control line. In a page read operation, page data in a group of memory cells selected by the word line is read to sense amplifier circuits, and in at least one operation among the page write operation, the page erase operation, and the page read operation, a voltage applied to at least one of the source line, the bit line, the word line, or the first driving control line is controlled by a reference voltage generating circuit combined with a temperature-compensating circuit.
Provided on a substrate 1 are an N+ layer connecting to a source line SL, a first Si pillar as a P+ layer standing in an upright position along the vertical direction, and a second Si pillar as a P layer. An N+ layer connecting to a bit line BL is provided on the second Si pillar. A first gate insulating layer is provided so as to surround the first Si pillar, and a second gate insulating layer is provided so as to surround the second Si pillar. A first gate conductor layer connecting to a plate line PL is provided so as to surround the first insulating layer, and a second gate conductor layer connecting to a word line WL is provided so as to surround the second insulating layer. A voltage applied to each of the source line SL, the plate line PL, the word line WL, and the bit line BL is controlled to perform a data write operation for retaining holes, which have been generated through an impact ionization phenomenon or using a gate induced drain leakage current, in a channel region, and a data erase operation for removing the holes from the channel region.
H01L 29/66 - Types de dispositifs semi-conducteurs
H01L 21/8238 - Transistors à effet de champ complémentaires, p.ex. CMOS
H01L 27/12 - Dispositifs consistant en une pluralité de composants semi-conducteurs ou d'autres composants à l'état solide formés dans ou sur un substrat commun comprenant des éléments de circuit passif intégrés avec au moins une barrière de potentiel ou une barrière de surface le substrat étant autre qu'un corps semi-conducteur, p.ex. un corps isolant
H01L 29/78 - Transistors à effet de champ l'effet de champ étant produit par une porte isolée
A memory device includes pages, each being composed of a plurality of memory cells arrayed on a substrate in row form, and controls voltages to be applied to a first gate conductor layer, a second gate conductor layer, a first impurity layer, and a second impurity layer of each of the memory cells included in the pages to perform a page write operation of holding a hole group generated by an impact ionization phenomenon or a gate induced drain leakage current in a channel semiconductor layer, and controls voltages to be applied to the first gate conductor layer, the second gate conductor layer, the third gate conductor layer, the fourth gate conductor layer, the first impurity layer, and the second impurity layer to perform a page erase operation of removing the hole group out of the channel semiconductor layer.
G11C 16/04 - Mémoires mortes programmables effaçables programmables électriquement utilisant des transistors à seuil variable, p.ex. FAMOS
G11C 16/12 - Circuits de commutation de la tension de programmation
G11C 16/16 - Circuits pour effacer électriquement, p.ex. circuits de commutation de la tension d'effacement pour effacer des blocs, p.ex. des réseaux, des mots, des groupes
An N+ layer, a Si base material formed of a first channel region and a second channel region, and an N+ layer are disposed parallel to a substrate so as to be connected to each other. A first gate insulating layer that surrounds the first channel region and a second gate insulating layer that surrounds the second channel region are disposed. A first gate conductor layer that surrounds the first gate insulating layer and a second gate conductor layer that surrounds the second gate insulating layer are disposed. The first gate conductor layer is connected to a plate line PL, and the second gate conductor layer is connected to a word line WL. The N+ layer is connected to a source line, and the N+ layer is connected to a bit line BL. These constitute one dynamic flash memory cell. A plurality of cells are disposed in the vertical direction and in the horizontal direction relative to the substrate to form a dynamic flash memory.
H01L 29/66 - Types de dispositifs semi-conducteurs
H01L 21/8238 - Transistors à effet de champ complémentaires, p.ex. CMOS
H01L 27/12 - Dispositifs consistant en une pluralité de composants semi-conducteurs ou d'autres composants à l'état solide formés dans ou sur un substrat commun comprenant des éléments de circuit passif intégrés avec au moins une barrière de potentiel ou une barrière de surface le substrat étant autre qu'un corps semi-conducteur, p.ex. un corps isolant
H01L 29/78 - Transistors à effet de champ l'effet de champ étant produit par une porte isolée
An N+ layer 21 connected to a source line SL on a substrate 20 has thereon first Si pillars 22aa to 22da. The Si pillars 22aa to 22da are surrounded, and Lg1 between opposing intersections among intersections between a line X-X′ and outer peripheral edges of HfO2 layers 24a serving as gate insulating layers surrounding the Si pillars 22aa and 22ba is larger than a thickness Lg2 of the HfO2 layers 24a crossing a line Y-Y′ and is smaller than twice the thickness Lg2. Further, TiN layers 25aa and 25ba are connected to plate lines PL1a and PL1br, and TiN layers 25ab and 25bb are connected to plate lines PL2a and PL2b, the TiN layers 25aa and 25ba and the TiN layers 25ab and 25bb surrounding the HfO2 layers 24a, extending in the line X-X′ direction, and being separated from each other. Further, TiN layers 27a and 27b surround Si pillars 22ab to 22db respectively positioned on the Si pillars 22aa to 22da and are connected to word lines WL1 and WL2, and metal wiring layers 32a and 32b are connected to N+ layers 28a to 28d positioned on the Si pillars 22ab to 22db and are connected to bit lines BL1 and BL2. As a result, a dynamic flash memory cell is formed.
Provided on a substrate are an N+ layer connecting to a source line SL and an N+ layer connecting to a bit line BL that are located at opposite ends of a Si pillar standing in an upright position along the vertical direction, an N layer continuous with the N+ layer, an N layer continuous with the N+ layer, a first gate insulating layer surrounding the Si pillar, a first gate conductor layer surrounding the first gate insulating layer and connecting to a plate line PL, and a second gate conductor layer surrounding a second gate insulating layer surrounding the Si pillar and connecting to a word line WL. A voltage applied to each of the source line SL, the plate line PL, the word line WL, and the bit line BL is controlled to perform a data retention operation for retaining holes, which have been generated through an impact ionization phenomenon or using a gate induced drain leakage current, in a channel region of the Si pillar, and a data erase operation for removing the holes from the channel region.
A memory device includes pages arranged in columns and each constituted by a plurality of memory cells on a substrate, voltages applied to a first gate conductor layer, a second gate conductor layer, a first impurity layer, and a second impurity layer in each memory cell included in each of the pages are controlled to perform a page write operation of retaining, inside a channel semiconductor layer, a group of positive holes generated by an impact ionization phenomenon or by a gate-induced drain leakage current, and the voltages applied to the first gate conductor layer, the second gate conductor layer, the first impurity layer, and the second impurity layer are controlled to perform a page erase operation of discharging the group of positive holes from inside the channel semiconductor layer. The first impurity layer of the memory cell is connected to a source line, the second impurity layer thereof is connected to a bit line, one of the first gate conductor layer or the second gate conductor layer thereof is connected to a word line, the other of the first gate conductor layer or the second gate conductor layer thereof is connected to a first driving control line, and the bit lines are connected to sense amplifier circuits with a switch circuit therebetween. In a page read operation, page data in a group of memory cells selected by the word line is read to the sense amplifier circuits, and in a page addition read operation, at least two sets of page data selected by at least two word lines in multiple selection are added up for each of the bit lines and read to a corresponding one of the sense amplifier circuits.
H01L 29/66 - Types de dispositifs semi-conducteurs
H01L 21/8238 - Transistors à effet de champ complémentaires, p.ex. CMOS
H01L 27/12 - Dispositifs consistant en une pluralité de composants semi-conducteurs ou d'autres composants à l'état solide formés dans ou sur un substrat commun comprenant des éléments de circuit passif intégrés avec au moins une barrière de potentiel ou une barrière de surface le substrat étant autre qu'un corps semi-conducteur, p.ex. un corps isolant
H01L 29/78 - Transistors à effet de champ l'effet de champ étant produit par une porte isolée
On a substrate, an N+ layer connecting to a source line SL, a first Si pillar standing in a perpendicular direction, and a second Si pillar on the first Si pillar are disposed. In a central portion of the first Si pillar, a P+ layer is disposed, and a P layer is disposed so as to surround the P+ layer. In a central portion of the second Si pillar, a P+ layer is disposed, and a P layer is disposed so as to surround the P+ layer. On the second Si pillar, an N+ layer is disposed so as to connect to a bit line BL. A first gate insulating layer is disposed so as to surround the first Si pillar, and a second gate insulating layer is disposed so as to surround the second Si pillar. A first gate conductor layer is disposed so as to surround the first insulating layer and to connect to a plate line PL, and a second gate conductor layer is disposed so as to surround the second insulating layer and to connect to a word line WL. Voltages applied to the source line SL, the plate line PL, the word line WL, and the bit line BL are controlled, to perform a data retention operation of retaining a hole group generated within a channel region due to an impact ionization phenomenon or a gate induced drain leakage current and a data erase operation of discharging the hole group from within the channel region.
H01L 21/8238 - Transistors à effet de champ complémentaires, p.ex. CMOS
H01L 27/12 - Dispositifs consistant en une pluralité de composants semi-conducteurs ou d'autres composants à l'état solide formés dans ou sur un substrat commun comprenant des éléments de circuit passif intégrés avec au moins une barrière de potentiel ou une barrière de surface le substrat étant autre qu'un corps semi-conducteur, p.ex. un corps isolant
A memory device includes pages, each being composed of a plurality of memory cells arrayed on a substrate in row form. The memory device controls voltages to be applied to a first gate conductor layer, a second gate conductor layer, a first impurity region, and a second impurity region of each of the memory cells included in the pages to perform a page write operation of holding a hole group formed by an impact ionization phenomenon or a gate induced drain leakage current in a channel semiconductor layer, and controls voltages to be applied to the first gate conductor layer, the second gate conductor layer, the third gate conductor layer, the fourth gate conductor layer, the first impurity region, and the second impurity region to perform a page erase operation of removing the hole group out of the channel semiconductor layer. The first impurity layer of each of the memory cells is connected to a source line, the second impurity region is connected to a bit line, one of the first gate conductor layer and the second gate conductor layer is connected to a word line, and the other is connected to a first driving control line. The bit line is connected to a sense amplifier circuit via a switching circuit. When in a page read operation, the memory device reads page data in a memory cell group selected by the word line to the bit line, and performs charge sharing between the bit line and a charge sharing node of the switching circuit opposite to the bit line to accelerate a read determination by the sense amplifier circuit.
H01L 27/108 - Structures de mémoires dynamiques à accès aléatoire
G11C 11/404 - Mémoires numériques caractérisées par l'utilisation d'éléments d'emmagasinage électriques ou magnétiques particuliers; Eléments d'emmagasinage correspondants utilisant des éléments électriques utilisant des dispositifs à semi-conducteurs utilisant des transistors formant des cellules nécessitant un rafraîchissement ou une régénération de la charge, c. à d. cellules dynamiques avec régénération de la charge commune à plusieurs cellules de mémoire, c. à d. rafraîchissement externe avec une porte à transfert de charges, p.ex. un transistor MOS, par cellule
G11C 11/4096 - Circuits de commande ou de gestion d'entrée/sortie [E/S, I/O] de données, p.ex. circuits pour la lecture ou l'écriture, circuits d'attaque d'entrée/sortie ou commutateurs de lignes de bits
84.
METHOD FOR MANUFACTURING MEMORY DEVICE USING SEMICONDUCTOR ELEMENT
There are provided the steps of forming an N+ layer 21a and a Si pillar 26 on a substrate 20, the N+ layer 21a being connected to a source line SL, the Si pillar 26 standing in a vertical direction and being composed of a P+ layer 22a in a center portion thereof and a P layer 25a surrounding the P+ layer 22a; forming an N+ layer 3b and HfO2 layers 28a and 28b of gate insulating layers on the P+ layer 22a, the N+ layer 3b being connected to a bit line BL, the HfO2 layers 28a and 28b surrounding the Si pillar 26; and forming a TiN layer 30a of a gate conductor layer and a TiN layer 30b of a gate conductor layer, the TiN layer 30a surrounding the HfO2 layer 28a and being connected to a plate line PL, the TiN layer 30b surrounding the HfO2 layer 28b and being connected to a word line WL. Voltages to be applied to the source line SL, the plate line PL, the word line WL, and the bit line BL are controlled to perform a data write operation for holding a hole group generated by an impact ionization phenomenon or a gate induced drain leakage current in the Si pillar 26 and a data erase operation for discharging the hole group from within the Si pillar 26.
H01L 27/108 - Structures de mémoires dynamiques à accès aléatoire
G11C 11/404 - Mémoires numériques caractérisées par l'utilisation d'éléments d'emmagasinage électriques ou magnétiques particuliers; Eléments d'emmagasinage correspondants utilisant des éléments électriques utilisant des dispositifs à semi-conducteurs utilisant des transistors formant des cellules nécessitant un rafraîchissement ou une régénération de la charge, c. à d. cellules dynamiques avec régénération de la charge commune à plusieurs cellules de mémoire, c. à d. rafraîchissement externe avec une porte à transfert de charges, p.ex. un transistor MOS, par cellule
G11C 11/4096 - Circuits de commande ou de gestion d'entrée/sortie [E/S, I/O] de données, p.ex. circuits pour la lecture ou l'écriture, circuits d'attaque d'entrée/sortie ou commutateurs de lignes de bits
A memory device includes pages arranged in columns and each constituted by a plurality of memory cells on a substrate, voltages applied to a first gate conductor layer, a second gate conductor layer, a first impurity layer, and a second impurity layer in each memory cell included in each of the pages are controlled to perform a page write operation of retaining, inside a channel semiconductor layer, a group of positive holes generated by an impact ionization phenomenon or by a gate-induced drain leakage current, and the voltages applied to the first gate conductor layer, the second gate conductor layer, the first impurity layer, and the second impurity layer are controlled to perform a page erase operation of discharging the group of positive holes from inside the channel semiconductor layer. The first impurity layer of the memory cell is connected to a source line, the second impurity layer thereof is connected to a bit line, one of the first gate conductor layer or the second gate conductor layer thereof is connected to a word line, the other of the first gate conductor layer or the second gate conductor layer thereof is connected to a driving control line, and the bit lines are connected to sense amplifier circuits with a switch circuit therebetween. In a page read operation, page data in a group of memory cells selected by the word line is read to the sense amplifier circuits, and in a page sum-of-products read operation, a voltage is applied to the driving control line such that memory cell currents, in the group of memory cells, flowing into the bit lines multiply N-fold (N is a positive integer).
G11C 7/00 - Dispositions pour écrire une information ou pour lire une information dans une mémoire numérique
G11C 11/404 - Mémoires numériques caractérisées par l'utilisation d'éléments d'emmagasinage électriques ou magnétiques particuliers; Eléments d'emmagasinage correspondants utilisant des éléments électriques utilisant des dispositifs à semi-conducteurs utilisant des transistors formant des cellules nécessitant un rafraîchissement ou une régénération de la charge, c. à d. cellules dynamiques avec régénération de la charge commune à plusieurs cellules de mémoire, c. à d. rafraîchissement externe avec une porte à transfert de charges, p.ex. un transistor MOS, par cellule
G11C 11/4091 - Amplificateurs de lecture ou de lecture/rafraîchissement, ou circuits de lecture associés, p.ex. pour la précharge, la compensation ou l'isolation des lignes de bits couplées
G11C 11/4096 - Circuits de commande ou de gestion d'entrée/sortie [E/S, I/O] de données, p.ex. circuits pour la lecture ou l'écriture, circuits d'attaque d'entrée/sortie ou commutateurs de lignes de bits
H10B 12/00 - Mémoires dynamiques à accès aléatoire [DRAM]
In a memory device, pages are arrayed in a column direction, each page constituted by memory cells arrayed in row direction on an insulating substrate. Each memory cell includes a zonal P layer. N+ layers continuous with a source line and a bit line respectively are on both sides of the P layer. Gate insulating layers surround part of the P layer continuous with the N+ layer and part of the P layer continuous with the N+ layer 3b, respectively. One side surface and the other side surface of the gate insulating layer are covered with a gate conductor layer continuous with a first plate line and a gate conductor layer continuous with a second plate line, respectively. A gate conductor layer continuous with a word line surrounds the gate insulating layer.
H01L 27/108 - Structures de mémoires dynamiques à accès aléatoire
G11C 11/404 - Mémoires numériques caractérisées par l'utilisation d'éléments d'emmagasinage électriques ou magnétiques particuliers; Eléments d'emmagasinage correspondants utilisant des éléments électriques utilisant des dispositifs à semi-conducteurs utilisant des transistors formant des cellules nécessitant un rafraîchissement ou une régénération de la charge, c. à d. cellules dynamiques avec régénération de la charge commune à plusieurs cellules de mémoire, c. à d. rafraîchissement externe avec une porte à transfert de charges, p.ex. un transistor MOS, par cellule
G11C 11/4091 - Amplificateurs de lecture ou de lecture/rafraîchissement, ou circuits de lecture associés, p.ex. pour la précharge, la compensation ou l'isolation des lignes de bits couplées
G11C 11/4096 - Circuits de commande ou de gestion d'entrée/sortie [E/S, I/O] de données, p.ex. circuits pour la lecture ou l'écriture, circuits d'attaque d'entrée/sortie ou commutateurs de lignes de bits
In a memory device, pages are arrayed in a column direction on a substrate, each page constituted by memory cells arrayed in row direction on a substrate. Each memory cell includes a zonal P layer. N+ layers continuous with a source line and a bit line respectively are on both sides of the P layer. Gate insulating layers surround part of the P layer continuous with the N+ layer and part of the P layer continuous with the N+ layer, respectively. One side surface of the gate insulating layer is covered with a gate conductor layer continuous with a first plate line, and the other side surface is covered with a gate conductor layer continuous with a second plate line. A gate conductor layer continuous with a word line surrounds the gate insulating layer.
H01L 27/108 - Structures de mémoires dynamiques à accès aléatoire
G11C 11/404 - Mémoires numériques caractérisées par l'utilisation d'éléments d'emmagasinage électriques ou magnétiques particuliers; Eléments d'emmagasinage correspondants utilisant des éléments électriques utilisant des dispositifs à semi-conducteurs utilisant des transistors formant des cellules nécessitant un rafraîchissement ou une régénération de la charge, c. à d. cellules dynamiques avec régénération de la charge commune à plusieurs cellules de mémoire, c. à d. rafraîchissement externe avec une porte à transfert de charges, p.ex. un transistor MOS, par cellule
G11C 11/4091 - Amplificateurs de lecture ou de lecture/rafraîchissement, ou circuits de lecture associés, p.ex. pour la précharge, la compensation ou l'isolation des lignes de bits couplées
G11C 11/4096 - Circuits de commande ou de gestion d'entrée/sortie [E/S, I/O] de données, p.ex. circuits pour la lecture ou l'écriture, circuits d'attaque d'entrée/sortie ou commutateurs de lignes de bits
88.
Memory device using pillar-shaped semiconductor element
H10B 12/00 - Mémoires dynamiques à accès aléatoire [DRAM]
G11C 11/404 - Mémoires numériques caractérisées par l'utilisation d'éléments d'emmagasinage électriques ou magnétiques particuliers; Eléments d'emmagasinage correspondants utilisant des éléments électriques utilisant des dispositifs à semi-conducteurs utilisant des transistors formant des cellules nécessitant un rafraîchissement ou une régénération de la charge, c. à d. cellules dynamiques avec régénération de la charge commune à plusieurs cellules de mémoire, c. à d. rafraîchissement externe avec une porte à transfert de charges, p.ex. un transistor MOS, par cellule
G11C 11/4096 - Circuits de commande ou de gestion d'entrée/sortie [E/S, I/O] de données, p.ex. circuits pour la lecture ou l'écriture, circuits d'attaque d'entrée/sortie ou commutateurs de lignes de bits
G11C 11/412 - Mémoires numériques caractérisées par l'utilisation d'éléments d'emmagasinage électriques ou magnétiques particuliers; Eléments d'emmagasinage correspondants utilisant des éléments électriques utilisant des dispositifs à semi-conducteurs utilisant des transistors formant des cellules avec réaction positive, c. à d. des cellules ne nécessitant pas de rafraîchissement ou de régénération de la charge, p.ex. multivibrateur bistable, déclencheur de Schmitt utilisant uniquement des transistors à effet de champ
A memory apparatus includes pages each including a plurality of memory cells arranged in a column on a substrate. A voltage applied to each of a first gate conductor layer, a second gate conductor layer, a first impurity layer, and a second impurity layer in each memory cell included in each page is controlled to perform a page write operation for retaining holes, which have been formed through an impact ionization phenomenon or using a gate induced drain leakage current, in a channel semiconductor layer, or a voltage applied to each of the first gate conductor layer, the second gate conductor layer, a third gate conductor layer, a fourth gate conductor layer, the first impurity layer, and the second impurity layer is controlled to perform a page erase operation for removing the holes from the channel semiconductor layer. The first impurity layer in the memory cell connects to a source line. The second impurity layer connects to a bit line. One of the first gate conductor layer and the second gate conductor layer connects to a word line, and the other connects to a first drive control line. The bit line connects to a sense amplifier circuit via a switch circuit. During a page read operation, page data in a group of memory cells selected by the word line is read by the sense amplifier circuit. During each of the page write operation, the page erase operation, and the page read operation, an identical fixed voltage is applied to the first drive control line.
H01L 27/108 - Structures de mémoires dynamiques à accès aléatoire
G11C 11/4091 - Amplificateurs de lecture ou de lecture/rafraîchissement, ou circuits de lecture associés, p.ex. pour la précharge, la compensation ou l'isolation des lignes de bits couplées
G11C 11/4097 - Organisation de lignes de bits, p.ex. configuration de lignes de bits, lignes de bits repliées
A memory device according to the present invention includes memory cells, each of the memory cells includes a semiconductor base material that is formed on a substrate and that stands on the substrate in a vertical direction, voltages applied to a first gate conductor layer, a second gate conductor layer, a first impurity layer, and a second impurity layer in each of the memory cells are controlled to perform a write operation of retaining, inside a channel semiconductor layer, a group of positive holes generated by an impact ionization phenomenon or by a gate-induced drain leakage current, and the voltages applied to the first gate conductor layer, the second gate conductor layer, the first impurity layer, and the second impurity layer are controlled to perform an erase operation of discharging the group of positive holes from inside the channel semiconductor layer. The first gate conductor layer partially surrounds a side surface of the semiconductor base material, and the second gate conductor layer entirely surrounds the side surface of the semiconductor base material.
A memory device according to the present invention includes memory cells, each of the memory cells includes a semiconductor base material that stands on a substrate in a vertical direction or that extends in a horizontal direction along the substrate, voltages applied to a first gate conductor layer, a second gate conductor layer, a first impurity layer, and a second impurity layer in each of the memory cells are controlled to perform a write operation of retaining, inside a channel semiconductor layer, a group of positive holes generated by an impact ionization phenomenon or by a gate-induced drain leakage current, and the voltages applied to the first gate conductor layer, the second gate conductor layer, the first impurity layer, and the second impurity layer are controlled to perform an erase operation of discharging the group of positive holes from inside the channel semiconductor layer. A third impurity layer having a conductivity identical to a conductivity of the channel semiconductor layer and having a concentration higher than a concentration of the channel semiconductor layer is provided in a boundary region between the first gate insulating layer and the second gate insulating layer.
On a substrate, dynamic flash memory cell transistors and, on their outside, driving-signal processing circuit transistors are disposed. A source line wiring layer, a bit line wiring layer, a plate line wiring layer, and a word line wiring layer extend in the horizontal direction relative to the substrate and connect, from the outside of a dynamic flash memory region, in the perpendicular direction, to lead-out wiring layers on an insulating layer. The transistors in driving-signal processing circuit regions connect, via multilayered wiring layers, to upper wiring layers on the insulating layer. A high-thermal-conductivity layer is disposed over the entirety of the dynamic flash memory region and in a portion above the bit line wiring layer.
G11C 11/402 - Mémoires numériques caractérisées par l'utilisation d'éléments d'emmagasinage électriques ou magnétiques particuliers; Eléments d'emmagasinage correspondants utilisant des éléments électriques utilisant des dispositifs à semi-conducteurs utilisant des transistors formant des cellules nécessitant un rafraîchissement ou une régénération de la charge, c. à d. cellules dynamiques avec régénération de la charge propre à chaque cellule de mémoire, c. à d. rafraîchissement interne
G11C 11/4097 - Organisation de lignes de bits, p.ex. configuration de lignes de bits, lignes de bits repliées
G11C 5/10 - Dispositions pour interconnecter électriquement des éléments d'emmagasinage pour interconnecter des capacités
G11C 11/402 - Mémoires numériques caractérisées par l'utilisation d'éléments d'emmagasinage électriques ou magnétiques particuliers; Eléments d'emmagasinage correspondants utilisant des éléments électriques utilisant des dispositifs à semi-conducteurs utilisant des transistors formant des cellules nécessitant un rafraîchissement ou une régénération de la charge, c. à d. cellules dynamiques avec régénération de la charge propre à chaque cellule de mémoire, c. à d. rafraîchissement interne
A memory device includes a plurality of pages arranged in columns, each page is constituted by a plurality of memory cells arranged in rows on a substrate, the memory cells included in the page are memory cells of a plurality of semiconductor base materials that stand on the substrate in a vertical direction or that extend in a horizontal direction along the substrate, voltages applied to a first gate conductor layer, a second gate conductor layer, a first impurity layer, and a second impurity layer in each memory cell are controlled to perform a page write operation of retaining, inside a channel semiconductor layer, a group of positive holes generated by an impact ionization phenomenon or by a gate-induced drain leakage current, the voltages applied to the first gate conductor layer, the second gate conductor layer, the first impurity layer, and the second impurity layer are controlled to perform a page erase operation of discharging the group of positive holes from inside the channel semiconductor layer, and all memory cells included in a first page subjected to the page erase operation perform the page write operation at least once.
G11C 11/24 - Mémoires numériques caractérisées par l'utilisation d'éléments d'emmagasinage électriques ou magnétiques particuliers; Eléments d'emmagasinage correspondants utilisant des éléments électriques utilisant des condensateurs
G11C 11/402 - Mémoires numériques caractérisées par l'utilisation d'éléments d'emmagasinage électriques ou magnétiques particuliers; Eléments d'emmagasinage correspondants utilisant des éléments électriques utilisant des dispositifs à semi-conducteurs utilisant des transistors formant des cellules nécessitant un rafraîchissement ou une régénération de la charge, c. à d. cellules dynamiques avec régénération de la charge propre à chaque cellule de mémoire, c. à d. rafraîchissement interne
G11C 11/4097 - Organisation de lignes de bits, p.ex. configuration de lignes de bits, lignes de bits repliées
A memory device includes pages arranged in columns and each constituted by a plurality of memory cells on a substrate, voltages applied to a first gate conductor layer, a second gate conductor layer, a first impurity layer, and a second impurity layer in each memory cell included in each of the pages are controlled to perform a page write operation of retaining, inside a channel semiconductor layer, a group of positive holes generated by an impact ionization phenomenon or by a gate-induced drain leakage current, the voltages applied to the first gate conductor layer, the second gate conductor layer, the first impurity layer, and the second impurity layer are controlled to perform a page erase operation of discharging the group of positive holes from inside the channel semiconductor layer, the first impurity layer of the memory cell is connected to a source line, the second impurity layer thereof is connected to a bit line, one of the first gate conductor layer or the second gate conductor layer is connected to a word line, and the other of the first gate conductor layer or the second gate conductor layer is connected to a first driving control line, the bit line is connected to a sense amplifier circuit with a first switch circuit therebetween, and in a page refresh operation, page data in a first group of memory cells belonging to a first page is read to the sense amplifier circuits, the first switch circuit is put in a non-conducting state, the page erase operation of the first group of memory cells is performed, the first switch circuit is put in a conducting state, and the page write operation of writing the page data in the sense amplifier circuits back to the first group of memory cells is performed.
G11C 11/34 - Mémoires numériques caractérisées par l'utilisation d'éléments d'emmagasinage électriques ou magnétiques particuliers; Eléments d'emmagasinage correspondants utilisant des éléments électriques utilisant des dispositifs à semi-conducteurs
G11C 11/404 - Mémoires numériques caractérisées par l'utilisation d'éléments d'emmagasinage électriques ou magnétiques particuliers; Eléments d'emmagasinage correspondants utilisant des éléments électriques utilisant des dispositifs à semi-conducteurs utilisant des transistors formant des cellules nécessitant un rafraîchissement ou une régénération de la charge, c. à d. cellules dynamiques avec régénération de la charge commune à plusieurs cellules de mémoire, c. à d. rafraîchissement externe avec une porte à transfert de charges, p.ex. un transistor MOS, par cellule
G11C 11/4096 - Circuits de commande ou de gestion d'entrée/sortie [E/S, I/O] de données, p.ex. circuits pour la lecture ou l'écriture, circuits d'attaque d'entrée/sortie ou commutateurs de lignes de bits
G11C 11/4091 - Amplificateurs de lecture ou de lecture/rafraîchissement, ou circuits de lecture associés, p.ex. pour la précharge, la compensation ou l'isolation des lignes de bits couplées
G11C 11/406 - Organisation ou commande des cycles de rafraîchissement ou de régénération de la charge
H10B 12/00 - Mémoires dynamiques à accès aléatoire [DRAM]
A memory device includes a plurality of memory cells each including a semiconductor base material that stands on a substrate in a vertical direction or that extends in a horizontal direction along the substrate, voltages applied to a first gate conductor layer, a second gate conductor layer, a first impurity layer, and a second impurity layer in each of the memory cells are controlled to perform a memory write operation of retaining, inside a channel semiconductor layer, a group of positive holes generated by an impact ionization phenomenon or by a gate-induced drain leakage current, the voltages applied to the first gate conductor layer, the second gate conductor layer, the first impurity layer, and the second impurity layer are controlled to perform a memory erase operation of discharging the group of positive holes from inside the channel semiconductor layer, the first impurity layer is connected to a source line, the second impurity layer is connected to a bit line, one of the first gate conductor layer or the second gate conductor layer is connected to a word line, and the other of the first gate conductor layer or the second gate conductor layer is connected to a first driving control line, a voltage of the word line changes from a first voltage to a second voltage that is higher than the first voltage, and a voltage of the bit lines subsequently change from a third voltage to a fourth voltage that is higher than the third voltage to perform a memory read operation of reading to the bit lines, pieces of storage data in a plurality of semiconductor base materials selected by the word line.
A memory device includes a page made of a plurality of memory cells arranged in rows on a substrate. A page write operation is performed, during which, in each of the memory cells included in the page, a first voltage V1 is applied to a first drive control line PL, a second voltage V2 is applied to a word line WL, a third voltage V3 is applied to a source line SL, a fourth voltage V4 is applied to a bit line BL, a group of holes generated by an impact ionization phenomenon is retained in an inside of the channel semiconductor layer. A page erase operation is performed, during which the voltages to be applied to the first drive control line PL, the word line WL, the source line SL, and the bit line BL are controlled to discharge the group of holes from the inside of the channel semiconductor layer, and the voltage of the channel semiconductor layer is decreased. A page read operation is performed, during which a fifth voltage V5 that is lower than the first voltage V1 is applied to the first drive control line PL, a sixth voltage V6 that is lower than the second voltage V2 is applied to the word line WL, the third voltage V3 is applied to the source line, and a seventh voltage V7 that is lower than the fourth voltage V4 is applied to the bit line.
G11C 11/404 - Mémoires numériques caractérisées par l'utilisation d'éléments d'emmagasinage électriques ou magnétiques particuliers; Eléments d'emmagasinage correspondants utilisant des éléments électriques utilisant des dispositifs à semi-conducteurs utilisant des transistors formant des cellules nécessitant un rafraîchissement ou une régénération de la charge, c. à d. cellules dynamiques avec régénération de la charge commune à plusieurs cellules de mémoire, c. à d. rafraîchissement externe avec une porte à transfert de charges, p.ex. un transistor MOS, par cellule
G11C 11/4096 - Circuits de commande ou de gestion d'entrée/sortie [E/S, I/O] de données, p.ex. circuits pour la lecture ou l'écriture, circuits d'attaque d'entrée/sortie ou commutateurs de lignes de bits
H10B 12/00 - Mémoires dynamiques à accès aléatoire [DRAM]
In a dynamic flash memory cell including a HfO2 layer and a TiN layer surrounding a lower portion of a Si pillar standing on a P-layer substrate, a HfO2 layer and a TiN layer surrounding an upper portion of the Si pillar, and N+ layers connecting to a bottom portion and a top portion of the Si pillar, and a Fin transistor including a SiO2 layer surrounding a lower portion of a Si pillar standing also on the P-layer substrate, a HfO2 layer and a TiN layer surrounding an upper portion of the Si pillar, and N+ layers connecting to both side surfaces of the upper portion of the Si pillar, the bottom portion positions of the Si pillar and the Si pillar are both at Position A, and the bottom portions of an SGT transistor unit constituted by, in the upper portion of the Si pillar, the HfO2 layer and the TiN layer and a Fin transistor unit constituted by, in the upper portion of the Si pillar, the HfO2 layer and the TiN layer are both at Position B.
An N+ layer connects to the bottom portion of a Si pillar standing on a substrate 1 and an N+ layer connects to the top portion of the Si pillar. Of the N+ layer and the N+ layer, one serves as the source and the other serves as the drain. A region of the Si pillar between the N+ layer and the N+ layer serves as a channel region. A first gate insulating layer surrounds the lower portion of the Si pillar and a second gate insulating layer surrounds the upper portion of the Si pillar. The first gate insulating layer and the second gate insulating layer are respectively disposed in contact with or near the N+ layers serving as the source and the drain. A first gate conductor layer and a second gate conductor layer surround the first gate insulating layer. The first gate conductor layer and the second gate conductor layer are formed so as to surround the first gate insulating layer and to be isolated from each other. A third gate conductor layer surrounds the second gate insulating layer. Thus, a dynamic flash memory cell is formed.
H01L 27/108 - Structures de mémoires dynamiques à accès aléatoire
G11C 11/404 - Mémoires numériques caractérisées par l'utilisation d'éléments d'emmagasinage électriques ou magnétiques particuliers; Eléments d'emmagasinage correspondants utilisant des éléments électriques utilisant des dispositifs à semi-conducteurs utilisant des transistors formant des cellules nécessitant un rafraîchissement ou une régénération de la charge, c. à d. cellules dynamiques avec régénération de la charge commune à plusieurs cellules de mémoire, c. à d. rafraîchissement externe avec une porte à transfert de charges, p.ex. un transistor MOS, par cellule
G11C 11/4096 - Circuits de commande ou de gestion d'entrée/sortie [E/S, I/O] de données, p.ex. circuits pour la lecture ou l'écriture, circuits d'attaque d'entrée/sortie ou commutateurs de lignes de bits
100.
MEMORY DEVICE USING SEMICONDUCTOR ELEMENT AND METHOD FOR MANUFACTURING THE SAME
There are an N+ layer 3a connected to a source line SL and an N+ layer 3b connected to a bit line BL at both ends of a Si pillar 2 standing on a substrate 1 in a perpendicular direction, a P+ layer 8 connected to the N+ layer 3b, a first gate insulating layer 4a surrounding the Si pillar 2, a first gate conductor layer 5a surrounding the first gate insulating layer 4a and connected to a plate line PL, and a second gate conductor layer 5b surrounding a gate HfO2 layer 4b surrounding the Si pillar 2 and connected to a word line WL. The voltages applied to the source line SL, the plate line PL, the word line WL, and the bit line BL are controlled to perform a data hold operation of holding a group of holes generated by an impact ion phenomenon or a gate-induced drain leakage current inside a channel region 7 of the Si pillar 2 and a data erase operation of removing the group of holes from the channel region 7.
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