A method for video encoding, a method for video decoding, and a related product. The method may be comprised in a combined processing apparatus (800), and the combined processing apparatus (800) may further comprise a universal interconnection interface (804) and other processing apparatuses (806). A computing apparatus (802) interacts with the other processing apparatuses (806), so as to jointly complete a computing operation, which is specified by a user. The combined processing apparatus (800) may further comprise a storage apparatus (808), wherein the storage apparatus (808) is connected both to a device and the other processing apparatuses (806) and is used for storing data of the device and the other processing apparatuses (806). By means of the described technical solution, the compression efficiency of a video can be significantly improved.
The present invention relates to the field of artificial intelligence chips, and specifically relates to a neural network computation method and a related device. A computation device of the present application comprises a processor, a communication interface, and other processing devices. The processor and the communication interface are communicatively connected to each other by means of bus to jointly complete a computation operation specified by a user. The computation device can further comprise a storage device. The storage device is separately connected to the processor and other processing devices, and is used for data storage for the computation device and other processing devices. In the present application, pendulum type conversion is executed at most with respect to an input of an operator on the basis of an input pendulum type and a target pendulum type, such that unnecessary pendulum type conversions during a computation process can be reduced, thereby reducing memory overhead, and improving computation efficiency.
G06N 3/063 - Réalisation physique, c. à d. mise en œuvre matérielle de réseaux neuronaux, de neurones ou de parties de neurone utilisant des moyens électroniques
A computation graph optimization method, a data processing method, a computing apparatus, a computer-readable storage medium and a computer program product. The computing apparatus for executing a computation graph optimization method may be comprised in a combined processing apparatus, and the combined processing apparatus may further comprise an interface apparatus and other processing apparatuses. The computing apparatus interacts with the other processing apparatuses, so as to jointly complete a computing operation specified by a user. The combined processing apparatus may further comprise a storage apparatus, and the storage apparatus is connected to the computing apparatus and the other processing apparatuses and is used for storing data of the computing apparatus and the other processing apparatuses. According to the present solution, constructing a view-type operator subgraph can optimize the data memory access. Furthermore, optimizing the view-type operator subgraph can reduce the carrying of a device-end memory and the calling of an operator. Furthermore, backward deduction is performed to obtain a view-type operator which causes tensor data to change into in a memory non-continuous state, such that a suitable computing library operator can be called, so as to convert the tensor data into a memory continuous state, thereby reducing the data carrying of the device-end memory.
Disclosed in the present disclosure are a computing device for performing a binary operation of multi-dimensional data, a method for performing a binary operation by using the computing device, and a related product. The computing device may be comprised in a combined processing device. The combined processing device further comprises an interface device and another processing device. The computing device interacts with the another processing device to jointly complete a computing operation that is designated by a user. The combined processing device may further comprise a storage device. The storage device is respectively connected to the computing device and the another processing device, and is used for storing data of the computing device and the another processing device. According to the solution of the present disclosure, by reasonably allocating the loading frequency of operation data, the number of times of data exchange and loading can be reduced, the throughput pressure is relieved, and the processing efficiency of a machine is improved. Fig. 2
Provided in the embodiments of the present application are a graph task scheduling method, an execution-end device, a storage medium, and a program product. By means of the technical means of determining a task execution state of the previous task which has a dependency relationship with the current task, determining, according to the task execution state of the previous task and a task execution state of the current task, whether to execute the current task, and if so, updating the task execution state of the current task after the execution of the current task is finished, an execution-end device can directly acquire the task execution state of the previous task of the current task before executing the current task; and graph task scheduling processing of the execution-end device is implemented, such that there is no need for a host-end device to perform task scheduling for the task execution of the execution-end device, thereby reducing communication overheads, and improving the task running efficiency.
Provided in the present disclosure are a method and system for sorting data in single-core and multi-core processors. The system and method may be involved in a combined processing apparatus, and the combined processing apparatus may further comprise a universal interconnection interface and another processing apparatus. A computing apparatus interacts with the other processing apparatus to jointly complete a computing operation designated by a user. The combined processing apparatus may further comprise a storage apparatus, which is respectively connected to a device and the other processing apparatus, and is used for storing data of the device and the other processing apparatus. By means of the solution of the present disclosure, the running efficiency of operations can be improved in various fields of data processing including, for example, the field of artificial intelligence, thereby reducing the overall overheads and costs for operations.
The present invention relates to a device for optimizing parameters of a deep neural network. The device of the present invention is comprised in an integrated circuit apparatus, the integrated circuit apparatus comprising a universal interconnection interface and other processing apparatuses. A computing apparatus interacts with the other processing apparatuses to jointly complete a computing operation specified by a user. The integrated circuit apparatus may further comprise a storage apparatus. The storage apparatus is separately connected to the computing apparatus and the other processing apparatuses for storing data of the device apparatus and the other processing apparatuses.
Provided are a method and system for fusing operators of a neural network. The system and method may be comprised in a combined processing apparatus. The combined processing apparatus may further comprise a universal interconnection interface and another processing apparatus; a computing apparatus interacts with the another processing apparatus to jointly complete a computing operation designated by a user; the combined processing apparatus may further comprise a storage apparatus, and the storage apparatus is respectively connected to a device and the another processing apparatus, and is configured to store data of the device and the another processing apparatus.
Disclosed are a method for optimizing a convolution operation of a system on chip and a related product. The system on chip can be comprised in a computing processing device of a combined processing device, and the computing processing device can comprise one or more integrated circuit devices. The combined processing device can further comprise an interface device and another processing device. The computing processing device interacts with the another processing device to together complete a computing operation specified by a user. The combined processing device can further comprise a storage device, and the storage device is separately connected to an apparatus and the another processing device for storing data of the apparatus and the another processing device. By means of the solution of the present disclosure, the data transmission amount between an internal apparatus and an external storage device can be decreased, such that the problem of an I/O bottleneck caused due to a bandwidth limit is reduced to the maximum extent, and the overall performance of an integrated circuit device can be improved.
A method for optimizing a matrix multiplication operation on a system on chip, and a related product, the method comprising: receiving matrix information of a first matrix and a second matrix, which are to be split so as to execute a matrix multiplication operation, wherein the first matrix is in the form of M rows × K columns, and the second matrix is in the form of K rows × N columns; and by minimizing a cost function, determining a splitting coefficient for splitting the first matrix and the second matrix, wherein the splitting coefficient comprises the numbers of rows and columns of a matrix block obtained after the first matrix is split, and the numbers of rows and columns of a matrix block obtained after the second matrix is split, and the cost function is used to determine the cost caused by transferring matrix data between a system on chip and a system off chip on executing a matrix multiplication operation on the system on chip.
Disclosed are a data processing device and method, and a related product. The data processing device can be comprised as a computing device in a combined processing device; the combined processing device can further comprise an interface device and another processing device. The computing device interacts with the another processing device to jointly complete a computing operation specified by a user. The combined processing device can further comprise a storing device, and the storing device is separately connected to the computing device and the another processing device and is used for storing data of the computing device and the another processing device. According to the solution of the present disclosure, by means of partitioning and partial rearrangement, the IO time during operation is reduced, and the memory requirement is also lowered.
An integrated circuit apparatus, an electronic device, a board card, and a method for performing matrix multiplication using the integrated circuit apparatus. The integrated circuit apparatus can be comprised in a computing processing apparatus of a combination processing apparatus. The computing processing apparatus can comprise one or more integrated circuit apparatuses. The combination processing apparatus can also comprise an interface apparatus and the other processing apparatus, and the computing processing apparatus interacts with the other processing apparatus to jointly complete a computing operation specified by a user. The combination processing apparatus can also comprise a storage apparatus, and the storage apparatus is respectively connected to the computing apparatus and the other processing apparatus, and is used for storing data of the computing apparatus and the other processing apparatus. The present scheme can reduce the amount of data transmission between an internal device and an external storage apparatus, reducing the problem of I/O bottleneck caused by bandwidth limitation to the maximum extent, thereby improving the overall performance of the integrated circuit apparatus.
A data processing apparatus and method for executing a neural network model, and related products. The data processing apparatus can, as a computing apparatus, be comprised in a combination processing apparatus. The combination processing apparatus can also comprise an interface apparatus and other processing apparatuses. The computing apparatus interacts with other processing apparatuses to jointly complete a computing operation specified by a user. The combination processing apparatus can further comprise a storage apparatus, wherein the storage apparatus is connected to the computing apparatus and other processing apparatuses and is used for storing data of the computing apparatus and other processing apparatuses. According to the present solution, a convolution operation of a multi-dimensional array is optimized, thereby improving the operation processing efficiency.
An inter-chip communication circuit, method and system. The circuit comprises a first scheduling unit, a first computation unit and a sending unit. The first scheduling unit is configured to receive first task description information. The first computation unit is configured to receive the first task description information from the first scheduling unit and process first data according to the first task description information so as to obtain the first processed data. The first computing unit is further configured to transmit the first processed data to the sending unit. The sending unit is configured to send the first processed data off chip.
A data processing circuit, a data processing method, and related products. The data processing circuit can be implemented as a computing apparatus (201) and is comprised in a combination processing apparatus (20). The combination processing apparatus (20) can also comprise an interface apparatus (202) and the other processing apparatus (203). The computing apparatus (201) interacts with the other processing apparatus (203) to jointly complete a computing operation specified by a user. The combination processing apparatus (20) can also comprise a storage apparatus (204), the storage apparatus (204) being respectively connected to the computing apparatus (201) and the other processing apparatus (203), and being used for storing data of the computing apparatus (201) and the other processing apparatus (203). Provided are hardware implementations for structured sparse correlation operations, which can simplify processing and improve the processing efficiency of a machine.
G06N 3/063 - Réalisation physique, c. à d. mise en œuvre matérielle de réseaux neuronaux, de neurones ou de parties de neurone utilisant des moyens électroniques
16.
DATA PROCESSING DEVICE, DATA PROCESSING METHOD, AND RELATED PRODUCT
A data processing device, a data processing method, and a related product. The data processing device can be implemented as a computation device comprised in a combined processing device, and the combined processing device can further comprise an interface device and another processing device. The computation device interacts with the another processing device to jointly complete a computation operation specified by a user. The combined processing device can further comprise a storage device, and the storage device is respectively connected to the computation device and the another processing device and is used for storing data of the computation device and the another processing device. The solution provides a dedicated instruction for a structured sparsification related operation, can simplify processing, and improves the processing efficiency of a machine.
G06N 3/063 - Réalisation physique, c. à d. mise en œuvre matérielle de réseaux neuronaux, de neurones ou de parties de neurone utilisant des moyens électroniques
G06F 12/06 - Adressage d'un bloc physique de transfert, p.ex. par adresse de base, adressage de modules, extension de l'espace d'adresse, spécialisation de mémoire
17.
DATA PROCESSING APPARATUS, DATA PROCESSING METHOD AND RELATED PRODUCT
A data processing apparatus, a data processing method and a related product. The data processing apparatus can be implemented as a computation apparatus comprised in a combined processing apparatus. The combined processing apparatus may also comprise an interface apparatus and other processing apparatuses. The computation apparatus interacts with the other processing apparatuses to jointly complete a computation operation specified by a user. The combined processing apparatus may also comprise a storage apparatus, which is respectively connected to the computation apparatus and the other processing apparatuses, and is used for storing data of the computation apparatus and the other processing apparatuses. Provided is a special instruction for a structured sparse convolution operation, and the special instruction can simplify processing, thereby improving the processing efficiency of a machine.
G06N 3/063 - Réalisation physique, c. à d. mise en œuvre matérielle de réseaux neuronaux, de neurones ou de parties de neurone utilisant des moyens électroniques
G06F 12/06 - Adressage d'un bloc physique de transfert, p.ex. par adresse de base, adressage de modules, extension de l'espace d'adresse, spécialisation de mémoire
18.
DEVICE, BOARD AND METHOD FOR MERGING BRANCH STRUCTURES, AND READABLE STORAGE MEDIUM
A device, board and method for dynamically merging branch structures of a neural network according to a merging strategy, and a readable storage medium. A computing device is comprised in an integrated circuit device, and the integrated circuit device comprises a general-purpose interconnection interface and other processing devices. The computing device interacts with the other processing devices to together complete a computing operation specified by a user. The integrated circuit device can further comprise a storage device. The storage device is separately connected to the computing device and the other processing devices, and is used for the data storage of the computing device and the other processing devices.
The present invention relates to a computational neural network apparatus, a card, a method, and a readable storage medium, wherein a computational apparatus of the present invention is contained within an integrated circuit apparatus, and the integrated circuit apparatus comprises a general interconnection interface and an other processing apparatus. The computational apparatus and the other processing apparatus interact and jointly complete a computation operation specified by a user. The integrated circuit apparatus may further comprise a storage apparatus, the storage apparatus being separately connected to the computational apparatus and the other processing apparatus, and said storage apparatus being used for data storage for the computational apparatus and the other processing apparatus.
G06N 3/063 - Réalisation physique, c. à d. mise en œuvre matérielle de réseaux neuronaux, de neurones ou de parties de neurone utilisant des moyens électroniques
20.
METHOD AND APPARATUS FOR TRAINING NEURAL NETWORK, AND COMPUTER READABLE STORAGE MEDIUM
An apparatus (200) and method for training a neural network, and an integrated circuit board. The apparatus (200) is embodied by a computing device (610) in a combined processing device (600). The combined processing device (600) can further comprise a universal interconnect interface and other processing devices (606). The computing device (610) interacts with the other processing devices (606) to jointly complete a user-specified computing operation. The combined processing device (600) can further comprise a storage device (608). The storage device (608) is separately connected to the computing device (610) and the other processing devices (606) and is used for data of the computing device (610) and the other processing devices (606). The present invention can speed by the training of a neural network.
G06N 3/063 - Réalisation physique, c. à d. mise en œuvre matérielle de réseaux neuronaux, de neurones ou de parties de neurone utilisant des moyens électroniques
21.
ACCUMULATION DEVICE AND METHOD, AND READABLE STORAGE MEDIUM
An accumulation device and method, and a readable storage medium, for use in accumulating multiple floating-point numbers. Firstly, a reference exponent is identified, then an accumulation cluster is screened according to the reference exponent, and floating-point numbers of the accumulation cluster are accumulated.
A method, device and system for acquiring hardware performance data. The device may be included in a calculation processing apparatus of a combined processing apparatus. The calculation processing apparatus may comprise one or more data processing apparatuses. The described combined processing apparatus may further comprise an interface apparatus and another processing apparatus. The calculation processing apparatus interacts with the other processing apparatus to complete together a calculation operation specified by a user. The combined processing apparatus may further comprise a storage apparatus. The storage apparatus is respectively connected to the device and the other processing apparatus, and is used for storing data of the device and the other processing apparatus. The present method may effectively acquire hardware performance data related to the execution of an object code.
A processing method, a processing apparatus, and a related product. The processing apparatus can be implemented as a computing apparatus (510) included in a combined processing apparatus (500); the combined processing apparatus (500) further can comprise an interface apparatus (504) and other processing apparatuses (506); the computing apparatus (510) interacts with other processing apparatuses (506) so as to jointly complete a computing operation specified by a user; the combined processing apparatus (500) further can comprise a storage apparatus (508); and the storage apparatus (508) is separately connected to the computing apparatus (510) and other processing apparatuses (506) and used for storing the data of the computing apparatus (510) and other processing apparatuses (506). The method provides an instruction parallel solution that can improve instruction parallelism, thereby improving the processing efficiency of a machine.
A data processing apparatus (300), a data processing method (400), and a related product, relating to an instruction system for tensor data. The data processing apparatus (300) can serve as a computing apparatus (510) and is thus comprised in a combination processing apparatus (500). The combination processing apparatus (500) can also comprise an interface apparatus (504) and another processing apparatus (506). The computing apparatus (510) and the other processing apparatus (506) interact with each other, and jointly complete a computing operation designated by a user. The combination processing apparatus (500) can also comprise a storage apparatus (508), the storage apparatus (508) being respectively connected to the computing apparatus (510) and the other processing apparatus (506) and being used for storing data of the computing apparatus (510) and the other processing apparatus (506). By means of the data processing apparatus (300), the data processing method (400), and the related product, the time taken to access data can be shortened, thereby improving the processing efficiency of a machine.
An integrated computing apparatus, a machine learning operation apparatus, a neural network chip, a board card, an electronic device and a method. The integrated computing apparatus is comprised in a combined processing apparatus, the combined processing apparatus comprises an interface apparatus and other processing apparatuses, the integrated computing apparatus interacts with the other processing apparatuses, so as to jointly complete a computing operation designated by a user, the combined processing apparatus comprises a storage apparatus, and the storage apparatus is respectively connected to the integrated computing apparatus and the other processing apparatuses, so as to store the data of the integrated computing apparatus and the other processing apparatuses.
G06F 9/30 - Dispositions pour exécuter des instructions machines, p.ex. décodage d'instructions
G06N 3/063 - Réalisation physique, c. à d. mise en œuvre matérielle de réseaux neuronaux, de neurones ou de parties de neurone utilisant des moyens électroniques
A device and method for processing multi-dimensional data, and an electronic device and a compilation apparatus (1802). The compilation apparatus (1802) may be comprised in a combined processing apparatus (1800). The combined processing apparatus (1800) may also comprise a universal interconnection interface (1804) and other processing apparatuses (1806). The compilation apparatus (1802) interacts with the other processing apparatuses (1806), so as to jointly complete a user-specified computing operation. The combined processing apparatus (1800) may further comprise a storage apparatus (1808). The storage apparatus (1808) is respectively connected to the compilation apparatus (1802) and the other processing apparatuses (1806), and is used for storing data of the compilation apparatus (1802) and the other processing apparatuses (1806).
G06N 3/063 - Réalisation physique, c. à d. mise en œuvre matérielle de réseaux neuronaux, de neurones ou de parties de neurone utilisant des moyens électroniques
27.
ENCAPSULATION STRUCTURE, APPARATUS, BOARD CARD, AND METHOD FOR LAYING OUT INTEGRATED CIRCUIT
An encapsulation structure, an integrated circuit apparatus, a board card, and a method for laying out an integrated circuit on a wafer of an encapsulation structure. The method comprises: attaching a system-on-chip (501) to a system area on a wafer (51); attaching a memory (502) to a storage area (52) on the wafer; and attaching a plurality of capacitors (503) to a capacitor area (53) on the wafer, wherein the capacitor area (53) is a leftover area outside of the system area (51) and the storage area (52).
A device and method for neural network computing, and a board and a readable storage medium. A computing device (201) is comprised in an integrated circuit device. The integrated circuit device comprises a universal interconnection interface and another processing device (203). The computing device (201) interacts with the other processing device (203) to jointly complete computing operations specified by a user. The integrated circuit device can further comprise a storage device. The storage device is respectively connected to the computing device (201) and the other processing device (203) for storing data of the computing device (201) and the other processing device (203).
The present disclosure relates to a device and method for implementing live migration, wherein the system on chip of the present disclosure is comprised in an integrated circuit device, and the integrated circuit device comprises a universal interconnect interface and other processing devices. A computing device interacts with the other processing devices to jointly complete a computing operation specified by a user. The integrated circuit device may further comprise a storage device. The storage device is respectively connected to the computing device and the other processing devices for use in storing data of the computing device and the other processing devices.
G06F 9/455 - Dispositions pour exécuter des programmes spécifiques Émulation; Interprétation; Simulation de logiciel, p.ex. virtualisation ou émulation des moteurs d’exécution d’applications ou de systèmes d’exploitation
G06F 15/78 - Architectures de calculateurs universels à programmes enregistrés comprenant une seule unité centrale
30.
DATA PROCESSING DEVICE, INTEGRATED CIRCUIT CHIP, DEVICE, AND IMPLEMENTATION METHOD THEREFOR
A data processing device, a method, an integrated circuit chip, an electronic device, and a card. The data processing device is comprised in a computing device. The computing device may be comprised in a combined processing device. The combined processing device may also comprise a universal interconnect interface and other processing devices. The computing device interacts with the other processing devices to jointly complete a computing operation specified by a user. The combined processing device may also comprise a storage device. The storage device is connected respectively to the computing device and the other processing devices and is used for storing data of the computing device and of the other processing devices. This is broadly applicable in various conversions of multidimensional data and increases the efficiency of data conversion.
A device for forward fusion of a neural network, a board, a method, and a readable storage medium. A computing device (201) is comprised in an integrated circuit device (20), and the integrated circuit device (20) comprises an interface device (202) and a processing device (203). The computing device (201) and the processing device (203) interact with each other to jointly complete a computing operation specified by a user. The integrated circuit device (20) may further comprise a memory device DRAM (204), and the memory device DRAM (204) is separately connected to the computing device (201) and the processing device (203) and used for storing data of the computing device (201) and the processing device (203).
Disclosed are a computing apparatus, an integrated circuit chip, a board card, a device and a method. The computing apparatus may be comprised in a combined processing apparatus, and the combined processing apparatus may further comprise an interface apparatus and other processing apparatuses. The computing apparatus and the other processing apparatuses interact with each other, so as to jointly complete a computing operation specified by a user. The combined processing apparatus may further comprise a storage apparatus, and the storage apparatus is respectively connected to the computing apparatus and the other processing apparatuses and is used for storing data of the computing apparatus and the other processing apparatuses. By means of the solution of the present disclosure, operation processing can be executed by using at least two pieces of small-bit-width data that represent large-bit-width data, such that the processing capacity of a processor is not affected by bit width. Fig. 7
Provided are an address deduction method employing a control flow graph, a device, and a readable storage medium. A computing device is included in an integrated circuit device. The integrated circuit device comprises a universal interconnect interface and other processing devices. The computing device interacts with said other processing devices to jointly complete a computing operation specified by a user. The integrated circuit device may further comprise a storage device. The storage device is respectively connected to the computing device and said other processing devices for storing data of the computing device and said other processing devices.
A method for computing a data dependence relationship in a program, and a computer readable storage medium, applied in a computing device (902). The computing device (902) is comprised in an integrated circuit device, and the integrated circuit device comprises a universal interconnect interface (904) and other processing device (906). The computing device (902) interacts with the other processing device (906) to jointly complete a user-specified computing operation. The integrated circuit device may further comprise a storage device (908), and the storage device (908) is separately connected to the computing device (902) and the other processing device (906) and is used for data storage of the computing device (902) and the other processing device (906).
The present disclosure relates to a method and device for allocating storage addresses for data in a memory, and a computing apparatus, wherein the computing apparatus may be comprised in a combined processing apparatus, and the combined processing apparatus may also comprise a universal interconnection interface and other processing apparatuses. The computing apparatus interacts with other processing apparatuses to jointly complete a computing operation specified by a user. The combined processing apparatus may also comprise a storage apparatus, which is separately connected to the computing apparatus and other processing apparatuses, and which is used for data of the computing apparatus and the other processing apparatuses. The technical solution of the present disclosure may improve the storage space utilization rate of the memory.
Provided are a method for realizing live migration, a computing device, and a readable storage medium. The computing device is comprised in an integrated circuit device, and the integrated circuit device comprises a universal interconnect interface and other processing devices. The computing device interacts with other processing devices to jointly complete a computing operation specified by a user. The integrated circuit device may also comprise a storage device, and the storage device is respectively connected to the computing device and other processing devices and is used for data storage of the computing device and other processing devices.
G06F 9/455 - Dispositions pour exécuter des programmes spécifiques Émulation; Interprétation; Simulation de logiciel, p.ex. virtualisation ou émulation des moteurs d’exécution d’applications ou de systèmes d’exploitation
37.
INTER-NODE COMMUNICATION METHOD AND DEVICE BASED ON MULTIPLE PROCESSING NODES
The present invention relates to an inter-node communication method and device based on multiple processing nodes, and a communication configuration apparatus. The communication configuration apparatus may be comprised in a combined processing apparatus, and the combined processing apparatus may further comprise an interconnection interface and other processing apparatus. The communication configuration apparatus interacts with the other processing apparatus to jointly complete a calculation operation specified by a user. The combined processing apparatus may further comprise a storage apparatus, and the storage apparatus is connected to the communication configuration apparatus and the other processing apparatus, respectively, and is used for storing data of the communication configuration apparatus and of the other processing apparatus. The technical solution of the present invention can improve the efficiency of inter-node communication.
The present disclosure relates to a method and device for constructing a communication topology structure on the basis of multiple processing nodes, and a communication configuration apparatus. The communication configuration apparatus can be comprised in a combined processing apparatus. The combined processing apparatus can further comprise an interconnection interface and other processing apparatuses. The communication configuration apparatus interacts with the other processing apparatuses to jointly complete a computing operation specified by a user. The combined processing apparatus can further comprise a storage apparatus. The storage apparatus is respectively connected to the communication configuration apparatus and the other processing apparatuses, and is used for storing data of the communication configuration apparatus and the other processing apparatuses. By means of the technical solution of the present disclosure, the efficiency of inter-chip communication can be improved.
An operation method, a processor, and a related product. The product comprises a storage device (390), an interface apparatus (391), a control device (392), and an artificial intelligence chip (389); the artificial intelligence chip (389) is connected to the storage device (390), the control device (392), and the interface apparatus (391) respectively; the storage device (390) is used for storing data; the interface apparatus (391) is used for implementing data transmission between the artificial intelligence chip (389) and an external device; and the control device (392) is used for monitoring the state of the artificial intelligence chip (389). The operation method or related product can increase the operation efficiency of the related product when performing matrix multiplication.
The present disclosure relates to a data quantification processing method and apparatus, an electronic device and a storage medium. The apparatus comprises a control module, and the control module comprises an instruction cache unit, an instruction processing unit, and a storage queue unit. The instruction cache unit is used to store computing instructions correlated to artificial neural network operations, the instruction processing unit is used to parse the computing instructions so as to obtain a plurality of operation instructions, the storage queue unit is used to store an instruction queue, and the instruction queue comprises a plurality of operation instructions or computing instructions to be executed according to the sequential order of the queue. By means of the above method, the present disclosure may improve the operation efficiency of a related product when neural network model operations are performed.
The present application relates to a task migration method and apparatus, and a computer device and a readable storage medium. The method comprises: when it is detected that a migratable task satisfies a preset migration condition, determining a target node matching the migratable task from various nodes according to a task attribute of the migratable task, the task attribute comprising a target number of operation units required for executing the migratable task; and migrating the migratable task to the target node, so that the target node executes the migratable task. According to the present application, the waiting duration of the migratable task can be reduced, and the execution efficiency of the migratable task is improved. The present application relates to an operation processing method and apparatus, and a computer device and a readable storage medium.
A memory allocation method and device, and a computer readable storage medium. The device comprises a combined processing means, and the combined processing means comprises a universal interconnection interface (1204) and another processing means. A master device (1202) of the device interacts with another processing means to jointly complete a designated computing operation. The combined processing means also comprises a storage means (1208). The storage means (1208) is connected to the master device (1202) and another processing means, separately, and used for data storage of the master device (1202) and another processing means.
G06F 12/06 - Adressage d'un bloc physique de transfert, p.ex. par adresse de base, adressage de modules, extension de l'espace d'adresse, spécialisation de mémoire
43.
DATA PROCESSING METHOD AND APPARATUS, COMPUTER DEVICE, AND STORAGE MEDIUM
A data processing method and apparatus, a computer device, and a storage medium. The method comprises: splitting first data according to a preset splitting mode to obtain a plurality of pieces of second data (S21); for any of the second data, performing a winograd convolution operation on the second data and a weight to obtain a plurality of first convolution results (S22); and merging the plurality of first convolution results according to a preset merging mode to obtain a dilated convolution result of the first data and the weight, wherein the preset merging mode is an inverse process of the preset splitting mode. By means of the method, operation efficiency of related products during operation of a neural network model can be improved.
A data processing method and apparatus, a computer device and a storage medium. The computer device comprises a control module, and the control module comprises: an instruction caching unit, an instruction processing unit and a queue storage unit, wherein the instruction caching unit is used for storing a calculation instruction associated with the computation of an artificial neural network; the instruction processing unit is used for parsing the calculation instruction to obtain a plurality of computation instructions; and the queue storage unit is used for storing an instruction queue, and the instruction queue comprises: a plurality of computation instructions or calculation instructions to be executed in the sequential order of the queue. By means of the data processing method and apparatus, the computer device and the storage medium, the computation efficiency of a related product during the computation of a neural network model is improved.
The present application relates to a data processing method and apparatus, a computer device and a storage medium. Disclosed is a board card, the board card comprising: a storage device, an interface apparatus, a control device, and an artificial intelligence chip comprising a data processing apparatus, wherein the artificial intelligence chip is respectively connected to the storage device, the control device and the interface apparatus; the storage device is used for storing data; the interface apparatus is used for realizing data transmission between the artificial intelligence chip and an external device; and the control device is used for monitoring the state of the artificial intelligence chip. According to the data processing method and apparatus, the computer device and the storage medium provided in the embodiments of the present application, the precision of quantization can be improved, and the operation time for Winograd convolution and the energy consumption are also reduced.
A winograd convolution operation method, apparatus, and device, and a storage medium. The device comprises a processor (61) and a memory (62), wherein the memory (62) is used for storing a program code, and the processor (61) is used for invoking the program code stored in the memory (62) to implement an operation method. The present invention can reduce the performance loss of a computer system, improve an operation speed, and improve processing efficiency.
An operation apparatus (10), comprising a storage unit (12), a control unit (11), and an operation unit (13). The operation apparatus (10) can reduce resource consumption of a convolution operation, improve a convolution operation speed, and reduce operation time.
A Winograd convolution operation method and a related product. The method comprises: in a process of training a neural network on the basis of a preconfigured Winograd convolution algorithm, respectively decomposing forward transformation operation of a reverse input gradient of a jth layer in the neural network and forward transformation operation of forward input feature data of the jth layer into summation, so as to obtain a transformation result of the forward transformation operation of the reverse input gradient of the jth layer, and a transformation result of the forward transformation operation of the forward input feature data of the jth layer on the basis of the summation (201); performing element-wise multiplication on the transformation result of the forward transformation operation of the reverse input gradient of the jth layer and the transformation result of the forward transformation operation of the forward input feature data of the jth layer, and obtaining a first multiplication result (202); decomposing inverse transformation operation of the first multiplication result into summation, and using a result obtained by summation as a weight difference of the jth layer (203); and completing training of the neural network according to the weight difference of the jth layer (204).
An operational apparatus and a related product. The product comprises a control module; the control module comprises: an instruction cache unit, an instruction processing unit and a storage queue unit; the instruction cache unit is used for storing a calculation instruction associated with an artificial neural network operation; the instruction processing unit is used for parsing the calculation instruction to obtain multiple operation instructions; and the storage queue unit is used for storing an instruction queue, the instruction queue comprising multiple operation instructions or calculation instructions to be executed according to the sequence of the queue. The present application can improve the operation efficiency of a related product when carrying out an operation of a neural network model.
G06N 3/063 - Réalisation physique, c. à d. mise en œuvre matérielle de réseaux neuronaux, de neurones ou de parties de neurone utilisant des moyens électroniques
50.
DATA PROCESSING METHOD AND DEVICE, COMPUTER EQUIPMENT AND STORAGE MEDIUM
A data processing method and device, a computer equipment and a storage medium. The data processing method comprises: according to the mean value of the absolute value of quantized data obtained by using a plurality of pairs of truncation thresholds to quantize a set of data to be quantized, determining a pair of truncation thresholds from the plurality of pairs of truncation thresholds, wherein the set of data to be quantized is a set of data during a winograd convolution processing, and each pair of truncation thresholds of the plurality of pairs of truncation thresholds comprise a positive truncation value and a negative truncation value that are symmetrical (101); according to the determined one pair of truncation thresholds, quantizing the set of data to be quantized to obtain first quantized data (102); according to the first quantized data, continuing executing the winograd convolution processing to obtain a quantized winograd convolution result (103); and inversely quantizing the quantized winograd convolution result to obtain a winograd convolution result (104). The described method can improve quantization precision and calculating performances.
The present invention relates to a data processing method and apparatus, and a computer device and a storage medium. A board disclosed comprises: a storage device, an interface apparatus and a control device, and an artificial intelligence chip comprising the data processing apparatus. The artificial intelligence chip is separately connected to the storage device, the control device, and the interface apparatus. The storage device is used for storing data. The interface apparatus is used for implementing data transmission between the artificial intelligence chip and an external device. The control device is used for monitoring the state of the artificial intelligence chip. The data processing method and apparatus, and the computer device and the storage medium provided by embodiments of the present invention can improve the precision of quantization, save the operation time of winograd convolution, and reduce energy consumption.
A computing device and method, and a related product. The device comprises a master control unit, a slave control unit, a storage unit, a master computing unit, and a slave computing unit. The invention effectively improves the energy efficiency ratio and computing speed of deep learning networks in terms of hardware architecture, thus improving the performance of the deep learning networks.
G06N 3/063 - Réalisation physique, c. à d. mise en œuvre matérielle de réseaux neuronaux, de neurones ou de parties de neurone utilisant des moyens électroniques
An operation method and a related product, the method comprising: acquiring feature data outputted by an upper layer convolutional network and a feature transformation matrix used for performing forward transformation on the feature data (201); on the basis of the feature transformation matrix, transforming the feature data to obtain a feature transformation result, wherein the transformation operation of the feature data is disassembled into a summation operation, and the feature transformation result is determined on the basis of the summation operation (202); acquiring the weight transformation result of the present layer convolutional network after forward transformation and performing a bitwise multiplication operation on the feature transformation result and the weight transformation result to obtain a multiplication operation result (203); acquiring an inverse transformation matrix used for performing inverse transformation on the multiplication operation result and, on the basis of the inverse transformation matrix, performing transformation on the multiplication operation result to obtain an operation result, wherein the transformation operation of the multiplication operation result is disassembled into a summation operation, and the operation result is determined on the basis of the summation operation (204); and outputting the operation result to a lower layer convolutional network (205).
An operation apparatus and a related product. The product comprises a control module, with the control module comprising an instruction cache unit, an instruction processing unit and a storage queue unit, wherein the instruction cache unit is used for storing a computing instruction associated with artificial neural network operation; the instruction processing unit is used for parsing the computing instruction to obtain a plurality of operation instructions; and the storage queue unit is used for storing an instruction queue, with the instruction queue comprising a plurality of operation instructions or computing instructions to be executed according to the sequence of the queue. The operation efficiency of the related product during the operation of a neural network model can thus be improved.
G06N 3/063 - Réalisation physique, c. à d. mise en œuvre matérielle de réseaux neuronaux, de neurones ou de parties de neurone utilisant des moyens électroniques
55.
DATA PROCESSING METHOD AND APPARATUS, AND COMPUTER DEVICE AND STORAGE MEDIUM
A data processing method and apparatus, and a computer device and a storage medium. The method comprises: splitting a first convolution kernel according to a step length N to obtain a plurality of second convolution kernels (S11); splitting first input data according to the step length N to obtain a plurality of second input data corresponding to the plurality of first convolution kernels (S12); for any second input data, executing a Winograd convolution operation on the second input data and the corresponding second convolution kernel to obtain a convolution result corresponding to the second input data (S13); and determining that a sum of the convolution results corresponding to the plurality of second input data is a convolution result of the first convolution kernel and the first input data (S14). By means of the above method, the reusability of data can be improved.
A data processing method and apparatus capable of reducing calculation amount, saving calculation time, and saving energy, and a related product. The data processing method comprises: splitting a convolution kernel having a size of greater than 3*3 into a plurality of sub-convolution kernels having a size of smaller than or equal to 3*3 (S201); according to position distribution of the plurality of sub-convolution kernels in the convolution kernel, splitting input data into a plurality of pieces of target sub-input data having a size of smaller than or equal to 4*4, each of the sub-convolution kernels corresponding to one or more pieces of target sub-input data (S202); for any sub-convolution kernel, performing a winograd convolution operation on the sub-convolution kernel and the corresponding target sub-input data, so as to obtain a convolution result corresponding to the sub-convolution kernel (S203); and performing a summation operation on convolution results corresponding to the plurality of sub-convolution kernels, so as to obtain a convolution result of the convolution kernel and the input data (S204).
The present disclosure relates to a data processing method and apparatus, a computer device, and a storage medium. The computer device comprises a control module, and the control module comprises an instruction cache unit, an instruction processing unit, and a storage queue unit. The instruction cache unit is used to store computing instructions correlated to artificial neural network operations; the instruction processing unit is used to parse the computing instructions so as to obtain a plurality of operation instructions; the storage queue unit is used to store an instruction queue, the instruction queue comprising a plurality of operation instructions or computing instructions to be executed according to the sequential order of the queue. By means of the foregoing method, the present disclosure may increase the operation efficiency of a related product when carrying out neural network model training.
G06N 3/063 - Réalisation physique, c. à d. mise en œuvre matérielle de réseaux neuronaux, de neurones ou de parties de neurone utilisant des moyens électroniques
58.
DATA SYNCHRONIZATION METHOD AND APPARATUS AND RELATED PRODUCT
A data synchronization method and apparatus and a related product. The method comprises: when receiving a state query instruction from a first processor, determining a descriptor of tensor data to be synchronized (S31); determining the amount of data that can be synchronized for the tensor data according to the descriptor of the tensor data (S32); generating a synchronous state instruction according to the descriptor of the tensor data and the amount of data that can be synchronized (S33); and sending the synchronous state instruction to the first processor (S34). According to the method, the efficiency of synchronizing data can be improved.
G06F 16/27 - Réplication, distribution ou synchronisation de données entre bases de données ou dans un système de bases de données distribuées; Architectures de systèmes de bases de données distribuées à cet effet
59.
DATA SYNCHRONIZATION METHOD AND DEVICE, AND RELATED PRODUCTS
The present application relates to a data synchronization method and device, and related products. Said method is applied to a first processor, and comprises: according to a descriptor of tensor data to be synchronized, determining the data features of said tensor data, the descriptor being used for indicating the shape of said tensor data; according to the data features of said tensor data, generating a status query instruction and sending the status query instruction to a second processor, the status query instruction being used for instructing the second processor to determine the amount of synchronizable data with respect to the tensor data and to generate a synchronization status instruction. Said method is able to improve the efficiency of data synchronization.
A neural network quantization method and apparatus, a chip, an electronic device and a board card. The method comprises: selecting a target quantization layer of a target neural network, wherein the target quantization layer comprises one or more of calculation layers of the target neural network (S110); and performing quantization on the selected target quantization layer (S120). By means of the method, the neural network quantization is realized, while the network accuracy loss caused by quantization can be reduced.
A data synchronization apparatus and a related product. The product comprises a control module, and the control module comprises: an instruction caching unit, an instruction processing unit and a queue storage unit. The instruction caching unit is used for storing computing instructions associated with an artificial neural network operation; the instruction processing unit is used for parsing the computing instructions to obtain a plurality of operation instructions; and the queue storage unit is used for storing an instruction queue, the instruction queue comprising a plurality of operation instructions or computing instructions to be executed according to a sequential order of the queue. By means of the described method, the present disclosure may improve the operation efficiency of the related product when carrying out neural network model operations.
The present application relates to a fractal calculating device and method, an integrated circuit, and a board card. The fractal computing device of the present application is included in an integrated circuit device. The integrated circuit device comprises a universal interconnect interface and other processing devices. The calculating device interacts with other processing devices to jointly complete a user specified calculation operation. The integrated circuit device may also comprise a storage device, the storage device is respectively connected with the calculating device and other processing devices and is used for data storage of the computing device and other processing devices.
Disclosed is an operation apparatus. The operation apparatus may comprise a processor, a memory controller, a storage unit and a plurality of operation nodes, wherein the processor is used for receiving an input instruction, the memory controller is used for loading an operand to the storage unit, and the operation nodes are used for executing the input instruction according to the input instruction and the operand to realize the processing of the the input instruction on the operand. The operation apparatus can improve operation efficiency.
G06N 3/063 - Réalisation physique, c. à d. mise en œuvre matérielle de réseaux neuronaux, de neurones ou de parties de neurone utilisant des moyens électroniques
Provided are a data processing method and a processing apparatus. The data processing method comprises: a general-purpose processor generates a binary instruction according to the device information of an end-side artificial intelligence processor, and generates an artificial intelligence learning task according to the binary instruction; the general-purpose processor transmits the artificial intelligence learning task to a cloud-side artificial intelligence processor to be run; the general-purpose processor receives a running result corresponding to the artificial intelligence learning task; the general-purpose processor determines an offline running file according to the running result, wherein the offline running file is generated according to the device information of the corresponding end-side artificial intelligence processor and the binary instruction when the running result meets a preset requirement. The present invention can realize debugging between an artificial intelligence algorithm model and the artificial intelligence processor in advance.
A data processing method and apparatus and a related product. The method comprises: when an operand of a decoded first processing instruction comprises an identifier of a descriptor, acquiring, according to the identifier of the descriptor, the content of the descriptor (S11a); and executing, according to the content of the descriptor, the first processing instruction (S12a). By means of the method, the operation efficiency, when an operation of a neural network model is performed, of a related product can be improved.
A data processing apparatus and a related product. The product comprises a control module, and the control module comprises: an instruction caching unit, an instruction processing unit and a queue storage unit, wherein the instruction caching unit is used for storing computing instructions associated with an artificial neural network operation; the instruction processing unit is used for resolving the computing instructions to obtain a plurality of operation instructions; and the queue storage unit is used for storing instruction queues, the instruction queues comprising a plurality of operation instructions to be executed or computing instructions to be executed according to a sequential order of the queues. The operation efficiency, when an operation of a neural network model is performed, of a related product can be improved.
The present application provides an artificial intelligence computing device and a related product. The artificial intelligence computing device is used for executing machine learning computation. For instructions in more than two instruction sets constituting a loop body, embodiments of the present application use the same operation code of an operation code storage region for repeat instructions, saving the storage space of the operation code. The amount of codes of each instruction in the instruction set of a second time slice can be reduced, the instruction storage space can be saved, and the computation efficiency is improved.
G06N 3/063 - Réalisation physique, c. à d. mise en œuvre matérielle de réseaux neuronaux, de neurones ou de parties de neurone utilisant des moyens électroniques
68.
NETWORK OFFLINE MODEL PROCESSING METHOD, ARTIFICIAL INTELLIGENCE PROCESSING DEVICE, AND RELATED PRODUCT
Disclosed in the present application are a network offline model processing method, an artificial intelligence processing device, and a related product. The related product comprises a combined processing device; the combined processing device comprises the artificial intelligence processing device, a universal interconnection interface, and other processing devices; the artificial intelligence processing device interacts with the other processing devices to jointly complete a calculation operation specified by a user. Embodiments of the present application facilitate improving the operation speed of a network offline model.
Provided in the present application are a computing device and a board card. The computing device is used for executing an LSTM operation. The board card comprises: a storage device, an interface device and a control device, and a neural network chip, wherein the neural network chip comprises a computing device, and the storage device is used for storing data; the interface device is used for realizing data transmission between the chip and an external device; and the control device is used for monitoring the state of the chip. The computing device provided in the present application has the advantage of low power consumption.
G06N 3/063 - Réalisation physique, c. à d. mise en œuvre matérielle de réseaux neuronaux, de neurones ou de parties de neurone utilisant des moyens électroniques
A computation method and apparatus, and a related product. A combined processing apparatus therein comprises: a machine learning computation apparatus, a universal interconnection interface, and other processing apparatuses; the machine learning computation apparatus interacts with the other processing apparatuses to collectively implement calculation operations specified by a user, and the combined processing apparatus also comprises: a storage apparatus, the storage apparatus respectively being connected to the machine learning computation apparatus and the other processing apparatuses, and being used for storing data of the machine learning computation apparatus and the other processing apparatuses. The present computation method and apparatus and related product can be used across platforms, and have good usability, rapid command conversion speed, high processing efficiency, low probability of error, and low labour and material costs for development.
A distribution system for machine learning operation. An operation result having low accuracy can be obtained when an operation task is calculated by using a first machine learning algorithm having low operational capability in a terminal server according to a terminal server control instruction. Moreover, an operation result having high accuracy can be obtained when the aforementioned same operation task is also calculated by using a second machine learning algorithm having high operational capability in a cloud server according to a cloud server control instruction. A user can separately obtain one operation result having the low accuracy and one operation result having the high accuracy by flexibly using different machine learning algorithms for respectively performing the same operation task, so as to satisfy user requirements. Moreover, because the operational capability of the terminal server is weak, a terminal operation result can be firstly output, so as to avoid waiting for a long time by a user and improve processing efficiency.
G06N 3/063 - Réalisation physique, c. à d. mise en œuvre matérielle de réseaux neuronaux, de neurones ou de parties de neurone utilisant des moyens électroniques
72.
DATA PREPROCESSING METHOD AND APPARATUS, COMPUTER DEVICE, AND STORAGE MEDIUM
A data preprocessing method and apparatus, a computer device, and a storage medium. Target output data corresponding to a target computational operation is stored in a first memory (200) adjacent to a processor (100) so as to reduce the number of times the target output data being read, thereby reducing the time taken to perform I/O read operations in a computational process, and improving speed and efficiency of the processor.
A model conversion method, an apparatus, a computer device, and a storage medium, wherein the method may convert an initial offline model into a target offline model. The described model conversion method, apparatus, computer device, and storage medium greatly reduce the data input volume of a computer device, and the conversion process is simple; thus, the data processing volume of the computer device may be reduced, processing efficiency may thereby be increased, and power consumption is reduced.
The present disclosure relates to a video retrieval method, a method, system and device for generating a video retrieval mapping relationship, and a storage medium. The video retrieval method comprises: acquiring a retrieval instruction, wherein the retrieval instruction carries retrieval information for retrieving a target frame picture; and obtaining the target frame picture according to the retrieval information and a preset mapping relationship. The method for generating a video retrieval mapping relationship comprises: performing a feature extraction operation on each frame picture in a video stream by using a feature extraction model so as to obtain a key feature sequence corresponding to each frame picture; inputting the key feature sequence corresponding to each frame picture into a text sequence extraction model for processing so as to obtain a text description sequence corresponding to each frame picture; and constructing a mapping relationship according to the text description sequence corresponding to each frame picture. By means of the video retrieval method and the method for generating a video retrieval mapping relationship provided in the present application, the efficiency of video retrieval can be improved, and human-machine interaction is made more intelligent.
G06F 17/00 - TRAITEMENT ÉLECTRIQUE DE DONNÉES NUMÉRIQUES Équipement ou méthodes de traitement de données ou de calcul numérique, spécialement adaptés à des fonctions spécifiques
75.
ALLOCATION SYSTEM, METHOD AND APPARATUS FOR MACHINE LEARNING, AND COMPUTER DEVICE
An allocation system for machine learning, comprising a terminal server (20) and a cloud server (10). The terminal server (20) is used for: acquiring demand information; generating a control instruction according to the demand information, wherein the control instruction comprises a terminal control instruction and a cloud control instruction; parsing the terminal control instruction to obtain a terminal control signal; and calculating a terminal workload of a machine learning algorithm of each stage according to the terminal control signal to obtain a terminal operation result. The cloud server (10) is used for parsing the cloud control instruction to obtain a cloud control signal, and calculating a cloud workload of the machine learning algorithm of each stage according to the cloud control signal to obtain a cloud operation result. The terminal operation result and the cloud operation result together compose an output result. The system utilizes computational resources of the terminal server (20) and the cloud server (10), and accelerates the operating speed. Also disclosed are an allocation method and apparatus for machine learning, a computer device and a computer-readable storage medium.
Provided in the present application are a compressor circuit, a Wallace tree circuit, a multiplier circuit, a chip and a device, the compressor circuit comprising a first full adder, a second full adder and a first selection circuit; an output end of the first full adder is connected to an input end of the first selection circuit, and an output end of the first selection circuit is connected to an input end of the second full adder; the first selection circuit is used to determine, according to the first selection signal, an input signal that is outputted by the first selection circuit to the second full adder; the input signal outputted by the first selection circuit to the second full adder and the highest bit signal of a multi-bit input signal of the compressor circuit are used to control the startup or shutdown of the second full adder, which may reduce the power consumption of a circuit as well as time delays.
H03K 19/20 - Circuits logiques, c. à d. ayant au moins deux entrées agissant sur une sortie; Circuits d'inversion caractérisés par la fonction logique, p.ex. circuits ET, OU, NI, NON
Disclosed are a scheduling method and a related apparatus. A computing apparatus in a server can be chosen to implement a computation request, thereby improving the running efficiency of the server.
A neural network processing method, comprising the following steps: obtaining a model dataset and model structure parameters of an original network (S100); obtaining an operational attribute of each compute node in the original network; operating the original network according to the model dataset and the model structure parameters of the original network and the operational attribute of each compute node, to obtain an instruction corresponding to each compute node in the original network (S200); and if the operational attribute of the current compute node is a first operational attribute, storing a network weight and the instruction corresponding to the current compute node into a first non-volatile memory, so as to obtain a first offline model corresponding to the original network (S300). Further provided are a computer system and a storage medium. The neural network processing method, the computer system, and the storage medium shorten the time for a processor to operate the same network, and improve the processing speed and efficiency of the processor.
G06N 3/063 - Réalisation physique, c. à d. mise en œuvre matérielle de réseaux neuronaux, de neurones ou de parties de neurone utilisant des moyens électroniques
79.
INTEGRATED CIRCUIT CHIP DEVICE AND RELATED PRODUCT
An integrated circuit chip device and a related product, the integrated circuit chip device comprising: a main processing circuit and a plurality of basic processing circuits; the main processing circuit or at least one basic processing circuits from among the plurality of basic processing circuits comprises: a compression mapping circuit (101), the compression mapping circuit (101) being used to execute the compression processing of each piece of data in a neural network computation. The integrated circuit chip device and the related product have the advantages of calculation volume being small and power consumption being low.
G06N 3/063 - Réalisation physique, c. à d. mise en œuvre matérielle de réseaux neuronaux, de neurones ou de parties de neurone utilisant des moyens électroniques
Provided are an integrated circuit chip device and related products. The integrated circuit chip device is used for performing a multiplication operation, a convolution operation or a training operation of a neural network. The device has the advantages of small calculation amount and low power consumption.
G06N 3/063 - Réalisation physique, c. à d. mise en œuvre matérielle de réseaux neuronaux, de neurones ou de parties de neurone utilisant des moyens électroniques
A neural network processing module. A mapping unit (101) of the neural network processing module receives an input neuron and a weight and processes the input neuron and/or the weight, so as to obtain a processed input neuron and a processed weight. A calculation unit (108) of the neural network processing module performs artificial neural network calculations on the processed input neuron and the processed weight. The technical solution reduces additional installation expenses and reduces traffic, thereby improving the efficiency of neural network calculations.
Provided are an integrated circuit chip apparatus and a related product, the integrated circuit chip apparatus being used for executing a multiplication operation, a convolution operation or a training operation of a neural network. The present technical solution has the advantages of a small amount of calculation and low power consumption.
A chip device and a related product. The chip device comprises a main unit and multiple basic units communicating with the main unit. Functions of the main unit comprise: obtaining a data block to be computed and an operation instruction (S201); classifying, as a distributed data block or a broadcast data block on the basis of the operation instruction, the data block to be computed (S202); and splitting the distributed data block to obtain multiple basic data blocks, distributing the multiple basic data blocks to the multiple basic units, and broadcasting the broadcast data block to the multiple basic units (S203). Functions of the basic units comprise: performing an inner product operation on the basic data blocks and the broadcast data block to obtain an operation result and sending the operation result to the main unit (S204). The main unit processes the operation result to obtain the data block to be computed and an instruction result of the operation instruction (S205). The invention shortens processing time periods and has low power consumption.
SHANGHAI CAMBRICON INFORMATION TECHNOLOGY CO., LTD (Chine)
Inventeur(s)
Liu, Shaoli
Hao, Yifan
Chen, Yunji
Guo, Qi
Chen, Tianshi
Abrégé
An operation apparatus and method for an artificial neural network. The operation apparatus for an artificial neural network comprises: a mapping unit for receiving an input neural cell and a weight value, producing connection relationship data of the input neural cell and an output neural cell, and outputting the input neural cell and the weight value after mapping, wherein a correlation between the input neural cell and the weight value after mapping is an input neural cell-weight value pair, and the mapping unit comprises: a first mapping unit for removing a weight value, the absolute value of which is less than or equal to a first threshold value or the value of which is 0 or less than the first threshold value; and/or a second mapping unit for removing an input neural cell, the absolute value of which is less than or equal to a second threshold value or the value of which is 0 or less than the second threshold value.
SHANGHAI CAMBRICON INFORMATION TECHNOLOGY CO., LTD (Chine)
Inventeur(s)
Liu, Shaoli
Hao, Yifan
Chen, Yunji
Guo, Qi
Chen, Tianshi
Abrégé
The device and method for supporting a fast artificial neural network operation. The device comprises: a mapping unit for receiving an input neuron, a weight value, and a connection relationship between the input neuron and an output neuron, optimizing the connection relationship, and outputting the mapped input neuron and the mapped weight value, wherein the correlation between the mapped input neuron and the mapped weight value is an input neuron-weight value pair. By means of the device and method, the connection relationship between the input neuron and the weight value is optimized by means of a sparse mapping unit and/or a fast mapping unit, thereby reducing the calculation amount, solving the problem of insufficient operational performance of a CPU and a GPU and large front-end decoding costs, and effectively improving the support for multi-level artificial neural network operation algorithms.
A simultaneous Localization and Mapping (SLAM) hardware accelerator apparatus, comprising: a storage portion for use in storing input data; temporary operation result data; final operation result data; instruction sets and/or algorithm parameter data required for an operation process; an operation portion which is connected to the storage portion, and which is used for completing a calculation of a SLAM-related algorithm and an application; and a control portion which is connected to the storage portion and the operation portion, and which used for controlling and coordinating the storage portion and the operation portion. Further provided is a method for completing a SLAM operation, said method controlling data transport, data operation, and running of a program by means of an instruction. Said apparatus and method may effectively accelerate SLAM algorithms according to different needs, and meet different operation needs while offering the advantages of being highly flexible, being highly configurable, performing operations quickly, having low power consumption, and the like.
G06F 15/16 - Associations de plusieurs calculateurs numériques comportant chacun au moins une unité arithmétique, une unité programme et un registre, p.ex. pour le traitement simultané de plusieurs programmes
A neural network training apparatus and method, for use in training parameters within a neural network: said method first using a nonlinear function to perform a nonlinear transformation on parameters to obtain transformation parameters (S1); then converting the transformation parameters to perform bit width conversion to obtain low bit width transformation parameters (S2); next acquiring a to-be-updated gradient value of the low bit width transformation parameters by means of a reverse process in the neural network to obtain a to-be-updated gradient value of the parameters prior to the nonlinear transformation according to the nonlinear function and said to-be-updated gradient value of the low bit width transformation parameters (S3); and finally updating the parameters according to the to-be-updated gradient value of the parameters (S4). The present method results in the parameters having a lower bit width after training while precision loss is lower.
A neural network computation apparatus and method. The neural network computation apparatus comprises: a control unit (100), a storage unit (200), a sparse selection unit (300), and a neural network computation unit (400); the control unit (100) is used for producing micro-commands respectively corresponding to each unit, and sending the micro-commands to each corresponding unit; the sparse selection unit (300) is used for selecting neural network data corresponding to an effective weighted value for computation from the neural network data stored in the storage unit (200) on the basis of the micro-command corresponding to the sparse selection unit (300) issued by the control unit (100) and according to position information indicated by the sparse data therein; and the neural network computation unit (400) is used for executing neural network computation on the neural network data selected by the sparse selection unit (300) on the basis of the micro-command corresponding to the neural network computation unit (400) issued by the control unit (100), in order to obtain computation results. The present apparatus and method improve the ability of the neural network computation apparatus to process different types of data, increasing the speed of neural network computation whilst reducing power consumption.
Provided are an apparatus and a method for performing an artificial neural network operation, the apparatus comprising a clock gating unit (7), an instruction cache unit (1), a controller unit (2), a direct memory access unit (3), an interconnection module (4), a main operation module (5) and a plurality of subordinate operation modules (6). The apparatus can realize the operation of multi-layer artificial neural network with low power consumption. During the artificial neural network operation, the clock gating unit (7), according to an instruction, controls clock signals of the following to turn on or set to be 0: the instruction cache unit (1), the controller unit (2), the direct memory access unit (3), the interconnection module (4), the main operation unit (5) and the plurality of subordinate operation modules (6), whereby the clock signals of the specific operation relevant units are preserved and the clock signals of the irrelevant units are set to be 0, thus reducing the number of modules involved in the operation and performing the artificial neural network with low power consumption.
G06N 3/063 - Réalisation physique, c. à d. mise en œuvre matérielle de réseaux neuronaux, de neurones ou de parties de neurone utilisant des moyens électroniques
90.
TLB DEVICE SUPPORTING MULTIPLE DATA FLOWS AND UPDATE METHOD FOR TLB MODULE
A TLB device supporting multiple data flows and an update method for a TLB module. The device comprises: a control unit corresponding to k data flows of a streaming application to be processed. k TLB modules are set, each of the TLB modules has two parts, namely a page and a page frame in one-to-one correspondence, and conversion from a logical address to a physical address is completed by means of a mapping relationship between the page and the page frame, wherein k is a natural number. According to the device and method, with regard to inherent features of streaming application data flows, the occurrence of the TLB miss situation can be greatly reduced during the conversion from a logical address to a physical address, so as to reduce the number of times a memory is accessed, thus greatly improving the performance of data accessing.
G06F 12/1027 - Traduction d'adresses utilisant des moyens de traduction d’adresse associatifs ou pseudo-associatifs, p.ex. un répertoire de pages actives [TLB]
91.
OPERATION UNIT, METHOD AND DEVICE CAPABLE OF SUPPORTING OPERATION DATA OF DIFFERENT BIT WIDTHS
An operation unit, operation method and operation device for configuring a bit width of operation data involved in an operation by configuring a bit-width domain in a configuration instruction. The method comprises: upon executing an operation according to an instruction, firstly determining if an operator having a bit width identical to that of operation data indicated by an operand in the instruction is present; if yes, sending the operand directly to a corresponding operator; otherwise, generating an operator merging policy and merging multiple operators into a new operator according to the operator merging policy, such that a bit width of the new operator matches the bit width of the operand, and then sending the operand to the new operator; and enabling the operator acquiring the operand to execute a neural network operation/matrix operation/vector operation. The operation unit, operation method and operation device can support operations on operation data having different bit widths, thus realizing highly effective neural network operations, matrix operations and vector operations, while also reducing the quantity of operators and reducing hardware area at the same time.
G06N 3/063 - Réalisation physique, c. à d. mise en œuvre matérielle de réseaux neuronaux, de neurones ou de parties de neurone utilisant des moyens électroniques
An operation device and a method of operating the same. The device comprises an instruction module (10); a data module (20); and an operation module (30). The instruction module (10) performs an operation on an instruction, including instruction buffering, instruction processing and determining a dependence relationship and the like. The data module (20) performs an operation on data, including reading data from a memory or writing data into a memory and inputting operation data into the operation module. The operation module (30) is used to perform a related operation on data according to an instruction. Upon executing an instruction, the device and method can perform a corresponding adjustment according to a length of data to be operated on and a scale of the operation module, improving performance when executing a task comprising a large amount of vector operations. The invention has the advantages of having a concise instruction structure and flexible and highly effective data operation.
A device and method for executing a neural network operation. The device comprises: an on-chip interconnection module and a plurality of neural network processing modules connected thereto and communicating therewith. The neural network processing modules can read or write, via the on-chip interconnection module, data to or form another neural network processing module. For multi-core multi-layer artificial neural network operations, the neural network operations in each layer are divided for the plurality of neural network processing modules to execute the same, so as to obtain data of respective operation results. Further, the plurality of neural network processing modules exchange therebetween the data of respective operation results.
G06N 3/063 - Réalisation physique, c. à d. mise en œuvre matérielle de réseaux neuronaux, de neurones ou de parties de neurone utilisant des moyens électroniques
94.
RMSPROP GRADIENT DESCENT ALGORITHM EXECUTION APPARATUS AND METHOD
Disclosed in the present invention are an RMSprop gradient descent algorithm execution apparatus and method. The apparatus comprises: a direct memory access unit, an instruction cache unit, a controller unit, a data cache unit, and a data processing module. The method comprises: first reading a gradient vector and a to-be-updated value vector, and initializing a mean square vector; and during each iteration, first updating the mean square vector by using the gradient vector, then calculating, by using the mean square vector, a corresponding gradient descent amount during the update, updating the to-be-updated parameter vector, and repeating the process until the to-be-updated vector converges. In the whole process, the mean square vector is always stored in the data cache unit. By means of the present invention, application of an RMSprop gradient descent algorithm can be implemented, and the efficiency of data processing can be greatly improved.
A device and method for performing Adam gradient descent training algorithm, the device comprising a direct memory access unit (1), an instruction cache unit (2), a controller unit (3), a data cache unit (4) and a data processing module (5). The method comprises: firstly, reading a gradient vector and a to-be-updated value vector, and initializing a first-order vector, a second-order vector and a corresponding exponential decay rate; at each iteration, updating the first-order vector and second-order vector by using the gradient vector, and calculating a first-order biased estimation vector and a second-order biased estimation vector; updating to-be-updated parameters by using the first-order biased estimation vector and second-order biased estimation vector; and continuing with training till the vector of the to-be-updated parameters is converged. The present invention may achieve the application of the Adam gradient descent algorithm, and greatly improve the data processing efficiency.
G06N 3/063 - Réalisation physique, c. à d. mise en œuvre matérielle de réseaux neuronaux, de neurones ou de parties de neurone utilisant des moyens électroniques
An apparatus for executing a vector merging operation. The apparatus comprises: a storage unit, for storing vector data related to a vector merging operation instruction; a register unit, used for storing scalar data related to the vector merging operation instruction; a control unit, used for encoding the vector merging operation instruction, and controlling an operation process of the vector merging operation instruction; and a vector merging unit, used for performing a vector merging operation on two pieces of to-be-merged input vector data according to the encoded vector merging operation instruction, the vector merging unit being a customized hardware circuit. By means of the apparatus and method for executing a vector merging operation, a full process for simplifying a vector merging instruction is implemented by means of a customized hardware circuit, that is, the vector merging operation can be implemented by means of a simplified vector merging instruction.
A device for performing a convolutional neural network, comprising an instruction storage unit (1), a controller unit (2), a data access unit (3), an interconnection module (4), a master operation module (5), and a plurality of slave operation modules (6). The device can implement a forward operation of one or more convolutional layers of an artificial neural network. For each layer, first, data is selected from an input neuron vector according to a convolution window, then convolution operation is performed with a convolution kernel to calculate an intermediate result of the layer, and then the intermediate result is biased and activated to obtain output data. The output data is used as input data of a next layer.
The present invention provides a device for executing a forwarding operation of a fully-connected layered neural network. The device comprises an instruction storage unit, a controller unit, a data access unit, a mutual connection module, a primary operating module, and multiple secondary operating modules. By using the device, forwarding operation on fully-connected layers of one or more layers of neural network can be implemented. For each layer, first, weighted summation of input neuron vectors is performed to calculate intermediate result vectors of this layer, then the intermediate result vectors are biased and activated to obtain output neuron vectors. The output neuron vectors are used as input neuron vectors of a next layer.
Disclosed in the present invention are a device and method for generating random vectors conforming to certain distribution. The device comprises: a storage unit, used for storing vector data related to a random vector generation instruction; a register unit, used for storing scalar data related to the random vector generation instruction; a control unit, used for encoding the random vector generation instruction, and controlling an execution process of the random vector generation instruction; and a random vector generation unit, used for generating, according to the encoded random vector generation instruction, random vectors conforming to a specified distribution, the random vector generation unit being a customized hardware circuit. In the device and method for generating random vectors provided in the present invention, a whole process for simplifying a random vector generation instruction is implemented by means of a customized hardware circuit, that is, a random vector generation operation can be implemented by means of a simplified random vector generation instruction.
A device and method for performing back training of a convolutional neural network. The device comprises an instruction storage unit (1), a controller unit (2), a data access unit (3), an interconnection module (4), a master operation module (5), and a plurality of slave operation modules (6). For each layer, first, data is selected from an input neuron vector according to a convolution window; then a gradient between data selected from a previous layer and data selected from a next layer is used as an input of an operation unit of the device; a convolution kernel is calculated an updated; next, a data gradient output by the device is calculated according to the convolution kernel, the data gradient, and a derivative function of an activation function, and is stored in a memory and output to the previous layer for back propagation calculation. The device and method temporarily store, on a scratchpad memory, data and weight parameters involved in the calculation, such that the back training operation of a convolutional neural network can be supported more flexibly and effectively, and the execution performance of an application containing a great amount of memory access can be improved.
brevets
