Abrégé

Provided are a spin orbit torque magnetic random access memory cell, a spin orbit torque magnetic random access memory array and a method for calculating a Hamming distance, wherein the spin orbit torque magnetic random access memory cell includes a magnetic tunnel junction; a first transistor, a drain terminal of the first transistor being connected to a bottom of the magnetic tunnel junction; and a second transistor, a drain terminal of the second transistor being connected to a top of the magnetic tunnel junction.

Classes IPC  ?

• G06F 7/57 - Unités arithmétiques et logiques [UAL], c. à d. dispositions ou dispositifs pour accomplir plusieurs des opérations couvertes par les groupes  ou pour accomplir des opérations logiques
• G11C 11/16 - Mémoires numériques caractérisées par l'utilisation d'éléments d'emmagasinage électriques ou magnétiques particuliers; Eléments d'emmagasinage correspondants utilisant des éléments magnétiques utilisant des éléments dans lesquels l'effet d'emmagasinage est basé sur l'effet de spin

Abrégé

The present disclosure provides an SOT-MRAM memory cell, comprising: a bottom electrode; a magnetic tunnel junction layer located on the bottom electrode; an orbital Hall effect layer located on the magnetic tunnel junction layer; a first transistor having a drain connected to the orbital Hall effect layer; and a second transistor having a drain connected to the bottom electrode. The present disclosure further provides an SOT-MRAM memory, an operation method, and an SOT-MRAM memory array.

Classes IPC  ?

• G11C 11/16 - Mémoires numériques caractérisées par l'utilisation d'éléments d'emmagasinage électriques ou magnétiques particuliers; Eléments d'emmagasinage correspondants utilisant des éléments magnétiques utilisant des éléments dans lesquels l'effet d'emmagasinage est basé sur l'effet de spin
• G11C 11/18 - Mémoires numériques caractérisées par l'utilisation d'éléments d'emmagasinage électriques ou magnétiques particuliers; Eléments d'emmagasinage correspondants utilisant des dispositifs à effet Hall

Abrégé

A compact vertical semiconductor device and a manufacturing method thereof, and an electronic apparatus including the semiconductor device are provided. According to the embodiments, the vertical semiconductor device may include: a plurality of vertical unit devices stacked on each other, in which the unit devices include respective gate stacks extending in a lateral direction, and each of the gate stacks includes a main body, an end portion, and a connection portion located between the main body and the end portion, and in a top view, a periphery of the connection portion is recessed relative to peripheries of the main body and the end portion; and a contact portion located on the end portion of each of the gate stacks, in which the contact portion is in contact with the end portion.

Classes IPC  ?

• H01L 29/78 - Transistors à effet de champ l'effet de champ étant produit par une porte isolée
• H01L 21/8234 - Technologie MIS
• H01L 27/088 - Dispositifs consistant en une pluralité de composants semi-conducteurs ou d'autres composants à l'état solide formés dans ou sur un substrat commun comprenant des éléments de circuit passif intégrés avec au moins une barrière de potentiel ou une barrière de surface le substrat étant un corps semi-conducteur comprenant uniquement des composants semi-conducteurs d'un seul type comprenant uniquement des composants à effet de champ les composants étant des transistors à effet de champ à porte isolée
• H01L 29/423 - Electrodes caractérisées par leur forme, leurs dimensions relatives ou leur disposition relative ne transportant pas le courant à redresser, à amplifier ou à commuter
• H01L 29/45 - Electrodes à contact ohmique

Abrégé

The present disclosure relates to the technical field of artificial neuron memory devices, and provides a reconfigurable neuron device based on ion gate regulation and a manufacturing method therefor. The device comprises: a synthetic antiferromagnetic layer, a metal oxide layer, an ionic liquid layer, and a top electrode layer stacked in sequence from bottom to top. The two opposite edges of the bottom end of the synthetic antiferromagnetic layer are provided with a left boundary antiferromagnetic layer and a right boundary antiferromagnetic layer having opposite magnetization directions, and a magnetic tunnel junction for outputting a spike signal is further provided in the middle of the bottom end of the synthetic antiferromagnetic layer. The metal oxide layer, the ionic liquid layer, and the top electrode layer constitute an ion gate, and the ionic liquid layer comprises positive ions and negative ions. When an input voltage is applied to the top electrode layer, oxygen ions in the metal oxide layer move along with the distribution of the positive ions and the negative ions in the ionic liquid layer to adjust the charge accumulation of a top interface of the synthetic antiferromagnetic layer, so as to regulate the leakage motion speed of a magnetic domain wall at the bottom of the synthetic antiferromagnetic layer by means of an RKKY action.

Classes IPC  ?

• H01L 43/00 - Dispositifs utilisant les effets galvanomagnétiques ou des effets magnétiques analogues; Procédés ou appareils spécialement adaptés à la fabrication ou au traitement de ces dispositifs ou de leurs parties constitutives
• H01L 43/08 - Résistances commandées par un champ magnétique
• H01L 43/12 - Procédés ou appareils spécialement adaptés à la fabrication ou le traitement de ces dispositifs ou de leurs parties constitutives
• G06N 3/063 - Réalisation physique, c. à d. mise en œuvre matérielle de réseaux neuronaux, de neurones ou de parties de neurone utilisant des moyens électroniques

Abrégé

Provided are a spin orbit torque magnetic random access memory cell, a memory array and a memory, wherein the spin orbit torque magnetic random access memory cell includes: a magnetic tunnel and a selector; the selector is a two-dimensional material based selector; the magnetic tunnel junction is arranged above or below the selector; the magnetic tunnel junction includes an antiferromagnetic layer and a free layer; the free layer is adjacent to the antiferromagnetic layer; when the selector is turned on, the memory cell is conducted, a current generates a spin current which is injected into the free layer, and a magnetization direction of the free layer is switched by the exchange bias effect between the free layer and the antiferromagnetic layer. A deterministic magnetization switching of SOT-MRAM memory cell under zero magnetic field at room temperature may be implemented without an external magnetic field by using the exchange bias effect and applying an optimized bias voltage of the magnetic tunnel junction, so as to achieve a purpose of data writing and implement SOT-MRAM memory cell with double terminal structure.

Classes IPC  ?

• H10B 61/00 - Dispositifs de mémoire magnétique, p.ex. dispositifs RAM magnéto-résistifs [MRAM]
• H10N 52/85 - Matériaux actifs magnétiques

Abrégé

Provided are a symmetric memory cell and a BNN circuit. The symmetric memory cell includes a first complementary structure and a second complementary structure, the second complementary structure being symmetrically connected to the first complementary structure in a first direction, wherein the first complementary structure includes a first control transistor configured to be connected to the second complementary structure, the second complementary structure includes a second control transistor, a drain electrode of the second control transistor and a drain electrode of the first control transistor being symmetrically arranged in the first direction and connected to a bit line, and the symmetric memory cell is configured to store a weight value 1 or 0.

Classes IPC  ?

• G11C 11/4096 - Circuits de commande ou de gestion d'entrée/sortie [E/S, I/O] de données, p.ex. circuits pour la lecture ou l'écriture, circuits d'attaque d'entrée/sortie ou commutateurs de lignes de bits
• G11C 11/408 - Circuits d'adressage
• G11C 11/4094 - Circuits de commande ou de gestion de lignes de bits
• H03K 19/017 - Modifications pour accélérer la commutation dans les circuits à transistor à effet de champ

Abrégé

Disclosed are a NOR-type memory device, a method of manufacturing the NOR-type memory device, and an electronic apparatus including the NOR-type memory device. The NOR-type memory device may include: a first gate stack extending vertically on a substrate, and a gate conductor layer and a memory functional layer; a first semiconductor layer surrounding a periphery of the first gate stack, extending along a sidewall of the first gate stack, and a first source/drain region, a first channel region and a second source/drain region arranged vertically in sequence; a conductive shielding layer surrounding a periphery of the first channel region; and a dielectric layer between the first channel region and the conductive shielding layer. The memory functional layer is located between the first semiconductor layer and the gate conductor layer. A memory cell is defined at an intersection of the first gate stack and the first semiconductor layer.

Classes IPC  ?

• H10B 43/27 - Dispositifs EEPROM avec des isolants de grille à piégeage de charge caractérisés par les agencements tridimensionnels, p ex. avec des cellules à des niveaux différents de hauteur la région de source et la région de drain étant à différents niveaux, p.ex. avec des canaux inclinés les canaux comprenant des parties verticales, p.ex. des canaux en forme de U
• H10B 43/10 - Dispositifs EEPROM avec des isolants de grille à piégeage de charge caractérisés par la configuration vue du dessus
• H01L 23/528 - Configuration de la structure d'interconnexion
• H10B 51/10 - Dispositifs de RAM ferro-électrique [FeRAM] comprenant des transistors ferro-électriques de mémoire caractérisés par la configuration vue du dessus
• H10B 51/20 - Dispositifs de RAM ferro-électrique [FeRAM] comprenant des transistors ferro-électriques de mémoire caractérisés par les agencements tridimensionnels, p ex. avec des cellules à des niveaux différents de hauteur
• H01L 29/06 - Corps semi-conducteurs caractérisés par les formes, les dimensions relatives, ou les dispositions des régions semi-conductrices
• H01L 29/775 - Transistors à effet de champ avec un canal à gaz de porteurs de charge à une dimension, p.ex. FET à fil quantique
• H01L 29/66 - Types de dispositifs semi-conducteurs
• H01L 29/786 - Transistors à couche mince
• H01L 29/423 - Electrodes caractérisées par leur forme, leurs dimensions relatives ou leur disposition relative ne transportant pas le courant à redresser, à amplifier ou à commuter

Abrégé

The present disclosure relates to a field of memory technical, and in particular to a magnetoresistive device, a method for changing a resistance state of the magnetoresistive device, and a synapse learning module. The magnetoresistive device includes a top electrode, a ferromagnetic reference layer, a tunneling layer, a ferromagnetic free layer, a spin-orbit coupling layer, and a bottom electrode that are arranged in sequence along a preset direction, where the spin-orbit coupling layer includes a first thickness region and a second thickness region distributed alternately, and a thickness of the first thickness region is different form a thickness of the second thickness region; and the ferromagnetic free layer includes a pinning region, and a position of the pinning region is in one-to-one correspondence with a position of the first thickness region.

Classes IPC  ?

• H10N 50/10 - Dispositifs magnéto-résistifs
• H10B 61/00 - Dispositifs de mémoire magnétique, p.ex. dispositifs RAM magnéto-résistifs [MRAM]
• H10N 50/85 - Matériaux actifs magnétiques
• G11C 11/16 - Mémoires numériques caractérisées par l'utilisation d'éléments d'emmagasinage électriques ou magnétiques particuliers; Eléments d'emmagasinage correspondants utilisant des éléments magnétiques utilisant des éléments dans lesquels l'effet d'emmagasinage est basé sur l'effet de spin

Abrégé

A semiconductor device and a method of manufacturing the same are disclosed. The semiconductor device includes: a substrate and a channel portion. The channel portion includes a first portion including a fin-shaped structure protruding with respect to the substrate and a second portion located above the first portion and spaced apart from the first portion. The second portion includes one or more nanowires or nanosheets spaced apart from each other. Source/drain portions are arranged on two opposite sides of the channel portion in a first direction and in contact with the channel portion. A gate stack extends on the substrate in a second direction intersecting with the first direction, so as to intersect with the channel portion.

Classes IPC  ?

• H01L 29/06 - Corps semi-conducteurs caractérisés par les formes, les dimensions relatives, ou les dispositions des régions semi-conductrices
• H01L 29/423 - Electrodes caractérisées par leur forme, leurs dimensions relatives ou leur disposition relative ne transportant pas le courant à redresser, à amplifier ou à commuter
• H01L 29/66 - Types de dispositifs semi-conducteurs
• H01L 29/775 - Transistors à effet de champ avec un canal à gaz de porteurs de charge à une dimension, p.ex. FET à fil quantique
• H01L 29/78 - Transistors à effet de champ l'effet de champ étant produit par une porte isolée

Abrégé

A metallization stack is provided. The metallization stack may include at least one interconnection line layer and at least one via hole layer arranged alternately on a substrate. At least one pair of adjacent interconnection line layer and via hole layer in the metallization stack includes an interconnection line in the interconnection line layer; and a via hole in the via hole layer. The via hole layer is arranged closer to the substrate than the interconnection line layer, and at least part of the interconnection line extends longitudinally in a first direction, and a sidewall of the at least part of the interconnection line in the first direction is substantially coplanar with at least upper portion of a corresponding sidewall of the via hole under the at least part of the interconnection line.

Classes IPC  ?

• H01L 23/528 - Configuration de la structure d'interconnexion
• H01L 21/768 - Fixation d'interconnexions servant à conduire le courant entre des composants distincts à l'intérieur du dispositif
• H01L 23/522 - Dispositions pour conduire le courant électrique à l'intérieur du dispositif pendant son fonctionnement, d'un composant à un autre comprenant des interconnexions externes formées d'une structure multicouche de couches conductrices et isolantes inséparables du corps semi-conducteur sur lequel elles ont été déposées

Abrégé

Provided is a cache memory, including: a first field-effect transistor, a field-like spin torque layer underneath a magnetic tunnel junction, an electrode, and a second field-effect transistor sequentially arranged and connected; wherein the first field-effect transistor is configured to provide a writing current and to control the on-off of the writing current through a gate electrode; the field-like spin torque layer is configured to generate field-like spin torques for switching a first ferromagnetic layer of the magnetic tunnel junction; the magnetic tunnel junction includes a first ferromagnetic layer, a tunneling layer, a second ferromagnetic layer and a pinning layer arranged sequentially; the electrode is configured to connect the cache memory with the second field-effect transistor; and the second field-effect transistor is configured to control the on-off of the second field-effect transistor through the gate electrode to read the resistive state of the magnetic tunnel junction.

Classes IPC  ?

• G11C 11/16 - Mémoires numériques caractérisées par l'utilisation d'éléments d'emmagasinage électriques ou magnétiques particuliers; Eléments d'emmagasinage correspondants utilisant des éléments magnétiques utilisant des éléments dans lesquels l'effet d'emmagasinage est basé sur l'effet de spin
• H10B 61/00 - Dispositifs de mémoire magnétique, p.ex. dispositifs RAM magnéto-résistifs [MRAM]
• H10N 50/20 - Dispositifs à courant commandé à polarisation de spin
• H10N 50/80 - Dispositifs galvanomagnétiques - Détails de structure
• H10N 50/85 - Matériaux actifs magnétiques
• H10N 50/01 - Fabrication ou traitement

Abrégé

The present invention provides a three-dimensional reservoir based on a volatile three-dimensional memristor and a manufacturing method therefor. A storage layer, a selection layer and an electrode layer in each through hole in a three-dimensional reservoir form a memristor, i.e., form a reservoir unit, and a three-dimensional reservoir based on a volatile three-dimensional memristor is formed based on a stack structure and a plurality of through holes. Specifically, in the present invention, virtual nodes generated on the basis of the dynamic characteristics of a three-dimensional memristor are used to construct a three-dimensional reservoir. First, an interfacial memristor is constructed and the volatile characteristics thereof are confirmed by means of electrical tests; a vertical three-dimensional array is prepared on the basis of the volatile memristor, and the dynamic characteristics of the device are adjusted by means of a Schottky barrier, different layers of the three-dimensional reservoir respectively corresponding to reservoirs of different layers. Different reservoirs are constructed by respectively regulating devices of different layers, thereby increasing the richness of the virtual nodes, improving the parallelism and the recognition accuracy of a system, and reducing the area of the system.

Classes IPC  ?

• H01L 27/24 - Dispositifs consistant en une pluralité de composants semi-conducteurs ou d'autres composants à l'état solide formés dans ou sur un substrat commun comprenant des composants à l'état solide pour le redressement, l'amplification ou la commutation, sans barrière de potentiel ni barrière de surface

Abrégé

The present invention provides a photolithography device, a gas bath apparatus and a gas bath generator thereof. The gas bath generator comprises a closed annular body. The closed annular body is arranged around a working area. An annular flow channel is formed in the closed annular body. The closed annular body is further provided with circumferentially distributed gas outlets in communication with the annular flow channel. By means of the gas outlets, a closed airflow layer distributed around the working area is generated. The gas bath generator provided by the present invention can be used for a photolithography device and circumferentially arranged around an exposure area of the photolithography device to form a closed airflow layer isolating the exposure area from the outside around the periphery of the exposure area. The present invention solves the problem of how to reduce gas contamination and particle contamination in the silicon wafer microenvironment located in the exposure area of the photolithography device.

Classes IPC  ?

• G03F 7/20 - Exposition; Appareillages à cet effet

Abrégé

Provided are a semiconductor device, a method of manufacturing the semiconductor device, and an electronic apparatus including the semiconductor device. According to the embodiments, the semiconductor device may include: a vertical structure extending in a vertical direction relative to a substrate; and a nanosheet extending from the vertical structure and spaced apart from the substrate in the vertical direction, wherein the nanosheet includes a first portion in a first orientation, and at least one of an upper surface and a lower surface of the first portion is not parallel to a horizontal surface of the substrate.

Classes IPC  ?

• H01L 29/10 - Corps semi-conducteurs caractérisés par les formes, les dimensions relatives, ou les dispositions des régions semi-conductrices avec des régions semi-conductrices connectées à une électrode ne transportant pas le courant à redresser, amplifier ou commuter, cette électrode faisant partie d'un dispositif à semi-conducteur qui comporte trois électrodes ou plus
• H01L 27/092 - Transistors à effet de champ métal-isolant-semi-conducteur complémentaires
• H01L 29/06 - Corps semi-conducteurs caractérisés par les formes, les dimensions relatives, ou les dispositions des régions semi-conductrices
• H01L 29/423 - Electrodes caractérisées par leur forme, leurs dimensions relatives ou leur disposition relative ne transportant pas le courant à redresser, à amplifier ou à commuter
• H01L 29/49 - Electrodes du type métal-isolant-semi-conducteur
• H01L 29/775 - Transistors à effet de champ avec un canal à gaz de porteurs de charge à une dimension, p.ex. FET à fil quantique
• H01L 21/8238 - Transistors à effet de champ complémentaires, p.ex. CMOS
• H01L 29/66 - Types de dispositifs semi-conducteurs

Abrégé

Disclosed are a vertical semiconductor device having a conductive layer, a method of manufacturing the vertical semiconductor device, and an electronic device including the vertical semiconductor device. According to an embodiment, the semiconductor device may include: a substrate; a first metallic layer, a channel layer and a second metallic layer which are sequentially disposed on the substrate; and a gate stack formed around at least a part of a periphery of the channel layer, wherein each of the first metallic layer, the second metallic layer, and the channel layer is of single crystal structure.

Classes IPC  ?

• H01L 29/423 - Electrodes caractérisées par leur forme, leurs dimensions relatives ou leur disposition relative ne transportant pas le courant à redresser, à amplifier ou à commuter
• H01L 29/786 - Transistors à couche mince
• H01L 29/06 - Corps semi-conducteurs caractérisés par les formes, les dimensions relatives, ou les dispositions des régions semi-conductrices
• H01L 29/66 - Types de dispositifs semi-conducteurs
• H01L 29/775 - Transistors à effet de champ avec un canal à gaz de porteurs de charge à une dimension, p.ex. FET à fil quantique
• H01L 27/088 - Dispositifs consistant en une pluralité de composants semi-conducteurs ou d'autres composants à l'état solide formés dans ou sur un substrat commun comprenant des éléments de circuit passif intégrés avec au moins une barrière de potentiel ou une barrière de surface le substrat étant un corps semi-conducteur comprenant uniquement des composants semi-conducteurs d'un seul type comprenant uniquement des composants à effet de champ les composants étant des transistors à effet de champ à porte isolée
• H01L 21/8234 - Technologie MIS

Abrégé

A hardware implementation method and apparatus for a reservoir computing model based on a random resistor array, and an electronic device, which relate to the fields of machine learning and artificial intelligence. The method comprises: acquiring a random weight of a reservoir layer, which is generated on the basis of a resistance-variable device crossbar array; applying a breakdown voltage to the resistance-variable device crossbar array, so as to form a randomly distributed random resistance matrix; converting an input signal into a read voltage signal by means of a circuit of a printed circuit board, and performing, on the basis of the read voltage signal and the random resistance matrix, vector matrix multiplication to determine an output voltage signal; and repeating the step of converting an input signal into a read voltage signal by means of the circuit of the printed circuit board and performing, on the basis of the read voltage signal and the random resistance matrix, vector matrix multiplication to determine an output voltage signal, and then simulating a loop iteration process of the reservoir layer. Therefore, the efficient hardware realization of a large-scale random weight and a reservoir computing model is achieved, and in an edge computing application scenario in which the computing power is limited, the possibility is provided for the efficient hardware realization of the reservoir computing model.

Classes IPC  ?

• G06N 3/063 - Réalisation physique, c. à d. mise en œuvre matérielle de réseaux neuronaux, de neurones ou de parties de neurone utilisant des moyens électroniques

Abrégé

A method of manufacturing a parallel structure of semiconductor devices includes: disposing a semiconductor stack, which includes source/drain layers disposed vertically in sequence and channel layers therebetween, on a substrate; patterning the semiconductor stack into a predetermined shape to define an active region; forming gate stacks around at least part of peripheries of the channel layers; forming an isolation layer on peripheries of the active region and the gate stack; forming first to third conductive channels on a sidewall of the isolation layer; determining the pre-determined shape and a shape of the gate stacks, such that one of the source/drain layers on two sides of the channel layer passes through the isolation layer to contact the first conductive channel, while the other one passes through the isolation layer to contact the second conductive channel, and the gate stack passes through the isolation layer to contact the third conductive channel.

Classes IPC  ?

• H01L 27/088 - Dispositifs consistant en une pluralité de composants semi-conducteurs ou d'autres composants à l'état solide formés dans ou sur un substrat commun comprenant des éléments de circuit passif intégrés avec au moins une barrière de potentiel ou une barrière de surface le substrat étant un corps semi-conducteur comprenant uniquement des composants semi-conducteurs d'un seul type comprenant uniquement des composants à effet de champ les composants étant des transistors à effet de champ à porte isolée
• H01L 21/77 - Fabrication ou traitement de dispositifs consistant en une pluralité de composants à l'état solide ou de circuits intégrés formés dans ou sur un substrat commun
• H01L 25/065 - Ensembles consistant en une pluralité de dispositifs à semi-conducteurs ou d'autres dispositifs à l'état solide les dispositifs étant tous d'un type prévu dans le même sous-groupe des groupes , ou dans une seule sous-classe de , , p.ex. ensembles de diodes redresseuses les dispositifs n'ayant pas de conteneurs séparés les dispositifs étant d'un type prévu dans le groupe
• H01L 29/66 - Types de dispositifs semi-conducteurs
• H01L 29/78 - Transistors à effet de champ l'effet de champ étant produit par une porte isolée

Abrégé

The present invention belongs to the technical field of artificial intelligence, and particularly relates to a method for preparing a reservoir element. The method comprises the following steps: a) sequentially arranging, on a substrate, a bottom electrode layer, a dielectric layer, a resistive layer and a top electrode layer, so as to obtain a reservoir element to be annealed; and b) performing annealing processing on the reservoir element to be annealed, so as to obtain a reservoir element, wherein the temperature of the annealing processing ranges from 300ºC to 700ºC, and the time of the annealing processing ranges from 30s to 100s. In the method provided in the present invention, after being prepared, the reservoir element is subjected to rapid annealing processing, such that defects are re-distributed after rapid annealing, thereby forming a more stable membrane; and a ferroelectric O phase can also be introduced into the membrane. By means of rapid annealing processing, the power consumption of a reservoir element can be effectively reduced, and the computing accuracy can be improved.

Classes IPC  ?

• H01L 45/00 - Dispositifs à l'état solide spécialement adaptés pour le redressement, l'amplification, la production d'oscillations ou la commutation, sans barrière de potentiel ni barrière de surface, p.ex. triodes diélectriques; Dispositifs à effet Ovshinsky; Procédés ou appareils spécialement adaptés à la fabrication ou au traitement de ces dispositifs ou de leurs parties constitutives

Abrégé

Provided are a memory cell structure, a memory array structure, and a voltage biasing method. The memory cell structure includes: a substrate layer, a well layer and a transistor. The substrate layer is configured to support the memory cell structure; the well layer is embedded in the substrate layer, an upper surface of the well layer is flush with an upper surface of the substrate layer, and a transistor is arranged on the well layer. In the present disclosure, a deep well bias is performed on the memory cell structure, so that the well voltage of the memory cell may be individually biased to a specific voltage, and in combination with the redesigned memory cell array structure, the applied programming voltage mostly falls on the memory cell structure. This reduces the programming voltage of the memory cell, and avoids a breakdown of the selecting transistor due to an excessively large voltage, thereby ensuring a great reliability of the device and a higher efficiency within the area of the memory cell array structure.

Classes IPC  ?

• G11C 13/00 - Mémoires numériques caractérisées par l'utilisation d'éléments d'emmagasinage non couverts par les groupes , ou

Abrégé

Provided in the embodiments of the present application are a semiconductor device and a manufacturing method therefor. The semiconductor device comprises a substrate, a first electrode layer, a functional layer and a second electrode layer, wherein the functional layer is located between the first electrode layer and the second electrode layer, the functional layer comprises a first area, and a second area which surrounds the first area and is of a U-shaped structure, and the orientation of a U-shaped opening of the second area is parallel to the substrate and faces away from the first area, that is, the U-shaped opening faces an outer side; the material of the first area at least comprises germanium; and the second area comprises a U-shaped ferroelectric layer and a U-shaped gate electrode which are sequentially stacked. In the embodiments of the present application, a ferroelectric layer of a U-shaped structure is used as a storage layer of a memory device, and when a gate voltage is kept unchanged, a U-shaped channel can increase an electric field of the ferroelectric layer, thereby increasing a storage window of the whole semiconductor device; and when the storage window of the whole semiconductor device is kept unchanged, the gate voltage can be reduced, thereby reducing the power consumption of the semiconductor device, and improving the performance of the memory device.

Classes IPC  ?

• H01L 29/78 - Transistors à effet de champ l'effet de champ étant produit par une porte isolée
• H01L 21/336 - Transistors à effet de champ à grille isolée

Abrégé

The present application provides a semiconductor device and a manufacturing method therefor. The method comprises: providing a substrate, wherein the substrate is provided with a first source-drain layer, a channel layer and a second source-drain layer that are sequentially stacked, and the periphery of the channel layer is provided with a gate dielectric layer and a gate structure which surround the channel layer in the horizontal direction; forming a spacer layer on the outer side wall of the gate structure; etching the gate structure, so as to reduce the thickness of the gate structure; forming a sacrificial structure covering the gate structure, and a covering layer covering the second source-drain layer, the sacrificial structure and the spacer layer, so that the sacrificial structure is located on the periphery of the second source-drain layer and located on the inner side of the spacer layer; then etching the covering layer to obtain a first contact hole passing through the sacrificial structure, and removing the sacrificial structure at the bottom of the first contact hole to form a gap below the first contact hole; and forming first contact structures in the first contact hole and the gap, thereby realizing self-alignment of the bottoms of the first contact structures and the gate structure, and improving the reliability of a device.

Classes IPC  ?

• H01L 29/423 - Electrodes caractérisées par leur forme, leurs dimensions relatives ou leur disposition relative ne transportant pas le courant à redresser, à amplifier ou à commuter
• H01L 29/78 - Transistors à effet de champ l'effet de champ étant produit par une porte isolée
• H01L 21/336 - Transistors à effet de champ à grille isolée

Abrégé

Disclosed are a nanowire/sheet device and a manufacturing method therefor, and electronic equipment comprising the nanowire/sheet device. According to embodiments, the nanowire/sheet device comprises: a substrate; a nanowire/sheet spaced apart from the surface of the substrate and extending in a first direction; a source/drain layer located at two opposite ends of the nanowire/sheet in the first direction and connected to the nanowire/sheet; a gate stack extending in a second direction intersecting the first direction to surround the nanowires/sheet; and a first side wall disposed on a sidewall of the gate stack, wherein the first side wall comprises a continuously extending material layer having a first portion along the surface of the nanowire/sheet, a second portion along a sidewall of the source/drain layer facing the gate stack, and a third portion along the sidewall of the gate stack facing the source/drain layer, with a slot or interface between the second portion and the third portion.

Classes IPC  ?

• H01L 29/06 - Corps semi-conducteurs caractérisés par les formes, les dimensions relatives, ou les dispositions des régions semi-conductrices
• H01L 29/78 - Transistors à effet de champ l'effet de champ étant produit par une porte isolée
• H01L 21/336 - Transistors à effet de champ à grille isolée

Abrégé

Provided in the embodiments of the present application are a semiconductor device and a method for manufacturing same. The method comprises: sequentially forming a first electrode layer, a semiconductor layer and a second electrode layer on a substrate; then etching away part of the semiconductor layer from a side wall of the semiconductor layer to form an opening; then forming a channel layer in the opening and on a side wall of the first electrode layer and a side wall of the second electrode layer, wherein the channel layer comprises a first channel portion located in the opening and a second channel portion other than the first channel portion in the opening; filling the first channel portion with a dummy gate layer; then etching away part of the dummy gate layer from a side wall of the dummy gate layer by taking the second channel portion as a mask; then removing the second channel portion and the first channel portion which is in contact with an upper and a lower surface of the dummy gate layer, so as to form a recess formed by the first electrode layer or the second electrode layer, the channel layer and the dummy gate layer; and filling the recess with a dielectric material to form an isolation side wall, wherein the formed isolation side wall can reduce the parasitic capacitance of a semiconductor device and optimize the performance thereof.

Classes IPC  ?

• H01L 29/78 - Transistors à effet de champ l'effet de champ étant produit par une porte isolée
• H01L 29/08 - Corps semi-conducteurs caractérisés par les formes, les dimensions relatives, ou les dispositions des régions semi-conductrices avec des régions semi-conductrices connectées à une électrode transportant le courant à redresser, amplifier ou commuter, cette électrode faisant partie d'un dispositif à semi-conducteur qui comporte trois électrodes ou plus

Abrégé

Disclosed are a nanowire/sheet component having a crystal sidewall, a manufacturing method therefor, and an electronic device comprising the nanowire/sheet component. According to an embodiment, a nanowire/sheet component may comprise: a substrate; a nanowire/sheet spaced apart from a surface of the substrate and extending along a first direction; a source/drain layer located at two opposite ends of the nanowire/sheet in the first direction and connected to the nanowire/sheet; a gate stack extending along a second direction intersecting the first direction to surround the nanowire/sheet; and a sidewall disposed on a side wall of the gate stack, the sidewall having substantially the same crystal structure as the nanowire/sheet in at least a part of a region adjacent to the nanowire/sheet.

Classes IPC  ?

• H01L 21/336 - Transistors à effet de champ à grille isolée
• H01L 29/06 - Corps semi-conducteurs caractérisés par les formes, les dimensions relatives, ou les dispositions des régions semi-conductrices
• H01L 29/78 - Transistors à effet de champ l'effet de champ étant produit par une porte isolée

Abrégé

A semiconductor apparatus having a staggered structure, a method of manufacturing a semiconductor apparatus, and an electronic device including the semiconductor apparatus. The semiconductor apparatus includes a first element and a second element on a substrate. The first element and the second element each include a comb-shaped structure. The comb-shaped structure includes a first portion extending in a vertical direction relative to the substrate, and at least one second portion extending from the first portion in a lateral direction relative to the substrate and spaced from the substrate. A height of the second portion of the first element in the vertical direction is staggered with respect to a height of the second portion of the second element in the vertical direction. A material of the comb-shaped structure of the first element is different from a material of the comb-shaped structure of the second element.

Classes IPC  ?

• H01L 29/06 - Corps semi-conducteurs caractérisés par les formes, les dimensions relatives, ou les dispositions des régions semi-conductrices
• H01L 29/786 - Transistors à couche mince
• H01L 27/092 - Transistors à effet de champ métal-isolant-semi-conducteur complémentaires
• H01L 29/66 - Types de dispositifs semi-conducteurs
• H01L 29/78 - Transistors à effet de champ l'effet de champ étant produit par une porte isolée

Abrégé

A semiconductor device having a zigzag structure, a method of manufacturing the semiconductor device, and an electronic including the semiconductor device. The semiconductor device may include a semiconductor layer (1031) extending in zigzag in a vertical direction with respect to a substrate (1001). The semiconductor layer (1031) includes one or more first portions disposed in sequence and spaced apart from each other in the vertical direction and second portions respectively disposed on and connected to opposite ends of each first portion. A second portion at one end of each first portion extends from the one end in a direction of leaving the substrate, and a second portion at the other end of the each first portion extends from the other end in a direction of approaching the substrate. First portions adjacent in the vertical direction are connected to each other by the same second portion.

Classes IPC  ?

• H01L 29/786 - Transistors à couche mince
• H01L 27/092 - Transistors à effet de champ métal-isolant-semi-conducteur complémentaires
• H01L 29/10 - Corps semi-conducteurs caractérisés par les formes, les dimensions relatives, ou les dispositions des régions semi-conductrices avec des régions semi-conductrices connectées à une électrode ne transportant pas le courant à redresser, amplifier ou commuter, cette électrode faisant partie d'un dispositif à semi-conducteur qui comporte trois électrodes ou plus
• H01L 29/423 - Electrodes caractérisées par leur forme, leurs dimensions relatives ou leur disposition relative ne transportant pas le courant à redresser, à amplifier ou à commuter
• H01L 21/8238 - Transistors à effet de champ complémentaires, p.ex. CMOS
• H01L 29/66 - Types de dispositifs semi-conducteurs

Abrégé

The present invention relates to a vertical MOSFET device and a manufacturing method therefor and the application thereof. The method comprises: forming, on a substrate, a first silicon layer, a first germanium silicon layer, a second germanium silicon layer, a third germanium silicon layer and a second silicon layer which are vertically stacked from bottom to top, wherein the molar content of germanium in the first germanium silicon layer and the molar content of germanium in the third germanium silicon layer are both greater than the content of germanium in the second germanium silicon layer; performing etching to form a nano-stack structure; selectively etching the first germanium silicon layer and the third germanium silicon layer, so as to form a first groove and a third groove; forming inner side walls of extension regions in the first groove and the third groove; selectively etching the second germanium silicon layer, so as to form a gate groove; forming a dummy gate in the gate groove; forming a source electrode and a drain electrode; forming an active region having a shallow trench isolation layer; and removing the dummy gate, so as to form a gate dielectric layer and a gate electrode. The present invention can effectively control the size of a trench, the sizes of inner side walls of extension regions, the size of a gate electrode, etc., and is applicable to nanosheet or nanowire structures.

Classes IPC  ?

• H01L 21/335 - Transistors à effet de champ
• H01L 29/06 - Corps semi-conducteurs caractérisés par les formes, les dimensions relatives, ou les dispositions des régions semi-conductrices

Abrégé

A memory device and a manufacturing method therefor, which relate to the technical field of semiconductors. The memory device comprises a substrate; a memory unit array, which is located on the substrate and comprises a plurality of memory units, wherein each memory unit comprises a left laminate and a right laminate, which are arranged at an interval in a horizontal direction, the left laminate and the right laminate each comprise a lower isolation layer, a PMOS layer, a first NMOS layer, an upper isolation layer and a second NMOS layer, which are sequentially arranged on the substrate in a stacked manner, the PMOS layer, the first NMOS layer and the second NMOS layer each comprise a first source/drain layer, a channel layer and a second source/drain layer, which are vertically arranged in a stacked manner, and the channel layer is transversely recessed relative to the first source/drain layer and the second source/drain layer; and grid stacks, which are between the first source/drain layer and the second source/drain layer in a vertical direction, and are arranged on two opposite sides of the channel layer, so as to be embedded into transverse recesses of the channel layer.

Classes IPC  ?

• H01L 27/11 - Structures de mémoires statiques à accès aléatoire
• H01L 21/8244 - Structures de mémoires statiques à accès aléatoire (SRAM)

Abrégé

The invention relates to the technical field of semiconductors. Disclosed are a vertical MOSFET device and a preparation method thereof. The vertical MOSFET device comprises: a substrate; an active region, comprising a first source/drain layer, a channel layer and a second source/drain layer that are sequentially and vertically stacked on the substrate, the periphery of the channel layer being recessed relative to the periphery of the first source/drain layer and the outer periphery of the second source/drain layer; a spacer layer, comprising an upper spacer layer and a lower spacer layer, the upper spacer layer being formed on the lower surface of the second source/drain layer exposed by the recess of the channel layer, the lower spacer layer being formed on the upper surface of the first source/drain layer exposed by the recess of the channel layer, and the upper spacer layer and the lower spacer layer both being in contact with, but not in communication with, a lateral surface of the channel layer; a gate stack, formed at least on the transverse outer periphery of the channel layer and embedded in the groove space between the upper spacer layer and the lower spacer layer.

Classes IPC  ?

• H01L 29/10 - Corps semi-conducteurs caractérisés par les formes, les dimensions relatives, ou les dispositions des régions semi-conductrices avec des régions semi-conductrices connectées à une électrode ne transportant pas le courant à redresser, amplifier ou commuter, cette électrode faisant partie d'un dispositif à semi-conducteur qui comporte trois électrodes ou plus
• H01L 29/423 - Electrodes caractérisées par leur forme, leurs dimensions relatives ou leur disposition relative ne transportant pas le courant à redresser, à amplifier ou à commuter
• H01L 29/78 - Transistors à effet de champ l'effet de champ étant produit par une porte isolée
• H01L 21/336 - Transistors à effet de champ à grille isolée

Abrégé

A metal oxide semiconductor field effect transistor (MOSFET), a method for manufacturing MOSFET, and an electronic apparatus including MOSFET are disclosed. The MOSFET include: a vertical channel portion on a substrate; source/drain portions respectively located at upper and lower ends of the channel portion with respect to the substrate; and a gate stack opposite to the channel portion. The channel portion has doping concentration distribution, so that when the MOSFET is an n-type MOSFET (nMOSFET), a threshold voltage of a first portion of the channel portion close to one of the source/drain portions is lower than a threshold voltage of a second portion adjacent to the first portion; or when the MOSFET is a p-type MOSFET (pMOSFET), a threshold voltage of a first portion in the channel portion close to one of the source/drain portions is higher than a threshold voltage of a second portion adjacent to the first portion.

Classes IPC  ?

• H01L 29/10 - Corps semi-conducteurs caractérisés par les formes, les dimensions relatives, ou les dispositions des régions semi-conductrices avec des régions semi-conductrices connectées à une électrode ne transportant pas le courant à redresser, amplifier ou commuter, cette électrode faisant partie d'un dispositif à semi-conducteur qui comporte trois électrodes ou plus
• H01L 29/04 - Corps semi-conducteurs caractérisés par leur structure cristalline, p.ex. polycristalline, cubique ou à orientation particulière des plans cristallins
• H01L 29/08 - Corps semi-conducteurs caractérisés par les formes, les dimensions relatives, ou les dispositions des régions semi-conductrices avec des régions semi-conductrices connectées à une électrode transportant le courant à redresser, amplifier ou commuter, cette électrode faisant partie d'un dispositif à semi-conducteur qui comporte trois électrodes ou plus
• H01L 29/66 - Types de dispositifs semi-conducteurs

Abrégé

An in-memory computing circuit having reconfigurable logic, including: an input stage and N output stages which are cascaded. The input stage includes 2N STT-MTJs. Each output stage includes STT-MTJs, of which a quantity is equal to a half of a quantity of STT-MTJs in a just previous stage. Two STT-MTJs in the previous stage and one STT-MTJ in the subsequent stage form a double-input single-output in-memory computing unit. Each double-input single-output in-memory computing unit can implement the four logical operations, i.e., NAND, NOR, AND, and OR, under different configurations. Data storage and logical operations can be realized under the same circuit architecture, and reconfigurations among different logic can be achieved.

Classes IPC  ?

• G11C 11/16 - Mémoires numériques caractérisées par l'utilisation d'éléments d'emmagasinage électriques ou magnétiques particuliers; Eléments d'emmagasinage correspondants utilisant des éléments magnétiques utilisant des éléments dans lesquels l'effet d'emmagasinage est basé sur l'effet de spin
• H03K 19/20 - Circuits logiques, c. à d. ayant au moins deux entrées agissant sur une sortie; Circuits d'inversion caractérisés par la fonction logique, p.ex. circuits ET, OU, NI, NON

Abrégé

The present invention relates to a semiconductor storage unit structure and a preparation method therefor and use thereof, and a semiconductor memory. The semiconductor storage unit structure comprises a substrate, a first transistor layer, an isolation layer and a second transistor layer, wherein the first transistor layer comprises a first stacked structure formed by a first source electrode, a first channel and a first drain electrode which are arranged in a stacked manner from bottom to top, and a first gate electrode located on a side wall of the first stacked structure; and the second transistor layer comprises: a second stacked structure formed by a second drain electrode, a second channel and a second source electrode which are arranged in a stacked manner from bottom to top, and a second gate electrode located on a side wall of the second stacked structure. At least part of the side wall of the second drain electrode is in direct contact with the first gate electrode. The present invention provides a 2T0C-type DRAM unit with an improved structure, has the advantages of vertical stacking integration, a high integration level, low electric leakage, a short refreshing time, etc., and has significant advantages compared with existing 2T0C-type DRAMs.

Classes IPC  ?

• H01L 27/108 - Structures de mémoires dynamiques à accès aléatoire
• H01L 27/06 - Dispositifs consistant en une pluralité de composants semi-conducteurs ou d'autres composants à l'état solide formés dans ou sur un substrat commun comprenant des éléments de circuit passif intégrés avec au moins une barrière de potentiel ou une barrière de surface le substrat étant un corps semi-conducteur comprenant une pluralité de composants individuels dans une configuration non répétitive

Abrégé

A storage device and a method for manufacturing same, and an electronic device comprising a storage device. The storage device comprises a substrate, a storage unit array on the substrate, and a plurality of word lines, which extend in a first direction, on the substrate. The storage unit array comprises a plurality of storage units, which are arranged in rows in the first direction and in columns in a second direction. Each storage unit comprises: an active region, which extends in a third direction, and comprises a vertical stack of a first source/drain layer, a channel layer and a second source/drain layer; and a gate stack, which is located between the first source/drain layer and the second source/drain layer in a vertical direction, and sandwiches the channel layer between at least two opposite sides of the channel layer. First source/drain layers in active regions of each column are continuous, so as to form a bit line, which extends continuously in a zigzag in the second direction. Each word line extends in the first direction, so as to intersect with active regions in a corresponding row, and is electrically connected to the gate stack on two opposite sides of the channel layer of each storage unit.

Classes IPC  ?

• H01L 27/108 - Structures de mémoires dynamiques à accès aléatoire

Abrégé

A two-dimensional material-based selector includes: a stack unit, wherein the stack unit has a metal-two-dimensional semiconductor-metal structure comprising a two-dimensional semiconductor layer, and metal layers arranged on an upper surface and a lower surface of the two-dimensional semiconductor layer, respectively. The number of the stack units is N, where N≥1. In each stack unit, a Schottky contact is formed on two metal-two-dimensional conductor interfaces, and the stack unit includes two Schottky diode structures connected in reverse series in response to the two-dimensional material-based selector being turned on. Alternatively, the number of the stack units is M, where M≥2. In each stack unit, a Schottky contact and an Ohmic contact are formed the two metal-two-dimensional conductor interfaces, respectively. The M stack units include M Schottky diode structures connected in reverse series in response to the two-dimensional material-based selector being turned on.

Classes IPC  ?

• H10B 61/00 - Dispositifs de mémoire magnétique, p.ex. dispositifs RAM magnéto-résistifs [MRAM]
• G11C 11/16 - Mémoires numériques caractérisées par l'utilisation d'éléments d'emmagasinage électriques ou magnétiques particuliers; Eléments d'emmagasinage correspondants utilisant des éléments magnétiques utilisant des éléments dans lesquels l'effet d'emmagasinage est basé sur l'effet de spin

Abrégé

Disclosed are a semiconductor device having a U-shaped structure, a method of manufacturing the semiconductor device, and an electronic including the semiconductor device. According to an embodiment, the semiconductor device may include: a first fin and a second fin disposed opposite to each other, wherein the first fin and the second fin extend in a vertical direction with respect to a substrate; a connection nanosheet connecting a bottom end of the first fin to a bottom end of a second fin to form a U-shaped structure, wherein the connection nanosheet is spaced apart from a top surface of the substrate.

Classes IPC  ?

• H01L 29/775 - Transistors à effet de champ avec un canal à gaz de porteurs de charge à une dimension, p.ex. FET à fil quantique
• H01L 27/088 - Dispositifs consistant en une pluralité de composants semi-conducteurs ou d'autres composants à l'état solide formés dans ou sur un substrat commun comprenant des éléments de circuit passif intégrés avec au moins une barrière de potentiel ou une barrière de surface le substrat étant un corps semi-conducteur comprenant uniquement des composants semi-conducteurs d'un seul type comprenant uniquement des composants à effet de champ les composants étant des transistors à effet de champ à porte isolée
• H01L 29/423 - Electrodes caractérisées par leur forme, leurs dimensions relatives ou leur disposition relative ne transportant pas le courant à redresser, à amplifier ou à commuter
• H01L 29/06 - Corps semi-conducteurs caractérisés par les formes, les dimensions relatives, ou les dispositions des régions semi-conductrices
• H01L 29/66 - Types de dispositifs semi-conducteurs

Abrégé

A memory device, a manufacturing method therefor, and an electronic device comprising the memory device. The memory device may comprise: a substrate; a plurality of word lines on the substrate extending in a first direction; a plurality of bit lines on the substrate extending in a second direction perpendicular to the first direction; and a memory cell array on the substrate comprising a plurality of memory cells electrically connected to corresponding word lines and bit lines, respectively. Each memory cell may comprise: an active region extending in a third direction inclined with respect to the first direction and comprising a vertical stack of a first source/drain layer, a channel layer, and a second source/drain layer; and gate stacks provided between the first source/drain layer and the second source/drain layer in a vertical direction and provided on the opposite sides of the channel layer in a fourth direction orthogonal to the third direction, so as to sandwich the channel layer. A corresponding word line of each memory cell extends across the memory cell in the first direction to be in contact with and electrically connected to the gate stacks on the opposite sides of the memory cell.

Classes IPC  ?

• H01L 27/108 - Structures de mémoires dynamiques à accès aléatoire

Abrégé

The present disclosure provides a memory cell, comprising: a stack layer, stacked on a substrate, and comprising: a plurality of channel holes running through the stack layer and part of the substrate, wherein at least one second laminated material layer in the stack layer after the plurality of channel holes are formed is etched to form an annular limiting structure; a gate dielectric layer, located on the surfaces of the plurality of channel holes which are etched to form the annular limiting structure; a channel layer, located on the surface of the gate dielectric layer; and a resistive layer, located on the surface of the channel layer corresponding to the annular limiting structure. A gate voltage applied to the at least one second laminated material layer and a bit line pulse signal connected to the channel layer are controlled, a resistance state of the resistive layer is changed, and a reading, writing or erasing operation of the memory cell on the resistive layer is implemented. The present disclosure further provides a preparation method for the memory cell, and a three-dimensional memory and an operation method therefor.

Classes IPC  ?

• H01L 27/24 - Dispositifs consistant en une pluralité de composants semi-conducteurs ou d'autres composants à l'état solide formés dans ou sur un substrat commun comprenant des composants à l'état solide pour le redressement, l'amplification ou la commutation, sans barrière de potentiel ni barrière de surface
• G11C 16/04 - Mémoires mortes programmables effaçables programmables électriquement utilisant des transistors à seuil variable, p.ex. FAMOS

Abrégé

Disclosed in the present invention is a correction method for a surface plasma photolithographic pattern, comprising: forming multiple test patterns on a test mask, each test pattern at least being represented by a first test parameter and a second test parameter related to the first test parameter; exposing a photoresist layer by using the test mask containing the test patterns to form multiple photoresist patterns, each photoresist pattern at least being represented by a first exposure parameter and a second exposure parameter related to the first exposure parameter; establishing a first data table on the basis of a correspondence between the first test parameters and second test parameters of the test patterns and the first exposure parameters and second exposure parameters of the photoresist patterns; processing the first data table according to the first exposure parameters to obtain a second data table; and correcting second test parameters of multiple design patterns on the basis of the second data table to obtain corrected design patterns, and using the corrected design patterns to manufacture a mask for exposure.

Classes IPC  ?

• H01L 21/027 - Fabrication de masques sur des corps semi-conducteurs pour traitement photolithographique ultérieur, non prévue dans le groupe ou
• G03F 7/20 - Exposition; Appareillages à cet effet

Abrégé

The present invention provides a storage cell, comprising: a channel layer array comprising N channel layers, the N channel layers being vertically provided on a substrate in a first direction, a tunneling layer and a storage layer being sequentially provided outside the N channel layers, and N being a positive integer; N heat conduction cores respectively located in the N channel layers and penetrating through the substrate; and a thermocouple array comprising a thermocouple word line layer growing on the substrate in a negative direction of the first direction and N thermocouple layers located on the thermocouple word line layer, the N thermocouple layers being connected to the N heat conduction cores in a one-to-one correspondence mode. A first potential difference is applied between the thermocouple word line layer and a part of the thermocouple layers in the N thermocouple layers, and the heat conduction core connected to the part of the thermocouple layers is heated, such that the channel layer and the storage layer corresponding to the heat conduction core are respectively kept at a first preset temperature and a second preset temperature under the heat insulation effect of the tunneling layer. The present invention further provides a three-dimensional memory and an operation method therefor.

Classes IPC  ?

• H01L 23/34 - Dispositions pour le refroidissement, le chauffage, la ventilation ou la compensation de la température
• H01L 27/11582 - Mémoires mortes programmables électriquement; Procédés de fabrication à étapes multiples de ces dispositifs avec isolateurs de grille à piégeage de charge, p.ex. MNOS ou NROM caractérisées par des agencements tridimensionnels, p.ex. avec des cellules à des niveaux différents de hauteur la région de source et la région de drain étant à différents niveaux, p.ex. avec des canaux inclinés les canaux comprenant des parties verticales, p.ex. canaux en forme de U
• H01L 27/1157 - Mémoires mortes programmables électriquement; Procédés de fabrication à étapes multiples de ces dispositifs avec isolateurs de grille à piégeage de charge, p.ex. MNOS ou NROM caractérisées par la région noyau de mémoire avec transistors de sélection de cellules, p.ex. NON-ET
• H01L 27/11556 - Mémoires mortes programmables électriquement; Procédés de fabrication à étapes multiples de ces dispositifs avec grilles flottantes caractérisées par des agencements tridimensionnels, p.ex. avec des cellules à des niveaux différents de hauteur la région de source et la région de drain étant à différents niveaux, p.ex. avec des canaux inclinés les canaux comprenant des parties verticales, p.ex. des canaux en forme de U
• H01L 27/11524 - Mémoires mortes programmables électriquement; Procédés de fabrication à étapes multiples de ces dispositifs avec grilles flottantes caractérisées par la région noyau de mémoire avec transistors de sélection de cellules, p.ex. NON-ET
• G11C 16/04 - Mémoires mortes programmables effaçables programmables électriquement utilisant des transistors à seuil variable, p.ex. FAMOS
• G11C 16/26 - Circuits de détection ou de lecture; Circuits de sortie de données

Abrégé

Provided in the embodiments of the present application are a ferroelectric tunnel junction device and a manufacturing method therefor. The ferroelectric tunnel junction device comprises a first electrode, a dielectric layer, a ferroelectric layer and a second electrode, which are sequentially stacked, wherein the thickness of the ferroelectric layer is less than five nanometers. The thickness of the ferroelectric layer is relatively thin, such that a relatively large tunneling current can be provided for the device, and the relatively thin ferroelectric layer can also increase depolarization field strength in the ferroelectric tunnel junction device, accelerate depolarization and reduce a data holding capability, so as to obtain a volatile data storage device. The volatile ferroelectric tunnel junction device can be applied to a reservoir computing network system. A plurality of polarization currents that are collected by the ferroelectric tunnel junction device during a running process are used as virtual nodes of a reservoir computing network system, and data can be input into the plurality of virtual nodes in parallel, that is, the data can be processed in parallel by the reservoir computing network system based on the ferroelectric tunnel junction device, such that the calculation of a neural network model is efficiently performed, and the requirement of the neural network model for efficient training is met.

Classes IPC  ?

• H01L 45/00 - Dispositifs à l'état solide spécialement adaptés pour le redressement, l'amplification, la production d'oscillations ou la commutation, sans barrière de potentiel ni barrière de surface, p.ex. triodes diélectriques; Dispositifs à effet Ovshinsky; Procédés ou appareils spécialement adaptés à la fabrication ou au traitement de ces dispositifs ou de leurs parties constitutives

Abrégé

Provided are a semiconductor device, a method of manufacturing the semiconductor device, and an electronic apparatus including the semiconductor device. According to the embodiments, the semiconductor device may include: a nanosheet stack layer on a substrate including a plurality of nanosheets spaced apart from each other in a vertical direction relative to the substrate, wherein at least one of the plurality of nanosheets includes a first portion in a first orientation, and at least one of an upper surface and a lower surface of the first portion is not parallel to a horizontal surface of the substrate.

Classes IPC  ?

• H01L 29/06 - Corps semi-conducteurs caractérisés par les formes, les dimensions relatives, ou les dispositions des régions semi-conductrices
• H01L 29/08 - Corps semi-conducteurs caractérisés par les formes, les dimensions relatives, ou les dispositions des régions semi-conductrices avec des régions semi-conductrices connectées à une électrode transportant le courant à redresser, amplifier ou commuter, cette électrode faisant partie d'un dispositif à semi-conducteur qui comporte trois électrodes ou plus
• H01L 29/66 - Types de dispositifs semi-conducteurs
• H01L 29/786 - Transistors à couche mince
• H01L 29/775 - Transistors à effet de champ avec un canal à gaz de porteurs de charge à une dimension, p.ex. FET à fil quantique
• H01L 27/092 - Transistors à effet de champ métal-isolant-semi-conducteur complémentaires
• H01L 21/8238 - Transistors à effet de champ complémentaires, p.ex. CMOS

Abrégé

Provided is a photoetching quality optimization method, comprising: determining, on the basis of a characteristic matrix method and the Bloch's theorem, a stray item of a wave function introduced from the roughness of the surface of a metal film layer (S101); inputting the stray item of the wave function into a photoetching quality deviation mathematical model for calculation simulation, thereby obtaining an effect analysis curve of the roughness of the metal film layer on the photoetching quality, the effect analysis curve representing an effect result of the roughness of the metal film layer on the photoetching quality (S102); and according to the effect result, reducing the roughness of the surface of the metal film layer and/or providing a metal-dielectric multilayer film structure between a mask above a metal-dielectric unit and air so as to optimize the photoetching quality of the metal-dielectric unit (S103). Provided are a photoetching quality optimization apparatus (1400), an electronic device (1500), a computer-readable storage medium, and a computer program product.

Classes IPC  ?

• G06F 30/23 - Optimisation, vérification ou simulation de l’objet conçu utilisant les méthodes des éléments finis [MEF] ou les méthodes à différences finies [MDF]
• G06F 17/16 - Calcul de matrice ou de vecteur
• G03F 7/20 - Exposition; Appareillages à cet effet

Abrégé

A mask parameter optimization method, comprising: acquiring a test pattern, a light source parameter, and an initial mask parameter, wherein the initial mask parameter comprises a mask thickness and an initial mask side wall angle; generating a plurality of candidate mask parameters according to the initial mask side wall angle in the initial mask parameter, the plurality of candidate mask parameters comprising different mask side wall angles and the same mask thickness; obtaining an imaging contrast ratio of each candidate mask parameter on the basis of the test pattern and the light source parameter; and selecting an optimal mask side wall angle from the plurality of candidate mask parameters according to the imaging contrast ratio. By optimizing the mask parameter of a multilayer film lens structure, the imaging contrast ratio is significantly improved, and the imaging resolution is improved.

Classes IPC  ?

• G03F 1/00 - Originaux pour la production par voie photomécanique de surfaces texturées, p.ex. masques, photomasques ou réticules; Masques vierges ou pellicules à cet effet; Réceptacles spécialement adaptés à ces originaux; Leur préparation
• G03F 1/70 - Adaptation du tracé ou de la conception de base du masque aux exigences du procédé lithographique, p.ex. correction par deuxième itération d'un motif de masque pour l'imagerie
• G03F 7/20 - Exposition; Appareillages à cet effet

Abrégé

An analytic method and device for quantitatively calculating line edge roughness in a plasma ultra-diffraction photoetching process, related to the field of semiconductor manufacturing. The method comprises: determining a theoretical point spread function of a light source on the basis of field intensity distribution data of the light source at an opening of a focusing element in plasma ultra-diffraction photoetching (101); determining a plurality of transverse point width values of a point mapping graph on the basis of the point mapping graph (102); respectively determining an actual point spread function corresponding to the plurality of transverse point width values on the basis of the theoretical point spread function and the plurality of transverse point width values (103); determining an actual line spread function of a line graph on the basis of an attenuation constant and the actual point spread function (104); and determining a line edge roughness theoretical analysis formula of the plasma ultra-diffraction photoetching on the basis of a line edge roughness change value, the exposure dose of the line graph, the near-field photoresist contrast, and the graph logarithmic slope relationship of the line graph (109). The analysis method greatly improves the actual applicability of the surface plasma ultra-diffraction photoetching technology.

Classes IPC  ?

• G03F 7/20 - Exposition; Appareillages à cet effet

Abrégé

Embodiments of the present application provide a fabrication method for a semiconductor device. A photolithographic coating is formed on a structure to be led out. The photolithographic coating comprises a first film layer, a photolithographic film layer and a second film layer. The refractive indexes of the first film layer and the second film layer are both smaller than 1, so that the photolithographic coating forms an optical structure having a relatively high reflection coefficient. The photolithographic coating is exposed by using light of a target wavelength and a mask. The structure is reflected by the photolithographic coating. The structure is used as a mask for imaging to the photolithographic film layer; meanwhile, the pattern of the mask is also imaged to the photolithographic film layer. That is, the patterns of the structure and the mask are both imaged to a target region of the photolithographic film layer, and the target region corresponds to the structure, which achieves the self-alignment of a pattern layer of the structure and a pattern layer in which a contact hole is located. The target region only corresponds to the structure in an overlapping region in which the patterns of the structure and the mask are simultaneously imaged on the photolithographic film layer during one exposure process, which may improve the alignment accuracy between different pattern layers and reduce alignment errors.

Classes IPC  ?

• H01L 21/027 - Fabrication de masques sur des corps semi-conducteurs pour traitement photolithographique ultérieur, non prévue dans le groupe ou

Abrégé

Embodiments of the present application provide a manufacturing method for a semiconductor device. A photoetching coating is formed on a structure to be led out, the photoetching coating comprises a first film layer, a photoetching film layer and a second film layer, and the refractive indexes of the first film layer and the second film layer are both smaller than 1, so that the photoetching coating forms an optical structure having a relatively high reflection coefficient; the photoetching coating is exposed by utilizing light having a first wavelength, and the structure to be led out is reflected by the photoetching coating; the structure to be led out is used as a mask for imaging to a first area of the photoetching film layer, the photoetching coating is exposed by using light having a second wavelength and the mask, and the pattern of the mask is imaged to a second area of the photoetching film layer, wherein an overlapping area of the first area and the second area is a leading-out area, and the leading-out area corresponds to the structure to be led out. Self-alignment of the layer of the structure to be led out and the layer where a contact hole is located is achieved, and only the overlapping area of imaging on the photoetching film layer in two exposures can correspond to the structure to be led out, so that the alignment precision between different layers can be improved, and alignment errors are reduced.

Classes IPC  ?

• H01L 21/027 - Fabrication de masques sur des corps semi-conducteurs pour traitement photolithographique ultérieur, non prévue dans le groupe ou
• H01L 21/311 - Gravure des couches isolantes
• H01L 21/768 - Fixation d'interconnexions servant à conduire le courant entre des composants distincts à l'intérieur du dispositif

Abrégé

The present application discloses a spin Hall device, a method for obtaining a Hall voltage, and a max pooling method. The spin Hall device includes a cobalt ferroboron layer. A top view and a bottom view of the spin Hall device are completely the same as a cross-shaped graph that has two axes of symmetry perpendicular to each other and equally divided by each other. The spin Hall device of the present application has non-volatility and analog polymorphic characteristics, can be used for obtaining a Hall voltage and applied to various circuits, is simple in structure and small in size, can save on-chip resources, and can meet computation requirements.

Classes IPC  ?

• G01R 15/20 - Adaptations fournissant une isolation en tension ou en courant, p.ex. adaptations pour les réseaux à haute tension ou à courant fort utilisant des dispositifs galvano-magnétiques, p.ex. des dispositifs à effet Hall
• G01R 19/25 - Dispositions pour procéder aux mesures de courant ou de tension ou pour en indiquer l'existence ou le signe utilisant une méthode de mesure numérique
• G06N 3/063 - Réalisation physique, c. à d. mise en œuvre matérielle de réseaux neuronaux, de neurones ou de parties de neurone utilisant des moyens électroniques

Abrégé

An optical method and apparatus for quickly realizing precise calibration of a lithography system, which relate to the field of optics. The optical method for quickly realizing precise calibration of a lithography system comprises: determining a spot width fitting relationship between spot light sources on the basis of field intensity distribution data of the spot light sources at an opening of a focusing element (101); on the basis of the spot width fitting relationship between the spot light sources, determining first correlations between spot widths of the spot light sources and exposure parameters of a photoresist under an optical microscope (102); determining first spot width data sets of the spot light sources on the basis of an optical microscopic image of a spot mapping pattern on a surface of the photoresist (103); on the basis of the first spot width data sets of the spot light sources, determining second correlations between the spot widths of the spot light sources and the exposure parameters of the photoresist (104); and when the first correlations and the second correlations meet a preset condition, determining the exposure parameters of the photoresist by using the first correlations (105). By means of the optical method, exposure parameters can be quickly acquired, and can be measured in a timely manner.

Classes IPC  ?

• G03F 7/20 - Exposition; Appareillages à cet effet

Abrégé

The method includes: reading a memory cell having a encoded information bit, so as to obtain an LLR value of a current memory cell with reference to a pre-established LLR table according to a storage time, a threshold voltage partition and a comprehensive distribution corresponding to the current memory cell during reading; and performing a soft decoding operation on a codeword in the memory cell having the encoded information bit according to the read LLR value of the current memory cell, wherein the comprehensive distribution of the current memory cell is determined according to an influence of a memory cell adjacent to the current memory cell on a distribution of the current memory cell; an input of the pre-established LLR table comprises a storage time, a threshold voltage partition and a comprehensive distribution, and an output of the pre-established LLR table comprises an LLR value.

Classes IPC  ?

• H03M 13/11 - Détection d'erreurs ou correction d'erreurs transmises par redondance dans la représentation des données, c.à d. mots de code contenant plus de chiffres que les mots source utilisant un codage par blocs, c.à d. un nombre prédéterminé de bits de contrôle ajouté à un nombre prédéterminé de bits d'information utilisant plusieurs bits de parité
• H03M 13/15 - Codes cycliques, c. à d. décalages cycliques de mots de code produisant d'autres mots de code, p.ex. codes définis par un générateur polynomial, codes de Bose-Chaudhuri-Hocquenghen [BCH]
• H03M 13/39 - Estimation de séquence, c.à d. utilisant des méthodes statistiques pour la reconstitution des codes originaux

Abrégé

A spintronic device, a storage unit, a storage array, and a read-write circuit, applied to the technical field of integration. The spintronic device comprises: bottom electrodes (101, 104); a spin-orbit coupling layer (102) provided on the bottom electrodes (101, 104); at least one pair of magnetic tunnel junctions (103) provided on the spin-orbit coupling layer (102), each of the magnetic tunnel junctions (103) comprising a free layer (1031), a tunneling layer (1032), and a reference layer (1033) that are successively arranged from bottom to top, and the reference layers (1033) of two magnetic tunnel junctions in each pair of magnetic tunnel junctions (103) being opposite in magnetization direction; and a top electrode (1034) provided on the reference layer (1033) of each of the magnetic tunnel junctions (103).

Classes IPC  ?

• G11C 11/16 - Mémoires numériques caractérisées par l'utilisation d'éléments d'emmagasinage électriques ou magnétiques particuliers; Eléments d'emmagasinage correspondants utilisant des éléments magnétiques utilisant des éléments dans lesquels l'effet d'emmagasinage est basé sur l'effet de spin
• H01L 43/08 - Résistances commandées par un champ magnétique

Abrégé

A method of manufacturing a semiconductor memory device is provided. The method include: providing a stack of a sacrificial layer, a first source/drain layer, a channel layer, and a second source/drain layer on a substrate; defining a plurality of pillar-shaped active regions arranged in rows and columns in the first source/drain layer, the channel layer, and the second source/drain layer; removing the sacrificial layer and forming a plurality of bit lines extending below the respective columns of active regions in a space left by the removal of the sacrificial layer; forming gate stacks around peripheries of the channel layer in the respective active regions; and forming a plurality of word lines between the respective rows of active regions, wherein each of the word lines is electrically connected to the gate stacks of the respective memory cells in a corresponding one of the rows.

Classes IPC  ?

• H01L 29/423 - Electrodes caractérisées par leur forme, leurs dimensions relatives ou leur disposition relative ne transportant pas le courant à redresser, à amplifier ou à commuter
• H01L 29/78 - Transistors à effet de champ l'effet de champ étant produit par une porte isolée
• H01L 29/739 - Dispositifs du type transistor, c.à d. susceptibles de répondre en continu aux signaux de commande appliqués commandés par effet de champ
• H01L 29/66 - Types de dispositifs semi-conducteurs
• H01L 29/786 - Transistors à couche mince

Abrégé

A correction method for an electron beam proximity effect, comprising first setting an electron beam initial dose for each exposure grid region to calculate a proximity effect energy value that affects the energy distribution of the current exposure grid region when all exposure grid regions other than the current exposure grid region are exposed; calculating an electron beam correction dose of the current exposure grid region; and successively calculating the electron beam correction dose of each exposure grid region in the electron beam exposure layout matrix. Afterward, an iterative calculation is performed T times, and the final electron beam correction dose of each exposure grid region can be obtained. The central exposure energy value of the current exposure grid region and the proximity effect energy value of the current exposure grid region when exposing surrounding exposure grid regions are differentiated, which is convenient for directly solving the incident dose of the current exposure grid region and the amount of calculation is reduced. Furthermore, within a small number of instances of optimization iterative calculations, the incident dose of an electron beam having ideal precision can be obtained. Also disclosed is a correction device for an electron beam proximity effect.

Classes IPC  ?

• H01L 21/027 - Fabrication de masques sur des corps semi-conducteurs pour traitement photolithographique ultérieur, non prévue dans le groupe ou
• G03F 7/20 - Exposition; Appareillages à cet effet

Abrégé

A semiconductor apparatus including a capacitor and a method of manufacturing the same, and an electronic device including the semiconductor apparatus are provided. According to embodiments, the semiconductor apparatus may include: a vertical semiconductor device including an active region extending vertically on a substrate; and a capacitor including a first capacitor electrode, a capacitor dielectric layer and a second capacitor electrode sequentially stacked. The first capacitor electrode extends vertically on the substrate and includes a conductive material, and the conductive material includes at least one semiconductor element contained in the active region of the vertical semiconductor device.

Classes IPC  ?

• H01L 27/06 - Dispositifs consistant en une pluralité de composants semi-conducteurs ou d'autres composants à l'état solide formés dans ou sur un substrat commun comprenant des éléments de circuit passif intégrés avec au moins une barrière de potentiel ou une barrière de surface le substrat étant un corps semi-conducteur comprenant une pluralité de composants individuels dans une configuration non répétitive
• H01L 29/94 - Dispositifs à métal-isolant-semi-conducteur, p.ex. MOS
• H01L 29/78 - Transistors à effet de champ l'effet de champ étant produit par une porte isolée
• H01L 29/66 - Types de dispositifs semi-conducteurs

Abrégé

The present disclosure provides a semiconductor device and a manufacturing method thereof, and an electronic device including the semiconductor device. The method includes: forming a first material layer and a second material layer sequentially on a substrate; defining an active region of the semiconductor device on the substrate, the first material layer and the second material layer, wherein the active region includes a channel region; forming spacers around an outer periphery of the channel region, respectively at set positions of the substrate and the second material layer; forming a first source/drain region and a second source/drain region on the substrate and the second material layer respectively; and forming a gate stack around the outer periphery of the channel region; wherein the spacers each have a thickness varying in a direction perpendicular to a direction from the first source/drain region pointing to the second source/drain region.

Classes IPC  ?

• H01L 29/66 - Types de dispositifs semi-conducteurs
• H01L 21/02 - Fabrication ou traitement des dispositifs à semi-conducteurs ou de leurs parties constitutives
• H01L 21/225 - Diffusion des impuretés, p.ex. des matériaux de dopage, des matériaux pour électrodes, à l'intérieur ou hors du corps semi-conducteur, ou entre les régions semi-conductrices; Redistribution des impuretés, p.ex. sans introduction ou sans élimination de matériau dopant supplémentaire en utilisant la diffusion dans ou hors d'un solide, à partir d'une ou en phase solide, p.ex. une couche d'oxyde dopée
• H01L 21/28 - Fabrication des électrodes sur les corps semi-conducteurs par emploi de procédés ou d'appareils non couverts par les groupes
• H01L 29/08 - Corps semi-conducteurs caractérisés par les formes, les dimensions relatives, ou les dispositions des régions semi-conductrices avec des régions semi-conductrices connectées à une électrode transportant le courant à redresser, amplifier ou commuter, cette électrode faisant partie d'un dispositif à semi-conducteur qui comporte trois électrodes ou plus
• H01L 29/49 - Electrodes du type métal-isolant-semi-conducteur
• H01L 29/78 - Transistors à effet de champ l'effet de champ étant produit par une porte isolée

Abrégé

A semiconductor device and a manufacturing method thereof, and an electronic device including the semiconductor device. The semiconductor device includes: a substrate; an active region including a first source/drain region, a channel region and a second source/drain region stacked sequentially on the substrate and adjacent to each other; a gate stack formed around an outer periphery of the channel region; and spacers formed around the outer periphery of the channel region, respectively between the gate stack and the first source/drain region and between the gate stack and the second source/drain region; wherein the spacers each have a thickness varying in a direction perpendicular to a direction from the first source/drain region pointing to the second source/drain region; wherein the spacers each have the thickness gradually decreasing from a surface exposed on an outer peripheral surface of the active region to an inside of the active region.

Classes IPC  ?

• H01L 29/66 - Types de dispositifs semi-conducteurs
• H01L 21/02 - Fabrication ou traitement des dispositifs à semi-conducteurs ou de leurs parties constitutives
• H01L 21/225 - Diffusion des impuretés, p.ex. des matériaux de dopage, des matériaux pour électrodes, à l'intérieur ou hors du corps semi-conducteur, ou entre les régions semi-conductrices; Redistribution des impuretés, p.ex. sans introduction ou sans élimination de matériau dopant supplémentaire en utilisant la diffusion dans ou hors d'un solide, à partir d'une ou en phase solide, p.ex. une couche d'oxyde dopée
• H01L 21/28 - Fabrication des électrodes sur les corps semi-conducteurs par emploi de procédés ou d'appareils non couverts par les groupes
• H01L 29/08 - Corps semi-conducteurs caractérisés par les formes, les dimensions relatives, ou les dispositions des régions semi-conductrices avec des régions semi-conductrices connectées à une électrode transportant le courant à redresser, amplifier ou commuter, cette électrode faisant partie d'un dispositif à semi-conducteur qui comporte trois électrodes ou plus
• H01L 29/49 - Electrodes du type métal-isolant-semi-conducteur
• H01L 29/78 - Transistors à effet de champ l'effet de champ étant produit par une porte isolée

Abrégé

A semiconductor device with a C-shaped channel portion, a method of manufacturing the semiconductor device, and an electronic apparatus including the semiconductor device are provided. The semiconductor device may include: a channel portion on a substrate, wherein the channel portion includes a curved nanosheet/nanowire with a C-shaped cross section; source/drain portions respectively located at upper and lower ends of the channel portion with respect to the substrate; and a gate stack surrounding a periphery of the channel portion.

Classes IPC  ?

• H01L 29/06 - Corps semi-conducteurs caractérisés par les formes, les dimensions relatives, ou les dispositions des régions semi-conductrices
• H01L 29/786 - Transistors à couche mince
• H01L 29/423 - Electrodes caractérisées par leur forme, leurs dimensions relatives ou leur disposition relative ne transportant pas le courant à redresser, à amplifier ou à commuter
• H01L 29/08 - Corps semi-conducteurs caractérisés par les formes, les dimensions relatives, ou les dispositions des régions semi-conductrices avec des régions semi-conductrices connectées à une électrode transportant le courant à redresser, amplifier ou commuter, cette électrode faisant partie d'un dispositif à semi-conducteur qui comporte trois électrodes ou plus
• H01L 29/775 - Transistors à effet de champ avec un canal à gaz de porteurs de charge à une dimension, p.ex. FET à fil quantique
• H01L 29/66 - Types de dispositifs semi-conducteurs
• H01L 21/8234 - Technologie MIS

Abrégé

Disclosed are a semiconductor device having a double-gate structure and a manufacturing method therefor, and an electronic apparatus comprising the semiconductor device. According to an embodiment, a semiconductor device comprises a vertical channel portion on a substrate; source/drain portions at the upper and lower ends of the channel portion with respect to the substrate, respectively; and a first gate stack on a first side of the channel portion in a first direction transverse to the substrate and a second gate stack on a second side of the channel portion opposite to the first side in the first direction. The distance between at least one of the upper edge and the lower edge of the end of the first gate stack close to the channel portion in the vertical direction and the corresponding source/drain portion is less than the distance between at least one edge, corresponding to the aforementioned at least one edge, among the upper edge and the lower edge of the end of the second gate stack close to the channel portion in the vertical direction and the corresponding source/drain.

Classes IPC  ?

• H01L 29/786 - Transistors à couche mince
• H01L 27/088 - Dispositifs consistant en une pluralité de composants semi-conducteurs ou d'autres composants à l'état solide formés dans ou sur un substrat commun comprenant des éléments de circuit passif intégrés avec au moins une barrière de potentiel ou une barrière de surface le substrat étant un corps semi-conducteur comprenant uniquement des composants semi-conducteurs d'un seul type comprenant uniquement des composants à effet de champ les composants étant des transistors à effet de champ à porte isolée
• H01L 21/336 - Transistors à effet de champ à grille isolée

Abrégé

A NOR type memory and an electronic device comprising the NOR type memory are disclosed. According to an embodiment, the NOR type memory may comprise a NOR cell array and a peripheral circuit. The NOR cell array may comprise: a first substrate; an array of memory cells on the first substrate, each memory cell comprising a first gate stack extending vertically relative to the first substrate, and an active region surrounding an outer periphery of the first gate stack; a first bond pad electrically connected to the first gate stack; and a second bond pad electrically connected to the active region of the memory cell. The peripheral circuit may comprise: a second substrate; a peripheral circuit element on the second substrate; and a third bond pad, at least a portion of the third bond pad being electrically connected to the peripheral circuit element. The NOR cell array and the peripheral circuit are arranged such that at least some of the first bond pads and the second bond pads are opposite at least some of the third bond pads.

Classes IPC  ?

• H01L 27/11575 - Mémoires mortes programmables électriquement; Procédés de fabrication à étapes multiples de ces dispositifs avec isolateurs de grille à piégeage de charge, p.ex. MNOS ou NROM caractérisées par la région limite entre la région noyau et la région de circuit périphérique
• H01L 27/11582 - Mémoires mortes programmables électriquement; Procédés de fabrication à étapes multiples de ces dispositifs avec isolateurs de grille à piégeage de charge, p.ex. MNOS ou NROM caractérisées par des agencements tridimensionnels, p.ex. avec des cellules à des niveaux différents de hauteur la région de source et la région de drain étant à différents niveaux, p.ex. avec des canaux inclinés les canaux comprenant des parties verticales, p.ex. canaux en forme de U
• H01L 27/11573 - Mémoires mortes programmables électriquement; Procédés de fabrication à étapes multiples de ces dispositifs avec isolateurs de grille à piégeage de charge, p.ex. MNOS ou NROM caractérisées par la région de circuit périphérique

Abrégé

Disclosed are a NOR type memory device and a manufacturing method therefor, and an electronic device comprising the NOR type memory device. According to an embodiment, the NOR type memory device may comprise: a memory device layer, which comprises a first source/drain region, a second source/drain region, and a first channel region between the first source/drain region and the second source/drain region; a first gate stack, which extends vertically to pass through the memory device layer, and comprises a first gate conductor layer and a storage functional layer disposed between the first gate conductor layer and the memory device layer, and defines a memory cell at an intersection between the first gate stack and the memory device layer; a selection device layer on the memory device layer, the selection device layer comprising a third source/drain region, a fourth source/drain region, and a second channel region between the third source/drain region and the fourth source/drain region; a second gate stack, which is disposed over the first gate stack and extends vertically to pass through the selection device layer; and a connecting portion, which electrically connects the third source/drain region to the first gate conductor layer.

Classes IPC  ?

• H01L 27/11575 - Mémoires mortes programmables électriquement; Procédés de fabrication à étapes multiples de ces dispositifs avec isolateurs de grille à piégeage de charge, p.ex. MNOS ou NROM caractérisées par la région limite entre la région noyau et la région de circuit périphérique
• H01L 27/11582 - Mémoires mortes programmables électriquement; Procédés de fabrication à étapes multiples de ces dispositifs avec isolateurs de grille à piégeage de charge, p.ex. MNOS ou NROM caractérisées par des agencements tridimensionnels, p.ex. avec des cellules à des niveaux différents de hauteur la région de source et la région de drain étant à différents niveaux, p.ex. avec des canaux inclinés les canaux comprenant des parties verticales, p.ex. canaux en forme de U
• H01L 27/11573 - Mémoires mortes programmables électriquement; Procédés de fabrication à étapes multiples de ces dispositifs avec isolateurs de grille à piégeage de charge, p.ex. MNOS ou NROM caractérisées par la région de circuit périphérique

Abrégé

Disclosed are a NOR type memory device and a manufacturing method therefor, and an electronic device comprising the NOR type memory device. According to an embodiment, the NOR type memory device may comprise a first gate stack, which extends vertically on a substrate, and comprises a gate conductor layer and a storage functional layer; and a first semiconductor layer, which extends around an outer periphery of the first gate stack and along a sidewall of the first gate stack. The storage functional layer is disposed between the first semiconductor layer and the gate conductor layer. The first semiconductor layer comprises a first source/drain region, a first channel region and a second source/drain region which are sequentially disposed in a vertical direction. A memory cell is defined at an intersection between the first gate stack and the first semiconductor layer. The NOR type memory device further comprises a conductive shielding layer surrounding an outer periphery of the first channel region of the first semiconductor layer, and a dielectric layer between the first channel region of the first semiconductor layer and the conductive shielding layer.

Classes IPC  ?

• H01L 27/11565 - Mémoires mortes programmables électriquement; Procédés de fabrication à étapes multiples de ces dispositifs avec isolateurs de grille à piégeage de charge, p.ex. MNOS ou NROM caractérisées par la configuration vue du dessus

Abrégé

A metallic stack and a preparing method therefor, and an electronic device including the metallic stack. The metallic stack includes at least one interconnection wire layer and at least one via layer alternately arranged on a substrate. At least one pair of interconnection wire layer and via layer in the metallic stack includes interconnection wires in the interconnection wire layer and conductive vias in the via layer, wherein the interconnection wire layer is closer to the substrate than the via layer. At least a part of the interconnection wires is integrated with the conductive vias on the at least a part of the interconnection wires.

Classes IPC  ?

• H01L 23/528 - Configuration de la structure d'interconnexion
• H01L 21/8234 - Technologie MIS
• H01L 23/522 - Dispositions pour conduire le courant électrique à l'intérieur du dispositif pendant son fonctionnement, d'un composant à un autre comprenant des interconnexions externes formées d'une structure multicouche de couches conductrices et isolantes inséparables du corps semi-conducteur sur lequel elles ont été déposées
• H01L 23/532 - Dispositions pour conduire le courant électrique à l'intérieur du dispositif pendant son fonctionnement, d'un composant à un autre comprenant des interconnexions externes formées d'une structure multicouche de couches conductrices et isolantes inséparables du corps semi-conducteur sur lequel elles ont été déposées caractérisées par les matériaux
• H01L 21/768 - Fixation d'interconnexions servant à conduire le courant entre des composants distincts à l'intérieur du dispositif

Abrégé

The method for manufacturing a three-dimensional static random-access memory, including: manufacturing a first semiconductor structure including multiple MOS transistors and a first insulating layer thereon; bonding a first material layer to the first insulating layer to form a first substrate layer; manufacturing multiple first low-temperature MOS transistors at a low temperature on the first substrate layer, and forming a second insulating layer thereon to form a second semiconductor structure; bonding a second material layer to the second insulating layer to form a second substrate layer; manufacturing multiple second low-temperature MOS transistors at a low temperature on the second substrate layer, and forming a third insulating layer thereon to form a third semiconductor structure; and forming an interconnection layer which interconnets the first semiconductor structure, the second semiconductor structure and the third semiconductor structure.

Classes IPC  ?

• H01L 27/11 - Structures de mémoires statiques à accès aléatoire

Abrégé

A metallization stack and a method of manufacturing the same, and an electronic device including the metallization stack are provided. The metallization stack may include at least one interconnection line layer and at least one via hole layer arranged alternately on a substrate. At least one pair of adjacent interconnection line layer and via hole layer in the metallization stack includes: an interconnection line in the interconnection line layer, and a via hole in the via hole layer. The interconnection line layer is closer to the substrate than the via hole layer. A peripheral sidewall of a via hole on at least part of the interconnection line does not exceed a peripheral sidewall of the at least part of the interconnection line.

Classes IPC  ?

• H01L 23/528 - Configuration de la structure d'interconnexion
• H01L 23/522 - Dispositions pour conduire le courant électrique à l'intérieur du dispositif pendant son fonctionnement, d'un composant à un autre comprenant des interconnexions externes formées d'une structure multicouche de couches conductrices et isolantes inséparables du corps semi-conducteur sur lequel elles ont été déposées
• H01L 21/768 - Fixation d'interconnexions servant à conduire le courant entre des composants distincts à l'intérieur du dispositif

Abrégé

The present disclosure provides a semiconductor device, a method for manufacturing the semiconductor device, and electronic equipment including the semiconductor device. According to embodiments, a semiconductor device may include a channel portion, source/drain portions in contact with the channel portion on opposite sides of the channel portion, and a gate stack intersecting the channel portion. The channel portion includes a first part extending in a vertical direction relative to the substrate and a second part extending from the first part in a lateral direction relative to the substrate.

Classes IPC  ?

• H01L 29/423 - Electrodes caractérisées par leur forme, leurs dimensions relatives ou leur disposition relative ne transportant pas le courant à redresser, à amplifier ou à commuter
• H01L 29/786 - Transistors à couche mince
• H01L 29/06 - Corps semi-conducteurs caractérisés par les formes, les dimensions relatives, ou les dispositions des régions semi-conductrices
• H01L 29/417 - Electrodes caractérisées par leur forme, leurs dimensions relatives ou leur disposition relative transportant le courant à redresser, à amplifier ou à commuter
• H01L 21/265 - Bombardement par des radiations ondulatoires ou corpusculaires par des radiations d'énergie élevée produisant une implantation d'ions
• H01L 29/66 - Types de dispositifs semi-conducteurs

Abrégé

Disclosed are a semiconductor apparatus, a manufacturing method therefor, and an electronic equipment comprising the semiconductor apparatus. According to the embodiments, the semiconductor apparatus includes a first device and a second device on a substrate that are opposite each other. The first device and the second device each include a channel portion, source/drain portions on both sides of the channel portion that are connected to the channel portion, and a gate stack overlapping the channel portion. The channel portion includes a first portion extending in a vertical direction relative to the substrate and a second portion extending from the first portion in a transverse direction relative to the substrate. The second portion of the channel portion of the first device and the second portion of the channel portion of the second device extend toward or away from each other.

Classes IPC  ?

• H01L 29/06 - Corps semi-conducteurs caractérisés par les formes, les dimensions relatives, ou les dispositions des régions semi-conductrices
• H01L 29/66 - Types de dispositifs semi-conducteurs
• H01L 29/775 - Transistors à effet de champ avec un canal à gaz de porteurs de charge à une dimension, p.ex. FET à fil quantique
• H01L 29/786 - Transistors à couche mince
• H01L 29/78 - Transistors à effet de champ l'effet de champ étant produit par une porte isolée
• H01L 29/08 - Corps semi-conducteurs caractérisés par les formes, les dimensions relatives, ou les dispositions des régions semi-conductrices avec des régions semi-conductrices connectées à une électrode transportant le courant à redresser, amplifier ou commuter, cette électrode faisant partie d'un dispositif à semi-conducteur qui comporte trois électrodes ou plus
• H01L 21/8238 - Transistors à effet de champ complémentaires, p.ex. CMOS

Abrégé

th period.

Classes IPC  ?

• H03M 3/00 - Conversion de valeurs analogiques en, ou à partir d'une modulation différentielle

Abrégé

A semiconductor device and a method of manufacturing the same, and an electronic apparatus including the semiconductor device are provided. The semiconductor device includes: an active region, on a substrate, extending substantially in a vertical direction; a gate stack formed around at least a part of a periphery of the active region, the active region including a channel region opposite to the gate stack, and a first source/drain region and a second source/drain region, and the gate stack including a gate dielectric layer, a work function tuning layer and a gate electrode material layer, and the work function tuning layer being between the gate electrode material layer and the channel region; and a first low-k dielectric layer extending from a first end of the work function tuning layer to surround a first corner of an end portion, on a side facing the channel region, of the gate electrode material layer.

Classes IPC  ?

• H01L 29/786 - Transistors à couche mince
• H01L 29/49 - Electrodes du type métal-isolant-semi-conducteur
• H01L 21/28 - Fabrication des électrodes sur les corps semi-conducteurs par emploi de procédés ou d'appareils non couverts par les groupes
• H01L 29/66 - Types de dispositifs semi-conducteurs

Abrégé

Provided in the present disclosure are a quantiser for use in a ∑-Δ modulator, a ∑-Δ modulator, and a noise shaping method. The quantiser comprises: an integrator, used for producing a quantisation signal of a K-th period in a K-th sampling period according to an internal signal, a quantisation signal of a K-1-th period, a filtered quantisation signal in the K-1-th period, and a filtered quantisation signal in a K-2-th period, wherein K is a positive integer greater than 1; an integrating capacitor, used for storing the quantisation signal of the K-th period and weighting the internal signal in a K+1-th sampling period; a passive low-pass filter, used for collecting quantisation signals of a K-th period in a K-th discharge period, producing a filtered quantisation signal on the basis of same, and feeding back the filtered quantisation signal to the integrator in the K+1-th sampling period and a K+2-th sampling period; and a comparator, used for quantising the quantisation signal of the K-th period in the K-th discharge period in order to output a digital code.

Classes IPC  ?

• H03M 3/00 - Conversion de valeurs analogiques en, ou à partir d'une modulation différentielle

Abrégé

12121212121212122).

Classes IPC  ?

• H01L 27/088 - Dispositifs consistant en une pluralité de composants semi-conducteurs ou d'autres composants à l'état solide formés dans ou sur un substrat commun comprenant des éléments de circuit passif intégrés avec au moins une barrière de potentiel ou une barrière de surface le substrat étant un corps semi-conducteur comprenant uniquement des composants semi-conducteurs d'un seul type comprenant uniquement des composants à effet de champ les composants étant des transistors à effet de champ à porte isolée
• H01L 21/8234 - Technologie MIS

Abrégé

Provided are a nanowire/nanosheet device with a support portion, a method of manufacturing the same, and an electronic apparatus including the nanowire/nanosheet device. According to the embodiments, the nanowire/nanosheet device may include: a substrate; a first source/drain layer and a second source/drain layer opposite to each other in a first direction on the substrate; a first nanowire/nanosheet and a second nanowire/nanosheet, wherein the first nanowire/nanosheet and the second nanowire/nanosheet are spaced apart from a surface of the substrate, the first nanowire/nanosheet and the second nanowire/nanosheet extend from the first source/drain layer to the second source/drain layer, respectively, and are arranged adjacent to each other in a direction parallel to the surface of the substrate; a first support portion connected between the first nanowire/nanosheet and the second nanowire/nanosheet; and a gate stack extending in a second direction intersecting the first direction to surround the first nanowire/nanosheet and the second nanowire/nanosheet.

Classes IPC  ?

• H01L 29/06 - Corps semi-conducteurs caractérisés par les formes, les dimensions relatives, ou les dispositions des régions semi-conductrices
• H01L 29/423 - Electrodes caractérisées par leur forme, leurs dimensions relatives ou leur disposition relative ne transportant pas le courant à redresser, à amplifier ou à commuter
• H01L 29/786 - Transistors à couche mince
• H01L 29/66 - Types de dispositifs semi-conducteurs
• H01L 21/8234 - Technologie MIS

Abrégé

A semiconductor apparatus with an isolation portion between vertically adjacent elements and an electronic device including the semiconductor apparatus are provided. The semiconductor apparatus may include: a substrate; a first vertical semiconductor element and a second vertical semiconductor element stacked on the substrate sequentially, each of the first vertical semiconductor element and the second vertical semiconductor element including a first source/drain region, a channel region and a second source/drain region stacked sequentially in a vertical direction; and an isolation structure configured to electrically isolate the first vertical semiconductor element from the second vertical semiconductor element, and the isolation structure including a pn junction.

Classes IPC  ?

• H01L 29/06 - Corps semi-conducteurs caractérisés par les formes, les dimensions relatives, ou les dispositions des régions semi-conductrices
• H01L 29/08 - Corps semi-conducteurs caractérisés par les formes, les dimensions relatives, ou les dispositions des régions semi-conductrices avec des régions semi-conductrices connectées à une électrode transportant le courant à redresser, amplifier ou commuter, cette électrode faisant partie d'un dispositif à semi-conducteur qui comporte trois électrodes ou plus
• H01L 29/10 - Corps semi-conducteurs caractérisés par les formes, les dimensions relatives, ou les dispositions des régions semi-conductrices avec des régions semi-conductrices connectées à une électrode ne transportant pas le courant à redresser, amplifier ou commuter, cette électrode faisant partie d'un dispositif à semi-conducteur qui comporte trois électrodes ou plus

Abrégé

Provided are a nanowire/nanosheet device with a support portion, a method of manufacturing the nanowire/nanosheet device, and an electronic apparatus including the nanowire/nanosheet device. According to the embodiments, the nanowire/nanosheet device may include: a substrate; a first source/drain layer and a second source/drain layer opposite to each other in a first direction on the substrate; a first nanowire/nanosheet spaced apart from a surface of the substrate and extending from the first source/drain layer to the second source/drain layer; one or more support portions penetrating the first nanowire/nanosheet in a direction perpendicular to the surface of the substrate; and a gate stack extending in a second direction to surround the first nanowire/nanosheet, wherein the second direction intersects the first direction.

Classes IPC  ?

• H01L 29/423 - Electrodes caractérisées par leur forme, leurs dimensions relatives ou leur disposition relative ne transportant pas le courant à redresser, à amplifier ou à commuter
• H01L 29/06 - Corps semi-conducteurs caractérisés par les formes, les dimensions relatives, ou les dispositions des régions semi-conductrices
• H01L 29/786 - Transistors à couche mince
• H01L 27/088 - Dispositifs consistant en une pluralité de composants semi-conducteurs ou d'autres composants à l'état solide formés dans ou sur un substrat commun comprenant des éléments de circuit passif intégrés avec au moins une barrière de potentiel ou une barrière de surface le substrat étant un corps semi-conducteur comprenant uniquement des composants semi-conducteurs d'un seul type comprenant uniquement des composants à effet de champ les composants étant des transistors à effet de champ à porte isolée
• H01L 29/66 - Types de dispositifs semi-conducteurs

Abrégé

The present disclosure provides a storage unit, a data writing method and a data reading method thereof, a memory and an electronic device. The storage unit includes a semiconductor substrate, a first insulating medium layer, a ferroelectric thin film layer, a bottom electrode, a tunnel junction, a first metal interconnection portion, a second metal interconnection portion, a third metal interconnection portion and a fourth metal interconnection portion. The first insulating medium layer is formed on the semiconductor substrate, the ferroelectric thin film layer is disposed on the first insulating medium layer, the bottom electrode is formed on the ferroelectric thin film layer, and the tunnel junction is formed on the bottom electrode. The first metal interconnection portion is connected to a first end of the bottom electrode, and the third metal interconnection portion is connected to a second end of the bottom electrode. The second metal interconnection portion is connected to the ferroelectric thin film layer, and the fourth metal interconnection portion is connected to the tunnel junction. As compared with the prior art, the present disclosure can control a directional flipping of the magnetic moment in the tunnel junction based on the ferroelectric thin film layer provided. Based on the structural design of the storage unit, the present disclosure does not require an external magnetic field, and fully meets the requirement of high integration of the device.

Classes IPC  ?

• H01L 43/04 - Dispositifs utilisant les effets galvanomagnétiques ou des effets magnétiques analogues; Procédés ou appareils spécialement adaptés à la fabrication ou au traitement de ces dispositifs ou de leurs parties constitutives - Détails de dispositifs à effet Hall
• H01L 27/22 - Dispositifs consistant en une pluralité de composants semi-conducteurs ou d'autres composants à l'état solide formés dans ou sur un substrat commun utilisant des effets de champ magnétique analogues
• H01L 43/06 - Dispositifs à effet Hall
• G11C 11/16 - Mémoires numériques caractérisées par l'utilisation d'éléments d'emmagasinage électriques ou magnétiques particuliers; Eléments d'emmagasinage correspondants utilisant des éléments magnétiques utilisant des éléments dans lesquels l'effet d'emmagasinage est basé sur l'effet de spin
• G11C 11/18 - Mémoires numériques caractérisées par l'utilisation d'éléments d'emmagasinage électriques ou magnétiques particuliers; Eléments d'emmagasinage correspondants utilisant des dispositifs à effet Hall

Abrégé

Provided are a semiconductor device, a method of manufacturing the semiconductor device, and an electronic apparatus including the device. According to the embodiments, the semiconductor device may include: an active region extending substantially in a vertical direction on a substrate; a gate stack formed around at least a portion of an outer periphery of a middle section of the active region in the vertical direction, wherein the active region comprises a channel region opposite to the gate stack, and a first source/drain region and a second source/drain region located on two opposite sides of the channel region in the vertical direction; a first spacer located between a conductor layer of the gate stack and the first source/drain region, and a second spacer located between the conductor layer of the gate stack and the second source/drain region.

Classes IPC  ?

• H01L 29/66 - Types de dispositifs semi-conducteurs
• H01L 29/78 - Transistors à effet de champ l'effet de champ étant produit par une porte isolée
• H01L 29/08 - Corps semi-conducteurs caractérisés par les formes, les dimensions relatives, ou les dispositions des régions semi-conductrices avec des régions semi-conductrices connectées à une électrode transportant le courant à redresser, amplifier ou commuter, cette électrode faisant partie d'un dispositif à semi-conducteur qui comporte trois électrodes ou plus
• H01L 21/8234 - Technologie MIS

Abrégé

Provided in the present disclosure is a memristor, comprising a transistor and a resistive random access memory, wherein a drain of the transistor is connected to a bottom electrode of the resistive random access memory; and the resistive random access memory comprises: the bottom electrode, a resistive random material layer, a current limiting layer and a top electrode from bottom to top, wherein the current limiting layer stabilizes the fluctuation of a low resistance by means of reducing a surge current and optimizing a heat distribution, thereby improving the precision of calculating a Hamming distance.

Classes IPC  ?

• G11C 13/00 - Mémoires numériques caractérisées par l'utilisation d'éléments d'emmagasinage non couverts par les groupes , ou

Abrégé

The present disclosure provides a semiconductor device and a method of manufacturing the same thereof, and an electronic apparatus including the semiconductor device. According to embodiments of the present disclosure, the semiconductor device includes a channel portion, source/drain portions connected to the channel portion on two opposite sides of the channel portion, and a gate stack intersecting with the channel portion. The channel portion includes a first portion extending in a vertical direction with respect to a substrate and a second portion extending from the first portion to two opposite sides in a lateral direction with respect to the substrate, respectively.

Classes IPC  ?

• H01L 29/06 - Corps semi-conducteurs caractérisés par les formes, les dimensions relatives, ou les dispositions des régions semi-conductrices
• H01L 29/775 - Transistors à effet de champ avec un canal à gaz de porteurs de charge à une dimension, p.ex. FET à fil quantique
• H01L 29/66 - Types de dispositifs semi-conducteurs
• H01L 29/786 - Transistors à couche mince
• H01L 21/8234 - Technologie MIS

Abrégé

The present disclosure relates to a data recovery method used for a flash memory, comprising: reading data from a flash memory by using a preset read voltage; calculating a check node error rate corresponding to the data; calculating a read voltage adjustment step according to the check node error rate; adjusting the preset read voltage according to the read voltage adjustment step, reading the data from the flash memory by using the adjusted preset read voltage, and repeating from the operation of calculating the check node error rate corresponding to the data to the operation of adjusting the preset read voltage according to the read voltage adjustment step, until the check node error rate is minimal; and selecting a read voltage corresponding to the minimum check node error rate to read the data from the flash memory so as to perform data recovery. In the method, the read voltage adjustment step can be dynamically adjusted so as to reduce the time required for optimal read voltage searching in a reread error correcting algorithm, and reduce unnecessary ECC decoding, thereby reducing the time required for data recovery.

Classes IPC  ?

• G06F 11/10 - Détection ou correction d'erreur par introduction de redondance dans la représentation des données, p.ex. en utilisant des codes de contrôle en ajoutant des chiffres binaires ou des symboles particuliers aux données exprimées suivant un code, p.ex. contrôle de parité, exclusion des 9 ou des 11

Abrégé

The present disclosure provides a method for fabricating an anti-reflective layer on a quartz surface by using a metal-induced self-masking etching technique, comprising: performing reactive ion etching to a metal material and a quartz substrate by using a mixed gas containing a fluorine-based gas, wherein metal atoms and/or ions of the metal material are sputtered to a surface of the quartz substrate, to form a non-volatile metal fluoride on the surface of the quartz substrate; forming a micromask by a product of etching generated by reactive ion etching gathering around the non-volatile metal fluoride; and etching the micromask and the quartz substrate simultaneously, to form an anti-reflective layer having a sub-wavelength structure.

Classes IPC  ?

• G02B 1/12 - Revêtements optiques obtenus par application sur les éléments optiques ou par traitement de la surface de ceux-ci par traitement de la surface, p.ex. par irradiation
• G02B 1/02 - OPTIQUE ÉLÉMENTS, SYSTÈMES OU APPAREILS OPTIQUES Éléments optiques caractérisés par la substance dont ils sont faits; Revêtements optiques pour éléments optiques faits de cristaux, p.ex. sel gemme, semi-conducteurs
• G02B 1/118 - Revêtements antiréfléchissants ayant des structures de surface de longueur d’onde sous-optique conçues pour améliorer la transmission, p.ex. structures du type œil de mite
• G03F 7/20 - Exposition; Appareillages à cet effet

Abrégé

A method for packaging a semiconductor structure, a packaging structure, and a chip. The method includes: forming the semiconductor structure on a SOI chip, where the semiconductor structure includes an edge coupler or a cavity structure; forming, through PECVD, silicon oxide on a surface of the semiconductor structure, where the surface is provided with an opening of a trench; and performing subsequent packaging. A characteristic of low step coverage of the PECVD is utilized for sealing an opening of a trench of the semiconductor structure, and addressed is an issue of a device failure due to the trench blocked by a packaging material in subsequent packaging.

Classes IPC  ?

• G02B 6/132 - Circuits optiques intégrés caractérisés par le procédé de fabrication par le dépôt de couches minces
• H01L 21/02 - Fabrication ou traitement des dispositifs à semi-conducteurs ou de leurs parties constitutives
• H01L 21/768 - Fixation d'interconnexions servant à conduire le courant entre des composants distincts à l'intérieur du dispositif
• H01L 23/48 - Dispositions pour conduire le courant électrique vers le ou hors du corps à l'état solide pendant son fonctionnement, p.ex. fils de connexion ou bornes
• H01L 25/16 - Ensembles consistant en une pluralité de dispositifs à semi-conducteurs ou d'autres dispositifs à l'état solide les dispositifs étant de types couverts par plusieurs des groupes principaux , ou dans une seule sous-classe de , , p.ex. circuit hybrides
• H01L 27/12 - Dispositifs consistant en une pluralité de composants semi-conducteurs ou d'autres composants à l'état solide formés dans ou sur un substrat commun comprenant des éléments de circuit passif intégrés avec au moins une barrière de potentiel ou une barrière de surface le substrat étant autre qu'un corps semi-conducteur, p.ex. un corps isolant
• G02B 6/30 - Moyens de couplage optique pour usage entre fibre et dispositif à couche mince

Abrégé

An interconnection structure and a method of manufacturing the same, and an electronic device including the interconnection structure are provided. According to an embodiment, the interconnection structure includes: a first interconnection line at a first level, including at least a first portion extending along a first direction; a second interconnection line at a second level higher than the first level, including at least a second portion extending along a second direction crossing the first direction; a via plug disposed between the first portion of the first interconnection line and the second portion of the second interconnection line, and configured to electrically connect the first interconnection line and the second interconnection line, wherein the via plug includes a first pair of sidewalls respectively extending substantially parallel to corresponding sidewalls of the first portion and a second pair of sidewalls respectively extending substantially parallel to corresponding sidewalls of the second portion.

Classes IPC  ?

• H01L 23/522 - Dispositions pour conduire le courant électrique à l'intérieur du dispositif pendant son fonctionnement, d'un composant à un autre comprenant des interconnexions externes formées d'une structure multicouche de couches conductrices et isolantes inséparables du corps semi-conducteur sur lequel elles ont été déposées
• H01L 21/768 - Fixation d'interconnexions servant à conduire le courant entre des composants distincts à l'intérieur du dispositif
• H01L 23/532 - Dispositions pour conduire le courant électrique à l'intérieur du dispositif pendant son fonctionnement, d'un composant à un autre comprenant des interconnexions externes formées d'une structure multicouche de couches conductrices et isolantes inséparables du corps semi-conducteur sur lequel elles ont été déposées caractérisées par les matériaux

Abrégé

An activation function generator based on a magnetic domain wall driving type magnetic tunnel junction, and a preparation method therefor. The activation function generator comprises: a spin-orbit coupling layer, which is configured to generate a spin-orbit torque; a ferromagnetic free layer, which is formed on the spin-orbit coupling layer, and is configured to provide a magnetic domain wall motion orbit; a non-magnetic barrier layer, which is formed on the ferromagnetic free layer; a ferromagnetic reference layer, which is formed on the non-magnetic barrier layer; a top electrode, which is formed on the ferromagnetic reference layer; an antiferromagnetic pinning layer, which is formed on two ends of the ferromagnetic free layer; and a left electrode and a right electrode, which are respectively formed at two positions on the antiferromagnetic pinning layer.

Classes IPC  ?

• G06N 3/063 - Réalisation physique, c. à d. mise en œuvre matérielle de réseaux neuronaux, de neurones ou de parties de neurone utilisant des moyens électroniques
• H01L 43/00 - Dispositifs utilisant les effets galvanomagnétiques ou des effets magnétiques analogues; Procédés ou appareils spécialement adaptés à la fabrication ou au traitement de ces dispositifs ou de leurs parties constitutives
• H01L 43/02 - Dispositifs utilisant les effets galvanomagnétiques ou des effets magnétiques analogues; Procédés ou appareils spécialement adaptés à la fabrication ou au traitement de ces dispositifs ou de leurs parties constitutives - Détails

Abrégé

Disclosed are an NOR type memory device and a manufacturing method therefor, and an electronic apparatus comprising the NOR type memory device. According to embodiments, the NOR type memory device may comprise: a plurality of device layers stacked on a substrate, wherein each device layer comprises a first source/drain region and a second source/drain region located at two opposite ends in a vertical direction, and a channel region located between the first source/drain region and the second source/drain region in the vertical direction; and a gate stack vertically extending relative to the substrate to pass through the device layers, the gate stack comprising gate conductor layers and memory functional layers arranged between the gate conductor layers and the device layers, and memory cells being defined at intersections of the gate stack and the device layers, wherein the doping concentration in the first source/drain region and the second source/drain region decreases toward the channel region in the vertical direction.

Classes IPC  ?

• H01L 27/11565 - Mémoires mortes programmables électriquement; Procédés de fabrication à étapes multiples de ces dispositifs avec isolateurs de grille à piégeage de charge, p.ex. MNOS ou NROM caractérisées par la configuration vue du dessus

Abrégé

Disclosed are an NOR type memory device and a manufacturing method therefor, and an electronic device comprising same. According to embodiments, the NOR type memory device may comprise: a plurality of device layers provided on a substrate, each device layer comprising a stacked layer of a first source/drain layer, a first channel layer, and a second source/drain layer; and a gate stack vertically extending with respect to the substrate to pass through the stacked layer in each device layer, the gate stack comprising a gate conductor layer and a storage function layer provided between the gate conductor layer and the stacked layer, and a storage cell being defined at an intersection of the gate stack and the stacked layer.

Classes IPC  ?

• H01L 27/11565 - Mémoires mortes programmables électriquement; Procédés de fabrication à étapes multiples de ces dispositifs avec isolateurs de grille à piégeage de charge, p.ex. MNOS ou NROM caractérisées par la configuration vue du dessus

Abrégé

An NOR-type memory device and a manufacturing method therefor, and an electronic apparatus comprising the NOR-type memory device. According to embodiments, the NOR-type memory device may comprise: a gate stack vertically extending on a substrate and comprising a gate conductor layer and a storage function layer; and a first semiconductor layer and a second semiconductor layer which surround the periphery of the gate stack and extend along the sidewall of the gate stack, the first semiconductor layer and the second semiconductor layer being respectively located at different heights relative to the substrate. The storage function layer is located between the first semiconductor layer and the gate conductor layer and between the second semiconductor layer and the gate conductor layer. Each of the first semiconductor layer and the second semiconductor layer comprises a first source/drain region, a channel region, and a second source/drain region which are sequentially arranged in the vertical direction. Memory units are defined at an intersection of the gate stack and the first semiconductor layer and at an intersection of the gate stack and the second semiconductor layer, respectively.

Classes IPC  ?

• H01L 27/11578 - Mémoires mortes programmables électriquement; Procédés de fabrication à étapes multiples de ces dispositifs avec isolateurs de grille à piégeage de charge, p.ex. MNOS ou NROM caractérisées par des agencements tridimensionnels, p.ex. avec des cellules à des niveaux différents de hauteur

Abrégé

The present invention relates to the technical field of circuit design. Disclosed are a light-emitting drive circuit and method, and a display drive circuit, used for improving the output stability of the light-emitting drive circuit. The light-emitting drive circuit comprises: an input circuit, a first potential control circuit, a second potential control circuit, a first output circuit, and a second output circuit. The method is used for driving the light-emitting drive circuit to output a light-emitting drive signal. The display drive circuit comprises the light-emitting drive circuit.

Classes IPC  ?

• G09G 3/30 - Dispositions ou circuits de commande présentant un intérêt uniquement pour l'affichage utilisant des moyens de visualisation autres que les tubes à rayons cathodiques pour la présentation d'un ensemble de plusieurs caractères, p.ex. d'une page, en composant l'ensemble par combinaison d'éléments individuels disposés en matrice utilisant des sources lumineuses commandées utilisant des panneaux électroluminescents

Abrégé

A NOR-type storage device, a method of manufacturing the same, and an electronic apparatus including the same are provided. The NOR-type storage device includes: a gate stack extending vertically on a substrate; an active region surrounding a periphery of the gate stack, the active region including first and second source/drain regions, a first channel region between the first and second source/drain regions, third and fourth source/drain regions, and a second channel region between the third and fourth source/drain regions; first, second, third and fourth interconnection layers extending laterally from the first to fourth source/drain regions, respectively; and a source line contact part extending vertically with respect to the substrate to pass through the first to fourth interconnection layers and electrically connected to one of the first interconnection layer and the second interconnection layer, and to one of the third interconnection layer and the fourth interconnection layer.

Classes IPC  ?

• H01L 29/417 - Electrodes caractérisées par leur forme, leurs dimensions relatives ou leur disposition relative transportant le courant à redresser, à amplifier ou à commuter
• H01L 27/11565 - Mémoires mortes programmables électriquement; Procédés de fabrication à étapes multiples de ces dispositifs avec isolateurs de grille à piégeage de charge, p.ex. MNOS ou NROM caractérisées par la configuration vue du dessus
• H01L 27/11582 - Mémoires mortes programmables électriquement; Procédés de fabrication à étapes multiples de ces dispositifs avec isolateurs de grille à piégeage de charge, p.ex. MNOS ou NROM caractérisées par des agencements tridimensionnels, p.ex. avec des cellules à des niveaux différents de hauteur la région de source et la région de drain étant à différents niveaux, p.ex. avec des canaux inclinés les canaux comprenant des parties verticales, p.ex. canaux en forme de U
• H01L 27/11587 - Mémoires mortes programmables électriquement; Procédés de fabrication à étapes multiples de ces dispositifs les électrodes de grille comprenant une couche utilisée pour ses propriétés de mémoire ferro-électrique, p.ex. semi-conducteur métal-ferro-électrique [MFS] ou semi-conducteur d’isolation métal-ferro-électrique-métal [MFMIS] caractérisées par la configuration vue du dessus
• H01L 27/11597 - Mémoires mortes programmables électriquement; Procédés de fabrication à étapes multiples de ces dispositifs les électrodes de grille comprenant une couche utilisée pour ses propriétés de mémoire ferro-électrique, p.ex. semi-conducteur métal-ferro-électrique [MFS] ou semi-conducteur d’isolation métal-ferro-électrique-métal [MFMIS] caractérisées par des agencements tridimensionnels, p.ex. avec des cellules à des niveaux différents de hauteur
• H01L 29/08 - Corps semi-conducteurs caractérisés par les formes, les dimensions relatives, ou les dispositions des régions semi-conductrices avec des régions semi-conductrices connectées à une électrode transportant le courant à redresser, amplifier ou commuter, cette électrode faisant partie d'un dispositif à semi-conducteur qui comporte trois électrodes ou plus
• H01L 21/28 - Fabrication des électrodes sur les corps semi-conducteurs par emploi de procédés ou d'appareils non couverts par les groupes
• H01L 29/423 - Electrodes caractérisées par leur forme, leurs dimensions relatives ou leur disposition relative ne transportant pas le courant à redresser, à amplifier ou à commuter
• H01L 29/51 - Matériaux isolants associés à ces électrodes
• H01L 29/66 - Types de dispositifs semi-conducteurs
• H01L 29/78 - Transistors à effet de champ l'effet de champ étant produit par une porte isolée
• H01L 29/792 - Transistors à effet de champ l'effet de champ étant produit par une porte isolée à isolant de grille à emmagasinage de charges, p.ex. transistor de mémoire MNOS

Abrégé

A vertical storage device, a method of manufacturing the same, and an electronic apparatus including the storage device are provided. The storage device includes: a first source/drain layer located at a first height with respect to a substrate and a second source/drain layer located at a second height different from the first height; a channel layer connecting the first source/drain layer and the second source/drain layer; and a gate stack including a storage function layer, the storage function layer extending on a sidewall of the channel layer and extending in-plane from the sidewall of the channel layer onto a sidewall of the first source/drain layer and a sidewall of the second source/drain layer.

Classes IPC  ?

• H01L 29/788 - Transistors à effet de champ l'effet de champ étant produit par une porte isolée à grille flottante
• H01L 29/792 - Transistors à effet de champ l'effet de champ étant produit par une porte isolée à isolant de grille à emmagasinage de charges, p.ex. transistor de mémoire MNOS
• H01L 21/28 - Fabrication des électrodes sur les corps semi-conducteurs par emploi de procédés ou d'appareils non couverts par les groupes
• H01L 29/78 - Transistors à effet de champ l'effet de champ étant produit par une porte isolée
• H01L 21/02 - Fabrication ou traitement des dispositifs à semi-conducteurs ou de leurs parties constitutives
• H01L 21/225 - Diffusion des impuretés, p.ex. des matériaux de dopage, des matériaux pour électrodes, à l'intérieur ou hors du corps semi-conducteur, ou entre les régions semi-conductrices; Redistribution des impuretés, p.ex. sans introduction ou sans élimination de matériau dopant supplémentaire en utilisant la diffusion dans ou hors d'un solide, à partir d'une ou en phase solide, p.ex. une couche d'oxyde dopée
• H01L 21/3065 - Gravure par plasma; Gravure au moyen d'ions réactifs
• H01L 29/08 - Corps semi-conducteurs caractérisés par les formes, les dimensions relatives, ou les dispositions des régions semi-conductrices avec des régions semi-conductrices connectées à une électrode transportant le courant à redresser, amplifier ou commuter, cette électrode faisant partie d'un dispositif à semi-conducteur qui comporte trois électrodes ou plus
• H01L 29/10 - Corps semi-conducteurs caractérisés par les formes, les dimensions relatives, ou les dispositions des régions semi-conductrices avec des régions semi-conductrices connectées à une électrode ne transportant pas le courant à redresser, amplifier ou commuter, cette électrode faisant partie d'un dispositif à semi-conducteur qui comporte trois électrodes ou plus
• H01L 29/66 - Types de dispositifs semi-conducteurs

Abrégé

A three-dimensional memory and a method for manufacturing the three-dimensional memory, the three-dimensional memory includes a storage unit and a logic control unit, a front of the storage unit and a front of the logic control unit are attached to each other, and the logic control unit is connected to a control circuit, wherein a second metal line of the storage unit and a first metal line of the storage unit are respectively disposed on upper and lower sides of a channel layer of the storage unit, and the first metal line and the second metal line are electrically connected to the control circuit.

Classes IPC  ?

• H01L 27/11556 - Mémoires mortes programmables électriquement; Procédés de fabrication à étapes multiples de ces dispositifs avec grilles flottantes caractérisées par des agencements tridimensionnels, p.ex. avec des cellules à des niveaux différents de hauteur la région de source et la région de drain étant à différents niveaux, p.ex. avec des canaux inclinés les canaux comprenant des parties verticales, p.ex. des canaux en forme de U
• H01L 27/11524 - Mémoires mortes programmables électriquement; Procédés de fabrication à étapes multiples de ces dispositifs avec grilles flottantes caractérisées par la région noyau de mémoire avec transistors de sélection de cellules, p.ex. NON-ET
• H01L 27/11582 - Mémoires mortes programmables électriquement; Procédés de fabrication à étapes multiples de ces dispositifs avec isolateurs de grille à piégeage de charge, p.ex. MNOS ou NROM caractérisées par des agencements tridimensionnels, p.ex. avec des cellules à des niveaux différents de hauteur la région de source et la région de drain étant à différents niveaux, p.ex. avec des canaux inclinés les canaux comprenant des parties verticales, p.ex. canaux en forme de U
• H01L 27/1157 - Mémoires mortes programmables électriquement; Procédés de fabrication à étapes multiples de ces dispositifs avec isolateurs de grille à piégeage de charge, p.ex. MNOS ou NROM caractérisées par la région noyau de mémoire avec transistors de sélection de cellules, p.ex. NON-ET
• H01L 23/528 - Configuration de la structure d'interconnexion
• H01L 27/11526 - Mémoires mortes programmables électriquement; Procédés de fabrication à étapes multiples de ces dispositifs avec grilles flottantes caractérisées par la région de circuit périphérique
• H01L 27/11573 - Mémoires mortes programmables électriquement; Procédés de fabrication à étapes multiples de ces dispositifs avec isolateurs de grille à piégeage de charge, p.ex. MNOS ou NROM caractérisées par la région de circuit périphérique

Abrégé

A storage unit, a method of manufacturing the storage unit, and a three-dimensional memory. The storage unit includes: a first conductivity-type substrate; a channel layer stacked on the first conductivity-type substrate in a first direction; a second conductivity-type conduction layer including a first part and a second part that are connected, the first part being located between the first conductivity-type substrate and the channel layer, and the second part being formed in a via hole passing through the channel layer; a channel passage layer penetrating the channel layer and the first part in a negative direction of the first direction, and extending into an interior of the first conductivity-type substrate; and an insulating layer located in the channel layer and surrounding a periphery of the channel passage layer. The first conductivity-type substrate and the second conductivity-type conduction layer provide carriers required for reading and erasing operations, respectively.

Classes IPC  ?

• H01L 27/11582 - Mémoires mortes programmables électriquement; Procédés de fabrication à étapes multiples de ces dispositifs avec isolateurs de grille à piégeage de charge, p.ex. MNOS ou NROM caractérisées par des agencements tridimensionnels, p.ex. avec des cellules à des niveaux différents de hauteur la région de source et la région de drain étant à différents niveaux, p.ex. avec des canaux inclinés les canaux comprenant des parties verticales, p.ex. canaux en forme de U

Abrégé

A semiconductor apparatus with a heat dissipation conduit in a sidewall interconnection structure, a method of manufacturing the semiconductor apparatus, and an electronic device including the semiconductor apparatus. According to the embodiments, the semiconductor apparatus includes: a carrier substrate having a first region and a second region adjacent to each other; a semiconductor device on the first region; and an interconnection structure on the second region, wherein the interconnection structure includes: an electrical isolation layer; a conductive structure in the electrical isolation layer, wherein at least a part of components require to be electrically connected in the semiconductor device is in contact with and therefore electrically connected to the conductive structure in a lateral direction, wherein the conductive structure is located at a corresponding height in the interconnection structure; and a heat dissipation conduit in the electrical isolation layer.

Classes IPC  ?

• H01L 23/46 - Dispositions pour le refroidissement, le chauffage, la ventilation ou la compensation de la température impliquant le transfert de chaleur par des fluides en circulation
• H01L 21/48 - Fabrication ou traitement de parties, p.ex. de conteneurs, avant l'assemblage des dispositifs, en utilisant des procédés non couverts par l'un uniquement des groupes

Abrégé

An interconnection structure for semiconductor devices formed on a substrate may be arranged under the semiconductor devices. The interconnection structure includes at least one via layer and at least one interconnection layer alternately arranged in a direction from the semiconductor device to the substrate, wherein each via layer includes via holes respectively arranged under at least a part of the semiconductor devices, and each interconnection layer includes conductive nodes respectively arranged under at least a part of the semiconductor devices, and in a same interconnection layer, a conductive channel is provided between at least one conductive node and at least another node; and the via holes in each via layer and the conductive nodes in each interconnection layer corresponding to the via holes at least partially overlap with each other in the direction from the semiconductor device to the substrate.

Classes IPC  ?

• H01L 23/522 - Dispositions pour conduire le courant électrique à l'intérieur du dispositif pendant son fonctionnement, d'un composant à un autre comprenant des interconnexions externes formées d'une structure multicouche de couches conductrices et isolantes inséparables du corps semi-conducteur sur lequel elles ont été déposées
• H01L 23/528 - Configuration de la structure d'interconnexion

Abrégé

There is provided an L-shaped stepped word line structure, a method of manufacturing the same, and a three-dimensional memory. the word line structure includes: a plurality of L-shaped word line units, wherein each L-shaped word line unit includes a long side extending in a second direction and arranged adjacent to a gate line slit, and a short side extending in a first direction and including a word line terminal; wherein the word line terminal is formed in a stepped stacked layer structure including a plurality of stacked layer pairs formed of an insulating material, a region close to the gate line slit in a stacked layer of each stacked layer pair serves as a replacement metal region, the replacement metal region includes a short side region surface metal layer located on a surface and a short side region internal metal layer located in an interior, a length of the short side region surface metal layer in the first direction is greater than that of the short side region internal metal layer in the first direction, and the word line terminal corresponds to the short side region surface metal layer. It may be ensured that even if the etching is excessive in a case that the etching selection ratio is not high enough, a word line short circuit may not occur.

Classes IPC  ?

• H01L 23/528 - Configuration de la structure d'interconnexion
• H01L 23/535 - Dispositions pour conduire le courant électrique à l'intérieur du dispositif pendant son fonctionnement, d'un composant à un autre comprenant des interconnexions internes, p.ex. structures d'interconnexions enterrées
• H01L 21/768 - Fixation d'interconnexions servant à conduire le courant entre des composants distincts à l'intérieur du dispositif

Abrégé

The present disclosure provides a three-state spintronic device, a memory cell, an array, and a read-write circuit. The three-state spintronic device comprises, from bottom to top, bottom electrodes, a magnetic tunnel junction, and a top electrode; the magnetic tunnel junction comprises: a spin-orbit coupling layer, a ferromagnetic free layer, a barrier tunneling layer, a ferromagnetic reference layer, three local magnetic domain wall pinning centers, and magnetic domain wall nucleation centers; the antisymmetric exchange interaction is modulated, and the magnetic domain wall pinning centers are embedded in the interface between a heavy metal and the ferromagnetic free layer; the magnetic domain wall nucleation centers are disposed at two ends of the ferromagnetic free layer; a current pulse flows through the spin-orbit coupling layer to generate a spin current and the spin current is injected into the ferromagnetic free layer. Under the control of the full electric field, the effective field of the spin-orbit torque drives the displacement of a domain wall, the displacement can be modulated by the number of pulses, pulse width and direction of the current, and CMOS process compatibility and high reliability are provided; the present disclosure also provides a three-state read-write circuit and a ternary network computing application scheme thereof, and achieves the high-performance GXNOR operation of a ternary spintronic device.

Classes IPC  ?

• G11C 11/16 - Mémoires numériques caractérisées par l'utilisation d'éléments d'emmagasinage électriques ou magnétiques particuliers; Eléments d'emmagasinage correspondants utilisant des éléments magnétiques utilisant des éléments dans lesquels l'effet d'emmagasinage est basé sur l'effet de spin

Abrégé

A method for reducing impact of phase grating asymmetry on position measurement precision, comprising the following steps: determining an asymmetry change range according to a design value and processing precision of a phase grating, and then determining an asymmetric grating structure; establishing an asymmetric grating simulation model; inputting the asymmetric grating structure into the asymmetric grating simulation model to simulate a position error curve of each diffraction order within the asymmetry change range; and determining the weight of each diffraction order according to the obtained difference in position error of each diffraction order, to reduce the impact of asymmetric changes. Without a need to measure the morphology of a grating, and only by determining a grating asymmetry change range according to processing precision, the impact of asymmetric changes in the range on position measurement precision can be reduced.

Classes IPC  ?

• G01B 11/00 - Dispositions pour la mesure caractérisées par l'utilisation de techniques optiques
• G03F 9/00 - Mise en registre ou positionnement d'originaux, de masques, de trames, de feuilles photographiques, de surfaces texturées, p.ex. automatique

Abrégé

A semiconductor structure, a method for manufacturing the semiconductor structure, and a transistor. A doped structure is provided, where the doped structure includes a dopant. A surface of the doped structure is oxidized to form the oxide film. In such case, the dopant at an interface between the oxide film and the doped structure may be redistributed, and thereby a segregated-dopant layer is formed inside or at a surface of the doped structure under the oxide film. A concentration of the dopant is higher in the segregated-dopant layer than in other regions of the doped structure. After the oxide film is removed, the doped structure with a high surface doping concentration can be obtained without an additional doping process. Therefore, after a conducting structure is formed on the segregated-dopant layer, a low contact resistance between the conducting structure and the doped structure is obtained, and a device performance is improved.

Classes IPC  ?

• H01L 29/423 - Electrodes caractérisées par leur forme, leurs dimensions relatives ou leur disposition relative ne transportant pas le courant à redresser, à amplifier ou à commuter
• H01L 29/417 - Electrodes caractérisées par leur forme, leurs dimensions relatives ou leur disposition relative transportant le courant à redresser, à amplifier ou à commuter
• H01L 29/40 - Electrodes
• H01L 29/06 - Corps semi-conducteurs caractérisés par les formes, les dimensions relatives, ou les dispositions des régions semi-conductrices
• H01L 29/786 - Transistors à couche mince
• H01L 29/66 - Types de dispositifs semi-conducteurs

Abrégé

The present application provides a semiconductor structure and a manufacturing method therefor, and a transistor. A doped structure is provided, and the doped structure may comprise doped elements; the surface of the doped structure is oxidized to form an oxide film, such that the doped elements at an interface between the oxide film and the doped structure would be redistributed, a segregation impurity layer is formed in the doped structure under the oxide film, and the doping concentration of the segregation impurity layer is higher than that of other positions of the doped structure; after the oxide film is removed, a doped structure having a relatively high surface doping concentration can be obtained without an additional doping process, such that after a conductor structure is formed on the segregation impurity layer, the contact resistance between the conductor structure and the doped structure is relatively low, and the device performance is improved.

Classes IPC  ?

• H01L 21/336 - Transistors à effet de champ à grille isolée
• H01L 29/78 - Transistors à effet de champ l'effet de champ étant produit par une porte isolée
• H01L 29/08 - Corps semi-conducteurs caractérisés par les formes, les dimensions relatives, ou les dispositions des régions semi-conductrices avec des régions semi-conductrices connectées à une électrode transportant le courant à redresser, amplifier ou commuter, cette électrode faisant partie d'un dispositif à semi-conducteur qui comporte trois électrodes ou plus
• H01L 29/10 - Corps semi-conducteurs caractérisés par les formes, les dimensions relatives, ou les dispositions des régions semi-conductrices avec des régions semi-conductrices connectées à une électrode ne transportant pas le courant à redresser, amplifier ou commuter, cette électrode faisant partie d'un dispositif à semi-conducteur qui comporte trois électrodes ou plus
• H01L 29/36 - Corps semi-conducteurs caractérisés par la concentration ou la distribution des impuretés

Abrégé

The present disclosure provides a multi-resistive spin electronic device, comprising: a top electrode and a bottom electrode respectively connected to a read-write circuit; and a magnetic tunnel junction located between the two electrodes and sequentially comprising, from top to bottom, a ferromagnetic reference layer, a barrier tunneling layer, a ferromagnetic free layer, and a spin-orbit coupling layer. Both ends of the ferromagnetic free layer are provided with nucleation centers for generating a magnetic domain wall; the spin-orbit coupling layer is connected to the bottom electrode, generates an electron spin current when applied with a write pulse, and drives the magnetic domain wall to move by means of spin-orbit torque; and interfaces of the spin-orbit coupling layer and the ferromagnetic free layer are provided with a plurality of local magnetic domain wall pinning centers for enhancing the interfacial Dzyaloshinskii-Moriya interaction coefficient strength. The device respectively drives and pins the magnetic domain wall in the ferromagnetic free layer by regulating spin coupling torque and the Dzyaloshinskii-Moriya interaction strength, so as to realize multi-resistive switching under a full electric field condition. The present disclosure further provides an in-memory computing Boolean logic and full-add operator based on the multi-resistive spin electronic device.

Classes IPC  ?

• G11C 11/02 - Mémoires numériques caractérisées par l'utilisation d'éléments d'emmagasinage électriques ou magnétiques particuliers; Eléments d'emmagasinage correspondants utilisant des éléments magnétiques
• H01L 43/02 - Dispositifs utilisant les effets galvanomagnétiques ou des effets magnétiques analogues; Procédés ou appareils spécialement adaptés à la fabrication ou au traitement de ces dispositifs ou de leurs parties constitutives - Détails

Abrégé

A Static Random Access Memory (SRAM) cell that may include a first pull-up transistor, a second pull-up transistor, a first pull-down transistor, a second pull-down transistor, a first pass-gate transistor and a second pass-gate transistor provided at two levels on a substrate. The respective transistors may be vertical transistors. The first pull-up transistor and the second pull-up transistor may be provided at a first level, and the first pull-down transistor, the second pull-down transistor, the first pass-gate transistor and the second pass-gate transistor may be provided at a second level different from the first level. A region where the first pull-up transistor and the second pull-up transistor are located and a region where the first pull-down transistor, the second pull-down transistor, the first pass-gate transistor and the second pass-gate transistor are located may at least partially overlap in a vertical direction with respect to an upper surface of the substrate.

Classes IPC  ?

• G11C 11/00 - Mémoires numériques caractérisées par l'utilisation d'éléments d'emmagasinage électriques ou magnétiques particuliers; Eléments d'emmagasinage correspondants
• G11C 11/412 - Mémoires numériques caractérisées par l'utilisation d'éléments d'emmagasinage électriques ou magnétiques particuliers; Eléments d'emmagasinage correspondants utilisant des éléments électriques utilisant des dispositifs à semi-conducteurs utilisant des transistors formant des cellules avec réaction positive, c. à d. des cellules ne nécessitant pas de rafraîchissement ou de régénération de la charge, p.ex. multivibrateur bistable, déclencheur de Schmitt utilisant uniquement des transistors à effet de champ
• G11C 11/417 - Circuits auxiliaires, p.ex. pour l'adressage, le décodage, la commande, l'écriture, la lecture, la synchronisation ou la réduction de la consommation pour des cellules de mémoire du type à effet de champ
• H01L 27/105 - Dispositifs consistant en une pluralité de composants semi-conducteurs ou d'autres composants à l'état solide formés dans ou sur un substrat commun comprenant des éléments de circuit passif intégrés avec au moins une barrière de potentiel ou une barrière de surface le substrat étant un corps semi-conducteur comprenant une pluralité de composants individuels dans une configuration répétitive comprenant des composants à effet de champ
• H01L 27/11 - Structures de mémoires statiques à accès aléatoire
• H01L 29/78 - Transistors à effet de champ l'effet de champ étant produit par une porte isolée

Abrégé

Provided is a signal driving system with a constant slew rate. The signal driving system comprises: a step voltage generation unit, which is configured to be used for providing multiple voltage signals that progressively change at equal differences; a multiplexer, wherein one input end of the multiplexer is connected to the step voltage generation unit so as to receive the multiple voltage signals that progressively change at equal differences, and the other input end of the multiplexer is connected to a control signal generation unit, and is configured to be used for selectively outputting, under the control by a control signal sent by the control signal generation unit, the multiple voltage signals that progressively change at equal differences; a voltage following unit, which is connected to the multiplexer, and plays a role in isolation and improves driving capability; and an output following unit, which is connected to the voltage following unit and is configured to be used for driving a load unit connected later.

Classes IPC  ?

• H03K 19/0175 - Dispositions pour le couplage; Dispositions pour l'interface

Abrégé

A strained vertical channel semiconductor device, a method of manufacturing the same, and an electronic apparatus including the same are provided. The method includes: providing a vertical channel layer on a substrate, wherein the vertical channel layer is held by a first supporting layer on a first side in a lateral direction, and is held by a second supporting layer on a second side opposite to the first side; replacing the first supporting layer with a first gate stack while the vertical channel layer is held by the second supporting layer; and replacing the second supporting layer with a second gate stack while the vertical channel layer is held by the first gate stack.

Classes IPC  ?

• H01L 29/786 - Transistors à couche mince
• H01L 29/78 - Transistors à effet de champ l'effet de champ étant produit par une porte isolée
• H01L 29/66 - Types de dispositifs semi-conducteurs