Institute of Microelectronics, Chinese Academy of Sciences

Chine

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        International 760
        États-Unis 535
Date
Nouveautés (dernières 4 semaines) 8
2024 mai (MACJ) 5
2024 avril 6
2024 mars 5
2024 février 3
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Classe IPC
H01L 29/78 - Transistors à effet de champ l'effet de champ étant produit par une porte isolée 386
H01L 21/336 - Transistors à effet de champ à grille isolée 358
H01L 29/66 - Types de dispositifs semi-conducteurs 220
H01L 29/06 - Corps semi-conducteurs caractérisés par les formes, les dimensions relatives, ou les dispositions des régions semi-conductrices 149
H01L 21/8238 - Transistors à effet de champ complémentaires, p.ex. CMOS 127
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Statut
En Instance 105
Enregistré / En vigueur 1 190
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1.

SEMICONDUCTOR DEVICE AND METHOD FOR MANUFACTURING THE SAME

      
Numéro d'application 17783627
Statut En instance
Date de dépôt 2021-12-23
Date de la première publication 2024-05-16
Propriétaire
  • BEIJING SUPERSTRING ACADEMY OF MEMORY TECHNOLOGY (Chine)
  • INSTITUTE OF MICROELECTRONICS, CHINESE ACADEMY OF SCIENCES (Chine)
Inventeur(s)
  • Huang, Weixing
  • Zhu, Huilong

Abrégé

A semiconductor device, including a substrate, a first electrode layer, a functional layer, and a second electrode layer. The functional layer is located between the first electrode layer and the second electrode layer, and includes a first region and a second region having a C-shaped structure surrounding the first region. The C-shape structure opens toward a direction that is parallel with the substrate and away from the first region, that is, the C-shaped structure opens toward a distal side. The first region is made of at least germanium, and the second region includes a C-shaped ferroelectric layer and a C-shaped gate that are sequentially stacked. In embodiments of the present disclosure, the C-shaped ferroelectric layer serves as a memory layer of the memory device. A C-shaped channel is capable to increase an electric field within the ferroelectric layer under a fixed gate voltage, so as to increase a memory window of the semiconductor device. Moreover, the C-shaped channel is capable to reduce a gate voltage decreased under a fixed storage window of the whole semiconductor device, so as to reduce power consumption of the semiconductor device. Hence, a performance of the memory device is improved.

Classes IPC  ?

  • H10B 51/30 - Dispositifs de RAM ferro-électrique [FeRAM] comprenant des transistors ferro-électriques de mémoire caractérisés par la région noyau de mémoire

2.

VERTICAL MOSFET DEVICE, MANUFACTURING METHOD AND APPLICATION THEREOF

      
Numéro d'application 17770871
Statut En instance
Date de dépôt 2021-12-13
Date de la première publication 2024-05-02
Propriétaire
  • Beijing Superstring Academy of Memory Technology (Chine)
  • INSTITUTE OF MICROELECTRONICS, CHINESE ACADEMY OF SCIENCES (Chine)
Inventeur(s)
  • Chen, Zhuo
  • Zhu, Huilong

Abrégé

The present disclosure relates to a vertical MOSFET device, a manufacturing method and application thereof. The method includes: forming a first silicon layer, a first germanium-silicon layer, a second germanium-silicon layer, a third germanium-silicon layer and a second silicon layer that are vertically stacked from bottom to top on a substrate, where molar contents of germanium in the first germanium-silicon layer and the third germanium-silicon layer are both greater than the content of germanium in the second germanium-silicon layer; etching to form a nano stack structure; selectively etching the first germanium-silicon layer and the third germanium-silicon layer to form a first groove and a third groove; forming inner spacers of an extension region in the first groove and the third groove; selectively etching the second germanium-silicon layer to form a gate groove; forming a dummy gate in the gate groove; forming sources/drains; forming an active region with a shallow trench isolation layer; and removing the dummy gate to form a gate dielectric layer and a gate. The present disclosure can well control the size of channel, the size of inner spacers of the extension region, the size of the gates, and the like, and is applicable to either nanosheet or nanowire structures.

Classes IPC  ?

  • H01L 29/78 - Transistors à effet de champ l'effet de champ étant produit par une porte isolée
  • H01L 29/10 - Corps semi-conducteurs caractérisés par les formes, les dimensions relatives, ou les dispositions des régions semi-conductrices avec des régions semi-conductrices connectées à une électrode ne transportant pas le courant à redresser, amplifier ou commuter, cette électrode faisant partie d'un dispositif à semi-conducteur qui comporte trois électrodes ou plus
  • H01L 29/417 - Electrodes caractérisées par leur forme, leurs dimensions relatives ou leur disposition relative transportant le courant à redresser, à amplifier ou à commuter
  • H01L 29/66 - Types de dispositifs semi-conducteurs

3.

SOLID-STATE DRIVE AND LIMITED ACCESS CONTROL METHOD THEREFOR, AND ELECTRONIC DEVICE

      
Numéro d'application CN2023119454
Numéro de publication 2024/087939
Statut Délivré - en vigueur
Date de dépôt 2023-09-18
Date de publication 2024-05-02
Propriétaire INSTITUTE OF MICROELECTRONICS , CHINESE ACADEMY OF SCIENCES (Chine)
Inventeur(s)
  • Xie, Yuanlu
  • Xi, Kai
  • Ji, Lanlong
  • Xu, Xiaoxin
  • Hu, Hongyang
  • Lu, Nianduan
  • Dong, Danian

Abrégé

Disclosed are a solid-state drive and a limited access control method therefor, and an electronic device. The solid-state drive comprises: a master chip, a flash memory array and a limited access circuit. The master chip comprises: a host interface controller, a central processing unit and a flash memory controller. The limited access circuit comprises: a limit counter, a first logic gate circuit and a state machine. Initialization data of all storage units of the limit counter are "1", and the first logic gate circuit performs or calculates multi-bit counting data separately read from storage units of the limit counter and transmits an OR operation result to the state machine; the state machine writes a "0" value into the limit counter every time the state machine detects that a host accesses the flash memory array, and prohibits the host from accessing the flash memory array when it is detected that the OR operation result is "0". In this way, an upper limit can be set for the number of times the flash memory array can be accessed in the solid-state drive, thereby effectively improving the security of data in the solid-state drive.

Classes IPC  ?

  • G06F 21/79 - Protection de composants spécifiques internes ou périphériques, où la protection d'un composant mène à la protection de tout le calculateur pour assurer la sécurité du stockage de données dans les supports de stockage à semi-conducteurs, p.ex. les mémoires adressables directement
  • G06F 21/60 - Protection de données
  • G06F 21/44 - Authentification de programme ou de dispositif
  • G06M 1/272 - Caractéristiques d'ordre général pour représenter le résultat d'un comptage sous la forme de signaux électriques, p.ex. par lecture de marques sur un tambour de compteur utilisant des moyens photo-électriques

4.

SEMICONDUCTOR MEMORY CELL STRUCTURE, SEMICONDUCTOR MEMORY, PREPARATION METHOD AND APPLICATION THEREOF

      
Numéro d'application 17770856
Statut En instance
Date de dépôt 2021-12-09
Date de la première publication 2024-05-02
Propriétaire
  • Beijing Superstring Academy of Memory Technology (Chine)
  • INSTITUTE OF MICROELECTRONICS, CHINESE ACADEMY OF SCIENCES (Chine)
Inventeur(s)
  • Wang, Qi
  • Zhu, Huilong

Abrégé

The present invention relates to a semiconductor memory cell structure, a semiconductor memory as well as preparation method and application thereof. The semiconductor memory cell structure includes: a substrate; and a first transistor layer, an isolation layer and a second transistor layer. The first transistor layer includes a first stack structure formed by stacking a first source, a first channel, and a first drain from bottom to top; and a first gate located on a sidewall of the first stack structure. The second transistor layer includes: a second stack structure formed by stacking a second drain, a second channel, and a second source from bottom to top; and a second gate located on a sidewall of the second stack structure, at least a part of a sidewall of the second drain is in direct contact with the first gate. The present invention provides a 2T0C type DRAM cell with an improved structure, has the advantages of vertical stack integration, high integration level, low leakage current, short refresh time and the like, and is significantly superior to the existing 2T0C type DRAM.

Classes IPC  ?

  • H10B 12/00 - Mémoires dynamiques à accès aléatoire [DRAM]
  • H01L 29/66 - Types de dispositifs semi-conducteurs
  • H01L 29/786 - Transistors à couche mince

5.

VERTICAL GATE-ALL-AROUND TRANSISTOR STRUCTURE AND PREPARATION METHOD THEREFOR, AND VERTICAL GATE-ALL-AROUND CAPACITOR-LESS MEMORY STRUCTURE AND PREPARATION METHOD THEREFOR

      
Numéro d'application CN2022143242
Numéro de publication 2024/087380
Statut Délivré - en vigueur
Date de dépôt 2022-12-29
Date de publication 2024-05-02
Propriétaire
  • BEIJING SUPERSTRING ACADEMY OF MEMORY TECHNOLOGY (Chine)
  • INSTITUTE OF MICROELECTRONICS, CHINESE ACADEMY OF SCIENCES (Chine)
Inventeur(s)
  • Xu, Gaobo
  • Song, Zhiyu
  • Yan, Gangping
  • Yang, Shangbo
  • Yin, Huaxiang
  • Luo, Jun

Abrégé

The present invention relates to a vertical gate-all-around transistor structure and a preparation method therefor, and a vertical gate-all-around capacitor-less memory structure and a preparation method therefor. The capacitor-less memory structure comprises, from bottom to top: a base; an isolation layer; a read bit line layer; first columnar stacking structures, which are arranged on the upper surface of the read bit line layer, and are each formed by stacking a first channel layer, a read word line layer and a first hard mask layer; a first gate dielectric layer, which is arranged, in a surrounding manner, on side surfaces and upper surfaces of the first stacking structures and on the upper surface of the read bit line layer; a first gate layer, which covers a surface of the first gate dielectric layer; second columnar stacking structures, which are arranged on the upper surface of the first gate layer, and are each formed by sequentially stacking a second channel layer, a write bit line layer and a second hard mask layer from bottom to top; a second gate dielectric layer, which is arranged, in a surrounding manner, on side surfaces and upper surfaces of the second stacking structures and on the upper surface of the first gate layer; and a second gate layer. The present invention solves the problem of a low integration density caused by the horizontal arrangement of channels, and enhances the capability of a gate electrode to control a conductive channel.

Classes IPC  ?

  • H10B 12/00 - Mémoires dynamiques à accès aléatoire [DRAM]

6.

STORAGE DEVICE, METHOD FOR MANUFACTURING THE SAME, AND ELECTRONIC DEVICE INCLUDING STORAGE DEVICE

      
Numéro d'application 18548035
Statut En instance
Date de dépôt 2021-11-26
Date de la première publication 2024-04-25
Propriétaire
  • BEIJING SUPERSTRING ACADEMY OF MEMORY TECHNOLOGY (Chine)
  • INSTITUTE OF MICROELECTRONICS, CHINESE ACADEMY OF SCIENCES (Chine)
Inventeur(s)
  • Wang, Qi
  • Zhu, Huilong

Abrégé

A storage device is provided, including: a substrate; word lines extending in a first direction; bit lines extending in a second direction perpendicular to the first direction; and a storage unit including a plurality of storage units, each of which is electrically connected to a word line and a bit line. Each storage unit includes: an active region extending in a third direction inclined with the first direction; a vertical stack of a first source/drain layer, a channel layer and a second source/drain layer; and gate stacks between the first source/drain layer and the second source/drain layer, and on opposite sides of the channel layer in a fourth direction orthogonal to the third direction, to sandwich the channel layer. The word line corresponding to each storage unit extends across the storage unit in the first direction to be electrically connected to the gate stacks on opposite sides.

Classes IPC  ?

  • G11C 11/408 - Circuits d'adressage
  • G11C 11/4097 - Organisation de lignes de bits, p.ex. configuration de lignes de bits, lignes de bits repliées

7.

HARD MASK STRUCTURE FOR INTEGRATED CIRCUIT MANUFACTURING, AND METHOD FOR MANUFACTURING INTEGRATED CIRCUIT DEVICE

      
Numéro d'application CN2022127555
Numéro de publication 2024/082322
Statut Délivré - en vigueur
Date de dépôt 2022-10-26
Date de publication 2024-04-25
Propriétaire INSTITUTE OF MICROELECTRONICS, CHINESE ACADEMY OF SCIENCES (Chine)
Inventeur(s)
  • Yang, Tao
  • Li, Junjie
  • He, Xiaobin
  • Gao, Jianfeng
  • Wei, Yayi
  • Dai, Bowei
  • Wang, Wenwu

Abrégé

The present disclosure relates to the technical field of pattern transfer in a chip manufacturing process. Provided are a hard mask structure for integrated circuit manufacturing, and a method for manufacturing an integrated circuit device. The hard mask structure comprises a first hard mask layer and a second hard mask layer, which are stacked from top to bottom, wherein the first hard mask layer is used for forming a noble metal on the surface thereof and serves as a pattern transfer sacrificial layer, and the second hard mask layer serves as a protection layer and is used for etching the material of a pattern to be transferred; the first hard mask layer and the second hard mask layer are made of different materials, and can both tolerate the corrosion of a strong oxidizing chemical liquid which is used for removing the noble metal; and the second hard mask layer can tolerate the corrosion of a chemical liquid which is used for removing the first hard mask layer by means of wet etching, and a preset corrosion rate selection ratio of the second hard mask layer for the first hard mask layer is ensured. The present disclosure can avoid the killing of a device by means of noble metal ions, such that a noble metal thin film can be used for manufacturing large-scale integrated circuits.

Classes IPC  ?

  • H01L 21/027 - Fabrication de masques sur des corps semi-conducteurs pour traitement photolithographique ultérieur, non prévue dans le groupe ou

8.

THREE-DIMENSIONAL RESERVOIR BASED ON VOLATILE THREE-DIMENSIONAL MEMRISTOR AND MANUFACTURING METHOD THEREFOR

      
Numéro d'application 18277977
Statut En instance
Date de dépôt 2022-03-10
Date de la première publication 2024-04-18
Propriétaire INSTITUTE OF MICROELECTRONICS, CHINESE ACADEMY OF SCIENCES (Chine)
Inventeur(s)
  • Xu, Xiaoxin
  • Sun, Wenxuan
  • Yu, Jie
  • Zhang, Woyu
  • Dong, Danian
  • Lai, Jinru
  • Zheng, Xu
  • Shang, Dashan

Abrégé

A three-dimensional reservoir based on three-dimensional volatile memristors and a method for manufacturing the same. In the three-dimensional reservoir, a memory layer, a select layer, and an electrode layer in each via form a memristor which is a reservoir unit. The three-dimensional reservoir is formed based on a stacking structure and multiple vias. The three-dimensional reservoir is constructed by using virtual nodes generated from dynamic characteristics of the three-dimensional memristors. An interfacial memristor is first constructed, and its volatility is verified through electric tests. A vertical three-dimensional array is manufactured based on the volatile memristor. A dynamic characteristic of the memristor is adjusted through a Schottky barrier. Different layers in the three-dimensional reservoir correspond to different reservoirs, which are constructed by controlling memristors in the different layers, respectively.

Classes IPC  ?

  • H10N 70/20 - Dispositifs de commutation multistables, p.ex. memristors
  • H10B 63/00 - Dispositifs de mémoire par changement de résistance, p.ex. dispositifs RAM résistifs [ReRAM]
  • H10N 70/00 - Dispositifs à l’état solide sans barrière de potentiel ni de surface, spécialement adaptés au redressement, à l'amplification, à la production d'oscillations ou à la commutation

9.

STORAGE DEVICE, METHOD FOR MANUFACTURING THE SAME, AND ELECTRONIC APPARATUS INCLUDING STORAGE DEVICE

      
Numéro d'application 18262193
Statut En instance
Date de dépôt 2021-11-26
Date de la première publication 2024-04-11
Propriétaire
  • BEIJING SUPERSTRING ACADEMY OF MEMORY TECHNOLOGY (Chine)
  • INSTITUTE OF MICROELECTRONICS, CHINESE ACADEMY OF SCIENCES (Chine)
Inventeur(s)
  • Zhu, Huilong
  • Wang, Qi

Abrégé

A storage device includes a substrate, a storage unit array, and word lines extending in the first direction. The storage unit array includes storage units arranged along a first direction and a second direction. Each storage unit includes: an active region extending in a third direction and including a vertical stack of first source/drain, channel and second source/drain layers, and a gate stack between the first and second source/drain layers in a vertical direction and sandwiching the channel layer from at least two opposite sides. First source/drain layers of each column are continuous to form a bit line extending in the second direction in a zigzag shape. Each word line extends in the first direction to intersect the active regions of a respective row, and is electrically connected to the gate stack of each storage unit on two opposite sides of the channel layer.

Classes IPC  ?

  • H01L 29/08 - Corps semi-conducteurs caractérisés par les formes, les dimensions relatives, ou les dispositions des régions semi-conductrices avec des régions semi-conductrices connectées à une électrode transportant le courant à redresser, amplifier ou commuter, cette électrode faisant partie d'un dispositif à semi-conducteur qui comporte trois électrodes ou plus
  • H01L 29/04 - Corps semi-conducteurs caractérisés par leur structure cristalline, p.ex. polycristalline, cubique ou à orientation particulière des plans cristallins
  • H01L 29/06 - Corps semi-conducteurs caractérisés par les formes, les dimensions relatives, ou les dispositions des régions semi-conductrices
  • H01L 29/423 - Electrodes caractérisées par leur forme, leurs dimensions relatives ou leur disposition relative ne transportant pas le courant à redresser, à amplifier ou à commuter
  • H01L 29/66 - Types de dispositifs semi-conducteurs
  • H01L 29/775 - Transistors à effet de champ avec un canal à gaz de porteurs de charge à une dimension, p.ex. FET à fil quantique
  • H01L 29/786 - Transistors à couche mince
  • H10B 12/00 - Mémoires dynamiques à accès aléatoire [DRAM]

10.

ACTIVATION FUNCTION GENERATOR BASED ON MAGNETIC DOMAIN WALL DRIVEN MAGNETIC TUNNEL JUNCTION AND MANUFACTURING METHOD

      
Numéro d'application 18264903
Statut En instance
Date de dépôt 2021-03-19
Date de la première publication 2024-04-11
Propriétaire INSTITUTE OF MICROELECTRONICS, CHINESE ACADEMY OF SCIENCES (Chine)
Inventeur(s)
  • Xing, Guozhong
  • Liu, Long
  • Wang, Di
  • Lin, Huai
  • Wang, Yan
  • Xu, Xiaoxin
  • Liu, Ming

Abrégé

An activation function generator based on a magnetic domain wall driven magnetic tunnel junction and a method for manufacturing the same are provided, including: a spin orbit coupling layer configured to generate a spin orbit torque; a ferromagnetic free layer formed on the spin orbit coupling layer and configured to provide a magnetic domain wall motion racetrack; a nonmagnetic barrier layer formed on the ferromagnetic free layer; a ferromagnetic reference layer formed on the nonmagnetic barrier layer; a top electrode formed on the ferromagnetic reference layer; antiferromagnetic pinning layers formed on two ends of the ferromagnetic free layer; a left electrode and a right electrode respectively formed at two positions on the antiferromagnetic pinning layers.

Classes IPC  ?

  • H10N 50/20 - Dispositifs à courant commandé à polarisation de spin
  • G06N 3/063 - Réalisation physique, c. à d. mise en œuvre matérielle de réseaux neuronaux, de neurones ou de parties de neurone utilisant des moyens électroniques
  • H10B 61/00 - Dispositifs de mémoire magnétique, p.ex. dispositifs RAM magnéto-résistifs [MRAM]
  • H10N 50/01 - Fabrication ou traitement
  • H10N 50/80 - Dispositifs galvanomagnétiques - Détails de structure
  • H10N 50/85 - Matériaux actifs magnétiques

11.

MEMORY DEVICE AND METHOD OF MANUFACTURING MEMORY DEVICE

      
Numéro d'application 18256669
Statut En instance
Date de dépôt 2021-12-14
Date de la première publication 2024-04-04
Propriétaire
  • Beijing Superstring Academy of Memory Technology (Chine)
  • INSTITUTE OF MICROELECTRONICS, CHINESE ACADEMY OF SCIENCES (Chine)
Inventeur(s)
  • Liu, Ziyi
  • Zhu, Huilong

Abrégé

A memory device includes a memory unit array on substrate, the memory unit array includes a plurality of memory units, each memory unit includes: a left and a right stack arranged at intervals in a horizontal direction. The left stack and right stacks each include a lower isolation layer, PMOS layer, first NMOS layer, upper isolation layer and second NMOS layer stacked on the substrate sequentially. The PMOS layer, and the first and second NMOS layer each include first source/drain layer, channel layer and second source/drain layer vertically stacked. The channel layer is laterally recessed relative to the first and second source/drain layers; and a gate stack between the first and second source/drain layers in the vertical direction, and disposed on opposite sides of the channel layer and embedded into a lateral recess of the channel layer.

Classes IPC  ?

  • H10B 10/00 - Mémoires statiques à accès aléatoire [SRAM]

12.

SEMICONDUCTOR DEVICE WITH SPACER AND C-SHAPED CHANNEL PORTION, METHOD OF MANUFACTURING SEMICONDUCTOR DEVICE WITH SPACER AND C-SHAPED CHANNEL PORTION, AND ELECTRONIC APPARATUS

      
Numéro d'application 18343634
Statut En instance
Date de dépôt 2023-06-28
Date de la première publication 2024-03-21
Propriétaire INSTITUTE OF MICROELECTRONICS, CHINESE ACADEMY OF SCIENCES (Chine)
Inventeur(s) Zhu, Huilong

Abrégé

Disclosed are a semiconductor device with a spacer and a C-shaped channel portion, a method of manufacturing the same, and an electronic apparatus including the semiconductor device. The semiconductor device may include: a channel portion on a substrate, wherein the channel portion includes a curved nanosheet or nanowire with a C-shaped cross-section; a first source/drain portion and a second source/drain portion respectively located at upper and lower ends of the channel portion with respect to the substrate; a first gate stack and a second gate stack located on opposite sides of the channel portion; a first spacer located between the first gate stack and the first source/drain portion and between the first gate stack and the second source/drain portion respectively; and a second spacer located between the second gate stack and the first source/drain portion and between the second gate stack and the second source/drain portion respectively.

Classes IPC  ?

  • H01L 21/8238 - Transistors à effet de champ complémentaires, p.ex. CMOS
  • H01L 29/06 - Corps semi-conducteurs caractérisés par les formes, les dimensions relatives, ou les dispositions des régions semi-conductrices
  • H01L 29/423 - Electrodes caractérisées par leur forme, leurs dimensions relatives ou leur disposition relative ne transportant pas le courant à redresser, à amplifier ou à commuter
  • H01L 29/66 - Types de dispositifs semi-conducteurs
  • H01L 29/775 - Transistors à effet de champ avec un canal à gaz de porteurs de charge à une dimension, p.ex. FET à fil quantique

13.

MULTI-RESISTANCE-STATE SPINTRONIC DEVICE, READ-WRITE CIRCUIT, AND IN-MEMORY BOOLEAN LOGIC OPERATOR

      
Numéro d'application 18259747
Statut En instance
Date de dépôt 2020-12-30
Date de la première publication 2024-03-14
Propriétaire INSTITUTE OF MICROELECTRONICS, CHINESE ACADEMY OF SCIENCES (Chine)
Inventeur(s)
  • Xing, Guozhong
  • Lin, Huai
  • Zhang, Feng
  • Wang, Di
  • Liu, Long
  • Xie, Changqing
  • Li, Ling
  • Liu, Ming

Abrégé

A multi-resistance-state spintronic device, including: a top electrode and a bottom electrode respectively connected to a read-write circuit; and a magnetic tunnel junction between two electrodes. The magnetic tunnel junction includes from top to bottom: a ferromagnetic reference layer, a barrier tunneling layer, a ferromagnetic free layer, and a spin-orbit coupling layer. Nucleation centers are provided at two ends of the ferromagnetic free layer to generate a magnetic domain wall; the spin-orbit coupling layer is connected to the bottom electrode, and when a write pulse is applied, an electron spin current is generated and drives the magnetic domain wall through a spin-orbit torque to move; a plurality of local magnetic domain wall pinning centers are provided at an interface between the spin-orbit coupling layer and the ferromagnetic free layer to enhance a strength of a DM interaction constant between interfaces.

Classes IPC  ?

  • G11C 11/16 - Mémoires numériques caractérisées par l'utilisation d'éléments d'emmagasinage électriques ou magnétiques particuliers; Eléments d'emmagasinage correspondants utilisant des éléments magnétiques utilisant des éléments dans lesquels l'effet d'emmagasinage est basé sur l'effet de spin
  • H03K 19/21 - Circuits OU EXCLUSIF, c. à d. donnant un signal de sortie si un signal n'existe qu'à une seule entrée; Circuits à COÏNCIDENCES, c. à d. ne donnant un signal de sortie que si tous les signaux d'entrée sont identiques
  • H10B 61/00 - Dispositifs de mémoire magnétique, p.ex. dispositifs RAM magnéto-résistifs [MRAM]
  • H10N 50/20 - Dispositifs à courant commandé à polarisation de spin
  • H10N 50/80 - Dispositifs galvanomagnétiques - Détails de structure
  • H10N 50/85 - Matériaux actifs magnétiques

14.

SPIN ELECTRONIC DEVICE, ARRAY CIRCUIT, AND OPTIMIZATION METHOD FOR RECURRENT NEURAL NETWORK

      
Numéro d'application CN2022117035
Numéro de publication 2024/050661
Statut Délivré - en vigueur
Date de dépôt 2022-09-05
Date de publication 2024-03-14
Propriétaire INSTITUTE OF MICROELECTRONICS, CHINESE ACADEMY OF SCIENCES (Chine)
Inventeur(s)
  • Xing, Guozhong
  • Lin, Huai
  • Liu, Ming

Abrégé

A spin electronic device (100), an array circuit, and an optimization method for a recurrent neural network. The spin electronic device (100) comprises: a magnetic domain device (110) having a preset thickness, wherein the magnetic domain device (110) can form a labyrinth-like magnetic domain structure under the modulation of Dzyaloshinskii-Moriya interaction and dipole-dipole interaction, the labyrinth-like magnetic domain structure comprising a plurality of magnetic domain areas having random magnetic domain directions, and the junction of two adjacent magnetic domain areas being a magnetic domain wall; at least one cycle of heterogeneous thin film (120), which is arranged on a first surface of the magnetic domain device (110); and at least four electrodes (130), which are arranged on a second surface of the magnetic domain device (110), wherein the four electrodes (130) are respectively connected to different magnetic domain areas.

Classes IPC  ?

15.

METHOD FOR CORRECTING LITHOGRAPHY PATTERN OF SURFACE PLASMA

      
Numéro d'application 18262035
Statut En instance
Date de dépôt 2021-11-02
Date de la première publication 2024-03-07
Propriétaire INSTITUTE OF MICROELECTRONICS, CHINESE ACADEMY OF SCIENCES (Chine)
Inventeur(s)
  • Ma, Le
  • Wei, Yayi
  • Zhang, Libin
  • He, Jianfang

Abrégé

Provided is a method for correcting a lithography pattern of a surface plasma, including: forming a plurality of test patterns on a test mask; exposing a photoresist layer by using the test mask containing the test patterns to form a plurality of photoresist patterns; establishing a first data table based on a correspondence between the first test parameter and the second test parameter of the test pattern and the first exposure parameter and the second exposure parameter of the photoresist pattern; processing the first data table according to the first exposure parameter to obtain a second data table; and respectively correcting second test parameters of a plurality of design patterns according to the second data table to obtain corrected design patterns, and manufacturing a mask for exposure by using the corrected design patterns.

Classes IPC  ?

  • G03F 1/44 - Aspects liés au test ou à la mesure, p.ex. motifs de grille, contrôleurs de focus, échelles en dents de scie ou échelles à encoches
  • G03F 1/72 - Réparation ou correction des défauts dans un masque
  • G03F 7/20 - Exposition; Appareillages à cet effet

16.

LAMINATED STRUCTURE AND PREPARATION METHOD THEREFOR, PATTERN TRANSFER METHOD, AND REWORKING METHOD

      
Numéro d'application CN2022124813
Numéro de publication 2024/045270
Statut Délivré - en vigueur
Date de dépôt 2022-10-12
Date de publication 2024-03-07
Propriétaire INSTITUTE OF MICROELECTRONICS, CHINESE ACADEMY OF SCIENCES (Chine)
Inventeur(s)
  • He, Xiaobin
  • Li, Tingting
  • Yang, Tao
  • Liu, Jinbiao
  • Li, Junfeng
  • Luo, Jun

Abrégé

A laminated structure and a preparation method therefor, a pattern transfer method, and a reworking method. A stripping layer (100) capable of being etched and removed by means of a wetting method is arranged below a bottom anti-reflection structure (200), so that pattern transfer can be realized, and when reworking is needed, a substrate can be separated by removing the stripping layer (100) by means of the wetting method, so that the reworking difficulty is greatly reduced, and the substrate is not damaged, thereby avoiding the formation of defects.

Classes IPC  ?

  • H01L 21/027 - Fabrication de masques sur des corps semi-conducteurs pour traitement photolithographique ultérieur, non prévue dans le groupe ou
  • G03F 7/09 - Matériaux photosensibles - caractérisés par des détails de structure, p.ex. supports, couches auxiliaires
  • G03F 7/11 - Matériaux photosensibles - caractérisés par des détails de structure, p.ex. supports, couches auxiliaires avec des couches de recouvrement ou des couches intermédiaires, p.ex. couches d'ancrage

17.

MEMORY DEVICE AND METHOD OF MANUFACTURING THE SAME, AND ELECTRONIC APPARATUS INCLUDING MEMORY DEVICE

      
Numéro d'application 18175907
Statut En instance
Date de dépôt 2023-02-28
Date de la première publication 2024-02-29
Propriétaire INSTITUTE OF MICROELECTRONICS, CHINESE ACADEMY OF SCIENCES (Chine)
Inventeur(s) Zhu, Huilong

Abrégé

A memory device, a method of manufacturing the same, and an electronic apparatus including the same. The memory device includes: a plurality of cell active layers vertically stacked on a substrate, each cell active layer including a lower source/drain region and an upper source/drain region located at different vertical heights and a channel region between the lower source/drain region and the upper source/drain region; a gate stack on the substrate and extending vertically relative to the substrate to pass through the cell active layers, the gate stack including a gate conductor layer and a memory functional layer arranged between the gate conductor layer and the cell active layers, and a memory cell being defined at an intersection of the gate stack and each cell active layer; and a conductive metal layer arranged on a lower surface of each cell active layer and/or an upper surface of each cell active layer.

Classes IPC  ?

  • H10B 43/27 - Dispositifs EEPROM avec des isolants de grille à piégeage de charge caractérisés par les agencements tridimensionnels, p ex. avec des cellules à des niveaux différents de hauteur la région de source et la région de drain étant à différents niveaux, p.ex. avec des canaux inclinés les canaux comprenant des parties verticales, p.ex. des canaux en forme de U
  • H10B 51/20 - Dispositifs de RAM ferro-électrique [FeRAM] comprenant des transistors ferro-électriques de mémoire caractérisés par les agencements tridimensionnels, p ex. avec des cellules à des niveaux différents de hauteur

18.

GATE-ALL-AROUND/MULTI-GATE SEMICONDUCTOR DEVICE WITH BODY CONTACT, METHOD OF MANUFACTURING GATE-ALL-AROUND/MULTI-GATE SEMICONDUCTOR DEVICE WITH BODY CONTACT, AND ELECTRONIC APPARATUS

      
Numéro d'application 18232513
Statut En instance
Date de dépôt 2023-08-10
Date de la première publication 2024-02-29
Propriétaire INSTITUTE OF MICROELECTRONICS, CHINESE ACADEMY OF SCIENCES (Chine)
Inventeur(s) Zhu, Huilong

Abrégé

Provided are a vertical semiconductor device with a body contact, a manufacturing method, and an electronic apparatus. The semiconductor device includes: an active region vertically disposed on a substrate relative to the substrate, including lower and upper source/drain regions, and a middle portion between the lower and upper source/drain regions for defining a channel region; first and second gate stacks which are disposed on first and second sides of the active region which are opposite to each other in a lateral direction relative to the substrate; and a body contact layer disposed on the second side of the active region to overlap a part of the middle portion of the active region, so as to apply a body bias to the active region, wherein the second gate stack includes first and second portions below and above the body contact layer respectively.

Classes IPC  ?

  • H01L 29/417 - Electrodes caractérisées par leur forme, leurs dimensions relatives ou leur disposition relative transportant le courant à redresser, à amplifier ou à commuter
  • H01L 21/8234 - Technologie MIS
  • H01L 27/088 - Dispositifs consistant en une pluralité de composants semi-conducteurs ou d'autres composants à l'état solide formés dans ou sur un substrat commun comprenant des éléments de circuit passif intégrés avec au moins une barrière de potentiel ou une barrière de surface le substrat étant un corps semi-conducteur comprenant uniquement des composants semi-conducteurs d'un seul type comprenant uniquement des composants à effet de champ les composants étant des transistors à effet de champ à porte isolée
  • H01L 29/06 - Corps semi-conducteurs caractérisés par les formes, les dimensions relatives, ou les dispositions des régions semi-conductrices
  • H01L 29/423 - Electrodes caractérisées par leur forme, leurs dimensions relatives ou leur disposition relative ne transportant pas le courant à redresser, à amplifier ou à commuter
  • H01L 29/66 - Types de dispositifs semi-conducteurs
  • H01L 29/775 - Transistors à effet de champ avec un canal à gaz de porteurs de charge à une dimension, p.ex. FET à fil quantique
  • H01L 29/786 - Transistors à couche mince

19.

VERTICAL SEMICONDUCTOR DEVICE WITH BODY CONTACT, METHOD OF MANUFACTURING VERTICAL SEMICONDUCTOR DEVICE WITH BODY CONTACT, AND ELECTRONIC APPARATUS

      
Numéro d'application 18236788
Statut En instance
Date de dépôt 2023-08-22
Date de la première publication 2024-02-29
Propriétaire INSTITUTE OF MICROELECTRONICS, CHINESE ACADEMY OF SCIENCES (Chine)
Inventeur(s) Zhu, Huilong

Abrégé

Disclosed are a vertical semiconductor device with a body contact, a manufacturing method, and an electronic apparatus. The semiconductor device includes: an active region vertically disposed on a substrate, including lower and upper source/drain regions, and a middle portion between lower and upper source/drain regions for defining a channel region; a gate stack on a first side of the active region in a lateral direction to at least overlap with the middle portion; and a body contact layer on a second side of the active region opposite to the first side in the lateral direction to overlap with the middle portion to apply a body bias to the active region. In a vertical direction, distances between a part of the middle portion overlapping with the body contact layer and the lower source/drain region and between the part and the upper source/drain region are first and second spacing distances, respectively.

Classes IPC  ?

20.

SPIN-WAVE-UNIT-BASED IN-MEMORY COMPUTING ARRAY STRUCTURE AND CONTROL METHOD THEREFOR

      
Numéro d'application CN2022124222
Numéro de publication 2024/040699
Statut Délivré - en vigueur
Date de dépôt 2022-10-09
Date de publication 2024-02-29
Propriétaire INSTITUTE OF MICROELECTRONICS, CHINESE ACADEMY OF SCIENCES (Chine)
Inventeur(s)
  • Xing, Guozhong
  • Zhao, Xuefeng
  • Liu, Ming

Abrégé

Disclosed in the present application are a spin-wave-unit-based in-memory computing array structure and a control method therefor, which relate to the field of integrated circuits. The spin-wave-unit-based in-memory computing array structure comprises a plurality of in-memory computing units which are connected to one another, each in-memory computing unit comprising a spin wave unit and a transistor unit connected to the spin wave unit. Each spin wave unit comprises: a spin wave body, the spin wave body comprising a spin wave signal generation end and a spin wave signal detection end which are oppositely arranged; a first magnetic domain wall driving unit and a second magnetic domain wall driving unit which are respectively arranged on two adjacent sides of the spin wave body away from one side of the spin wave signal generation end and from one side of the spin wave signal detection end; and a magnetic domain wall in the spin wave body. The weighting in Hopfield neutral network computing reaches a preset weighting. Due to the occurrence of scattering and reflection of spin waves during a propagation process and the presence of fluctuations during magnetization of the magnetic domain walls themselves, the reliability and stability of spin electronic devices and in-memory computing are improved.

Classes IPC  ?

  • G11C 11/16 - Mémoires numériques caractérisées par l'utilisation d'éléments d'emmagasinage électriques ou magnétiques particuliers; Eléments d'emmagasinage correspondants utilisant des éléments magnétiques utilisant des éléments dans lesquels l'effet d'emmagasinage est basé sur l'effet de spin
  • G06N 3/04 - Architecture, p.ex. topologie d'interconnexion
  • G06N 3/063 - Réalisation physique, c. à d. mise en œuvre matérielle de réseaux neuronaux, de neurones ou de parties de neurone utilisant des moyens électroniques

21.

RESERVOIR COMPUTING NETWORK OPTIMIZATION METHOD AND RELATED APPARATUS

      
Numéro d'application CN2022124762
Numéro de publication 2024/040714
Statut Délivré - en vigueur
Date de dépôt 2022-10-12
Date de publication 2024-02-29
Propriétaire INSTITUTE OF MICROELECTRONICS, CHINESE ACADEMY OF SCIENCES (Chine)
Inventeur(s)
  • Xu, Xiaoxin
  • Sun, Wenxuan
  • Zhang, Woyu
  • Yu, Jie
  • Li, Yi
  • Shang, Dashan
  • Lai, Jinru
  • Dong, Danian

Abrégé

Disclosed in the present application are a reservoir computing network optimization method and a related apparatus. The method comprises: sampling an input signal to obtain a sampling signal; performing quantization processing on the sampling signal by means of at least two kinds of quantization modes, so as to obtain at least two kinds of digital signals, values of elements in different digital signals being different; inputting voltage pulses corresponding to the elements in the different digital signals into reservoirs constructed by different quantities of virtual nodes, so as to extract signal features of the input signal in different quantization modes by the different reservoirs. By quantizing signals in different modes and inputting same into reservoirs constructed by different quantities of virtual nodes, the richness of internal states of the reservoirs can be improved, thereby further improving the signal identification accuracy of a reservoir system.

Classes IPC  ?

  • H04L 41/0823 - Réglages de configuration caractérisés par les objectifs d’un changement de paramètres, p.ex. l’optimisation de la configuration pour améliorer la fiabilité
  • H04L 43/024 - Capture des données de surveillance par échantillonnage par échantillonnage adaptatif

22.

THREE-STATE SPINTRONIC DEVICE, MEMORY CELL, MEMORY ARRAY AND READ-WRITE CIRCUIT

      
Numéro d'application 18261716
Statut En instance
Date de dépôt 2021-01-21
Date de la première publication 2024-02-29
Propriétaire INSTITUTE OF MICROELECTRONICS, CHINESE ACADEMY OF SCIENCES (Chine)
Inventeur(s)
  • Lin, Huai
  • Xing, Guozhong
  • Wu, Zuheng
  • Liu, Long
  • Wang, Di
  • Lu, Cheng
  • Zhang, Peiwen
  • Xie, Changqing
  • Li, Ling
  • Liu, Ming

Abrégé

The three-state spintronic device includes: a bottom electrode, a magnetic tunnel junction and a top electrode from bottom to top. The magnetic tunnel junction includes: a spin-orbit coupling layer, a ferromagnetic free layer, a barrier tunneling layer, a ferromagnetic reference layer, three local magnetic domain wall pinning centers and domain wall nucleation centers. An antisymmetric exchange interaction is modulated, and the magnetic domain wall pinning centers are embedded in an interface between a heavy metal and the ferromagnetic free layer. The magnetic domain wall nucleation centers are at two ends of the ferromagnetic free layer. A current pulse flows through the spin-orbit coupling layer to generate a spin current and the spin current is injected into the ferromagnetic free layer. Under a control of all-electrical controlled, an effective field of a spin-orbit torque drives domain wall to move and displace.

Classes IPC  ?

  • G11C 11/16 - Mémoires numériques caractérisées par l'utilisation d'éléments d'emmagasinage électriques ou magnétiques particuliers; Eléments d'emmagasinage correspondants utilisant des éléments magnétiques utilisant des éléments dans lesquels l'effet d'emmagasinage est basé sur l'effet de spin

23.

METHOD FOR MANUFACTURING SEMICONDUCTOR DEVICE

      
Numéro d'application 17630674
Statut En instance
Date de dépôt 2021-11-12
Date de la première publication 2024-02-15
Propriétaire INSTITUTE OF MICROELECTRONICS, CHINESE ACADEMY OF SCIENCES (Chine)
Inventeur(s)
  • Zhang, Libin
  • Wei, Yayi
  • Song, Zhen
  • Su, Yajuan
  • He, Jianfang
  • Ma, Le

Abrégé

A method for manufacturing a semiconductor device. A photolithographic coating, including a first film, a photolithographic film, and a second film, is formed on the to-be-connected structure. Refractive indexes of the first film and the second film are smaller than 1, so that the photolithographic coating forms an optical structure with a high reflection coefficient. The photolithographic coating is exposed to a light having a target wavelength through a mask. The to-be-connected structure is reflected in the photolithographic coating, and hence serves as another mask and is imaged to the photolithographic film. A pattern of the mask is simultaneously imaged to the photolithographic film. That is, both the to-be-connected structure and the pattern of the mask are imaged to a target region of the photolithographic film, and the target region corresponds to the to-be-connected structure.

Classes IPC  ?

  • H01L 21/027 - Fabrication de masques sur des corps semi-conducteurs pour traitement photolithographique ultérieur, non prévue dans le groupe ou
  • H01L 21/311 - Gravure des couches isolantes
  • H01L 21/768 - Fixation d'interconnexions servant à conduire le courant entre des composants distincts à l'intérieur du dispositif

24.

METHOD FOR MANUFACTURING SEMICONDUCTOR DEVICE

      
Numéro d'application 17631932
Statut En instance
Date de dépôt 2021-11-12
Date de la première publication 2024-02-01
Propriétaire INSTITUTE OF MICROELECTRONICS, CHINESE ACADEMY OF SCIENCES (Chine)
Inventeur(s)
  • Zhang, Libin
  • Wei, Yayi
  • Song, Zhen

Abrégé

A method for manufacturing a semiconductor device. A photolithographic coating, including a first film, a photolithographic film, and a second film, is formed on the to-be-connected structure. Refractive indexes of the first film and the second film are smaller than 1. The photolithographic coating is exposed to a light having a first wavelength, to image the to-be-connected structure to a first region of the photolithographic film. The photolithographic coating is exposed to a light having a second wavelength through a mask, to image the mask to a second region of the photolithographic film. A region in which the first region and the second region overlap serves as a connection region corresponding to the to-be-connected structure, and thereby self-alignment between a layer of the to-be-connected structure and a layer where a contact hole is arranged is implemented.

Classes IPC  ?

  • H01L 21/768 - Fixation d'interconnexions servant à conduire le courant entre des composants distincts à l'intérieur du dispositif
  • H01L 29/40 - Electrodes

25.

READ-WRITE METHOD AND APPARATUS FOR LEPS SOFT DECODING ESTIMATION, AND ELECTRONIC DEVICE

      
Numéro d'application 18254377
Statut En instance
Date de dépôt 2020-11-25
Date de la première publication 2024-02-01
Propriétaire INSTITUTE OF MICROELECTRONICS, CHINESE ACADEMY OF SCIENCES (Chine)
Inventeur(s)
  • Wang, Qi
  • Jiang, Yiyang
  • Li, Qianhui
  • Huo, Zongliang
  • Ye, Tianchun

Abrégé

A read-write method includes: sequentially writing, in a first direction, a code word obtained by information-bit encoding into a target memory cell in each layer of memory cell array in the three-dimensional memory; randomly reading the target memory cell in each layer of memory cell array, or sequentially reading the target memory cell in each layer of memory cell array in a second direction; and determining an LLR value of a current target memory cell according to a storage time corresponding to the current target memory cell when reading, a threshold voltage partition corresponding to the current target memory cell when reading, a comprehensive distribution state corresponding to the current target memory cell when reading, and a pre-established LLR table, so as to perform a soft decoding operation on the code word in the current target memory cell based on the LLR value of the current target memory cell.

Classes IPC  ?

  • G11C 29/42 - Dispositifs de vérification de réponse utilisant des codes correcteurs d'erreurs [ECC] ou un contrôle de parité
  • G11C 29/46 - Logique de déclenchement de test
  • G11C 29/12 - Dispositions intégrées pour les tests, p.ex. auto-test intégré [BIST]

26.

DEVICE HAVING FERROELECTRIC OR NEGATIVE CAPACITANCE MATERIAL AND METHOD OF MANUFACTURING THE SAME, AND ELECTRONIC APPARATUS

      
Numéro d'application 18025030
Statut En instance
Date de dépôt 2021-03-24
Date de la première publication 2024-01-25
Propriétaire INSTITUTE OF MICROELECTRONICS, CHINESE ACADEMY OF SCIENCES (Chine)
Inventeur(s)
  • Zhu, Huilong
  • Huang, Weixing

Abrégé

A nanowire/nanosheet device having a ferroelectric or negative capacitance material and a method of manufacturing the same, and an electronic apparatus including the nanowire/nanosheet device are provided. According to embodiments, the semiconductor device may include: a substrate; a nanowire/nanosheet on the substrate and spaced apart from a surface of the substrate; a gate electrode surrounding the nanowire/nanosheet; a ferroelectric or negative capacitance material layer formed on a sidewall of the gate electrode; and source/drain layers at opposite ends of the nanowire/nanosheet and adjoining the nanowire/nanosheet.

Classes IPC  ?

  • H01L 29/66 - Types de dispositifs semi-conducteurs
  • H01L 29/06 - Corps semi-conducteurs caractérisés par les formes, les dimensions relatives, ou les dispositions des régions semi-conductrices
  • H01L 29/786 - Transistors à couche mince
  • H01L 29/775 - Transistors à effet de champ avec un canal à gaz de porteurs de charge à une dimension, p.ex. FET à fil quantique
  • H01L 29/423 - Electrodes caractérisées par leur forme, leurs dimensions relatives ou leur disposition relative ne transportant pas le courant à redresser, à amplifier ou à commuter
  • H01L 27/088 - Dispositifs consistant en une pluralité de composants semi-conducteurs ou d'autres composants à l'état solide formés dans ou sur un substrat commun comprenant des éléments de circuit passif intégrés avec au moins une barrière de potentiel ou une barrière de surface le substrat étant un corps semi-conducteur comprenant uniquement des composants semi-conducteurs d'un seul type comprenant uniquement des composants à effet de champ les composants étant des transistors à effet de champ à porte isolée
  • H01L 21/8234 - Technologie MIS
  • H01L 29/51 - Matériaux isolants associés à ces électrodes

27.

NOR-TYPE MEMORY DEVICE, METHOD OF MANUFACTURING NOR-TYPE MEMORY DEVICE, AND ELECTRONIC APPARATUS INCLUDING MEMORY DEVICE

      
Numéro d'application 18043324
Statut En instance
Date de dépôt 2022-02-22
Date de la première publication 2024-01-25
Propriétaire INSTITUTE OF MICROELECTRONICS, CHINESE ACADEMY OF SCIENCES (Chine)
Inventeur(s) Zhu, Huilong

Abrégé

Disclosed are a NOR-type memory device, a method of manufacturing the NOR-type memory device, and an electronic apparatus including the NOR-type memory device. According to an embodiment, the NOR-type memory device may include: a plurality of device layers disposed on a substrate, wherein each of the plurality of device layers includes a stack of a first source/drain layer, a first channel layer, and a second source/drain layer; and a gate stack that extends vertically with respect to the substrate to pass through the stack in the each of the plurality of device layers, wherein the gate stack includes a gate conductor layer and a memory functional layer disposed between the gate conductor layer and the stack, and a memory cell is defined at an intersection of the gate stack and the stack.

Classes IPC  ?

  • H10B 51/20 - Dispositifs de RAM ferro-électrique [FeRAM] comprenant des transistors ferro-électriques de mémoire caractérisés par les agencements tridimensionnels, p ex. avec des cellules à des niveaux différents de hauteur
  • H10B 43/10 - Dispositifs EEPROM avec des isolants de grille à piégeage de charge caractérisés par la configuration vue du dessus
  • H10B 51/10 - Dispositifs de RAM ferro-électrique [FeRAM] comprenant des transistors ferro-électriques de mémoire caractérisés par la configuration vue du dessus
  • H10B 43/27 - Dispositifs EEPROM avec des isolants de grille à piégeage de charge caractérisés par les agencements tridimensionnels, p ex. avec des cellules à des niveaux différents de hauteur la région de source et la région de drain étant à différents niveaux, p.ex. avec des canaux inclinés les canaux comprenant des parties verticales, p.ex. des canaux en forme de U

28.

RESISTIVE RANDOM ACCESS MEMORY AND METHOD OF PREPARING THE SAME

      
Numéro d'application 18254981
Statut En instance
Date de dépôt 2020-12-14
Date de la première publication 2024-01-18
Propriétaire INSTITUTE OF MICROELECTRONICS, CHINESE ACADEMY OF SCIENCES (Chine)
Inventeur(s)
  • Xu, Xiaoxin
  • Li, Xiaoyan
  • Dong, Danian
  • Yu, Jie
  • Lv, Hangbing

Abrégé

The present disclosure provides a resistive random access memory and a method of preparing the same. The resistive random access memory includes: a resistive layer, an upper electrode and a barrier structure. The resistive layer is arranged on a substrate; the upper electrode is arranged on the resistive layer; and the barrier structure is arranged between the resistive layer and the upper electrode, and the barrier structure is configured for electrons to pass through a conduction band of the barrier structure when a device performs an erasing operation, so as to avoid forming of a defect in the resistive layer and causing a reverse breakdown of the resistive layer.

Classes IPC  ?

  • H10N 70/00 - Dispositifs à l’état solide sans barrière de potentiel ni de surface, spécialement adaptés au redressement, à l'amplification, à la production d'oscillations ou à la commutation
  • G11C 13/00 - Mémoires numériques caractérisées par l'utilisation d'éléments d'emmagasinage non couverts par les groupes , ou

29.

SEMICONDUCTOR DEVICE, MANUFACTURING METHOD THEREOF, AND ELECTRONIC DEVICE INCLUDING THE DEVICE

      
Numéro d'application 18477004
Statut En instance
Date de dépôt 2023-09-28
Date de la première publication 2024-01-18
Propriétaire Institute of Microelectronics, Chinese Academy of Sciences (Chine)
Inventeur(s)
  • Zhu, Huilong
  • Zhang, Yongkui
  • Yin, Xiaogen
  • Li, Chen
  • Liu, Yongbo
  • Jia, Kunpeng

Abrégé

The disclosed technology provides a semiconductor device, a manufacturing method thereof, and an electronic device including the device. An example semiconductor device includes a substrate; a first device and a second device on the substrate. Each of the first device and the second device include a first source/drain layer, a channel layer, and a second source layer that are sequentially stacked, from bottom to top, on the substrate, and a gate stack around at least a part of an outer periphery of the channel layer, with sidewalls of the respective channel layers of the first device and the second device extending at least partially along different crystal planes or crystal plane families.

Classes IPC  ?

  • H01L 21/8238 - Transistors à effet de champ complémentaires, p.ex. CMOS
  • H01L 27/092 - Transistors à effet de champ métal-isolant-semi-conducteur complémentaires

30.

MEMORY CELL AND PREPARATION METHOD THEREFOR, MEMORY, AND INFORMATION STORAGE METHOD

      
Numéro d'application CN2022105184
Numéro de publication 2024/011407
Statut Délivré - en vigueur
Date de dépôt 2022-07-12
Date de publication 2024-01-18
Propriétaire INSTITUTE OF MICROELECTRONICS, CHINESE ACADEMY OF SCIENCES (Chine)
Inventeur(s)
  • Xing, Guozhong
  • Zhang, Hao
  • Zhao, Xuefeng
  • Wang, Ziwei
  • Xie, Changqing
  • Liu, Ming

Abrégé

The present disclosure provides a memory cell and a preparation method therefor, a memory, and an information storage method. The memory cell comprises: a piezoelectric substrate layer, a first electrode and a second electrode being respectively provided at the two ends of the piezoelectric substrate layer, and current-free driving for a skyrmion being implemented by applying a voltage to the first electrode and the second electrode; and a magnetic layer, located on the surface of the piezoelectric substrate layer, forming a heterojunction with the piezoelectric substrate layer, and used for generating, stabilizing, and serving as a basic carrier for movement of the skyrmion, wherein the magnetic layer comprises a convex body, the convex body divides the magnetic layer into a bit region and a storage region, and a magnetic tunnel junction for performing skyrmion generation and detection functions is provided in the bit region.

Classes IPC  ?

  • G11C 19/08 - Mémoires numériques dans lesquelles l'information est déplacée par échelons, p.ex. registres à décalage utilisant des éléments magnétiques utilisant des couches minces dans une structure plane

31.

SPINTRONIC DEVICE, MEMORY CELL, MEMORY ARRAY AND READ AND WRITE CIRCUIT

      
Numéro d'application 18251699
Statut En instance
Date de dépôt 2021-10-13
Date de la première publication 2024-01-11
Propriétaire INSTITUTE OF MICROELECTRONICS, CHINESE ACADEMY OF SCIENCES (Chine)
Inventeur(s)
  • Xing, Guozhong
  • Wang, Di
  • Liu, Long
  • Lin, Huai
  • Liu, Ming

Abrégé

Provided is a spintronic device, a memory cell, a memory array, and a read and write circuit applied in a field of integration technology. The spintronic device includes: a bottom electrode; a spin orbit coupling layer, arranged on the bottom electrode; at least one pair of magnetic tunnel junctions, arranged on the spin orbit coupling layer, wherein each of the magnetic tunnel junctions includes a free layer, a tunneling layer, and a reference layer arranged sequentially from bottom to top, and wherein magnetization directions of reference layers of two magnetic tunnel junctions of each pair of the magnetic tunnel junctions are opposite; and a top electrode, arranged on a reference layer of each of the magnetic tunnel junctions.

Classes IPC  ?

  • G11C 11/16 - Mémoires numériques caractérisées par l'utilisation d'éléments d'emmagasinage électriques ou magnétiques particuliers; Eléments d'emmagasinage correspondants utilisant des éléments magnétiques utilisant des éléments dans lesquels l'effet d'emmagasinage est basé sur l'effet de spin
  • H10B 61/00 - Dispositifs de mémoire magnétique, p.ex. dispositifs RAM magnéto-résistifs [MRAM]
  • H10N 50/20 - Dispositifs à courant commandé à polarisation de spin
  • G06F 17/16 - Calcul de matrice ou de vecteur

32.

NOR-TYPE MEMORY DEVICE, METHOD OF MANUFACTURING NOR-TYPE MEMORY DEVICE, AND ELECTRONIC APPARATUS INCLUDING MEMORY DEVICE

      
Numéro d'application 18176002
Statut En instance
Date de dépôt 2023-02-28
Date de la première publication 2024-01-04
Propriétaire Institute of Microelectronics, Chinese Academy of Sciences (Chine)
Inventeur(s) Zhu, Huilong

Abrégé

Disclosed are a NOR-type memory device, a method of manufacturing the NOR-type memory device, and an electronic apparatus. The NOR-type memory device includes: at least one memory cell layer including a first source/drain layer, a first channel layer, a second source/drain layer, a second channel layer, and a third source/drain layer that are stacked on each other; at least one gate stack that extends vertically and includes a gate conductor layer and a memory functional layer between the gate conductor layer and the at least one memory cell layer. A memory cell is defined at an intersection of the gate stack and the memory cell layer. At least one bit line is electrically connected to the second source/drain layer in the memory cell layer; and at least one source line is electrically connected to the first and third source/drain layers in the memory cell layer.

Classes IPC  ?

  • H10B 51/20 - Dispositifs de RAM ferro-électrique [FeRAM] comprenant des transistors ferro-électriques de mémoire caractérisés par les agencements tridimensionnels, p ex. avec des cellules à des niveaux différents de hauteur
  • H10B 43/27 - Dispositifs EEPROM avec des isolants de grille à piégeage de charge caractérisés par les agencements tridimensionnels, p ex. avec des cellules à des niveaux différents de hauteur la région de source et la région de drain étant à différents niveaux, p.ex. avec des canaux inclinés les canaux comprenant des parties verticales, p.ex. des canaux en forme de U
  • H10B 43/35 - Dispositifs EEPROM avec des isolants de grille à piégeage de charge caractérisés par la région noyau de mémoire avec transistors de sélection de cellules, p.ex. NON-ET
  • H10B 51/30 - Dispositifs de RAM ferro-électrique [FeRAM] comprenant des transistors ferro-électriques de mémoire caractérisés par la région noyau de mémoire
  • G11C 11/22 - Mémoires numériques caractérisées par l'utilisation d'éléments d'emmagasinage électriques ou magnétiques particuliers; Eléments d'emmagasinage correspondants utilisant des éléments électriques utilisant des éléments ferro-électriques
  • G11C 16/04 - Mémoires mortes programmables effaçables programmables électriquement utilisant des transistors à seuil variable, p.ex. FAMOS
  • G11C 16/06 - Circuits auxiliaires, p.ex. pour l'écriture dans la mémoire

33.

NOR-TYPE MEMORY DEVICE, METHOD OF MANUFACTURING NOR-TYPE MEMORY DEVICE, AND ELECTRONIC APPARATUS INCLUDING MEMORY DEVICE

      
Numéro d'application 18176238
Statut En instance
Date de dépôt 2023-02-28
Date de la première publication 2024-01-04
Propriétaire INSTITUTE OF MICROELECTRONICS, CHINESE ACADEMY OF SCIENCES (Chine)
Inventeur(s) Zhu, Huilong

Abrégé

Disclosed are a NOR-type memory device, a method of manufacturing the NOR-type memory device, and an electronic apparatus. The NOR-type memory device includes: a memory cell layer including a first source/drain layer, a first channel layer, a second source/drain layer, a second channel layer, and a third source/drain layer which are stacked in a vertical direction; a gate stack that extends vertically and includes a gate conductor layer and a memory functional layer between the gate conductor layer and the memory cell layer; and at least one of a source line contact portion and a bulk contact portion. The source line contact portion extends vertically to pass through the memory cell layer, and is electrically connected to the first and third source/drain layers. The bulk contact portion extends vertically to pass through the memory cell layer, and is electrically connected to the first and second channel layers.

Classes IPC  ?

  • H10B 53/20 - Dispositifs RAM ferro-électrique [FeRAM] comprenant des condensateurs ferro-électriques de mémoire caractérisés par les agencements tridimensionnels, p ex. avec des cellules à des niveaux différents de hauteur
  • H10B 43/27 - Dispositifs EEPROM avec des isolants de grille à piégeage de charge caractérisés par les agencements tridimensionnels, p ex. avec des cellules à des niveaux différents de hauteur la région de source et la région de drain étant à différents niveaux, p.ex. avec des canaux inclinés les canaux comprenant des parties verticales, p.ex. des canaux en forme de U
  • H10B 43/35 - Dispositifs EEPROM avec des isolants de grille à piégeage de charge caractérisés par la région noyau de mémoire avec transistors de sélection de cellules, p.ex. NON-ET
  • H10B 53/30 - Dispositifs RAM ferro-électrique [FeRAM] comprenant des condensateurs ferro-électriques de mémoire caractérisés par la région noyau de mémoire

34.

METHOD OF DESIGNING THIN FILM TRANSISTOR

      
Numéro d'application 18250461
Statut En instance
Date de dépôt 2020-10-30
Date de la première publication 2024-01-04
Propriétaire Institute of Microelectronics, Chinese Academy of Sciences (Chine)
Inventeur(s)
  • Lu, Nianduan
  • Li, Ling
  • Jiang, Wenfeng
  • Geng, Di
  • Wang, Jiawei
  • Liu, Ming

Abrégé

A method of designing a thin film transistor device, including: calculating characteristic parameters of searched materials; screening the materials according to a characteristic parameter threshold to obtain first active layer materials; simulating the first active layer material as an active layer material in a thin film transistor device model to obtain a device characteristic of the thin film transistor device; screening the first active layer materials according to a device characteristic threshold to obtain second active layer materials; taking the second active layer material as the active layer material of the thin film transistor device to perform an experiment; and selecting another second active layer material to perform the experiment once again when an experiment result does not meet a preset requirement, and a design of the thin film transistor device is completed until the experiment result meets the preset requirement.

Classes IPC  ?

  • G06F 30/39 - Conception de circuits au niveau physique
  • G16C 60/00 - Science informatique des matériaux, c. à d. TIC spécialement adaptées à la recherche des propriétés physiques ou chimiques de matériaux ou de phénomènes associés à leur conception, synthèse, traitement, caractérisation ou utilisation

35.

METHOD AND APPARATUS FOR OPTIMIZING LITHOGRAPHY QUALITY, ELECTRONIC DEVICE, MEDIUM AND PROGRAM PRODUCT

      
Numéro d'application 18255045
Statut En instance
Date de dépôt 2021-11-01
Date de la première publication 2024-01-04
Propriétaire Institute of Microelectronics, Chinese Academy of Sciences (Chine)
Inventeur(s)
  • Liu, Lihong
  • Wei, Yayi
  • Ding, Huwen

Abrégé

Provided is a method for optimizing a lithography quality, including: determining a wave function stray term introduced by a surface roughness of a metal film layer based on Eigen matrix method and Bloch theorem; inputting the wave function stray term into a lithography quality deviation mathematical model for calculation and simulation to obtain an influence analysis curve of a roughness of the metal film layer on a lithography quality, the influence analysis curve characterizes an influence result of the roughness of the metal film layer on the lithography quality; reducing the surface roughness of the metal film layer and/or providing a metal-dielectric multilayer film structure between a mask above a metal-dielectric unit and air according to the influence result, so as to optimize the lithography quality of the metal-dielectric unit. Provided is an apparatus for optimizing a lithography quality, an electronic device, a computer-readable storage medium and computer program product.

Classes IPC  ?

  • G06F 30/23 - Optimisation, vérification ou simulation de l’objet conçu utilisant les méthodes des éléments finis [MEF] ou les méthodes à différences finies [MDF]
  • G03F 7/00 - Production par voie photomécanique, p.ex. photolithographique, de surfaces texturées, p.ex. surfaces imprimées; Matériaux à cet effet, p.ex. comportant des photoréserves; Appareillages spécialement adaptés à cet effet
  • G06F 17/16 - Calcul de matrice ou de vecteur

36.

IN-MEMORY COMPUTING METHOD AND APPARATUS FOR GRAPH FEW-SHOT LEARNING, AND ELECTRONIC DEVICE

      
Numéro d'application CN2022112494
Numéro de publication 2023/240779
Statut Délivré - en vigueur
Date de dépôt 2022-08-15
Date de publication 2023-12-21
Propriétaire INSTITUTE OF MICROELECTRONICS, CHINESE ACADEMY OF SCIENCES (Chine)
Inventeur(s)
  • Shang, Dashan
  • Zhang, Woyu
  • Wang, Shaocong
  • Li, Yi

Abrégé

An in-memory computing method and apparatus for graph few-shot learning, and an electronic device, relating to the fields of machine learning and artificial intelligence. A memory augmented graph network model is developed to realize a graph few-shot learning function, and hardware implementation is performed by using an in-memory computing architecture. The method comprises: initializing parameters of an encoder, and dividing a graph data set into a training set and a test set; randomly selecting a preset category and a preset number of support sets in the training set, and inputting the support sets into a controller and the encoder to obtain a first binary feature vector; storing the first binary feature vector and a tag corresponding to the first binary feature vector into an external memory unit; randomly selecting the preset category and a preset number of query sets in the training set, and inputting the query sets into the controller and the encoder to obtain a second binary feature vector; and determining a prediction category of a sample on the basis of the first binary feature vector and the second binary feature vector, so that the sample category can be quickly determined.

Classes IPC  ?

  • G06N 3/063 - Réalisation physique, c. à d. mise en œuvre matérielle de réseaux neuronaux, de neurones ou de parties de neurone utilisant des moyens électroniques

37.

SEMICONDUCTOR APPARATUS WITH SIDEWALL INTERCONNECTION STRUCTURE, METHOD OF MANUFACTURING SEMICONDUCTOR APPARATUS WITH SIDEWALL INTERCONNECTION STRUCTURE, AND ELECTRONIC DEVICE

      
Numéro d'application 18250128
Statut En instance
Date de dépôt 2021-08-27
Date de la première publication 2023-12-14
Propriétaire INSTITUTE OF MICROELECTRONICS, CHINESE ACADEMY OF SCIENCES (Chine)
Inventeur(s) Zhu, Huilong

Abrégé

Disclosed are a semiconductor apparatus with a sidewall interconnection structure, a method of manufacturing the semiconductor apparatus, and an electronic device. The semiconductor apparatus includes: a plurality of device stacks, wherein each device stack includes a plurality of semiconductor devices stacked, and each semiconductor device includes a first source/drain layer, a channel layer, and a second source/drain layer stacked in a vertical direction, and a gate electrode surrounding the channel layer; and an interconnection structure between the plurality of device stacks. The interconnection structure includes: an electrical isolation layer; and a conductive structure in the electrical isolation layer. At least one of the first source/drain layer, the second source/drain layer, and the gate electrode of each of at least one of the semiconductor devices is in contact with and thus electrically connected to the conductive structure at a corresponding height in the interconnection structure in a lateral direction.

Classes IPC  ?

  • H01L 23/538 - Dispositions pour conduire le courant électrique à l'intérieur du dispositif pendant son fonctionnement, d'un composant à un autre la structure d'interconnexion entre une pluralité de puces semi-conductrices se trouvant au-dessus ou à l'intérieur de substrats isolants
  • H01L 29/423 - Electrodes caractérisées par leur forme, leurs dimensions relatives ou leur disposition relative ne transportant pas le courant à redresser, à amplifier ou à commuter
  • H01L 29/06 - Corps semi-conducteurs caractérisés par les formes, les dimensions relatives, ou les dispositions des régions semi-conductrices
  • H01L 29/786 - Transistors à couche mince
  • H01L 29/775 - Transistors à effet de champ avec un canal à gaz de porteurs de charge à une dimension, p.ex. FET à fil quantique
  • H01L 27/092 - Transistors à effet de champ métal-isolant-semi-conducteur complémentaires
  • H01L 21/8238 - Transistors à effet de champ complémentaires, p.ex. CMOS

38.

NOR-TYPE MEMORY DEVICE, METHOD OF MANUFACTURING NOR-TYPE MEMORY DEVICE, AND ELECTRONIC APPARATUS INCLUDING MEMORY DEVICE

      
Numéro d'application 18043080
Statut En instance
Date de dépôt 2022-02-22
Date de la première publication 2023-12-14
Propriétaire INSTITUTE OF MICROELECTRONICS, CHINESE ACADEMY OF SCIENCES (Chine)
Inventeur(s) Zhu, Huilong

Abrégé

An NOR-type memory device, a method of manufacturing the NOR-type memory device, and an electronic apparatus including the NOR-type memory device. The NOR-type memory device includes: a gate stack including a gate conductor layer and a memory functional layer; and a first semiconductor layer and a second semiconductor layer that surround a periphery of the gate stack. The first and second semiconductor layers are respectively located at different heights with respect to the substrate. The memory functional layer is located between the gate conductor layer and each of the first and second semiconductor layers. Each of the first and second semiconductor layers includes a first source/drain region, a channel region, and a second source/drain region that are disposed in sequence in a vertical direction. A memory cell is defined at an intersection of the gate stack and each of the first and second semiconductor layers.

Classes IPC  ?

  • H10B 43/27 - Dispositifs EEPROM avec des isolants de grille à piégeage de charge caractérisés par les agencements tridimensionnels, p ex. avec des cellules à des niveaux différents de hauteur la région de source et la région de drain étant à différents niveaux, p.ex. avec des canaux inclinés les canaux comprenant des parties verticales, p.ex. des canaux en forme de U
  • H10B 43/10 - Dispositifs EEPROM avec des isolants de grille à piégeage de charge caractérisés par la configuration vue du dessus
  • H10B 41/10 - Dispositifs de mémoire morte reprogrammable électriquement [EEPROM] comprenant des grilles flottantes caractérisés par la configuration vue du dessus
  • H10B 41/27 - Dispositifs de mémoire morte reprogrammable électriquement [EEPROM] comprenant des grilles flottantes caractérisés par les agencements tridimensionnels, p ex. avec des cellules à des niveaux différents de hauteur la région de source et la région de drain étant à différents niveaux, p.ex. avec des canaux inclinés les canaux comprenant des parties verticales, p.ex. des canaux en forme de U
  • H01L 29/786 - Transistors à couche mince
  • H01L 29/06 - Corps semi-conducteurs caractérisés par les formes, les dimensions relatives, ou les dispositions des régions semi-conductrices
  • H01L 29/775 - Transistors à effet de champ avec un canal à gaz de porteurs de charge à une dimension, p.ex. FET à fil quantique
  • H01L 29/423 - Electrodes caractérisées par leur forme, leurs dimensions relatives ou leur disposition relative ne transportant pas le courant à redresser, à amplifier ou à commuter
  • H01L 29/08 - Corps semi-conducteurs caractérisés par les formes, les dimensions relatives, ou les dispositions des régions semi-conductrices avec des régions semi-conductrices connectées à une électrode transportant le courant à redresser, amplifier ou commuter, cette électrode faisant partie d'un dispositif à semi-conducteur qui comporte trois électrodes ou plus

39.

ALL-ELECTRICALLY-CONTROLLED SPINTRONIC NEURON DEVICE, NEURON CIRCUIT AND NEURAL NETWORK

      
Numéro d'application 18249805
Statut En instance
Date de dépôt 2021-05-17
Date de la première publication 2023-12-07
Propriétaire Institute of Microelectronics, Chinese Academy of Sciences (Chine)
Inventeur(s)
  • Xing, Guozhong
  • Wang, Di
  • Liu, Ming

Abrégé

Provided is an all-electrically-controlled spintronic neuron device, a neuron circuit and a neural network. The neuron device includes: a bottom antiferromagnetic pinning layer; a synthetic antiferromagnetic layer formed on the bottom antiferromagnetic pinning layer; a potential barrier layer formed on the ferromagnetic free layer, wherein a region of the ferromagnetic free layer directly opposite to the potential barrier layer forms a threshold region; a ferromagnetic reference layer formed on the potential barrier layer; wherein the potential barrier layer, the ferromagnetic reference layer and the ferromagnetic free layer form a magnetic tunnel junction; a first antiferromagnetic pinning layer and a second antiferromagnetic pinning layer formed on an exposed region of the ferromagnetic free layer except the region directly opposite the potential barrier layer, and located on two sides of the potential barrier layer; and a first electrode formed on the ferromagnetic reference layer.

Classes IPC  ?

  • H10N 52/00 - Dispositifs à effet Hall
  • H10N 52/85 - Matériaux actifs magnétiques
  • H10N 59/00 - Dispositifs intégrés, ou ensembles de plusieurs dispositifs, comportant au moins un élément galvanomagnétique ou à effet Hall couvert par les groupes
  • G06N 3/063 - Réalisation physique, c. à d. mise en œuvre matérielle de réseaux neuronaux, de neurones ou de parties de neurone utilisant des moyens électroniques

40.

METHOD OF PREPARING PROGRAMMABLE DIODE, PROGRAMMABLE DIODE AND FERROELECTRIC MEMORY

      
Numéro d'application 18249890
Statut En instance
Date de dépôt 2020-10-22
Date de la première publication 2023-12-07
Propriétaire INSTITUTE OF MICROELECTRONICS, CHINESE ACADEMY OF SCIENCES (Chine)
Inventeur(s)
  • Luo, Qing
  • Lv, Hangbing
  • Liu, Ming

Abrégé

A method of preparing a programmable diode, including: forming a tungsten plug by a standard CMOS process; taking the tungsten plug as a lower electrode and depositing a functional layer material such as a ferroelectric film on the tungsten plug; depositing an upper electrode on the functional layer material; and patterning the upper electrode and a functional layer to complete a preparation of the programmable diode. The present disclosure further discloses a ferroelectric memory of a programmable diode prepared by the method of preparing a programmable diode. The method of preparing a programmable diode does not require growing a lower electrode and reduces a complexity of the process. The ferroelectric memory includes a transistor and a programmable diode. This design stores information according to different polarities of the diode, thus a device area may be further reduced and a storage density may be improved.

Classes IPC  ?

  • H10B 51/30 - Dispositifs de RAM ferro-électrique [FeRAM] comprenant des transistors ferro-électriques de mémoire caractérisés par la région noyau de mémoire
  • H01L 29/861 - Diodes
  • H10B 99/00 - Matière non prévue dans les autres groupes de la présente sous-classe
  • H01L 29/49 - Electrodes du type métal-isolant-semi-conducteur
  • H01L 21/28 - Fabrication des électrodes sur les corps semi-conducteurs par emploi de procédés ou d'appareils non couverts par les groupes
  • H01L 29/51 - Matériaux isolants associés à ces électrodes
  • H01L 29/78 - Transistors à effet de champ l'effet de champ étant produit par une porte isolée
  • H01L 29/66 - Types de dispositifs semi-conducteurs

41.

PHOTOELECTRIC DETECTION DEVICE WITH SEALED DESIGN AND UNDISTORTED PHOTOELECTRIC SIGNALS, AND IMPLEMENTATION METHOD THEREOF

      
Numéro d'application 18034050
Statut En instance
Date de dépôt 2020-11-30
Date de la première publication 2023-12-07
Propriétaire INSTITUTE OF MICROELECTRONICS, CHINESE ACADEMY OF SCIENCES (Chine)
Inventeur(s)
  • Li, Jing
  • Ma, Huijuan
  • Ding, Minxia
  • Wu, Zhipeng
  • Wang, Dan

Abrégé

A photoelectric detection device, including: a vacuum sealed housing, wherein the vacuum sealed housing includes a mounting interface for mounting the photodetector array so as to form a sealed space; the photodetector array has a detection surface facing an outside of the vacuum sealed housing and configured to receive multi-channel measurement optical signals; a photoelectric conversion and synchronous acquisition circuit and a high speed transmission circuit board are placed in the vacuum sealed housing, and the photodetector array is connected to the photoelectric conversion and synchronous acquisition circuit through a signal pin of the photodetector array; the photoelectric conversion and synchronous acquisition circuit is configured to synchronously convert the multi-channel measurement optical signals obtained by the photodetector array into multi-channel digital signals; and the high speed transmission circuit board is configured to perform a serial encoding processing on the converted multi-channel digital signals.

Classes IPC  ?

  • G01J 1/44 - Circuits électriques
  • G01J 1/02 - Photométrie, p.ex. posemètres photographiques - Parties constitutives

42.

NEURON DEVICE BASED ON SPIN ORBIT TORQUE

      
Numéro d'application 18034365
Statut En instance
Date de dépôt 2021-07-21
Date de la première publication 2023-12-07
Propriétaire INSTITUTE OF MICROELECTRONICS, CHINESE ACANDEMY OF SCIENCES (Chine)
Inventeur(s)
  • Xing, Guozhong
  • Wang, Di
  • Lin, Huai
  • Liu, Long
  • Liu, Ming

Abrégé

A neuron device including: an antiferromagnetic pinning layer, a first ferromagnetic layer and a spin orbit coupling layer formed on a substrate in sequence; a free layer formed on the spin orbit coupling layer and moving a magnetic domain wall according to a spin orbit torque; a tunneling layer formed on the free layer; a left pinning layer and a right pinning layer formed on two sides of the free layer and having opposite magnetization directions; and a reference layer formed on the tunneling layer; wherein the free layer, the tunneling layer and the reference layer constitute a magnetic tunnel junction, and the magnetic tunnel junction is configured to read neuronal signals. Also provided is a method for preparing a neuron device based on a spin orbit torque.

Classes IPC  ?

  • G06N 3/063 - Réalisation physique, c. à d. mise en œuvre matérielle de réseaux neuronaux, de neurones ou de parties de neurone utilisant des moyens électroniques
  • H01F 10/32 - Multicouches couplées par échange de spin, p.ex. superréseaux à structure nanométrique
  • H10N 50/85 - Matériaux actifs magnétiques
  • H10N 52/00 - Dispositifs à effet Hall

43.

MEMORY DEVICE, METHOD OF MANUFACTURING MEMORY DEVICE, AND ELECTRONIC APPARATUS INCLUDING MEMORY DEVICE

      
Numéro d'application 18318794
Statut En instance
Date de dépôt 2023-05-17
Date de la première publication 2023-11-23
Propriétaire INSTITUTE OF MICROELECTRONICS, CHINESE ACADEMY OF SCIENCES (Chine)
Inventeur(s) Zhu, Huilong

Abrégé

Disclosed are a memory device, a method of manufacturing the same, and an electronic apparatus. The memory device includes: first to fourth connection line layers sequentially disposed in a vertical direction relative to a substrate. The first connection line layer includes a plurality of first conductive lines extending parallel in a first direction. One of the second and third connection line layers includes a plurality of conductive lines extending parallel in a second direction intersecting the first direction. The fourth connection line layer includes a plurality of fourth conductive lines extending parallel in a third direction. A memory cell is provided at an intersection of conductive lines. Each memory cell includes first to third transistors stacked in the vertical direction. A fifth connection line layer is provided above the memory cell, and includes a plurality of fifth conductive lines extending in a fourth direction intersecting the third direction.

Classes IPC  ?

  • H10B 12/00 - Mémoires dynamiques à accès aléatoire [DRAM]

44.

MEMORY DEVICE, METHOD OF MANUFACTURING MEMORY DEVICE, AND ELECTRONIC APPARATUS INCLUDING MEMORY DEVICE

      
Numéro d'application 18311528
Statut En instance
Date de dépôt 2023-05-03
Date de la première publication 2023-11-23
Propriétaire INSTITUTE OF MICROELECTRONICS, CHINESE ACADEMY OF SCIENCES (Chine)
Inventeur(s) Zhu, Huilong

Abrégé

Disclosed are a memory device, a method of manufacturing the same, and an electronic apparatus. The memory device includes: first to fourth connection line layers sequentially disposed in a vertical direction, and adjacent connection line layers respectively include conductive lines extending in directions intersected; a plurality of memory cells respectively including first and second transistors stacked. A first active layer of the first transistor includes first and second source/drain regions respectively electrically connected with conductive lines in the first and second connection line layers. A second active layer of the second transistor includes a first source/drain region electrically connected with a gate conductor layer of the first transistor, and a second source/drain region electrically connected with a conductive line in the third connection line layer. A gate conductor layer of the second transistor of each memory cell is electrically connected to a conductive line in the fourth connection line layer.

Classes IPC  ?

  • H10B 12/00 - Mémoires dynamiques à accès aléatoire [DRAM]

45.

MEMORY CIRCUIT STRUCTURE AND METHOD OF OPERATING MEMORY CIRCUIT STRUCTURE

      
Numéro d'application 18247213
Statut En instance
Date de dépôt 2021-01-25
Date de la première publication 2023-11-16
Propriétaire INSTITUTE OF MICROELECTRONICS, CHINESE ACADEMY OF SCIENCES (Chine)
Inventeur(s)
  • Xu, Xiaoxin
  • Yu, Jie
  • Dong, Danian
  • Yu, Zhaoan
  • Lv, Hangbing

Abrégé

The memory circuit structure includes: a storage array, wherein the storage array includes at least two storage units; a decoder connected with a bit line and a word line of the storage array respectively; a programming circuit configured to generate a voltage pulse or a constant current pulse; a polarity switching circuit connected with the programming circuit, and configured to implement a switching between a voltage programming and a current programming of the programming circuit under a set operation and a reset operation; a detection circuit connected with the storage array, and configured to detect a detection signal of a current or a voltage corresponding to the specific storage unit in the storage array and feed back the detection signal to a control unit, wherein the detection signal output by the detection circuit is configured to enable the polarity switching circuit to switch; and the control unit.

Classes IPC  ?

  • G11C 13/00 - Mémoires numériques caractérisées par l'utilisation d'éléments d'emmagasinage non couverts par les groupes , ou

46.

PRESSURE SENSOR BASED ON ZINC OXIDE NANOWIRES AND METHOD OF MANUFACTURING PRESSURE SENSOR

      
Numéro d'application 18250742
Statut En instance
Date de dépôt 2020-10-26
Date de la première publication 2023-11-16
Propriétaire INSTITUTE OF MICROELECTRONICS, CHINESE ACADEMY OF SCIENCES (Chine)
Inventeur(s)
  • Li, Ling
  • Shi, Xuewen
  • Lu, Nianduan
  • Lu, Congyan
  • Geng, Di
  • Duan, Xinlv
  • Liu, Ming

Abrégé

A pressure sensor based on zinc oxide nanowires and a method of manufacturing a pressure sensor based on zinc oxide nanowires are provided. The manufacturing method includes: manufacturing a bottom electrode on a substrate; manufacturing a seed layer on the bottom electrode; manufacturing a zinc oxide nanowire layer on the seed layer; manufacturing a support layer on the zinc oxide nanowire layer; and manufacturing a top electrode on the support layer.

Classes IPC  ?

  • H10N 30/074 - Formation de parties ou de corps piézo-électriques ou électrostrictifs sur un élément électrique ou sur un autre support par dépôt de couches piézo-électriques ou électrostrictives, p.ex. par impression par aérosol ou par sérigraphie
  • G01L 1/16 - Mesure des forces ou des contraintes, en général en utilisant les propriétés des dispositifs piézo-électriques
  • H10N 30/067 - Formation d’électrodes à une seule couche de parties piézo-électriques ou électrostrictives multicouches

47.

SEMICONDUCTOR DEVICE, METHOD OF MANUFACTURING THE SAME AND ELECTRONIC DEVICE INCLUDING THE DEVICE

      
Numéro d'application 18317722
Statut En instance
Date de dépôt 2023-05-15
Date de la première publication 2023-11-16
Propriétaire INSTITUTE OF MICROELECTRONICS, CHINESE ACADEMY OF SCIENCES (Chine)
Inventeur(s) Zhu, Huilong

Abrégé

There are provided a semiconductor device, a method of manufacturing the same, and an electronic device including the device. According to an embodiment, the semiconductor device may include a substrate, and a first device and a second device formed on the substrate. Each of the first device and the second device includes a first source/drain layer, a channel layer and a second source/drain layer stacked on the substrate in sequence, and also a gate stack surrounding a periphery of the channel layer. The channel layer of the first device and the channel layer of the second device are substantially co-planar.

Classes IPC  ?

  • H01L 29/78 - Transistors à effet de champ l'effet de champ étant produit par une porte isolée
  • H01L 21/225 - Diffusion des impuretés, p.ex. des matériaux de dopage, des matériaux pour électrodes, à l'intérieur ou hors du corps semi-conducteur, ou entre les régions semi-conductrices; Redistribution des impuretés, p.ex. sans introduction ou sans élimination de matériau dopant supplémentaire en utilisant la diffusion dans ou hors d'un solide, à partir d'une ou en phase solide, p.ex. une couche d'oxyde dopée
  • H01L 29/06 - Corps semi-conducteurs caractérisés par les formes, les dimensions relatives, ou les dispositions des régions semi-conductrices
  • H01L 29/423 - Electrodes caractérisées par leur forme, leurs dimensions relatives ou leur disposition relative ne transportant pas le courant à redresser, à amplifier ou à commuter
  • H01L 29/786 - Transistors à couche mince
  • H01L 23/522 - Dispositions pour conduire le courant électrique à l'intérieur du dispositif pendant son fonctionnement, d'un composant à un autre comprenant des interconnexions externes formées d'une structure multicouche de couches conductrices et isolantes inséparables du corps semi-conducteur sur lequel elles ont été déposées
  • H01L 29/66 - Types de dispositifs semi-conducteurs
  • H01L 21/8238 - Transistors à effet de champ complémentaires, p.ex. CMOS
  • H01L 21/3065 - Gravure par plasma; Gravure au moyen d'ions réactifs
  • H01L 21/223 - Diffusion des impuretés, p.ex. des matériaux de dopage, des matériaux pour électrodes, à l'intérieur ou hors du corps semi-conducteur, ou entre les régions semi-conductrices; Redistribution des impuretés, p.ex. sans introduction ou sans élimination de matériau dopant supplémentaire en utilisant la diffusion dans ou hors d'un solide, à partir d'une ou en phase gazeuse
  • H01L 27/092 - Transistors à effet de champ métal-isolant-semi-conducteur complémentaires

48.

THREE-DIMENSIONAL INTEGRATED CIRCUIT AND MANUFACTURING METHOD THEREFOR

      
Numéro d'application CN2023079911
Numéro de publication 2023/216693
Statut Délivré - en vigueur
Date de dépôt 2023-03-06
Date de publication 2023-11-16
Propriétaire INSTITUTE OF MICROELECTRONICS , CHINESE ACADEMY OF SCIENCES (Chine)
Inventeur(s)
  • Li, Ling
  • Yang, Guanhua
  • Lu, Wendong

Abrégé

The present invention relates to the technical field of semiconductors. Disclosed are a three-dimensional integrated circuit and a manufacturing method therefor, used for improving the performance of the integrated circuit when the integrated circuit comprises a power gating circuit. The three-dimensional integrated circuit comprises a substrate, and a front-section circuit, a rear-section metal interconnection layer, and a rear-section power gating circuit that are formed on the substrate; the rear-section metal interconnection layer is formed on the front-section circuit; the rear-section power gating circuit is located in the rear-section metal interconnection layer; and the front-section circuit is electrically connected to a power supply or a ground wire by means of the rear-section metal interconnection layer and the rear-section power gating circuit.

Classes IPC  ?

  • H01L 27/06 - Dispositifs consistant en une pluralité de composants semi-conducteurs ou d'autres composants à l'état solide formés dans ou sur un substrat commun comprenant des éléments de circuit passif intégrés avec au moins une barrière de potentiel ou une barrière de surface le substrat étant un corps semi-conducteur comprenant une pluralité de composants individuels dans une configuration non répétitive
  • H01L 23/535 - Dispositions pour conduire le courant électrique à l'intérieur du dispositif pendant son fonctionnement, d'un composant à un autre comprenant des interconnexions internes, p.ex. structures d'interconnexions enterrées
  • H01L 21/8256 - Fabrication ou traitement de dispositifs consistant en une pluralité de composants à l'état solide ou de circuits intégrés formés dans ou sur un substrat commun avec une division ultérieure du substrat en plusieurs dispositifs individuels pour produire des dispositifs, p.ex. des circuits intégrés, consistant chacun en une pluralité de composants le substrat étant un semi-conducteur, en utilisant des technologies non couvertes par l'un des groupes , ou
  • H01L 29/786 - Transistors à couche mince
  • H01L 29/66 - Types de dispositifs semi-conducteurs
  • H01L 23/528 - Configuration de la structure d'interconnexion

49.

NOR-TYPE MEMORY DEVICE, METHOD OF MANUFACTURING NOR-TYPE MEMORY DEVICE, AND ELECTRONIC APPARATUS INCLUDING MEMORY DEVICE

      
Numéro d'application 18115227
Statut En instance
Date de dépôt 2023-02-28
Date de la première publication 2023-11-09
Propriétaire INSTITUTE OF MICROELECTRONICS, CHINESE ACADEMY OF SCIENCES (Chine)
Inventeur(s) Zhu, Huilong

Abrégé

Disclosed are a NOR-type memory device, a method of manufacturing the NOR-type memory device, and an electronic apparatus. The NOR-type memory device includes a plurality of device layers. Each device layer includes a first source/drain region and a second source/drain region at opposite ends of the device layer in a vertical direction, and a channel region between the first source/drain region and the second source/drain region; and a gate stack that extends vertically with respect to the substrate. The gate stack includes a gate conductor layer and a memory functional layer disposed between the gate conductor layer and the device layer. A memory cell is defined at an intersection of the gate stack and the device layer. The memory functional layer includes a first layer having a plurality of portions that correspond to the plurality of device layers respectively and are discontinuous with each other in the vertical direction.

Classes IPC  ?

  • H10B 41/27 - Dispositifs de mémoire morte reprogrammable électriquement [EEPROM] comprenant des grilles flottantes caractérisés par les agencements tridimensionnels, p ex. avec des cellules à des niveaux différents de hauteur la région de source et la région de drain étant à différents niveaux, p.ex. avec des canaux inclinés les canaux comprenant des parties verticales, p.ex. des canaux en forme de U
  • H10B 43/27 - Dispositifs EEPROM avec des isolants de grille à piégeage de charge caractérisés par les agencements tridimensionnels, p ex. avec des cellules à des niveaux différents de hauteur la région de source et la région de drain étant à différents niveaux, p.ex. avec des canaux inclinés les canaux comprenant des parties verticales, p.ex. des canaux en forme de U
  • H10B 51/20 - Dispositifs de RAM ferro-électrique [FeRAM] comprenant des transistors ferro-électriques de mémoire caractérisés par les agencements tridimensionnels, p ex. avec des cellules à des niveaux différents de hauteur

50.

DEVICE WITH FERROELECTRIC OR NEGATIVE CAPACITANCE MATERIAL, METHOD OF MANUFACTURING DEVICE WITH FERROELECTRIC OR NEGATIVE CAPACITANCE MATERIAL, AND ELECTRONIC APPARATUS

      
Numéro d'application 18042612
Statut En instance
Date de dépôt 2021-03-23
Date de la première publication 2023-11-02
Propriétaire INSTITUTE OF MICROELECTRONICS, CHINESE ACADEMY OF SCIENCES (Chine)
Inventeur(s)
  • Zhu, Huilong
  • Huang, Weixing

Abrégé

Disclosed are a semiconductor device with a ferroelectric or negative capacitance material layer on a sidewall of a gate electrode, a method of manufacturing the semiconductor device, and an electronic apparatus including the semiconductor device. According to embodiments, the semiconductor device may include: a substrate; a gate electrode formed on the substrate; a ferroelectric or negative capacitance material layer formed on a sidewall of the gate electrode; and a source region and a drain region that are located on opposite sides of the gate electrode on the substrate.

Classes IPC  ?

  • H01L 29/78 - Transistors à effet de champ l'effet de champ étant produit par une porte isolée
  • H01L 29/51 - Matériaux isolants associés à ces électrodes
  • H01L 29/40 - Electrodes
  • H01L 29/66 - Types de dispositifs semi-conducteurs

51.

SEMICONDUCTOR DEVICE AND METHOD FOR MANUFACTURING THE SAME

      
Numéro d'application 17783624
Statut En instance
Date de dépôt 2021-12-23
Date de la première publication 2023-10-26
Propriétaire
  • BEIJING SUPERSTRING ACADEMY OF MEMORY TECHNOLOGY (Chine)
  • INSTITUTE OF MICROELECTRONICS, CHINESE ACADEMY OF SCIENCES (Chine)
Inventeur(s)
  • Huang, Weixing
  • Zhu, Huilong

Abrégé

A semiconductor device and a method for manufacturing the same. A first electrode layer, a semiconductor layer, and a second electrode layer are sequentially formed on a substrate. Then, a part of the semiconductor layer is removed through etching a sidewall of the semiconductor layer to form a cavity. Afterwards, a channel layer is formed at the cavity, a sidewall of the first electrode layer, and a sidewall of the second electrode layer. The channel layer includes a first channel part located in the cavity and a second channel part located outside the cavity. The first channel part is filled with a dummy gate layer. Then, a part of the dummy gate layer is removed through etching a sidewall of the dummy gate layer with the second channel part serving as a shield. Afterwards, the second channel part and the first channel part, which is in contact with an upper surface and a lower surface of the dummy gate layer, are removed to form a recess. The recess is formed by either the first electrode layer or the second electrode layer, the channel layer, and the dummy gate layer. The recess is filled with a dielectric material to form an isolation sidewall. The formed isolation sidewall can reduce parasitic capacitance of the semiconductor device and improve a performance of the semiconductor device.

Classes IPC  ?

  • H01L 29/66 - Types de dispositifs semi-conducteurs
  • H01L 29/10 - Corps semi-conducteurs caractérisés par les formes, les dimensions relatives, ou les dispositions des régions semi-conductrices avec des régions semi-conductrices connectées à une électrode ne transportant pas le courant à redresser, amplifier ou commuter, cette électrode faisant partie d'un dispositif à semi-conducteur qui comporte trois électrodes ou plus
  • H01L 29/78 - Transistors à effet de champ l'effet de champ étant produit par une porte isolée

52.

NOR-TYPE MEMORY DEVICE, METHOD OF MANUFACTURING NOR-TYPE MEMORY DEVICE, AND ELECTRONIC APPARATUS INCLUDING MEMORY DEVICE

      
Numéro d'application 18042651
Statut En instance
Date de dépôt 2022-07-05
Date de la première publication 2023-10-19
Propriétaire INSTITUTE OF MICROELECTRONICS, CHINESE ACADEMY OF SCIENCES (Chine)
Inventeur(s) Zhu, Huilong

Abrégé

Disclosed are a NOR-type memory device and an electronic apparatus. The NOR-type memory device includes a NOR cell array and a peripheral circuit. The NOR cell array includes: a first substrate; an array of memory cells on the first substrate, wherein each memory cell includes a first gate stack extending vertically with respect to the first substrate and an active region surrounding a periphery of the first gate stack; first bonding pads electrically connected to the first gate stacks; and second bonding pads electrically connected to the active regions. The peripheral circuit includes: a second substrate; peripheral circuit elements on the second substrate; and third bonding pads, wherein at least some of the third bonding pads are electrically connected to the peripheral circuit elements. At least some of the first bonding pads and the second bonding pads are opposite to at least some of the third bonding pads.

Classes IPC  ?

  • H10B 80/00 - Ensembles de plusieurs dispositifs comprenant au moins un dispositif de mémoire couvert par la présente sous-classe
  • H10B 43/27 - Dispositifs EEPROM avec des isolants de grille à piégeage de charge caractérisés par les agencements tridimensionnels, p ex. avec des cellules à des niveaux différents de hauteur la région de source et la région de drain étant à différents niveaux, p.ex. avec des canaux inclinés les canaux comprenant des parties verticales, p.ex. des canaux en forme de U
  • H10B 43/30 - Dispositifs EEPROM avec des isolants de grille à piégeage de charge caractérisés par la région noyau de mémoire
  • H10B 43/40 - Dispositifs EEPROM avec des isolants de grille à piégeage de charge caractérisés par la région de circuit périphérique
  • H10B 51/20 - Dispositifs de RAM ferro-électrique [FeRAM] comprenant des transistors ferro-électriques de mémoire caractérisés par les agencements tridimensionnels, p ex. avec des cellules à des niveaux différents de hauteur
  • H10B 51/30 - Dispositifs de RAM ferro-électrique [FeRAM] comprenant des transistors ferro-électriques de mémoire caractérisés par la région noyau de mémoire
  • H10B 51/40 - Dispositifs de RAM ferro-électrique [FeRAM] comprenant des transistors ferro-électriques de mémoire caractérisés par la région de circuit périphérique
  • H01L 25/065 - Ensembles consistant en une pluralité de dispositifs à semi-conducteurs ou d'autres dispositifs à l'état solide les dispositifs étant tous d'un type prévu dans le même sous-groupe des groupes , ou dans une seule sous-classe de , , p.ex. ensembles de diodes redresseuses les dispositifs n'ayant pas de conteneurs séparés les dispositifs étant d'un type prévu dans le groupe
  • H01L 25/18 - Ensembles consistant en une pluralité de dispositifs à semi-conducteurs ou d'autres dispositifs à l'état solide les dispositifs étant de types prévus dans plusieurs sous-groupes différents du même groupe principal des groupes , ou dans une seule sous-classe de ,
  • H01L 25/00 - Ensembles consistant en une pluralité de dispositifs à semi-conducteurs ou d'autres dispositifs à l'état solide

53.

NOR-TYPE MEMORY DEVICE, METHOD OF MANUFACTURING NOR-TYPE MEMORY DEVICE, AND ELECTRONIC APPARATUS INCLUDING MEMORY DEVICE

      
Numéro d'application 18042754
Statut En instance
Date de dépôt 2022-02-22
Date de la première publication 2023-10-19
Propriétaire INSTITUTE OF MICROELECTRONICS, CHINESE ACADEMY OF SCIENCES (Chine)
Inventeur(s) Zhu, Huilong

Abrégé

Disclosed are a NOR-type memory device, a method of manufacturing the NOR-type memory device, and an electronic apparatus. The NOR-type memory device may include: a plurality of device layers stacked on a substrate, wherein each device layer includes a first source/drain region and a second source/drain region at opposite ends of the device layer in a vertical direction, and a channel region between the first and second source/drain region; and a gate stack that extends vertically with respect to the substrate to pass through each device layer. The gate stack includes a gate conductor layer and a memory functional layer between the gate conductor layer and the device layer. A memory cell is defined at an intersection of the gate stack and the device layer. A doping concentration in each of the first and second source/drain regions decreases towards the channel region in the vertical direction.

Classes IPC  ?

  • H10B 43/27 - Dispositifs EEPROM avec des isolants de grille à piégeage de charge caractérisés par les agencements tridimensionnels, p ex. avec des cellules à des niveaux différents de hauteur la région de source et la région de drain étant à différents niveaux, p.ex. avec des canaux inclinés les canaux comprenant des parties verticales, p.ex. des canaux en forme de U
  • H10B 43/10 - Dispositifs EEPROM avec des isolants de grille à piégeage de charge caractérisés par la configuration vue du dessus
  • H10B 51/10 - Dispositifs de RAM ferro-électrique [FeRAM] comprenant des transistors ferro-électriques de mémoire caractérisés par la configuration vue du dessus
  • H10B 51/20 - Dispositifs de RAM ferro-électrique [FeRAM] comprenant des transistors ferro-électriques de mémoire caractérisés par les agencements tridimensionnels, p ex. avec des cellules à des niveaux différents de hauteur
  • H01L 23/522 - Dispositions pour conduire le courant électrique à l'intérieur du dispositif pendant son fonctionnement, d'un composant à un autre comprenant des interconnexions externes formées d'une structure multicouche de couches conductrices et isolantes inséparables du corps semi-conducteur sur lequel elles ont été déposées
  • H01L 23/528 - Configuration de la structure d'interconnexion

54.

SOT-DRIVEN FIELD-FREE SWITCHING MRAM AND ARRAY THEREOF

      
Numéro d'application 18042249
Statut En instance
Date de dépôt 2020-08-20
Date de la première publication 2023-10-19
Propriétaire INSTITUTE OF MICROELECTRONICS, CHINESE ACADEMY OF SCIENCES (Chine)
Inventeur(s)
  • Xing, Guozhong
  • Lin, Huai
  • Liu, Yu
  • Zhang, Peiwen
  • Xie, Changqing
  • Li, Ling
  • Liu, Ming

Abrégé

An SOT-driven field-free switching MRAM and an array thereof. From top to bottom, the SOT-MRAM sequentially includes: a selector (1) configured to turn on or turn off the SOT-MRAM under an action of an external voltage; a magnetic tunnel junction (2), including a ferromagnetic reference layer, a tunneling layer and a ferromagnetic free layer arranged sequentially from top to bottom; and a spin-orbit coupling layer (3) made of one or more selected from heavy metal, doped heavy metal, heavy metal alloy, metal oxide, dual heavy metal layers, semiconductor material, two-dimensional semi-metal material and anti-ferromagnetic material. The spin-orbit coupling layer is configured to generate an in-plane effective field in the ferromagnetic free layer by using the interlayer exchange coupling effect and generate spin-orbit torques by using the spin Hall effect, so as to perform a deterministic data storage in the magnetic tunnel junction (2).

Classes IPC  ?

  • H10N 50/20 - Dispositifs à courant commandé à polarisation de spin
  • G11C 11/16 - Mémoires numériques caractérisées par l'utilisation d'éléments d'emmagasinage électriques ou magnétiques particuliers; Eléments d'emmagasinage correspondants utilisant des éléments magnétiques utilisant des éléments dans lesquels l'effet d'emmagasinage est basé sur l'effet de spin
  • H10B 61/00 - Dispositifs de mémoire magnétique, p.ex. dispositifs RAM magnéto-résistifs [MRAM]
  • H10N 50/85 - Matériaux actifs magnétiques
  • G06F 7/501 - Semi-additionneurs ou additionneurs complets, c. à d. cellules élémentaires d'addition pour une position

55.

DEVICE AND METHOD FOR TESTING FATIGUE CHARACTERISTICS OF SELECTOR

      
Numéro d'application 18042394
Statut En instance
Date de dépôt 2020-08-24
Date de la première publication 2023-10-19
Propriétaire INSTITUTE OF MICROELECTRONICS, CHINSE ACADEMY OF SCIENCES (Chine)
Inventeur(s)
  • Luo, Qing
  • Lv, Hangbing
  • Yu, Jie
  • Liu, Ming

Abrégé

The present disclosure discloses a device and a method for testing fatigue characteristics of a selector (210). The device includes: a voltage divider (220) and a counter (103). The voltage divider (220) is connected to a selector (210) to be tested and is configured to divide a voltage for the selector (210) to be tested during a test process. The counter (103) is connected to the selector (210) to be tested and is configured to detect voltage and/or current changes of the selector (210) to be tested.

Classes IPC  ?

  • G11C 29/54 - Dispositions pour concevoir les circuits de test, p.ex. outils de conception pour le test [DFT]
  • G11C 13/00 - Mémoires numériques caractérisées par l'utilisation d'éléments d'emmagasinage non couverts par les groupes , ou

56.

COMPLEMENTARY STORAGE UNIT AND METHOD OF PREPARING THE SAME, AND COMPLEMENTARY MEMORY

      
Numéro d'application 18042574
Statut En instance
Date de dépôt 2020-08-24
Date de la première publication 2023-10-19
Propriétaire Insitute of Microelectronics, Chinese Academy of Sciences (Chine)
Inventeur(s)
  • Luo, Qing
  • Chen, Bing
  • Lv, Hangbing
  • Liu, Ming
  • Lu, Cheng

Abrégé

A complementary storage unit and a method of preparing the same, and a complementary memory. The complementary storage unit includes: a control transistor, a pull-up diode and a pull-down diode. The control transistor is configured to control reading and writing of the storage unit. One end of the pull-up diode is connected to a positive selection line, and the other end thereof is connected to a source end of the control transistor, so as to control a high-level input. One end of the pull-down diode is connected to a negative selection line, and the other end thereof is connected to the source end of the control transistor, so as to control a low-level input. The pull-up diode and the pull-down diode are symmetrically arranged in a first direction.

Classes IPC  ?

  • G11C 11/4096 - Circuits de commande ou de gestion d'entrée/sortie [E/S, I/O] de données, p.ex. circuits pour la lecture ou l'écriture, circuits d'attaque d'entrée/sortie ou commutateurs de lignes de bits
  • G11C 11/408 - Circuits d'adressage
  • G11C 11/4094 - Circuits de commande ou de gestion de lignes de bits
  • H03K 19/017 - Modifications pour accélérer la commutation dans les circuits à transistor à effet de champ

57.

DATA TRANSMISSION DEVICE AND METHOD

      
Numéro d'application 18043479
Statut En instance
Date de dépôt 2020-08-28
Date de la première publication 2023-10-12
Propriétaire Institute of Microelectronics, Chinese Academy of Sciences (Chine)
Inventeur(s)
  • Bi, Chong
  • Liu, Ming

Abrégé

Provided are a data transmission device and a data transmission method, which are applied to a field of an information technology. The data transmission device includes: a signal conversion module (30) and a signal transmission module (20), wherein the signal conversion module (30) is configured to convert, at a data transmitting end, an electrical signal containing a data information into a magnon signal containing the data information; the signal transmission module (20) is configured to transmit the magnon signal containing the data information to a data receiving end; and the signal conversion module (30) is further configured to convert, at the data receiving end, the magnon signal containing the data information into the electrical signal containing the data information. The data transmission method includes transmitting the data by using the magnon signal, and no voltage or current is required in a process of transmitting the data.

Classes IPC  ?

58.

SEMICONDUCTOR DEVICE AND METHOD FOR MANUFACTURING THE SAME

      
Numéro d'application 18087347
Statut En instance
Date de dépôt 2022-12-22
Date de la première publication 2023-10-12
Propriétaire INSTITUTE OF MICROELECTRONICS, CHINESE ACADEMY OF SCIENCES (Chine)
Inventeur(s)
  • Li, Yongliang
  • Chen, Anlan
  • Zhao, Fei
  • Cheng, Xiaohong
  • Yin, Huaxiang
  • Luo, Jun
  • Wang, Wenwu

Abrégé

A semiconductor device and a method for manufacturing the same. The semiconductor device includes: a first gate-all-around (GAA) transistor disposed in the first region, including a first nanowire or nanosheet of at least one first layer, the at least one first layer and the substrate form a first group, among which all pairs of adjacent layers are separated by first distances, respectively; and a second GAA transistor disposed in the second region, including a second nanowire or nanosheet of at least two second layers, the at least two second layers and the substrate form a second group, among which the second layers are separated by second distances, respectively; where a minimum first distance is greater than a maximum second distance, and a quantity of the at least one first layer is less than a quantity of the at least two second layers.

Classes IPC  ?

  • H01L 29/786 - Transistors à couche mince
  • H01L 29/775 - Transistors à effet de champ avec un canal à gaz de porteurs de charge à une dimension, p.ex. FET à fil quantique
  • H01L 29/66 - Types de dispositifs semi-conducteurs
  • H01L 29/423 - Electrodes caractérisées par leur forme, leurs dimensions relatives ou leur disposition relative ne transportant pas le courant à redresser, à amplifier ou à commuter
  • H01L 29/06 - Corps semi-conducteurs caractérisés par les formes, les dimensions relatives, ou les dispositions des régions semi-conductrices

59.

NANOWIRE/NANOSHEET DEVICE HAVING SELF-ALIGNED ISOLATION PORTION AND METHOD OF MANUFACTURING THE SAME, AND ELECTRONIC APPARATUS

      
Numéro d'application 18044090
Statut En instance
Date de dépôt 2021-03-24
Date de la première publication 2023-10-05
Propriétaire INSTITUTE OF MICROELECTRONICS, CHINESE ACADEMY OF SCIENCES (Chine)
Inventeur(s) Zhu, Huilong

Abrégé

A nanowire/nanosheet device having a self-aligned isolation portion and a method of manufacturing the same, and an electronic apparatus including the nanowire/nanosheet device are provided. According to embodiments, the nanowire/nanosheet device includes: a substrate; a nanowire/nanosheet spaced apart from a surface of the substrate and extending in a first direction; a gate stack extending in a second direction to surround the nanowire/nanosheet, where the second direction intersects the first direction; a spacer formed on a sidewall of the gate stack; source/drain layers at opposite ends of the nanowire/nanosheet in the first direction and adjoining the nanowire/nanosheet; and a first isolation portion between the gate stack and the substrate, where the first isolation portion is self-aligned with the gate stack.

Classes IPC  ?

  • H01L 29/775 - Transistors à effet de champ avec un canal à gaz de porteurs de charge à une dimension, p.ex. FET à fil quantique
  • H01L 29/06 - Corps semi-conducteurs caractérisés par les formes, les dimensions relatives, ou les dispositions des régions semi-conductrices
  • H01L 29/423 - Electrodes caractérisées par leur forme, leurs dimensions relatives ou leur disposition relative ne transportant pas le courant à redresser, à amplifier ou à commuter
  • H01L 29/66 - Types de dispositifs semi-conducteurs

60.

SPIN ORBIT TORQUE MAGNETIC RANDOM ACCESS MEMORY CELL, SPIN ORBIT TORQUE MAGNETIC RANDOM ACCESS MEMORY ARRAY, AND METHOD FOR CALCULATING HAMMING DISTANCE

      
Numéro d'application 18005756
Statut En instance
Date de dépôt 2021-01-21
Date de la première publication 2023-09-07
Propriétaire INSTITUTE OF MICROELECTRONICS, CHINESE ACADEMY OF SCIENCES (Chine)
Inventeur(s)
  • Xing, Guozhong
  • Lin, Huai
  • Wang, Di
  • Liu, Long
  • Zhang, Feng
  • Xie, Changqing
  • Li, Ling
  • Liu, Ming

Abrégé

Provided are a spin orbit torque magnetic random access memory cell, a spin orbit torque magnetic random access memory array and a method for calculating a Hamming distance, wherein the spin orbit torque magnetic random access memory cell includes a magnetic tunnel junction; a first transistor, a drain terminal of the first transistor being connected to a bottom of the magnetic tunnel junction; and a second transistor, a drain terminal of the second transistor being connected to a top of the magnetic tunnel junction.

Classes IPC  ?

  • G06F 7/57 - Unités arithmétiques et logiques [UAL], c. à d. dispositions ou dispositifs pour accomplir plusieurs des opérations couvertes par les groupes  ou pour accomplir des opérations logiques
  • G11C 11/16 - Mémoires numériques caractérisées par l'utilisation d'éléments d'emmagasinage électriques ou magnétiques particuliers; Eléments d'emmagasinage correspondants utilisant des éléments magnétiques utilisant des éléments dans lesquels l'effet d'emmagasinage est basé sur l'effet de spin

61.

SOT-MRAM MEMORY CELL, MEMORY ARRAY, MEMORY, AND OPERATION METHOD

      
Numéro d'application CN2022078760
Numéro de publication 2023/164827
Statut Délivré - en vigueur
Date de dépôt 2022-03-02
Date de publication 2023-09-07
Propriétaire INSTITUTE OF MICROELECTRONICS, CHINESE ACADEMY OF SCIENCES (Chine)
Inventeur(s)
  • Xing, Guozhong
  • Liu, Long
  • Zhao, Xuefeng
  • Wang, Di
  • Lin, Huai
  • Zhang, Hao
  • Wang, Ziwei

Abrégé

The present disclosure provides an SOT-MRAM memory cell, comprising: a bottom electrode; a magnetic tunnel junction layer located on the bottom electrode; an orbital Hall effect layer located on the magnetic tunnel junction layer; a first transistor having a drain connected to the orbital Hall effect layer; and a second transistor having a drain connected to the bottom electrode. The present disclosure further provides an SOT-MRAM memory, an operation method, and an SOT-MRAM memory array.

Classes IPC  ?

  • G11C 11/16 - Mémoires numériques caractérisées par l'utilisation d'éléments d'emmagasinage électriques ou magnétiques particuliers; Eléments d'emmagasinage correspondants utilisant des éléments magnétiques utilisant des éléments dans lesquels l'effet d'emmagasinage est basé sur l'effet de spin
  • G11C 11/18 - Mémoires numériques caractérisées par l'utilisation d'éléments d'emmagasinage électriques ou magnétiques particuliers; Eléments d'emmagasinage correspondants utilisant des dispositifs à effet Hall

62.

SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD THEREOF AND ELECTRONIC APPARATUS INCLUDING THE SAME

      
Numéro d'application 18315836
Statut En instance
Date de dépôt 2023-05-11
Date de la première publication 2023-09-07
Propriétaire INSTITUTE OF MICROELECTRONICS, CHINESE ACADEMY OF SCIENCES (Chine)
Inventeur(s) Zhu, Huilong

Abrégé

A compact vertical semiconductor device and a manufacturing method thereof, and an electronic apparatus including the semiconductor device are provided. According to the embodiments, the vertical semiconductor device may include: a plurality of vertical unit devices stacked on each other, in which the unit devices include respective gate stacks extending in a lateral direction, and each of the gate stacks includes a main body, an end portion, and a connection portion located between the main body and the end portion, and in a top view, a periphery of the connection portion is recessed relative to peripheries of the main body and the end portion; and a contact portion located on the end portion of each of the gate stacks, in which the contact portion is in contact with the end portion.

Classes IPC  ?

  • H01L 29/78 - Transistors à effet de champ l'effet de champ étant produit par une porte isolée
  • H01L 21/8234 - Technologie MIS
  • H01L 27/088 - Dispositifs consistant en une pluralité de composants semi-conducteurs ou d'autres composants à l'état solide formés dans ou sur un substrat commun comprenant des éléments de circuit passif intégrés avec au moins une barrière de potentiel ou une barrière de surface le substrat étant un corps semi-conducteur comprenant uniquement des composants semi-conducteurs d'un seul type comprenant uniquement des composants à effet de champ les composants étant des transistors à effet de champ à porte isolée
  • H01L 29/423 - Electrodes caractérisées par leur forme, leurs dimensions relatives ou leur disposition relative ne transportant pas le courant à redresser, à amplifier ou à commuter
  • H01L 29/45 - Electrodes à contact ohmique

63.

RECONFIGURABLE NEURON DEVICE BASED ON ION GATE REGULATION AND MANUFACTURING METHOD THEREFOR

      
Numéro d'application CN2022078959
Numéro de publication 2023/164860
Statut Délivré - en vigueur
Date de dépôt 2022-03-03
Date de publication 2023-09-07
Propriétaire INSTITUTE OF MICROELECTRONICS, CHINESE ACADEMY OF SCIENCES (Chine)
Inventeur(s)
  • Zhao, Xuefeng
  • Xing, Guozhong
  • Wang, Di
  • Wang, Ziwei
  • Liu, Long
  • Lin, Huai
  • Zhang, Hao

Abrégé

The present disclosure relates to the technical field of artificial neuron memory devices, and provides a reconfigurable neuron device based on ion gate regulation and a manufacturing method therefor. The device comprises: a synthetic antiferromagnetic layer, a metal oxide layer, an ionic liquid layer, and a top electrode layer stacked in sequence from bottom to top. The two opposite edges of the bottom end of the synthetic antiferromagnetic layer are provided with a left boundary antiferromagnetic layer and a right boundary antiferromagnetic layer having opposite magnetization directions, and a magnetic tunnel junction for outputting a spike signal is further provided in the middle of the bottom end of the synthetic antiferromagnetic layer. The metal oxide layer, the ionic liquid layer, and the top electrode layer constitute an ion gate, and the ionic liquid layer comprises positive ions and negative ions. When an input voltage is applied to the top electrode layer, oxygen ions in the metal oxide layer move along with the distribution of the positive ions and the negative ions in the ionic liquid layer to adjust the charge accumulation of a top interface of the synthetic antiferromagnetic layer, so as to regulate the leakage motion speed of a magnetic domain wall at the bottom of the synthetic antiferromagnetic layer by means of an RKKY action.

Classes IPC  ?

  • H01L 43/00 - Dispositifs utilisant les effets galvanomagnétiques ou des effets magnétiques analogues; Procédés ou appareils spécialement adaptés à la fabrication ou au traitement de ces dispositifs ou de leurs parties constitutives
  • H01L 43/08 - Résistances commandées par un champ magnétique
  • H01L 43/12 - Procédés ou appareils spécialement adaptés à la fabrication ou le traitement de ces dispositifs ou de leurs parties constitutives
  • G06N 3/063 - Réalisation physique, c. à d. mise en œuvre matérielle de réseaux neuronaux, de neurones ou de parties de neurone utilisant des moyens électroniques

64.

SPIN ORBIT TORQUE MAGNETIC RANDOM ACCESS MEMORY CELL, MEMORY ARRAY, AND MEMORY

      
Numéro d'application 18003038
Statut En instance
Date de dépôt 2020-06-24
Date de la première publication 2023-08-31
Propriétaire Institute of Microelectronics, Chinese Academy of Sciences (Chine)
Inventeur(s)
  • Xing, Guozhong
  • Lin, Huai
  • Liu, Ming

Abrégé

Provided are a spin orbit torque magnetic random access memory cell, a memory array and a memory, wherein the spin orbit torque magnetic random access memory cell includes: a magnetic tunnel and a selector; the selector is a two-dimensional material based selector; the magnetic tunnel junction is arranged above or below the selector; the magnetic tunnel junction includes an antiferromagnetic layer and a free layer; the free layer is adjacent to the antiferromagnetic layer; when the selector is turned on, the memory cell is conducted, a current generates a spin current which is injected into the free layer, and a magnetization direction of the free layer is switched by the exchange bias effect between the free layer and the antiferromagnetic layer. A deterministic magnetization switching of SOT-MRAM memory cell under zero magnetic field at room temperature may be implemented without an external magnetic field by using the exchange bias effect and applying an optimized bias voltage of the magnetic tunnel junction, so as to achieve a purpose of data writing and implement SOT-MRAM memory cell with double terminal structure.

Classes IPC  ?

  • H10B 61/00 - Dispositifs de mémoire magnétique, p.ex. dispositifs RAM magnéto-résistifs [MRAM]
  • H10N 52/85 - Matériaux actifs magnétiques

65.

SYMMETRIC MEMORY CELL AND BNN CIRCUIT

      
Numéro d'application 18005101
Statut En instance
Date de dépôt 2020-08-24
Date de la première publication 2023-08-24
Propriétaire INSTITUTE OF MICROELECTRONICS, CHINESE ACADEMY OF SCIENCES (Chine)
Inventeur(s)
  • Luo, Qing
  • Chen, Bing
  • Lv, Hangbing
  • Liu, Ming
  • Lu, Cheng

Abrégé

Provided are a symmetric memory cell and a BNN circuit. The symmetric memory cell includes a first complementary structure and a second complementary structure, the second complementary structure being symmetrically connected to the first complementary structure in a first direction, wherein the first complementary structure includes a first control transistor configured to be connected to the second complementary structure, the second complementary structure includes a second control transistor, a drain electrode of the second control transistor and a drain electrode of the first control transistor being symmetrically arranged in the first direction and connected to a bit line, and the symmetric memory cell is configured to store a weight value 1 or 0.

Classes IPC  ?

  • G11C 11/4096 - Circuits de commande ou de gestion d'entrée/sortie [E/S, I/O] de données, p.ex. circuits pour la lecture ou l'écriture, circuits d'attaque d'entrée/sortie ou commutateurs de lignes de bits
  • G11C 11/408 - Circuits d'adressage
  • G11C 11/4094 - Circuits de commande ou de gestion de lignes de bits
  • H03K 19/017 - Modifications pour accélérer la commutation dans les circuits à transistor à effet de champ

66.

NOR-TYPE MEMORY DEVICE, METHOD OF MANUFACTURING NOR-TYPE MEMORY DEVICE, AND ELECTRONIC APPARATUS INCLUDING MEMORY DEVICE

      
Numéro d'application 18041085
Statut En instance
Date de dépôt 2022-07-05
Date de la première publication 2023-08-24
Propriétaire INSTITUTE OF MICROELECTRONICS, CHINESE ACADEMY OF SCIENCES (Chine)
Inventeur(s) Zhu, Huilong

Abrégé

Disclosed are a NOR-type memory device, a method of manufacturing the NOR-type memory device, and an electronic apparatus including the NOR-type memory device. The NOR-type memory device may include: a first gate stack extending vertically on a substrate, and a gate conductor layer and a memory functional layer; a first semiconductor layer surrounding a periphery of the first gate stack, extending along a sidewall of the first gate stack, and a first source/drain region, a first channel region and a second source/drain region arranged vertically in sequence; a conductive shielding layer surrounding a periphery of the first channel region; and a dielectric layer between the first channel region and the conductive shielding layer. The memory functional layer is located between the first semiconductor layer and the gate conductor layer. A memory cell is defined at an intersection of the first gate stack and the first semiconductor layer.

Classes IPC  ?

  • H10B 43/27 - Dispositifs EEPROM avec des isolants de grille à piégeage de charge caractérisés par les agencements tridimensionnels, p ex. avec des cellules à des niveaux différents de hauteur la région de source et la région de drain étant à différents niveaux, p.ex. avec des canaux inclinés les canaux comprenant des parties verticales, p.ex. des canaux en forme de U
  • H10B 43/10 - Dispositifs EEPROM avec des isolants de grille à piégeage de charge caractérisés par la configuration vue du dessus
  • H01L 23/528 - Configuration de la structure d'interconnexion
  • H10B 51/10 - Dispositifs de RAM ferro-électrique [FeRAM] comprenant des transistors ferro-électriques de mémoire caractérisés par la configuration vue du dessus
  • H10B 51/20 - Dispositifs de RAM ferro-électrique [FeRAM] comprenant des transistors ferro-électriques de mémoire caractérisés par les agencements tridimensionnels, p ex. avec des cellules à des niveaux différents de hauteur
  • H01L 29/06 - Corps semi-conducteurs caractérisés par les formes, les dimensions relatives, ou les dispositions des régions semi-conductrices
  • H01L 29/775 - Transistors à effet de champ avec un canal à gaz de porteurs de charge à une dimension, p.ex. FET à fil quantique
  • H01L 29/66 - Types de dispositifs semi-conducteurs
  • H01L 29/786 - Transistors à couche mince
  • H01L 29/423 - Electrodes caractérisées par leur forme, leurs dimensions relatives ou leur disposition relative ne transportant pas le courant à redresser, à amplifier ou à commuter

67.

MAGNETORESISTIVE DEVICE, METHOD FOR CHANGING RESISTANCE STATE THEREOF, AND SYNAPSE LEARNING MODULE

      
Numéro d'application 18003913
Statut En instance
Date de dépôt 2020-12-31
Date de la première publication 2023-08-17
Propriétaire INSTITUTE OF MICROELECTRONICS, CHINESE ACADEMY OF SCIENCES (Chine)
Inventeur(s)
  • Xing, Guozhong
  • Wang, Di
  • Lin, Huai
  • Liu, Long
  • Liu, Yu
  • Lv, Hangbing
  • Xie, Changqing
  • Li, Ling
  • Liu, Ming

Abrégé

The present disclosure relates to a field of memory technical, and in particular to a magnetoresistive device, a method for changing a resistance state of the magnetoresistive device, and a synapse learning module. The magnetoresistive device includes a top electrode, a ferromagnetic reference layer, a tunneling layer, a ferromagnetic free layer, a spin-orbit coupling layer, and a bottom electrode that are arranged in sequence along a preset direction, where the spin-orbit coupling layer includes a first thickness region and a second thickness region distributed alternately, and a thickness of the first thickness region is different form a thickness of the second thickness region; and the ferromagnetic free layer includes a pinning region, and a position of the pinning region is in one-to-one correspondence with a position of the first thickness region.

Classes IPC  ?

  • H10N 50/10 - Dispositifs magnéto-résistifs
  • H10B 61/00 - Dispositifs de mémoire magnétique, p.ex. dispositifs RAM magnéto-résistifs [MRAM]
  • H10N 50/85 - Matériaux actifs magnétiques
  • G11C 11/16 - Mémoires numériques caractérisées par l'utilisation d'éléments d'emmagasinage électriques ou magnétiques particuliers; Eléments d'emmagasinage correspondants utilisant des éléments magnétiques utilisant des éléments dans lesquels l'effet d'emmagasinage est basé sur l'effet de spin

68.

SEMICONDUCTOR DEVICE HAVING HIGH DRIVING CAPABILITY AND STEEP SS CHARACTERISTIC AND METHOD OF MANUFACTURING THE SAME

      
Numéro d'application 18059960
Statut En instance
Date de dépôt 2022-11-29
Date de la première publication 2023-08-17
Propriétaire INSTITUTE OF MICROELECTRONICS, CHINESE ACADEMY OF SCIENCES (Chine)
Inventeur(s)
  • Li, Yongliang
  • Cheng, Xiaohong
  • Zhao, Fei
  • Luo, Jun
  • Wang, Wenwu

Abrégé

A semiconductor device and a method of manufacturing the same are disclosed. The semiconductor device includes: a substrate and a channel portion. The channel portion includes a first portion including a fin-shaped structure protruding with respect to the substrate and a second portion located above the first portion and spaced apart from the first portion. The second portion includes one or more nanowires or nanosheets spaced apart from each other. Source/drain portions are arranged on two opposite sides of the channel portion in a first direction and in contact with the channel portion. A gate stack extends on the substrate in a second direction intersecting with the first direction, so as to intersect with the channel portion.

Classes IPC  ?

  • H01L 29/06 - Corps semi-conducteurs caractérisés par les formes, les dimensions relatives, ou les dispositions des régions semi-conductrices
  • H01L 29/423 - Electrodes caractérisées par leur forme, leurs dimensions relatives ou leur disposition relative ne transportant pas le courant à redresser, à amplifier ou à commuter
  • H01L 29/66 - Types de dispositifs semi-conducteurs
  • H01L 29/775 - Transistors à effet de champ avec un canal à gaz de porteurs de charge à une dimension, p.ex. FET à fil quantique
  • H01L 29/78 - Transistors à effet de champ l'effet de champ étant produit par une porte isolée

69.

METALLIZATION STACK AND METHOD OF MANUFACTURING THE SAME, AND ELECTRONIC DEVICE INCLUDING METALLIZATION STACK

      
Numéro d'application 18300719
Statut En instance
Date de dépôt 2023-04-14
Date de la première publication 2023-08-10
Propriétaire Institute Of Microelectronics, Chinese Academy Of Sciences (Chine)
Inventeur(s) Zhu, Huilong

Abrégé

A metallization stack is provided. The metallization stack may include at least one interconnection line layer and at least one via hole layer arranged alternately on a substrate. At least one pair of adjacent interconnection line layer and via hole layer in the metallization stack includes an interconnection line in the interconnection line layer; and a via hole in the via hole layer. The via hole layer is arranged closer to the substrate than the interconnection line layer, and at least part of the interconnection line extends longitudinally in a first direction, and a sidewall of the at least part of the interconnection line in the first direction is substantially coplanar with at least upper portion of a corresponding sidewall of the via hole under the at least part of the interconnection line.

Classes IPC  ?

  • H01L 23/528 - Configuration de la structure d'interconnexion
  • H01L 21/768 - Fixation d'interconnexions servant à conduire le courant entre des composants distincts à l'intérieur du dispositif
  • H01L 23/522 - Dispositions pour conduire le courant électrique à l'intérieur du dispositif pendant son fonctionnement, d'un composant à un autre comprenant des interconnexions externes formées d'une structure multicouche de couches conductrices et isolantes inséparables du corps semi-conducteur sur lequel elles ont été déposées

70.

CACHE MEMORY AND METHOD OF ITS MANUFACTURE

      
Numéro d'application 18004968
Statut En instance
Date de dépôt 2020-07-20
Date de la première publication 2023-08-03
Propriétaire INSTITUTE OF MICROELECTRONICS, CHINESE ACADEMY OF SCIENCES (Chine)
Inventeur(s)
  • Bi, Chong
  • Liu, Ming

Abrégé

Provided is a cache memory, including: a first field-effect transistor, a field-like spin torque layer underneath a magnetic tunnel junction, an electrode, and a second field-effect transistor sequentially arranged and connected; wherein the first field-effect transistor is configured to provide a writing current and to control the on-off of the writing current through a gate electrode; the field-like spin torque layer is configured to generate field-like spin torques for switching a first ferromagnetic layer of the magnetic tunnel junction; the magnetic tunnel junction includes a first ferromagnetic layer, a tunneling layer, a second ferromagnetic layer and a pinning layer arranged sequentially; the electrode is configured to connect the cache memory with the second field-effect transistor; and the second field-effect transistor is configured to control the on-off of the second field-effect transistor through the gate electrode to read the resistive state of the magnetic tunnel junction.

Classes IPC  ?

  • G11C 11/16 - Mémoires numériques caractérisées par l'utilisation d'éléments d'emmagasinage électriques ou magnétiques particuliers; Eléments d'emmagasinage correspondants utilisant des éléments magnétiques utilisant des éléments dans lesquels l'effet d'emmagasinage est basé sur l'effet de spin
  • H10B 61/00 - Dispositifs de mémoire magnétique, p.ex. dispositifs RAM magnéto-résistifs [MRAM]
  • H10N 50/20 - Dispositifs à courant commandé à polarisation de spin
  • H10N 50/80 - Dispositifs galvanomagnétiques - Détails de structure
  • H10N 50/85 - Matériaux actifs magnétiques
  • H10N 50/01 - Fabrication ou traitement

71.

PHOTOLITHOGRAPHY DEVICE, GAS BATH APPARATUS AND GAS BATH GENERATOR THEREOF

      
Numéro d'application CN2022137428
Numéro de publication 2023/138251
Statut Délivré - en vigueur
Date de dépôt 2022-12-08
Date de publication 2023-07-27
Propriétaire INSTITUTE OF MICROELECTRONICS, CHINESE ACADEMY OF SCIENCES (Chine)
Inventeur(s)
  • Wang, Kuibo
  • Wu, Xiaobin
  • Han, Xiaoquan
  • Luo, Yan
  • Sha, Pengfei
  • Li, Hui
  • Sun, Jiazheng
  • Xie, Wanlu
  • Ma, He
  • Tan, Fangrui

Abrégé

The present invention provides a photolithography device, a gas bath apparatus and a gas bath generator thereof. The gas bath generator comprises a closed annular body. The closed annular body is arranged around a working area. An annular flow channel is formed in the closed annular body. The closed annular body is further provided with circumferentially distributed gas outlets in communication with the annular flow channel. By means of the gas outlets, a closed airflow layer distributed around the working area is generated. The gas bath generator provided by the present invention can be used for a photolithography device and circumferentially arranged around an exposure area of the photolithography device to form a closed airflow layer isolating the exposure area from the outside around the periphery of the exposure area. The present invention solves the problem of how to reduce gas contamination and particle contamination in the silicon wafer microenvironment located in the exposure area of the photolithography device.

Classes IPC  ?

  • G03F 7/20 - Exposition; Appareillages à cet effet

72.

THREE-DIMENSIONAL RESERVOIR BASED ON VOLATILE THREE-DIMENSIONAL MEMRISTOR AND MANUFACTURING METHOD THEREFOR

      
Numéro d'application CN2022080060
Numéro de publication 2023/137844
Statut Délivré - en vigueur
Date de dépôt 2022-03-10
Date de publication 2023-07-27
Propriétaire INSTITUTE OF MICROELECTRONICS, CHINESE ACADEMY OF SCIENCES (Chine)
Inventeur(s)
  • Xu, Xiaoxin
  • Sun, Wenxuan
  • Yu, Jie
  • Zhang, Woyu
  • Dong, Danian
  • Lai, Jinru
  • Zheng, Xu
  • Shang, Dashan

Abrégé

The present invention provides a three-dimensional reservoir based on a volatile three-dimensional memristor and a manufacturing method therefor. A storage layer, a selection layer and an electrode layer in each through hole in a three-dimensional reservoir form a memristor, i.e., form a reservoir unit, and a three-dimensional reservoir based on a volatile three-dimensional memristor is formed based on a stack structure and a plurality of through holes. Specifically, in the present invention, virtual nodes generated on the basis of the dynamic characteristics of a three-dimensional memristor are used to construct a three-dimensional reservoir. First, an interfacial memristor is constructed and the volatile characteristics thereof are confirmed by means of electrical tests; a vertical three-dimensional array is prepared on the basis of the volatile memristor, and the dynamic characteristics of the device are adjusted by means of a Schottky barrier, different layers of the three-dimensional reservoir respectively corresponding to reservoirs of different layers. Different reservoirs are constructed by respectively regulating devices of different layers, thereby increasing the richness of the virtual nodes, improving the parallelism and the recognition accuracy of a system, and reducing the area of the system.

Classes IPC  ?

  • H01L 27/24 - Dispositifs consistant en une pluralité de composants semi-conducteurs ou d'autres composants à l'état solide formés dans ou sur un substrat commun comprenant des composants à l'état solide pour le redressement, l'amplification ou la commutation, sans barrière de potentiel ni barrière de surface

73.

SEMICONDUCTOR DEVICE, FABRICATION METHOD FOR SAME, AND ELECTRONIC DEVICE COMPRISING SAME

      
Numéro d'application 17995907
Statut En instance
Date de dépôt 2021-03-10
Date de la première publication 2023-07-13
Propriétaire INSTITUTE OF MICROELECTRONICS, CHINESE ACADEMY OF SCIENCES (Chine)
Inventeur(s) Zhu, Huilong

Abrégé

Provided are a semiconductor device, a method of manufacturing the semiconductor device, and an electronic apparatus including the semiconductor device. According to the embodiments, the semiconductor device may include: a vertical structure extending in a vertical direction relative to a substrate; and a nanosheet extending from the vertical structure and spaced apart from the substrate in the vertical direction, wherein the nanosheet includes a first portion in a first orientation, and at least one of an upper surface and a lower surface of the first portion is not parallel to a horizontal surface of the substrate.

Classes IPC  ?

  • H01L 29/10 - Corps semi-conducteurs caractérisés par les formes, les dimensions relatives, ou les dispositions des régions semi-conductrices avec des régions semi-conductrices connectées à une électrode ne transportant pas le courant à redresser, amplifier ou commuter, cette électrode faisant partie d'un dispositif à semi-conducteur qui comporte trois électrodes ou plus
  • H01L 27/092 - Transistors à effet de champ métal-isolant-semi-conducteur complémentaires
  • H01L 29/06 - Corps semi-conducteurs caractérisés par les formes, les dimensions relatives, ou les dispositions des régions semi-conductrices
  • H01L 29/423 - Electrodes caractérisées par leur forme, leurs dimensions relatives ou leur disposition relative ne transportant pas le courant à redresser, à amplifier ou à commuter
  • H01L 29/49 - Electrodes du type métal-isolant-semi-conducteur
  • H01L 29/775 - Transistors à effet de champ avec un canal à gaz de porteurs de charge à une dimension, p.ex. FET à fil quantique
  • H01L 21/8238 - Transistors à effet de champ complémentaires, p.ex. CMOS
  • H01L 29/66 - Types de dispositifs semi-conducteurs

74.

VERTICAL SEMICONDUCTOR DEVICE HAVING CONDUCTIVE LAYER, METHOD OF MANUFACTURING VERTICAL SEMICONDUCTOR DEVICE, AND ELECTRONIC DEVICE

      
Numéro d'application 18009410
Statut En instance
Date de dépôt 2021-03-23
Date de la première publication 2023-07-13
Propriétaire INSTITUTE OF MICROELECTRONICS, CHINESE ACADEMY OF SCIENCES (Chine)
Inventeur(s) Zhu, Huilong

Abrégé

Disclosed are a vertical semiconductor device having a conductive layer, a method of manufacturing the vertical semiconductor device, and an electronic device including the vertical semiconductor device. According to an embodiment, the semiconductor device may include: a substrate; a first metallic layer, a channel layer and a second metallic layer which are sequentially disposed on the substrate; and a gate stack formed around at least a part of a periphery of the channel layer, wherein each of the first metallic layer, the second metallic layer, and the channel layer is of single crystal structure.

Classes IPC  ?

  • H01L 29/423 - Electrodes caractérisées par leur forme, leurs dimensions relatives ou leur disposition relative ne transportant pas le courant à redresser, à amplifier ou à commuter
  • H01L 29/786 - Transistors à couche mince
  • H01L 29/06 - Corps semi-conducteurs caractérisés par les formes, les dimensions relatives, ou les dispositions des régions semi-conductrices
  • H01L 29/66 - Types de dispositifs semi-conducteurs
  • H01L 29/775 - Transistors à effet de champ avec un canal à gaz de porteurs de charge à une dimension, p.ex. FET à fil quantique
  • H01L 27/088 - Dispositifs consistant en une pluralité de composants semi-conducteurs ou d'autres composants à l'état solide formés dans ou sur un substrat commun comprenant des éléments de circuit passif intégrés avec au moins une barrière de potentiel ou une barrière de surface le substrat étant un corps semi-conducteur comprenant uniquement des composants semi-conducteurs d'un seul type comprenant uniquement des composants à effet de champ les composants étant des transistors à effet de champ à porte isolée
  • H01L 21/8234 - Technologie MIS

75.

HARDWARE IMPLEMENTATION METHOD AND APPARATUS FOR RESERVOIR COMPUTING MODEL BASED ON RANDOM RESISTOR ARRAY, AND ELECTRONIC DEVICE

      
Numéro d'application CN2022112493
Numéro de publication 2023/130725
Statut Délivré - en vigueur
Date de dépôt 2022-08-15
Date de publication 2023-07-13
Propriétaire INSTITUTE OF MICROELECTRONICS, CHINESE ACADEMY OF SCIENCES (Chine)
Inventeur(s)
  • Shang, Dashan
  • Li, Yi
  • Zhang, Woyu
  • Wang, Shaocong
  • Wang, Zhongrui

Abrégé

A hardware implementation method and apparatus for a reservoir computing model based on a random resistor array, and an electronic device, which relate to the fields of machine learning and artificial intelligence. The method comprises: acquiring a random weight of a reservoir layer, which is generated on the basis of a resistance-variable device crossbar array; applying a breakdown voltage to the resistance-variable device crossbar array, so as to form a randomly distributed random resistance matrix; converting an input signal into a read voltage signal by means of a circuit of a printed circuit board, and performing, on the basis of the read voltage signal and the random resistance matrix, vector matrix multiplication to determine an output voltage signal; and repeating the step of converting an input signal into a read voltage signal by means of the circuit of the printed circuit board and performing, on the basis of the read voltage signal and the random resistance matrix, vector matrix multiplication to determine an output voltage signal, and then simulating a loop iteration process of the reservoir layer. Therefore, the efficient hardware realization of a large-scale random weight and a reservoir computing model is achieved, and in an edge computing application scenario in which the computing power is limited, the possibility is provided for the efficient hardware realization of the reservoir computing model.

Classes IPC  ?

  • G06N 3/063 - Réalisation physique, c. à d. mise en œuvre matérielle de réseaux neuronaux, de neurones ou de parties de neurone utilisant des moyens électroniques

76.

Parallel structure, method of manufacturing the same, and electronic device including the same

      
Numéro d'application 18172802
Numéro de brevet 11942474
Statut Délivré - en vigueur
Date de dépôt 2023-02-22
Date de la première publication 2023-07-06
Date d'octroi 2024-03-26
Propriétaire INSTITUTE OF MICROELECTRONICS, CHINESE ACADEMY OF SCIENCES (Chine)
Inventeur(s) Zhu, Huilong

Abrégé

A method of manufacturing a parallel structure of semiconductor devices includes: disposing a semiconductor stack, which includes source/drain layers disposed vertically in sequence and channel layers therebetween, on a substrate; patterning the semiconductor stack into a predetermined shape to define an active region; forming gate stacks around at least part of peripheries of the channel layers; forming an isolation layer on peripheries of the active region and the gate stack; forming first to third conductive channels on a sidewall of the isolation layer; determining the pre-determined shape and a shape of the gate stacks, such that one of the source/drain layers on two sides of the channel layer passes through the isolation layer to contact the first conductive channel, while the other one passes through the isolation layer to contact the second conductive channel, and the gate stack passes through the isolation layer to contact the third conductive channel.

Classes IPC  ?

  • H01L 29/66 - Types de dispositifs semi-conducteurs
  • H01L 21/77 - Fabrication ou traitement de dispositifs consistant en une pluralité de composants à l'état solide ou de circuits intégrés formés dans ou sur un substrat commun
  • H01L 25/065 - Ensembles consistant en une pluralité de dispositifs à semi-conducteurs ou d'autres dispositifs à l'état solide les dispositifs étant tous d'un type prévu dans le même sous-groupe des groupes , ou dans une seule sous-classe de , , p.ex. ensembles de diodes redresseuses les dispositifs n'ayant pas de conteneurs séparés les dispositifs étant d'un type prévu dans le groupe
  • H01L 27/088 - Dispositifs consistant en une pluralité de composants semi-conducteurs ou d'autres composants à l'état solide formés dans ou sur un substrat commun comprenant des éléments de circuit passif intégrés avec au moins une barrière de potentiel ou une barrière de surface le substrat étant un corps semi-conducteur comprenant uniquement des composants semi-conducteurs d'un seul type comprenant uniquement des composants à effet de champ les composants étant des transistors à effet de champ à porte isolée
  • H01L 29/78 - Transistors à effet de champ l'effet de champ étant produit par une porte isolée

77.

METHOD FOR PREPARING RESERVOIR ELEMENT

      
Numéro d'application CN2022080856
Numéro de publication 2023/115723
Statut Délivré - en vigueur
Date de dépôt 2022-03-15
Date de publication 2023-06-29
Propriétaire INSTITUTE OF MICROELECTRONICS, CHINESE ACADEMY OF SCIENCES (Chine)
Inventeur(s)
  • Xu, Xiaoxin
  • Sun, Wenxuan
  • Yu, Jie
  • Lai, Jinru
  • Zheng, Xu
  • Dong, Danian

Abrégé

The present invention belongs to the technical field of artificial intelligence, and particularly relates to a method for preparing a reservoir element. The method comprises the following steps: a) sequentially arranging, on a substrate, a bottom electrode layer, a dielectric layer, a resistive layer and a top electrode layer, so as to obtain a reservoir element to be annealed; and b) performing annealing processing on the reservoir element to be annealed, so as to obtain a reservoir element, wherein the temperature of the annealing processing ranges from 300ºC to 700ºC, and the time of the annealing processing ranges from 30s to 100s. In the method provided in the present invention, after being prepared, the reservoir element is subjected to rapid annealing processing, such that defects are re-distributed after rapid annealing, thereby forming a more stable membrane; and a ferroelectric O phase can also be introduced into the membrane. By means of rapid annealing processing, the power consumption of a reservoir element can be effectively reduced, and the computing accuracy can be improved.

Classes IPC  ?

  • H01L 45/00 - Dispositifs à l'état solide spécialement adaptés pour le redressement, l'amplification, la production d'oscillations ou la commutation, sans barrière de potentiel ni barrière de surface, p.ex. triodes diélectriques; Dispositifs à effet Ovshinsky; Procédés ou appareils spécialement adaptés à la fabrication ou au traitement de ces dispositifs ou de leurs parties constitutives

78.

MEMORY CELL STRUCTURE, MEMORY ARRAY STRUCTURE, AND VOLTAGE BIASING METHOD

      
Numéro d'application 17996194
Statut En instance
Date de dépôt 2020-04-14
Date de la première publication 2023-06-22
Propriétaire INSTITUTE OF MICROELECTRONICS, CHINESE ACADEMY OF SCIENCES (Chine)
Inventeur(s)
  • Lv, Hangbing
  • Yang, Jianguo
  • Xu, Xiaoxin
  • Liu, Ming

Abrégé

Provided are a memory cell structure, a memory array structure, and a voltage biasing method. The memory cell structure includes: a substrate layer, a well layer and a transistor. The substrate layer is configured to support the memory cell structure; the well layer is embedded in the substrate layer, an upper surface of the well layer is flush with an upper surface of the substrate layer, and a transistor is arranged on the well layer. In the present disclosure, a deep well bias is performed on the memory cell structure, so that the well voltage of the memory cell may be individually biased to a specific voltage, and in combination with the redesigned memory cell array structure, the applied programming voltage mostly falls on the memory cell structure. This reduces the programming voltage of the memory cell, and avoids a breakdown of the selecting transistor due to an excessively large voltage, thereby ensuring a great reliability of the device and a higher efficiency within the area of the memory cell array structure.

Classes IPC  ?

  • G11C 13/00 - Mémoires numériques caractérisées par l'utilisation d'éléments d'emmagasinage non couverts par les groupes , ou

79.

SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD THEREFOR

      
Numéro d'application CN2021140813
Numéro de publication 2023/108785
Statut Délivré - en vigueur
Date de dépôt 2021-12-23
Date de publication 2023-06-22
Propriétaire
  • BEIJING SUPERSTRING ACADEMY OF MEMORY TECHNOLOGY (Chine)
  • INSTITUTE OF MICROELECTRONICS, CHINESE ACADEMY OF SCIENCES (Chine)
Inventeur(s)
  • Huang, Weixing
  • Zhu, Huilong

Abrégé

Provided in the embodiments of the present application are a semiconductor device and a manufacturing method therefor. The semiconductor device comprises a substrate, a first electrode layer, a functional layer and a second electrode layer, wherein the functional layer is located between the first electrode layer and the second electrode layer, the functional layer comprises a first area, and a second area which surrounds the first area and is of a U-shaped structure, and the orientation of a U-shaped opening of the second area is parallel to the substrate and faces away from the first area, that is, the U-shaped opening faces an outer side; the material of the first area at least comprises germanium; and the second area comprises a U-shaped ferroelectric layer and a U-shaped gate electrode which are sequentially stacked. In the embodiments of the present application, a ferroelectric layer of a U-shaped structure is used as a storage layer of a memory device, and when a gate voltage is kept unchanged, a U-shaped channel can increase an electric field of the ferroelectric layer, thereby increasing a storage window of the whole semiconductor device; and when the storage window of the whole semiconductor device is kept unchanged, the gate voltage can be reduced, thereby reducing the power consumption of the semiconductor device, and improving the performance of the memory device.

Classes IPC  ?

  • H01L 29/78 - Transistors à effet de champ l'effet de champ étant produit par une porte isolée
  • H01L 21/336 - Transistors à effet de champ à grille isolée

80.

SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD THEREFOR

      
Numéro d'application CN2021141028
Numéro de publication 2023/108789
Statut Délivré - en vigueur
Date de dépôt 2021-12-24
Date de publication 2023-06-22
Propriétaire
  • BEIJING SUPERSTRING ACADEMY OF MEMORY TECHNOLOGY (Chine)
  • INSTITUTE OF MICROELECTRONICS, CHINESE ACADEMY OF SCIENCES (Chine)
Inventeur(s)
  • Liu, Ziyi
  • Zhu, Huilong

Abrégé

The present application provides a semiconductor device and a manufacturing method therefor. The method comprises: providing a substrate, wherein the substrate is provided with a first source-drain layer, a channel layer and a second source-drain layer that are sequentially stacked, and the periphery of the channel layer is provided with a gate dielectric layer and a gate structure which surround the channel layer in the horizontal direction; forming a spacer layer on the outer side wall of the gate structure; etching the gate structure, so as to reduce the thickness of the gate structure; forming a sacrificial structure covering the gate structure, and a covering layer covering the second source-drain layer, the sacrificial structure and the spacer layer, so that the sacrificial structure is located on the periphery of the second source-drain layer and located on the inner side of the spacer layer; then etching the covering layer to obtain a first contact hole passing through the sacrificial structure, and removing the sacrificial structure at the bottom of the first contact hole to form a gap below the first contact hole; and forming first contact structures in the first contact hole and the gap, thereby realizing self-alignment of the bottoms of the first contact structures and the gate structure, and improving the reliability of a device.

Classes IPC  ?

  • H01L 29/423 - Electrodes caractérisées par leur forme, leurs dimensions relatives ou leur disposition relative ne transportant pas le courant à redresser, à amplifier ou à commuter
  • H01L 29/78 - Transistors à effet de champ l'effet de champ étant produit par une porte isolée
  • H01L 21/336 - Transistors à effet de champ à grille isolée

81.

NANOWIRE/SHEET DEVICE WITH ALTERNATIVE SIDE WALL AND MANUFACTURING METHOD THEREFOR, AND ELECTRONIC EQUIPMENT

      
Numéro d'application CN2022076616
Numéro de publication 2023/108884
Statut Délivré - en vigueur
Date de dépôt 2022-02-17
Date de publication 2023-06-22
Propriétaire INSTITUTE OF MICROELECTRONICS, CHINESE ACADEMY OF SCIENCES (Chine)
Inventeur(s) Zhu, Huilong

Abrégé

Disclosed are a nanowire/sheet device and a manufacturing method therefor, and electronic equipment comprising the nanowire/sheet device. According to embodiments, the nanowire/sheet device comprises: a substrate; a nanowire/sheet spaced apart from the surface of the substrate and extending in a first direction; a source/drain layer located at two opposite ends of the nanowire/sheet in the first direction and connected to the nanowire/sheet; a gate stack extending in a second direction intersecting the first direction to surround the nanowires/sheet; and a first side wall disposed on a sidewall of the gate stack, wherein the first side wall comprises a continuously extending material layer having a first portion along the surface of the nanowire/sheet, a second portion along a sidewall of the source/drain layer facing the gate stack, and a third portion along the sidewall of the gate stack facing the source/drain layer, with a slot or interface between the second portion and the third portion.

Classes IPC  ?

  • H01L 29/06 - Corps semi-conducteurs caractérisés par les formes, les dimensions relatives, ou les dispositions des régions semi-conductrices
  • H01L 29/78 - Transistors à effet de champ l'effet de champ étant produit par une porte isolée
  • H01L 21/336 - Transistors à effet de champ à grille isolée

82.

SEMICONDUCTOR DEVICE AND METHOD FOR MANUFACTURING SAME

      
Numéro d'application CN2021140812
Numéro de publication 2023/108784
Statut Délivré - en vigueur
Date de dépôt 2021-12-23
Date de publication 2023-06-22
Propriétaire
  • BEIJING SUPERSTRING ACADEMY OF MEMORY TECHNOLOGY (Chine)
  • INSTITUTE OF MICROELECTRONICS, CHINESE ACADEMY OF SCIENCES (Chine)
Inventeur(s)
  • Huang, Weixing
  • Zhu, Huilong

Abrégé

Provided in the embodiments of the present application are a semiconductor device and a method for manufacturing same. The method comprises: sequentially forming a first electrode layer, a semiconductor layer and a second electrode layer on a substrate; then etching away part of the semiconductor layer from a side wall of the semiconductor layer to form an opening; then forming a channel layer in the opening and on a side wall of the first electrode layer and a side wall of the second electrode layer, wherein the channel layer comprises a first channel portion located in the opening and a second channel portion other than the first channel portion in the opening; filling the first channel portion with a dummy gate layer; then etching away part of the dummy gate layer from a side wall of the dummy gate layer by taking the second channel portion as a mask; then removing the second channel portion and the first channel portion which is in contact with an upper and a lower surface of the dummy gate layer, so as to form a recess formed by the first electrode layer or the second electrode layer, the channel layer and the dummy gate layer; and filling the recess with a dielectric material to form an isolation side wall, wherein the formed isolation side wall can reduce the parasitic capacitance of a semiconductor device and optimize the performance thereof.

Classes IPC  ?

  • H01L 29/78 - Transistors à effet de champ l'effet de champ étant produit par une porte isolée
  • H01L 29/08 - Corps semi-conducteurs caractérisés par les formes, les dimensions relatives, ou les dispositions des régions semi-conductrices avec des régions semi-conductrices connectées à une électrode transportant le courant à redresser, amplifier ou commuter, cette électrode faisant partie d'un dispositif à semi-conducteur qui comporte trois électrodes ou plus

83.

NANOWIRE/SHEET COMPONENT HAVING CRYSTAL SIDEWALL, MANUFACTURING METHOD AND ELECTRONIC DEVICE

      
Numéro d'application CN2022076636
Numéro de publication 2023/108885
Statut Délivré - en vigueur
Date de dépôt 2022-02-17
Date de publication 2023-06-22
Propriétaire INSTITUTE OF MICROELECTRONICS, CHINESE ACADEMY OF SCIENCES (Chine)
Inventeur(s) Zhu, Huilong

Abrégé

Disclosed are a nanowire/sheet component having a crystal sidewall, a manufacturing method therefor, and an electronic device comprising the nanowire/sheet component. According to an embodiment, a nanowire/sheet component may comprise: a substrate; a nanowire/sheet spaced apart from a surface of the substrate and extending along a first direction; a source/drain layer located at two opposite ends of the nanowire/sheet in the first direction and connected to the nanowire/sheet; a gate stack extending along a second direction intersecting the first direction to surround the nanowire/sheet; and a sidewall disposed on a side wall of the gate stack, the sidewall having substantially the same crystal structure as the nanowire/sheet in at least a part of a region adjacent to the nanowire/sheet.

Classes IPC  ?

  • H01L 21/336 - Transistors à effet de champ à grille isolée
  • H01L 29/06 - Corps semi-conducteurs caractérisés par les formes, les dimensions relatives, ou les dispositions des régions semi-conductrices
  • H01L 29/78 - Transistors à effet de champ l'effet de champ étant produit par une porte isolée

84.

SEMICONDUCTOR APPARATUS HAVING STAGGERED STRUCTURE AND METHOD OF MANUFACTURING THE SAME, AND ELECTRONIC DEVICE

      
Numéro d'application 17925913
Statut En instance
Date de dépôt 2021-03-18
Date de la première publication 2023-06-15
Propriétaire INSTITUTE OF MICROELECTRONICS, CHINESE ACADEMY OF SCIENCES (Chine)
Inventeur(s)
  • Zhu, Huilong
  • Ai, Xuezheng
  • Zhang, Yongkui

Abrégé

A semiconductor apparatus having a staggered structure, a method of manufacturing a semiconductor apparatus, and an electronic device including the semiconductor apparatus. The semiconductor apparatus includes a first element and a second element on a substrate. The first element and the second element each include a comb-shaped structure. The comb-shaped structure includes a first portion extending in a vertical direction relative to the substrate, and at least one second portion extending from the first portion in a lateral direction relative to the substrate and spaced from the substrate. A height of the second portion of the first element in the vertical direction is staggered with respect to a height of the second portion of the second element in the vertical direction. A material of the comb-shaped structure of the first element is different from a material of the comb-shaped structure of the second element.

Classes IPC  ?

  • H01L 29/06 - Corps semi-conducteurs caractérisés par les formes, les dimensions relatives, ou les dispositions des régions semi-conductrices
  • H01L 29/786 - Transistors à couche mince
  • H01L 27/092 - Transistors à effet de champ métal-isolant-semi-conducteur complémentaires
  • H01L 29/66 - Types de dispositifs semi-conducteurs
  • H01L 29/78 - Transistors à effet de champ l'effet de champ étant produit par une porte isolée

85.

SEMICONDUCTOR DEVICE HAVING ZIGZAG STRUCTURE, METHOD OF MANUFACTURING SEMICONDUCTOR DEVICE, AND ELECTRONIC DEVICE

      
Numéro d'application 17998456
Statut En instance
Date de dépôt 2021-03-11
Date de la première publication 2023-06-15
Propriétaire Institute of Microelectronics, Chinese Academy of Sciences (Chine)
Inventeur(s) Zhu, Huilong

Abrégé

A semiconductor device having a zigzag structure, a method of manufacturing the semiconductor device, and an electronic including the semiconductor device. The semiconductor device may include a semiconductor layer (1031) extending in zigzag in a vertical direction with respect to a substrate (1001). The semiconductor layer (1031) includes one or more first portions disposed in sequence and spaced apart from each other in the vertical direction and second portions respectively disposed on and connected to opposite ends of each first portion. A second portion at one end of each first portion extends from the one end in a direction of leaving the substrate, and a second portion at the other end of the each first portion extends from the other end in a direction of approaching the substrate. First portions adjacent in the vertical direction are connected to each other by the same second portion.

Classes IPC  ?

  • H01L 29/786 - Transistors à couche mince
  • H01L 27/092 - Transistors à effet de champ métal-isolant-semi-conducteur complémentaires
  • H01L 29/10 - Corps semi-conducteurs caractérisés par les formes, les dimensions relatives, ou les dispositions des régions semi-conductrices avec des régions semi-conductrices connectées à une électrode ne transportant pas le courant à redresser, amplifier ou commuter, cette électrode faisant partie d'un dispositif à semi-conducteur qui comporte trois électrodes ou plus
  • H01L 29/423 - Electrodes caractérisées par leur forme, leurs dimensions relatives ou leur disposition relative ne transportant pas le courant à redresser, à amplifier ou à commuter
  • H01L 21/8238 - Transistors à effet de champ complémentaires, p.ex. CMOS
  • H01L 29/66 - Types de dispositifs semi-conducteurs

86.

VERTICAL MOSFET DEVICE AND MANUFACTURING METHOD THEREFOR AND APPLICATION THEREOF

      
Numéro d'application CN2021137385
Numéro de publication 2023/102951
Statut Délivré - en vigueur
Date de dépôt 2021-12-13
Date de publication 2023-06-15
Propriétaire
  • BEIJING SUPERSTRING ACADEMY OF MEMORY TECHNOLOGY (Chine)
  • INSTITUTE OF MICROELECTRONICS, CHINESE ACADEMY OF SCIENCES (Chine)
Inventeur(s)
  • Chen, Zhuo
  • Zhu, Huilong

Abrégé

The present invention relates to a vertical MOSFET device and a manufacturing method therefor and the application thereof. The method comprises: forming, on a substrate, a first silicon layer, a first germanium silicon layer, a second germanium silicon layer, a third germanium silicon layer and a second silicon layer which are vertically stacked from bottom to top, wherein the molar content of germanium in the first germanium silicon layer and the molar content of germanium in the third germanium silicon layer are both greater than the content of germanium in the second germanium silicon layer; performing etching to form a nano-stack structure; selectively etching the first germanium silicon layer and the third germanium silicon layer, so as to form a first groove and a third groove; forming inner side walls of extension regions in the first groove and the third groove; selectively etching the second germanium silicon layer, so as to form a gate groove; forming a dummy gate in the gate groove; forming a source electrode and a drain electrode; forming an active region having a shallow trench isolation layer; and removing the dummy gate, so as to form a gate dielectric layer and a gate electrode. The present invention can effectively control the size of a trench, the sizes of inner side walls of extension regions, the size of a gate electrode, etc., and is applicable to nanosheet or nanowire structures.

Classes IPC  ?

  • H01L 21/335 - Transistors à effet de champ
  • H01L 29/06 - Corps semi-conducteurs caractérisés par les formes, les dimensions relatives, ou les dispositions des régions semi-conductrices

87.

MEMORY DEVICE AND MANUFACTURING METHOD THEREFOR

      
Numéro d'application CN2021137861
Numéro de publication 2023/102964
Statut Délivré - en vigueur
Date de dépôt 2021-12-14
Date de publication 2023-06-15
Propriétaire
  • BEIJING SUPERSTRING ACADEMY OF MEMORY TECHNOLOGY (Chine)
  • INSTITUTE OF MICROELECTRONICS, CHINESE ACADEMY OF SCIENCES (Chine)
Inventeur(s)
  • Liu, Ziyi
  • Zhu, Huilong

Abrégé

A memory device and a manufacturing method therefor, which relate to the technical field of semiconductors. The memory device comprises a substrate; a memory unit array, which is located on the substrate and comprises a plurality of memory units, wherein each memory unit comprises a left laminate and a right laminate, which are arranged at an interval in a horizontal direction, the left laminate and the right laminate each comprise a lower isolation layer, a PMOS layer, a first NMOS layer, an upper isolation layer and a second NMOS layer, which are sequentially arranged on the substrate in a stacked manner, the PMOS layer, the first NMOS layer and the second NMOS layer each comprise a first source/drain layer, a channel layer and a second source/drain layer, which are vertically arranged in a stacked manner, and the channel layer is transversely recessed relative to the first source/drain layer and the second source/drain layer; and grid stacks, which are between the first source/drain layer and the second source/drain layer in a vertical direction, and are arranged on two opposite sides of the channel layer, so as to be embedded into transverse recesses of the channel layer.

Classes IPC  ?

  • H01L 27/11 - Structures de mémoires statiques à accès aléatoire
  • H01L 21/8244 - Structures de mémoires statiques à accès aléatoire (SRAM)

88.

VERTICAL MOSFET DEVICE AND PREPARATION METHOD THEREOF

      
Numéro d'application CN2021137863
Numéro de publication 2023/102965
Statut Délivré - en vigueur
Date de dépôt 2021-12-14
Date de publication 2023-06-15
Propriétaire
  • BEIJING SUPERSTRING ACADEMY OF MEMORY TECHNOLOGY (Chine)
  • INSTITUTE OF MICROELECTRONICS, CHINESE ACADEMY OF SCIENCES (Chine)
Inventeur(s)
  • Zhu, Huilong
  • Xiao, Zhongrui

Abrégé

The invention relates to the technical field of semiconductors. Disclosed are a vertical MOSFET device and a preparation method thereof. The vertical MOSFET device comprises: a substrate; an active region, comprising a first source/drain layer, a channel layer and a second source/drain layer that are sequentially and vertically stacked on the substrate, the periphery of the channel layer being recessed relative to the periphery of the first source/drain layer and the outer periphery of the second source/drain layer; a spacer layer, comprising an upper spacer layer and a lower spacer layer, the upper spacer layer being formed on the lower surface of the second source/drain layer exposed by the recess of the channel layer, the lower spacer layer being formed on the upper surface of the first source/drain layer exposed by the recess of the channel layer, and the upper spacer layer and the lower spacer layer both being in contact with, but not in communication with, a lateral surface of the channel layer; a gate stack, formed at least on the transverse outer periphery of the channel layer and embedded in the groove space between the upper spacer layer and the lower spacer layer.

Classes IPC  ?

  • H01L 29/10 - Corps semi-conducteurs caractérisés par les formes, les dimensions relatives, ou les dispositions des régions semi-conductrices avec des régions semi-conductrices connectées à une électrode ne transportant pas le courant à redresser, amplifier ou commuter, cette électrode faisant partie d'un dispositif à semi-conducteur qui comporte trois électrodes ou plus
  • H01L 29/423 - Electrodes caractérisées par leur forme, leurs dimensions relatives ou leur disposition relative ne transportant pas le courant à redresser, à amplifier ou à commuter
  • H01L 29/78 - Transistors à effet de champ l'effet de champ étant produit par une porte isolée
  • H01L 21/336 - Transistors à effet de champ à grille isolée

89.

IN-MEMORY COMPUTING UNIT AND IN-MEMORY COMPUTING CIRCUIT HAVING RECONFIGURABLE LOGIC

      
Numéro d'application 17966476
Statut En instance
Date de dépôt 2022-10-14
Date de la première publication 2023-06-08
Propriétaire INSTITUTE OF MICROELECTRONICS, CHINESE ACADEMY OF SCIENCES (Chine)
Inventeur(s)
  • Cui, Yan
  • Luo, Jun
  • Yang, Meiyin
  • Xu, Jing

Abrégé

An in-memory computing circuit having reconfigurable logic, including: an input stage and N output stages which are cascaded. The input stage includes 2N STT-MTJs. Each output stage includes STT-MTJs, of which a quantity is equal to a half of a quantity of STT-MTJs in a just previous stage. Two STT-MTJs in the previous stage and one STT-MTJ in the subsequent stage form a double-input single-output in-memory computing unit. Each double-input single-output in-memory computing unit can implement the four logical operations, i.e., NAND, NOR, AND, and OR, under different configurations. Data storage and logical operations can be realized under the same circuit architecture, and reconfigurations among different logic can be achieved.

Classes IPC  ?

  • G11C 11/16 - Mémoires numériques caractérisées par l'utilisation d'éléments d'emmagasinage électriques ou magnétiques particuliers; Eléments d'emmagasinage correspondants utilisant des éléments magnétiques utilisant des éléments dans lesquels l'effet d'emmagasinage est basé sur l'effet de spin
  • H03K 19/20 - Circuits logiques, c. à d. ayant au moins deux entrées agissant sur une sortie; Circuits d'inversion caractérisés par la fonction logique, p.ex. circuits ET, OU, NI, NON

90.

MOSFET FOR SUPPRESSING GIDL, METHOD FOR MANUFACTURING MOSFET, AND ELECTRONIC APPARATUS INCLUDING MOSFET

      
Numéro d'application 18051434
Statut En instance
Date de dépôt 2022-10-31
Date de la première publication 2023-06-08
Propriétaire INSTITUTE OF MICROELECTRONICS, CHINESE ACADEMY OF SCIENCES (Chine)
Inventeur(s) Zhu, Huilong

Abrégé

A metal oxide semiconductor field effect transistor (MOSFET), a method for manufacturing MOSFET, and an electronic apparatus including MOSFET are disclosed. The MOSFET include: a vertical channel portion on a substrate; source/drain portions respectively located at upper and lower ends of the channel portion with respect to the substrate; and a gate stack opposite to the channel portion. The channel portion has doping concentration distribution, so that when the MOSFET is an n-type MOSFET (nMOSFET), a threshold voltage of a first portion of the channel portion close to one of the source/drain portions is lower than a threshold voltage of a second portion adjacent to the first portion; or when the MOSFET is a p-type MOSFET (pMOSFET), a threshold voltage of a first portion in the channel portion close to one of the source/drain portions is higher than a threshold voltage of a second portion adjacent to the first portion.

Classes IPC  ?

  • H01L 29/10 - Corps semi-conducteurs caractérisés par les formes, les dimensions relatives, ou les dispositions des régions semi-conductrices avec des régions semi-conductrices connectées à une électrode ne transportant pas le courant à redresser, amplifier ou commuter, cette électrode faisant partie d'un dispositif à semi-conducteur qui comporte trois électrodes ou plus
  • H01L 29/04 - Corps semi-conducteurs caractérisés par leur structure cristalline, p.ex. polycristalline, cubique ou à orientation particulière des plans cristallins
  • H01L 29/08 - Corps semi-conducteurs caractérisés par les formes, les dimensions relatives, ou les dispositions des régions semi-conductrices avec des régions semi-conductrices connectées à une électrode transportant le courant à redresser, amplifier ou commuter, cette électrode faisant partie d'un dispositif à semi-conducteur qui comporte trois électrodes ou plus
  • H01L 29/66 - Types de dispositifs semi-conducteurs

91.

SEMICONDUCTOR STORAGE UNIT STRUCTURE AND PREPARATION METHOD THEREFOR AND USE THEREOF, AND SEMICONDUCTOR MEMORY

      
Numéro d'application CN2021136853
Numéro de publication 2023/097743
Statut Délivré - en vigueur
Date de dépôt 2021-12-09
Date de publication 2023-06-08
Propriétaire
  • BEIJING SUPERSTRING ACADEMY OF MEMORY TECHNOLOGY (Chine)
  • INSTITUTE OF MICROELECTRONICS, CHINESE ACADEMY OF SCIENCES (Chine)
Inventeur(s)
  • Wang, Qi
  • Zhu, Huilong

Abrégé

The present invention relates to a semiconductor storage unit structure and a preparation method therefor and use thereof, and a semiconductor memory. The semiconductor storage unit structure comprises a substrate, a first transistor layer, an isolation layer and a second transistor layer, wherein the first transistor layer comprises a first stacked structure formed by a first source electrode, a first channel and a first drain electrode which are arranged in a stacked manner from bottom to top, and a first gate electrode located on a side wall of the first stacked structure; and the second transistor layer comprises: a second stacked structure formed by a second drain electrode, a second channel and a second source electrode which are arranged in a stacked manner from bottom to top, and a second gate electrode located on a side wall of the second stacked structure. At least part of the side wall of the second drain electrode is in direct contact with the first gate electrode. The present invention provides a 2T0C-type DRAM unit with an improved structure, has the advantages of vertical stacking integration, a high integration level, low electric leakage, a short refreshing time, etc., and has significant advantages compared with existing 2T0C-type DRAMs.

Classes IPC  ?

  • H01L 27/108 - Structures de mémoires dynamiques à accès aléatoire
  • H01L 27/06 - Dispositifs consistant en une pluralité de composants semi-conducteurs ou d'autres composants à l'état solide formés dans ou sur un substrat commun comprenant des éléments de circuit passif intégrés avec au moins une barrière de potentiel ou une barrière de surface le substrat étant un corps semi-conducteur comprenant une pluralité de composants individuels dans une configuration non répétitive

92.

STORAGE DEVICE AND METHOD FOR MANUFACTURING SAME, AND ELECTRONIC DEVICE COMPRISING STORAGE DEVICE

      
Numéro d'application CN2021133338
Numéro de publication 2023/087364
Statut Délivré - en vigueur
Date de dépôt 2021-11-26
Date de publication 2023-05-25
Propriétaire
  • BEIJING SUPERSTRING ACADEMY OF MEMORY TECHNOLOGY (Chine)
  • INSTITUTE OF MICROELECTRONICS, CHINESE ACADEMY OF SCIENCES (Chine)
Inventeur(s)
  • Zhu, Huilong
  • Wang, Qi

Abrégé

A storage device and a method for manufacturing same, and an electronic device comprising a storage device. The storage device comprises a substrate, a storage unit array on the substrate, and a plurality of word lines, which extend in a first direction, on the substrate. The storage unit array comprises a plurality of storage units, which are arranged in rows in the first direction and in columns in a second direction. Each storage unit comprises: an active region, which extends in a third direction, and comprises a vertical stack of a first source/drain layer, a channel layer and a second source/drain layer; and a gate stack, which is located between the first source/drain layer and the second source/drain layer in a vertical direction, and sandwiches the channel layer between at least two opposite sides of the channel layer. First source/drain layers in active regions of each column are continuous, so as to form a bit line, which extends continuously in a zigzag in the second direction. Each word line extends in the first direction, so as to intersect with active regions in a corresponding row, and is electrically connected to the gate stack on two opposite sides of the channel layer of each storage unit.

Classes IPC  ?

  • H01L 27/108 - Structures de mémoires dynamiques à accès aléatoire

93.

SEMICONDUCTOR DEVICE HAVING U-SHAPED STRUCTURE, METHOD OF MANUFACTURING SEMICONDUCTOR DEVICE, AND ELECTRONIC DEVICE

      
Numéro d'application 17919652
Statut En instance
Date de dépôt 2021-03-23
Date de la première publication 2023-05-25
Propriétaire INSTITUTE OF MICROELECTRONICS, CHINESE ACADEMY OF SCIENCES (Chine)
Inventeur(s)
  • Zhu, Huilong
  • Li, Chen

Abrégé

Disclosed are a semiconductor device having a U-shaped structure, a method of manufacturing the semiconductor device, and an electronic including the semiconductor device. According to an embodiment, the semiconductor device may include: a first fin and a second fin disposed opposite to each other, wherein the first fin and the second fin extend in a vertical direction with respect to a substrate; a connection nanosheet connecting a bottom end of the first fin to a bottom end of a second fin to form a U-shaped structure, wherein the connection nanosheet is spaced apart from a top surface of the substrate.

Classes IPC  ?

  • H01L 29/775 - Transistors à effet de champ avec un canal à gaz de porteurs de charge à une dimension, p.ex. FET à fil quantique
  • H01L 27/088 - Dispositifs consistant en une pluralité de composants semi-conducteurs ou d'autres composants à l'état solide formés dans ou sur un substrat commun comprenant des éléments de circuit passif intégrés avec au moins une barrière de potentiel ou une barrière de surface le substrat étant un corps semi-conducteur comprenant uniquement des composants semi-conducteurs d'un seul type comprenant uniquement des composants à effet de champ les composants étant des transistors à effet de champ à porte isolée
  • H01L 29/423 - Electrodes caractérisées par leur forme, leurs dimensions relatives ou leur disposition relative ne transportant pas le courant à redresser, à amplifier ou à commuter
  • H01L 29/06 - Corps semi-conducteurs caractérisés par les formes, les dimensions relatives, ou les dispositions des régions semi-conductrices
  • H01L 29/66 - Types de dispositifs semi-conducteurs

94.

TWO-DIMENSIONAL MATERIAL-BASED SELECTOR, MEMORY UNIT, ARRAY, AND METHOD OF OPERATING THE SAME

      
Numéro d'application 17998782
Statut En instance
Date de dépôt 2020-05-15
Date de la première publication 2023-05-25
Propriétaire INSTITUTE OF MICROELECTTRONICS, CHINESE ACADEMY OF SCIENCES (Chine)
Inventeur(s)
  • Lin, Huai
  • Xing, Guozhong
  • Liu, Ming

Abrégé

A two-dimensional material-based selector includes: a stack unit, wherein the stack unit has a metal-two-dimensional semiconductor-metal structure comprising a two-dimensional semiconductor layer, and metal layers arranged on an upper surface and a lower surface of the two-dimensional semiconductor layer, respectively. The number of the stack units is N, where N≥1. In each stack unit, a Schottky contact is formed on two metal-two-dimensional conductor interfaces, and the stack unit includes two Schottky diode structures connected in reverse series in response to the two-dimensional material-based selector being turned on. Alternatively, the number of the stack units is M, where M≥2. In each stack unit, a Schottky contact and an Ohmic contact are formed the two metal-two-dimensional conductor interfaces, respectively. The M stack units include M Schottky diode structures connected in reverse series in response to the two-dimensional material-based selector being turned on.

Classes IPC  ?

  • H10B 61/00 - Dispositifs de mémoire magnétique, p.ex. dispositifs RAM magnéto-résistifs [MRAM]
  • G11C 11/16 - Mémoires numériques caractérisées par l'utilisation d'éléments d'emmagasinage électriques ou magnétiques particuliers; Eléments d'emmagasinage correspondants utilisant des éléments magnétiques utilisant des éléments dans lesquels l'effet d'emmagasinage est basé sur l'effet de spin

95.

MEMORY DEVICE, MANUFACTURING METHOD THEREFOR, AND ELECTRONIC DEVICE COMPRISING MEMORY DEVICE

      
Numéro d'application CN2021133337
Numéro de publication 2023/087363
Statut Délivré - en vigueur
Date de dépôt 2021-11-26
Date de publication 2023-05-25
Propriétaire
  • BEIJING SUPERSTRING ACADEMY OF MEMORY TECHNOLOGY (Chine)
  • INSTITUTE OF MICROELECTRONICS, CHINESE ACADEMY OF SCIENCES (Chine)
Inventeur(s)
  • Wang, Qi
  • Zhu, Huilong

Abrégé

A memory device, a manufacturing method therefor, and an electronic device comprising the memory device. The memory device may comprise: a substrate; a plurality of word lines on the substrate extending in a first direction; a plurality of bit lines on the substrate extending in a second direction perpendicular to the first direction; and a memory cell array on the substrate comprising a plurality of memory cells electrically connected to corresponding word lines and bit lines, respectively. Each memory cell may comprise: an active region extending in a third direction inclined with respect to the first direction and comprising a vertical stack of a first source/drain layer, a channel layer, and a second source/drain layer; and gate stacks provided between the first source/drain layer and the second source/drain layer in a vertical direction and provided on the opposite sides of the channel layer in a fourth direction orthogonal to the third direction, so as to sandwich the channel layer. A corresponding word line of each memory cell extends across the memory cell in the first direction to be in contact with and electrically connected to the gate stacks on the opposite sides of the memory cell.

Classes IPC  ?

  • H01L 27/108 - Structures de mémoires dynamiques à accès aléatoire

96.

MEMORY CELL AND PREPARATION METHOD THEREFOR, AND THREE-DIMENSIONAL MEMORY AND OPERATION METHOD THEREFOR

      
Numéro d'application CN2021129800
Numéro de publication 2023/082096
Statut Délivré - en vigueur
Date de dépôt 2021-11-10
Date de publication 2023-05-19
Propriétaire INSTITUTE OF MICROELECTRONICS, CHINESE ACADEMY OF SCIENCES (Chine)
Inventeur(s)
  • Zhang, Gang
  • Li, Chunlong
  • Huo, Zongliang
  • Ye, Tianchun

Abrégé

The present disclosure provides a memory cell, comprising: a stack layer, stacked on a substrate, and comprising: a plurality of channel holes running through the stack layer and part of the substrate, wherein at least one second laminated material layer in the stack layer after the plurality of channel holes are formed is etched to form an annular limiting structure; a gate dielectric layer, located on the surfaces of the plurality of channel holes which are etched to form the annular limiting structure; a channel layer, located on the surface of the gate dielectric layer; and a resistive layer, located on the surface of the channel layer corresponding to the annular limiting structure. A gate voltage applied to the at least one second laminated material layer and a bit line pulse signal connected to the channel layer are controlled, a resistance state of the resistive layer is changed, and a reading, writing or erasing operation of the memory cell on the resistive layer is implemented. The present disclosure further provides a preparation method for the memory cell, and a three-dimensional memory and an operation method therefor.

Classes IPC  ?

  • H01L 27/24 - Dispositifs consistant en une pluralité de composants semi-conducteurs ou d'autres composants à l'état solide formés dans ou sur un substrat commun comprenant des composants à l'état solide pour le redressement, l'amplification ou la commutation, sans barrière de potentiel ni barrière de surface
  • G11C 16/04 - Mémoires mortes programmables effaçables programmables électriquement utilisant des transistors à seuil variable, p.ex. FAMOS

97.

CORRECTION METHOD FOR SURFACE PLASMA PHOTOLITHOGRAPHIC PATTERN

      
Numéro d'application CN2021128055
Numéro de publication 2023/077253
Statut Délivré - en vigueur
Date de dépôt 2021-11-02
Date de publication 2023-05-11
Propriétaire INSTITUTE OF MICROELECTRONICS, CHINESE ACADEMY OF SCIENCES (Chine)
Inventeur(s)
  • Ma, Le
  • Wei, Yayi
  • Zhang, Libin
  • He, Jianfang

Abrégé

Disclosed in the present invention is a correction method for a surface plasma photolithographic pattern, comprising: forming multiple test patterns on a test mask, each test pattern at least being represented by a first test parameter and a second test parameter related to the first test parameter; exposing a photoresist layer by using the test mask containing the test patterns to form multiple photoresist patterns, each photoresist pattern at least being represented by a first exposure parameter and a second exposure parameter related to the first exposure parameter; establishing a first data table on the basis of a correspondence between the first test parameters and second test parameters of the test patterns and the first exposure parameters and second exposure parameters of the photoresist patterns; processing the first data table according to the first exposure parameters to obtain a second data table; and correcting second test parameters of multiple design patterns on the basis of the second data table to obtain corrected design patterns, and using the corrected design patterns to manufacture a mask for exposure.

Classes IPC  ?

  • H01L 21/027 - Fabrication de masques sur des corps semi-conducteurs pour traitement photolithographique ultérieur, non prévue dans le groupe ou
  • G03F 7/20 - Exposition; Appareillages à cet effet

98.

STORAGE CELL, AND THREE-DIMENSIONAL MEMORY AND OPERATION METHOD THEREFOR

      
Numéro d'application CN2021128164
Numéro de publication 2023/077264
Statut Délivré - en vigueur
Date de dépôt 2021-11-02
Date de publication 2023-05-11
Propriétaire INSTITUTE OF MICROELECTRONICS, CHINESE ACADEMY OF SCIENCES (Chine)
Inventeur(s)
  • Zhang, Gang
  • Li, Chunlong
  • Huo, Zongliang
  • Ye, Tianchun

Abrégé

The present invention provides a storage cell, comprising: a channel layer array comprising N channel layers, the N channel layers being vertically provided on a substrate in a first direction, a tunneling layer and a storage layer being sequentially provided outside the N channel layers, and N being a positive integer; N heat conduction cores respectively located in the N channel layers and penetrating through the substrate; and a thermocouple array comprising a thermocouple word line layer growing on the substrate in a negative direction of the first direction and N thermocouple layers located on the thermocouple word line layer, the N thermocouple layers being connected to the N heat conduction cores in a one-to-one correspondence mode. A first potential difference is applied between the thermocouple word line layer and a part of the thermocouple layers in the N thermocouple layers, and the heat conduction core connected to the part of the thermocouple layers is heated, such that the channel layer and the storage layer corresponding to the heat conduction core are respectively kept at a first preset temperature and a second preset temperature under the heat insulation effect of the tunneling layer. The present invention further provides a three-dimensional memory and an operation method therefor.

Classes IPC  ?

  • H01L 23/34 - Dispositions pour le refroidissement, le chauffage, la ventilation ou la compensation de la température
  • H01L 27/11582 - Mémoires mortes programmables électriquement; Procédés de fabrication à étapes multiples de ces dispositifs avec isolateurs de grille à piégeage de charge, p.ex. MNOS ou NROM caractérisées par des agencements tridimensionnels, p.ex. avec des cellules à des niveaux différents de hauteur la région de source et la région de drain étant à différents niveaux, p.ex. avec des canaux inclinés les canaux comprenant des parties verticales, p.ex. canaux en forme de U
  • H01L 27/1157 - Mémoires mortes programmables électriquement; Procédés de fabrication à étapes multiples de ces dispositifs avec isolateurs de grille à piégeage de charge, p.ex. MNOS ou NROM caractérisées par la région noyau de mémoire avec transistors de sélection de cellules, p.ex. NON-ET
  • H01L 27/11556 - Mémoires mortes programmables électriquement; Procédés de fabrication à étapes multiples de ces dispositifs avec grilles flottantes caractérisées par des agencements tridimensionnels, p.ex. avec des cellules à des niveaux différents de hauteur la région de source et la région de drain étant à différents niveaux, p.ex. avec des canaux inclinés les canaux comprenant des parties verticales, p.ex. des canaux en forme de U
  • H01L 27/11524 - Mémoires mortes programmables électriquement; Procédés de fabrication à étapes multiples de ces dispositifs avec grilles flottantes caractérisées par la région noyau de mémoire avec transistors de sélection de cellules, p.ex. NON-ET
  • G11C 16/04 - Mémoires mortes programmables effaçables programmables électriquement utilisant des transistors à seuil variable, p.ex. FAMOS
  • G11C 16/26 - Circuits de détection ou de lecture; Circuits de sortie de données

99.

FERROELECTRIC TUNNEL JUNCTION DEVICE AND MANUFACTURING METHOD THEREFOR

      
Numéro d'application CN2022075627
Numéro de publication 2023/070986
Statut Délivré - en vigueur
Date de dépôt 2022-02-09
Date de publication 2023-05-04
Propriétaire INSTITUTE OF MICROELECTRONICS, CHINESE ACADEMY OF SCIENCES (Chine)
Inventeur(s)
  • Xu, Xiaoxin
  • Yu, Jie
  • Gao, Zhaomeng
  • Sun, Wenxuan
  • Zhang, Woyu
  • Li, Yi
  • Shang, Dashan

Abrégé

Provided in the embodiments of the present application are a ferroelectric tunnel junction device and a manufacturing method therefor. The ferroelectric tunnel junction device comprises a first electrode, a dielectric layer, a ferroelectric layer and a second electrode, which are sequentially stacked, wherein the thickness of the ferroelectric layer is less than five nanometers. The thickness of the ferroelectric layer is relatively thin, such that a relatively large tunneling current can be provided for the device, and the relatively thin ferroelectric layer can also increase depolarization field strength in the ferroelectric tunnel junction device, accelerate depolarization and reduce a data holding capability, so as to obtain a volatile data storage device. The volatile ferroelectric tunnel junction device can be applied to a reservoir computing network system. A plurality of polarization currents that are collected by the ferroelectric tunnel junction device during a running process are used as virtual nodes of a reservoir computing network system, and data can be input into the plurality of virtual nodes in parallel, that is, the data can be processed in parallel by the reservoir computing network system based on the ferroelectric tunnel junction device, such that the calculation of a neural network model is efficiently performed, and the requirement of the neural network model for efficient training is met.

Classes IPC  ?

  • H01L 45/00 - Dispositifs à l'état solide spécialement adaptés pour le redressement, l'amplification, la production d'oscillations ou la commutation, sans barrière de potentiel ni barrière de surface, p.ex. triodes diélectriques; Dispositifs à effet Ovshinsky; Procédés ou appareils spécialement adaptés à la fabrication ou au traitement de ces dispositifs ou de leurs parties constitutives

100.

SEMICONDUCTOR DEVICE, METHOD OF MANUFACTURING THE SAME, AND ELECTRONIC APPARATUS INCLUDING THE SAME

      
Numéro d'application 17995698
Statut En instance
Date de dépôt 2021-03-10
Date de la première publication 2023-05-04
Propriétaire INSTITUTE OF MICROELECTRONICS, CHINESE ACADEMY OF SCIENCES (Chine)
Inventeur(s) Zhu, Huilong

Abrégé

Provided are a semiconductor device, a method of manufacturing the semiconductor device, and an electronic apparatus including the semiconductor device. According to the embodiments, the semiconductor device may include: a nanosheet stack layer on a substrate including a plurality of nanosheets spaced apart from each other in a vertical direction relative to the substrate, wherein at least one of the plurality of nanosheets includes a first portion in a first orientation, and at least one of an upper surface and a lower surface of the first portion is not parallel to a horizontal surface of the substrate.

Classes IPC  ?

  • H01L 29/06 - Corps semi-conducteurs caractérisés par les formes, les dimensions relatives, ou les dispositions des régions semi-conductrices
  • H01L 29/08 - Corps semi-conducteurs caractérisés par les formes, les dimensions relatives, ou les dispositions des régions semi-conductrices avec des régions semi-conductrices connectées à une électrode transportant le courant à redresser, amplifier ou commuter, cette électrode faisant partie d'un dispositif à semi-conducteur qui comporte trois électrodes ou plus
  • H01L 29/66 - Types de dispositifs semi-conducteurs
  • H01L 29/786 - Transistors à couche mince
  • H01L 29/775 - Transistors à effet de champ avec un canal à gaz de porteurs de charge à une dimension, p.ex. FET à fil quantique
  • H01L 27/092 - Transistors à effet de champ métal-isolant-semi-conducteur complémentaires
  • H01L 21/8238 - Transistors à effet de champ complémentaires, p.ex. CMOS
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