Abstract

A storage device is provided, including: a substrate; word lines extending in a first direction; bit lines extending in a second direction perpendicular to the first direction; and a storage unit including a plurality of storage units, each of which is electrically connected to a word line and a bit line. Each storage unit includes: an active region extending in a third direction inclined with the first direction; a vertical stack of a first source/drain layer, a channel layer and a second source/drain layer; and gate stacks between the first source/drain layer and the second source/drain layer, and on opposite sides of the channel layer in a fourth direction orthogonal to the third direction, to sandwich the channel layer. The word line corresponding to each storage unit extends across the storage unit in the first direction to be electrically connected to the gate stacks on opposite sides.

IPC Classes  ?

• G11C 11/408 - Address circuits
• G11C 11/4097 - Bit-line organisation, e.g. bit-line layout, folded bit lines

Abstract

The present disclosure relates to the technical field of pattern transfer in a chip manufacturing process. Provided are a hard mask structure for integrated circuit manufacturing, and a method for manufacturing an integrated circuit device. The hard mask structure comprises a first hard mask layer and a second hard mask layer, which are stacked from top to bottom, wherein the first hard mask layer is used for forming a noble metal on the surface thereof and serves as a pattern transfer sacrificial layer, and the second hard mask layer serves as a protection layer and is used for etching the material of a pattern to be transferred; the first hard mask layer and the second hard mask layer are made of different materials, and can both tolerate the corrosion of a strong oxidizing chemical liquid which is used for removing the noble metal; and the second hard mask layer can tolerate the corrosion of a chemical liquid which is used for removing the first hard mask layer by means of wet etching, and a preset corrosion rate selection ratio of the second hard mask layer for the first hard mask layer is ensured. The present disclosure can avoid the killing of a device by means of noble metal ions, such that a noble metal thin film can be used for manufacturing large-scale integrated circuits.

IPC Classes  ?

• H01L 21/027 - Making masks on semiconductor bodies for further photolithographic processing, not provided for in group or

Abstract

A three-dimensional reservoir based on three-dimensional volatile memristors and a method for manufacturing the same. In the three-dimensional reservoir, a memory layer, a select layer, and an electrode layer in each via form a memristor which is a reservoir unit. The three-dimensional reservoir is formed based on a stacking structure and multiple vias. The three-dimensional reservoir is constructed by using virtual nodes generated from dynamic characteristics of the three-dimensional memristors. An interfacial memristor is first constructed, and its volatility is verified through electric tests. A vertical three-dimensional array is manufactured based on the volatile memristor. A dynamic characteristic of the memristor is adjusted through a Schottky barrier. Different layers in the three-dimensional reservoir correspond to different reservoirs, which are constructed by controlling memristors in the different layers, respectively.

IPC Classes  ?

• H10N 70/20 - Multistable switching devices, e.g. memristors
• H10B 63/00 - Resistance change memory devices, e.g. resistive RAM [ReRAM] devices
• H10N 70/00 - Solid-state devices without a potential-jump barrier or surface barrier, and specially adapted for rectifying, amplifying, oscillating or switching

Abstract

A storage device includes a substrate, a storage unit array, and word lines extending in the first direction. The storage unit array includes storage units arranged along a first direction and a second direction. Each storage unit includes: an active region extending in a third direction and including a vertical stack of first source/drain, channel and second source/drain layers, and a gate stack between the first and second source/drain layers in a vertical direction and sandwiching the channel layer from at least two opposite sides. First source/drain layers of each column are continuous to form a bit line extending in the second direction in a zigzag shape. Each word line extends in the first direction to intersect the active regions of a respective row, and is electrically connected to the gate stack of each storage unit on two opposite sides of the channel layer.

IPC Classes  ?

• H01L 29/08 - Semiconductor bodies characterised by the shapes, relative sizes, or dispositions of the semiconductor regions with semiconductor regions connected to an electrode carrying current to be rectified, amplified, or switched and such electrode being part of a semiconductor device which comprises three or more electrodes
• H01L 29/04 - Semiconductor bodies characterised by their crystalline structure, e.g. polycrystalline, cubic or particular orientation of crystalline planes
• H01L 29/06 - Semiconductor bodies characterised by the shapes, relative sizes, or dispositions of the semiconductor regions
• H01L 29/423 - Electrodes characterised by their shape, relative sizes or dispositions not carrying the current to be rectified, amplified or switched
• H01L 29/66 - Types of semiconductor device
• H01L 29/775 - Field-effect transistors with one-dimensional charge carrier gas channel, e.g. quantum wire FET
• H01L 29/786 - Thin-film transistors
• H10B 12/00 - Dynamic random access memory [DRAM] devices

Abstract

An activation function generator based on a magnetic domain wall driven magnetic tunnel junction and a method for manufacturing the same are provided, including: a spin orbit coupling layer configured to generate a spin orbit torque; a ferromagnetic free layer formed on the spin orbit coupling layer and configured to provide a magnetic domain wall motion racetrack; a nonmagnetic barrier layer formed on the ferromagnetic free layer; a ferromagnetic reference layer formed on the nonmagnetic barrier layer; a top electrode formed on the ferromagnetic reference layer; antiferromagnetic pinning layers formed on two ends of the ferromagnetic free layer; a left electrode and a right electrode respectively formed at two positions on the antiferromagnetic pinning layers.

IPC Classes  ?

• H10N 50/20 - Spin-polarised current-controlled devices
• G06N 3/063 - Physical realisation, i.e. hardware implementation of neural networks, neurons or parts of neurons using electronic means
• H10B 61/00 - Magnetic memory devices, e.g. magnetoresistive RAM [MRAM] devices
• H10N 50/01 - Manufacture or treatment
• H10N 50/80 - Constructional details
• H10N 50/85 - Magnetic active materials

Abstract

A memory device includes a memory unit array on substrate, the memory unit array includes a plurality of memory units, each memory unit includes: a left and a right stack arranged at intervals in a horizontal direction. The left stack and right stacks each include a lower isolation layer, PMOS layer, first NMOS layer, upper isolation layer and second NMOS layer stacked on the substrate sequentially. The PMOS layer, and the first and second NMOS layer each include first source/drain layer, channel layer and second source/drain layer vertically stacked. The channel layer is laterally recessed relative to the first and second source/drain layers; and a gate stack between the first and second source/drain layers in the vertical direction, and disposed on opposite sides of the channel layer and embedded into a lateral recess of the channel layer.

IPC Classes  ?

• H10B 10/00 - Static random access memory [SRAM] devices

Abstract

Disclosed are a semiconductor device with a spacer and a C-shaped channel portion, a method of manufacturing the same, and an electronic apparatus including the semiconductor device. The semiconductor device may include: a channel portion on a substrate, wherein the channel portion includes a curved nanosheet or nanowire with a C-shaped cross-section; a first source/drain portion and a second source/drain portion respectively located at upper and lower ends of the channel portion with respect to the substrate; a first gate stack and a second gate stack located on opposite sides of the channel portion; a first spacer located between the first gate stack and the first source/drain portion and between the first gate stack and the second source/drain portion respectively; and a second spacer located between the second gate stack and the first source/drain portion and between the second gate stack and the second source/drain portion respectively.

IPC Classes  ?

• H01L 21/8238 - Complementary field-effect transistors, e.g. CMOS
• H01L 29/06 - Semiconductor bodies characterised by the shapes, relative sizes, or dispositions of the semiconductor regions
• H01L 29/423 - Electrodes characterised by their shape, relative sizes or dispositions not carrying the current to be rectified, amplified or switched
• H01L 29/66 - Types of semiconductor device
• H01L 29/775 - Field-effect transistors with one-dimensional charge carrier gas channel, e.g. quantum wire FET

Abstract

A multi-resistance-state spintronic device, including: a top electrode and a bottom electrode respectively connected to a read-write circuit; and a magnetic tunnel junction between two electrodes. The magnetic tunnel junction includes from top to bottom: a ferromagnetic reference layer, a barrier tunneling layer, a ferromagnetic free layer, and a spin-orbit coupling layer. Nucleation centers are provided at two ends of the ferromagnetic free layer to generate a magnetic domain wall; the spin-orbit coupling layer is connected to the bottom electrode, and when a write pulse is applied, an electron spin current is generated and drives the magnetic domain wall through a spin-orbit torque to move; a plurality of local magnetic domain wall pinning centers are provided at an interface between the spin-orbit coupling layer and the ferromagnetic free layer to enhance a strength of a DM interaction constant between interfaces.

IPC Classes  ?

• G11C 11/16 - Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using magnetic elements using elements in which the storage effect is based on magnetic spin effect
• H03K 19/21 - EXCLUSIVE-OR circuits, i.e. giving output if input signal exists at only one input; COINCIDENCE circuits, i.e. giving output only if all input signals are identical
• H10B 61/00 - Magnetic memory devices, e.g. magnetoresistive RAM [MRAM] devices
• H10N 50/20 - Spin-polarised current-controlled devices
• H10N 50/80 - Constructional details
• H10N 50/85 - Magnetic active materials

Abstract

A spin electronic device (100), an array circuit, and an optimization method for a recurrent neural network. The spin electronic device (100) comprises: a magnetic domain device (110) having a preset thickness, wherein the magnetic domain device (110) can form a labyrinth-like magnetic domain structure under the modulation of Dzyaloshinskii-Moriya interaction and dipole-dipole interaction, the labyrinth-like magnetic domain structure comprising a plurality of magnetic domain areas having random magnetic domain directions, and the junction of two adjacent magnetic domain areas being a magnetic domain wall; at least one cycle of heterogeneous thin film (120), which is arranged on a first surface of the magnetic domain device (110); and at least four electrodes (130), which are arranged on a second surface of the magnetic domain device (110), wherein the four electrodes (130) are respectively connected to different magnetic domain areas.

IPC Classes  ?

• H10N 50/10 - Magnetoresistive devices

Abstract

Provided is a method for correcting a lithography pattern of a surface plasma, including: forming a plurality of test patterns on a test mask; exposing a photoresist layer by using the test mask containing the test patterns to form a plurality of photoresist patterns; establishing a first data table based on a correspondence between the first test parameter and the second test parameter of the test pattern and the first exposure parameter and the second exposure parameter of the photoresist pattern; processing the first data table according to the first exposure parameter to obtain a second data table; and respectively correcting second test parameters of a plurality of design patterns according to the second data table to obtain corrected design patterns, and manufacturing a mask for exposure by using the corrected design patterns.

IPC Classes  ?

• G03F 1/44 - Testing or measuring features, e.g. grid patterns, focus monitors, sawtooth scales or notched scales 
• G03F 1/72 - Repair or correction of mask defects
• G03F 7/20 - Exposure; Apparatus therefor

Abstract

A laminated structure and a preparation method therefor, a pattern transfer method, and a reworking method. A stripping layer (100) capable of being etched and removed by means of a wetting method is arranged below a bottom anti-reflection structure (200), so that pattern transfer can be realized, and when reworking is needed, a substrate can be separated by removing the stripping layer (100) by means of the wetting method, so that the reworking difficulty is greatly reduced, and the substrate is not damaged, thereby avoiding the formation of defects.

IPC Classes  ?

• H01L 21/027 - Making masks on semiconductor bodies for further photolithographic processing, not provided for in group or
• G03F 7/09 - Photosensitive materials - characterised by structural details, e.g. supports, auxiliary layers
• G03F 7/11 - Photosensitive materials - characterised by structural details, e.g. supports, auxiliary layers having cover layers or intermediate layers, e.g. subbing layers

Abstract

A memory device, a method of manufacturing the same, and an electronic apparatus including the same. The memory device includes: a plurality of cell active layers vertically stacked on a substrate, each cell active layer including a lower source/drain region and an upper source/drain region located at different vertical heights and a channel region between the lower source/drain region and the upper source/drain region; a gate stack on the substrate and extending vertically relative to the substrate to pass through the cell active layers, the gate stack including a gate conductor layer and a memory functional layer arranged between the gate conductor layer and the cell active layers, and a memory cell being defined at an intersection of the gate stack and each cell active layer; and a conductive metal layer arranged on a lower surface of each cell active layer and/or an upper surface of each cell active layer.

IPC Classes  ?

• H10B 43/27 - EEPROM devices comprising charge-trapping gate insulators characterised by three-dimensional arrangements, e.g. with cells on different height levels with source and drain on different levels, e.g. with sloping channels the channels comprising vertical portions, e.g. U-shaped channels
• H10B 51/20 - Ferroelectric RAM [FeRAM] devices comprising ferroelectric memory transistors characterised by the three-dimensional arrangements, e.g. with cells on different height levels

Abstract

Provided are a vertical semiconductor device with a body contact, a manufacturing method, and an electronic apparatus. The semiconductor device includes: an active region vertically disposed on a substrate relative to the substrate, including lower and upper source/drain regions, and a middle portion between the lower and upper source/drain regions for defining a channel region; first and second gate stacks which are disposed on first and second sides of the active region which are opposite to each other in a lateral direction relative to the substrate; and a body contact layer disposed on the second side of the active region to overlap a part of the middle portion of the active region, so as to apply a body bias to the active region, wherein the second gate stack includes first and second portions below and above the body contact layer respectively.

IPC Classes  ?

• H01L 29/417 - Electrodes characterised by their shape, relative sizes or dispositions carrying the current to be rectified, amplified or switched
• H01L 21/8234 - MIS technology
• H01L 27/088 - Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only the components being field-effect transistors with insulated gate
• H01L 29/06 - Semiconductor bodies characterised by the shapes, relative sizes, or dispositions of the semiconductor regions
• H01L 29/423 - Electrodes characterised by their shape, relative sizes or dispositions not carrying the current to be rectified, amplified or switched
• H01L 29/66 - Types of semiconductor device
• H01L 29/775 - Field-effect transistors with one-dimensional charge carrier gas channel, e.g. quantum wire FET
• H01L 29/786 - Thin-film transistors

Abstract

Disclosed are a vertical semiconductor device with a body contact, a manufacturing method, and an electronic apparatus. The semiconductor device includes: an active region vertically disposed on a substrate, including lower and upper source/drain regions, and a middle portion between lower and upper source/drain regions for defining a channel region; a gate stack on a first side of the active region in a lateral direction to at least overlap with the middle portion; and a body contact layer on a second side of the active region opposite to the first side in the lateral direction to overlap with the middle portion to apply a body bias to the active region. In a vertical direction, distances between a part of the middle portion overlapping with the body contact layer and the lower source/drain region and between the part and the upper source/drain region are first and second spacing distances, respectively.

IPC Classes  ?

• H01L 29/786 - Thin-film transistors
• H01L 29/66 - Types of semiconductor device

Abstract

Disclosed in the present application are a spin-wave-unit-based in-memory computing array structure and a control method therefor, which relate to the field of integrated circuits. The spin-wave-unit-based in-memory computing array structure comprises a plurality of in-memory computing units which are connected to one another, each in-memory computing unit comprising a spin wave unit and a transistor unit connected to the spin wave unit. Each spin wave unit comprises: a spin wave body, the spin wave body comprising a spin wave signal generation end and a spin wave signal detection end which are oppositely arranged; a first magnetic domain wall driving unit and a second magnetic domain wall driving unit which are respectively arranged on two adjacent sides of the spin wave body away from one side of the spin wave signal generation end and from one side of the spin wave signal detection end; and a magnetic domain wall in the spin wave body. The weighting in Hopfield neutral network computing reaches a preset weighting. Due to the occurrence of scattering and reflection of spin waves during a propagation process and the presence of fluctuations during magnetization of the magnetic domain walls themselves, the reliability and stability of spin electronic devices and in-memory computing are improved.

IPC Classes  ?

• G11C 11/16 - Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using magnetic elements using elements in which the storage effect is based on magnetic spin effect
• G06N 3/04 - Architecture, e.g. interconnection topology
• G06N 3/063 - Physical realisation, i.e. hardware implementation of neural networks, neurons or parts of neurons using electronic means

Abstract

Disclosed in the present application are a reservoir computing network optimization method and a related apparatus. The method comprises: sampling an input signal to obtain a sampling signal; performing quantization processing on the sampling signal by means of at least two kinds of quantization modes, so as to obtain at least two kinds of digital signals, values of elements in different digital signals being different; inputting voltage pulses corresponding to the elements in the different digital signals into reservoirs constructed by different quantities of virtual nodes, so as to extract signal features of the input signal in different quantization modes by the different reservoirs. By quantizing signals in different modes and inputting same into reservoirs constructed by different quantities of virtual nodes, the richness of internal states of the reservoirs can be improved, thereby further improving the signal identification accuracy of a reservoir system.

IPC Classes  ?

• H04L 41/0823 - Configuration setting characterised by the purposes of a change of settings, e.g. optimising configuration for enhancing reliability
• H04L 43/024 - Capturing of monitoring data by sampling by adaptive sampling

Abstract

The three-state spintronic device includes: a bottom electrode, a magnetic tunnel junction and a top electrode from bottom to top. The magnetic tunnel junction includes: a spin-orbit coupling layer, a ferromagnetic free layer, a barrier tunneling layer, a ferromagnetic reference layer, three local magnetic domain wall pinning centers and domain wall nucleation centers. An antisymmetric exchange interaction is modulated, and the magnetic domain wall pinning centers are embedded in an interface between a heavy metal and the ferromagnetic free layer. The magnetic domain wall nucleation centers are at two ends of the ferromagnetic free layer. A current pulse flows through the spin-orbit coupling layer to generate a spin current and the spin current is injected into the ferromagnetic free layer. Under a control of all-electrical controlled, an effective field of a spin-orbit torque drives domain wall to move and displace.

IPC Classes  ?

• G11C 11/16 - Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using magnetic elements using elements in which the storage effect is based on magnetic spin effect

Abstract

A method for manufacturing a semiconductor device. A photolithographic coating, including a first film, a photolithographic film, and a second film, is formed on the to-be-connected structure. Refractive indexes of the first film and the second film are smaller than 1, so that the photolithographic coating forms an optical structure with a high reflection coefficient. The photolithographic coating is exposed to a light having a target wavelength through a mask. The to-be-connected structure is reflected in the photolithographic coating, and hence serves as another mask and is imaged to the photolithographic film. A pattern of the mask is simultaneously imaged to the photolithographic film. That is, both the to-be-connected structure and the pattern of the mask are imaged to a target region of the photolithographic film, and the target region corresponds to the to-be-connected structure.

IPC Classes  ?

• H01L 21/027 - Making masks on semiconductor bodies for further photolithographic processing, not provided for in group or
• H01L 21/311 - Etching the insulating layers
• H01L 21/768 - Applying interconnections to be used for carrying current between separate components within a device

Abstract

A read-write method includes: sequentially writing, in a first direction, a code word obtained by information-bit encoding into a target memory cell in each layer of memory cell array in the three-dimensional memory; randomly reading the target memory cell in each layer of memory cell array, or sequentially reading the target memory cell in each layer of memory cell array in a second direction; and determining an LLR value of a current target memory cell according to a storage time corresponding to the current target memory cell when reading, a threshold voltage partition corresponding to the current target memory cell when reading, a comprehensive distribution state corresponding to the current target memory cell when reading, and a pre-established LLR table, so as to perform a soft decoding operation on the code word in the current target memory cell based on the LLR value of the current target memory cell.

IPC Classes  ?

• G11C 29/42 - Response verification devices using error correcting codes [ECC] or parity check
• G11C 29/46 - Test trigger logic
• G11C 29/12 - Built-in arrangements for testing, e.g. built-in self testing [BIST]

Abstract

A method for manufacturing a semiconductor device. A photolithographic coating, including a first film, a photolithographic film, and a second film, is formed on the to-be-connected structure. Refractive indexes of the first film and the second film are smaller than 1. The photolithographic coating is exposed to a light having a first wavelength, to image the to-be-connected structure to a first region of the photolithographic film. The photolithographic coating is exposed to a light having a second wavelength through a mask, to image the mask to a second region of the photolithographic film. A region in which the first region and the second region overlap serves as a connection region corresponding to the to-be-connected structure, and thereby self-alignment between a layer of the to-be-connected structure and a layer where a contact hole is arranged is implemented.

IPC Classes  ?

• H01L 21/768 - Applying interconnections to be used for carrying current between separate components within a device
• H01L 29/40 - Electrodes

Abstract

A nanowire/nanosheet device having a ferroelectric or negative capacitance material and a method of manufacturing the same, and an electronic apparatus including the nanowire/nanosheet device are provided. According to embodiments, the semiconductor device may include: a substrate; a nanowire/nanosheet on the substrate and spaced apart from a surface of the substrate; a gate electrode surrounding the nanowire/nanosheet; a ferroelectric or negative capacitance material layer formed on a sidewall of the gate electrode; and source/drain layers at opposite ends of the nanowire/nanosheet and adjoining the nanowire/nanosheet.

IPC Classes  ?

• H01L 29/66 - Types of semiconductor device
• H01L 29/06 - Semiconductor bodies characterised by the shapes, relative sizes, or dispositions of the semiconductor regions
• H01L 29/786 - Thin-film transistors
• H01L 29/775 - Field-effect transistors with one-dimensional charge carrier gas channel, e.g. quantum wire FET
• H01L 29/423 - Electrodes characterised by their shape, relative sizes or dispositions not carrying the current to be rectified, amplified or switched
• H01L 27/088 - Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only the components being field-effect transistors with insulated gate
• H01L 21/8234 - MIS technology
• H01L 29/51 - Insulating materials associated therewith

Abstract

Disclosed are a NOR-type memory device, a method of manufacturing the NOR-type memory device, and an electronic apparatus including the NOR-type memory device. According to an embodiment, the NOR-type memory device may include: a plurality of device layers disposed on a substrate, wherein each of the plurality of device layers includes a stack of a first source/drain layer, a first channel layer, and a second source/drain layer; and a gate stack that extends vertically with respect to the substrate to pass through the stack in the each of the plurality of device layers, wherein the gate stack includes a gate conductor layer and a memory functional layer disposed between the gate conductor layer and the stack, and a memory cell is defined at an intersection of the gate stack and the stack.

IPC Classes  ?

• H10B 51/20 - Ferroelectric RAM [FeRAM] devices comprising ferroelectric memory transistors characterised by the three-dimensional arrangements, e.g. with cells on different height levels
• H10B 43/10 - EEPROM devices comprising charge-trapping gate insulators characterised by the top-view layout
• H10B 51/10 - Ferroelectric RAM [FeRAM] devices comprising ferroelectric memory transistors characterised by the top-view layout
• H10B 43/27 - EEPROM devices comprising charge-trapping gate insulators characterised by three-dimensional arrangements, e.g. with cells on different height levels with source and drain on different levels, e.g. with sloping channels the channels comprising vertical portions, e.g. U-shaped channels

Abstract

The present disclosure provides a resistive random access memory and a method of preparing the same. The resistive random access memory includes: a resistive layer, an upper electrode and a barrier structure. The resistive layer is arranged on a substrate; the upper electrode is arranged on the resistive layer; and the barrier structure is arranged between the resistive layer and the upper electrode, and the barrier structure is configured for electrons to pass through a conduction band of the barrier structure when a device performs an erasing operation, so as to avoid forming of a defect in the resistive layer and causing a reverse breakdown of the resistive layer.

IPC Classes  ?

• H10N 70/00 - Solid-state devices without a potential-jump barrier or surface barrier, and specially adapted for rectifying, amplifying, oscillating or switching
• G11C 13/00 - Digital stores characterised by the use of storage elements not covered by groups , , or

Abstract

The disclosed technology provides a semiconductor device, a manufacturing method thereof, and an electronic device including the device. An example semiconductor device includes a substrate; a first device and a second device on the substrate. Each of the first device and the second device include a first source/drain layer, a channel layer, and a second source layer that are sequentially stacked, from bottom to top, on the substrate, and a gate stack around at least a part of an outer periphery of the channel layer, with sidewalls of the respective channel layers of the first device and the second device extending at least partially along different crystal planes or crystal plane families.

IPC Classes  ?

• H01L 21/8238 - Complementary field-effect transistors, e.g. CMOS
• H01L 27/092 - Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only the components being field-effect transistors with insulated gate complementary MIS field-effect transistors

Abstract

The present disclosure provides a memory cell and a preparation method therefor, a memory, and an information storage method. The memory cell comprises: a piezoelectric substrate layer, a first electrode and a second electrode being respectively provided at the two ends of the piezoelectric substrate layer, and current-free driving for a skyrmion being implemented by applying a voltage to the first electrode and the second electrode; and a magnetic layer, located on the surface of the piezoelectric substrate layer, forming a heterojunction with the piezoelectric substrate layer, and used for generating, stabilizing, and serving as a basic carrier for movement of the skyrmion, wherein the magnetic layer comprises a convex body, the convex body divides the magnetic layer into a bit region and a storage region, and a magnetic tunnel junction for performing skyrmion generation and detection functions is provided in the bit region.

IPC Classes  ?

• G11C 19/08 - Digital stores in which the information is moved stepwise, e.g. shift registers using magnetic elements using thin films in plane structure

Abstract

Provided is a spintronic device, a memory cell, a memory array, and a read and write circuit applied in a field of integration technology. The spintronic device includes: a bottom electrode; a spin orbit coupling layer, arranged on the bottom electrode; at least one pair of magnetic tunnel junctions, arranged on the spin orbit coupling layer, wherein each of the magnetic tunnel junctions includes a free layer, a tunneling layer, and a reference layer arranged sequentially from bottom to top, and wherein magnetization directions of reference layers of two magnetic tunnel junctions of each pair of the magnetic tunnel junctions are opposite; and a top electrode, arranged on a reference layer of each of the magnetic tunnel junctions.

IPC Classes  ?

• G11C 11/16 - Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using magnetic elements using elements in which the storage effect is based on magnetic spin effect
• H10B 61/00 - Magnetic memory devices, e.g. magnetoresistive RAM [MRAM] devices
• H10N 50/20 - Spin-polarised current-controlled devices
• G06F 17/16 - Matrix or vector computation

Abstract

Disclosed are a NOR-type memory device, a method of manufacturing the NOR-type memory device, and an electronic apparatus. The NOR-type memory device includes: at least one memory cell layer including a first source/drain layer, a first channel layer, a second source/drain layer, a second channel layer, and a third source/drain layer that are stacked on each other; at least one gate stack that extends vertically and includes a gate conductor layer and a memory functional layer between the gate conductor layer and the at least one memory cell layer. A memory cell is defined at an intersection of the gate stack and the memory cell layer. At least one bit line is electrically connected to the second source/drain layer in the memory cell layer; and at least one source line is electrically connected to the first and third source/drain layers in the memory cell layer.

IPC Classes  ?

• H10B 51/20 - Ferroelectric RAM [FeRAM] devices comprising ferroelectric memory transistors characterised by the three-dimensional arrangements, e.g. with cells on different height levels
• H10B 43/27 - EEPROM devices comprising charge-trapping gate insulators characterised by three-dimensional arrangements, e.g. with cells on different height levels with source and drain on different levels, e.g. with sloping channels the channels comprising vertical portions, e.g. U-shaped channels
• H10B 43/35 - EEPROM devices comprising charge-trapping gate insulators characterised by the memory core region with cell select transistors, e.g. NAND
• H10B 51/30 - Ferroelectric RAM [FeRAM] devices comprising ferroelectric memory transistors characterised by the memory core region
• G11C 11/22 - Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using ferroelectric elements
• G11C 16/04 - Erasable programmable read-only memories electrically programmable using variable threshold transistors, e.g. FAMOS
• G11C 16/06 - Auxiliary circuits, e.g. for writing into memory

Abstract

Disclosed are a NOR-type memory device, a method of manufacturing the NOR-type memory device, and an electronic apparatus. The NOR-type memory device includes: a memory cell layer including a first source/drain layer, a first channel layer, a second source/drain layer, a second channel layer, and a third source/drain layer which are stacked in a vertical direction; a gate stack that extends vertically and includes a gate conductor layer and a memory functional layer between the gate conductor layer and the memory cell layer; and at least one of a source line contact portion and a bulk contact portion. The source line contact portion extends vertically to pass through the memory cell layer, and is electrically connected to the first and third source/drain layers. The bulk contact portion extends vertically to pass through the memory cell layer, and is electrically connected to the first and second channel layers.

IPC Classes  ?

• H10B 53/20 - Ferroelectric RAM [FeRAM] devices comprising ferroelectric memory capacitors characterised by the three-dimensional arrangements, e.g. with cells on different height levels
• H10B 43/27 - EEPROM devices comprising charge-trapping gate insulators characterised by three-dimensional arrangements, e.g. with cells on different height levels with source and drain on different levels, e.g. with sloping channels the channels comprising vertical portions, e.g. U-shaped channels
• H10B 43/35 - EEPROM devices comprising charge-trapping gate insulators characterised by the memory core region with cell select transistors, e.g. NAND
• H10B 53/30 - Ferroelectric RAM [FeRAM] devices comprising ferroelectric memory capacitors characterised by the memory core region

Abstract

A method of designing a thin film transistor device, including: calculating characteristic parameters of searched materials; screening the materials according to a characteristic parameter threshold to obtain first active layer materials; simulating the first active layer material as an active layer material in a thin film transistor device model to obtain a device characteristic of the thin film transistor device; screening the first active layer materials according to a device characteristic threshold to obtain second active layer materials; taking the second active layer material as the active layer material of the thin film transistor device to perform an experiment; and selecting another second active layer material to perform the experiment once again when an experiment result does not meet a preset requirement, and a design of the thin film transistor device is completed until the experiment result meets the preset requirement.

IPC Classes  ?

• G06F 30/39 - Circuit design at the physical level
• G16C 60/00 - Computational materials science, i.e. ICT specially adapted for investigating the physical or chemical properties of materials or phenomena associated with their design, synthesis, processing, characterisation or utilisation

Abstract

Provided is a method for optimizing a lithography quality, including: determining a wave function stray term introduced by a surface roughness of a metal film layer based on Eigen matrix method and Bloch theorem; inputting the wave function stray term into a lithography quality deviation mathematical model for calculation and simulation to obtain an influence analysis curve of a roughness of the metal film layer on a lithography quality, the influence analysis curve characterizes an influence result of the roughness of the metal film layer on the lithography quality; reducing the surface roughness of the metal film layer and/or providing a metal-dielectric multilayer film structure between a mask above a metal-dielectric unit and air according to the influence result, so as to optimize the lithography quality of the metal-dielectric unit. Provided is an apparatus for optimizing a lithography quality, an electronic device, a computer-readable storage medium and computer program product.

IPC Classes  ?

• G06F 30/23 - Design optimisation, verification or simulation using finite element methods [FEM] or finite difference methods [FDM]
• G03F 7/00 - Photomechanical, e.g. photolithographic, production of textured or patterned surfaces, e.g. printed surfaces; Materials therefor, e.g. comprising photoresists; Apparatus specially adapted therefor
• G06F 17/16 - Matrix or vector computation

Abstract

An in-memory computing method and apparatus for graph few-shot learning, and an electronic device, relating to the fields of machine learning and artificial intelligence. A memory augmented graph network model is developed to realize a graph few-shot learning function, and hardware implementation is performed by using an in-memory computing architecture. The method comprises: initializing parameters of an encoder, and dividing a graph data set into a training set and a test set; randomly selecting a preset category and a preset number of support sets in the training set, and inputting the support sets into a controller and the encoder to obtain a first binary feature vector; storing the first binary feature vector and a tag corresponding to the first binary feature vector into an external memory unit; randomly selecting the preset category and a preset number of query sets in the training set, and inputting the query sets into the controller and the encoder to obtain a second binary feature vector; and determining a prediction category of a sample on the basis of the first binary feature vector and the second binary feature vector, so that the sample category can be quickly determined.

IPC Classes  ?

• G06N 3/063 - Physical realisation, i.e. hardware implementation of neural networks, neurons or parts of neurons using electronic means

Abstract

Disclosed are a semiconductor apparatus with a sidewall interconnection structure, a method of manufacturing the semiconductor apparatus, and an electronic device. The semiconductor apparatus includes: a plurality of device stacks, wherein each device stack includes a plurality of semiconductor devices stacked, and each semiconductor device includes a first source/drain layer, a channel layer, and a second source/drain layer stacked in a vertical direction, and a gate electrode surrounding the channel layer; and an interconnection structure between the plurality of device stacks. The interconnection structure includes: an electrical isolation layer; and a conductive structure in the electrical isolation layer. At least one of the first source/drain layer, the second source/drain layer, and the gate electrode of each of at least one of the semiconductor devices is in contact with and thus electrically connected to the conductive structure at a corresponding height in the interconnection structure in a lateral direction.

IPC Classes  ?

• H01L 23/538 - Arrangements for conducting electric current within the device in operation from one component to another the interconnection structure between a plurality of semiconductor chips being formed on, or in, insulating substrates
• H01L 29/423 - Electrodes characterised by their shape, relative sizes or dispositions not carrying the current to be rectified, amplified or switched
• H01L 29/06 - Semiconductor bodies characterised by the shapes, relative sizes, or dispositions of the semiconductor regions
• H01L 29/786 - Thin-film transistors
• H01L 29/775 - Field-effect transistors with one-dimensional charge carrier gas channel, e.g. quantum wire FET
• H01L 27/092 - Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only the components being field-effect transistors with insulated gate complementary MIS field-effect transistors
• H01L 21/8238 - Complementary field-effect transistors, e.g. CMOS

Abstract

An NOR-type memory device, a method of manufacturing the NOR-type memory device, and an electronic apparatus including the NOR-type memory device. The NOR-type memory device includes: a gate stack including a gate conductor layer and a memory functional layer; and a first semiconductor layer and a second semiconductor layer that surround a periphery of the gate stack. The first and second semiconductor layers are respectively located at different heights with respect to the substrate. The memory functional layer is located between the gate conductor layer and each of the first and second semiconductor layers. Each of the first and second semiconductor layers includes a first source/drain region, a channel region, and a second source/drain region that are disposed in sequence in a vertical direction. A memory cell is defined at an intersection of the gate stack and each of the first and second semiconductor layers.

IPC Classes  ?

• H10B 43/27 - EEPROM devices comprising charge-trapping gate insulators characterised by three-dimensional arrangements, e.g. with cells on different height levels with source and drain on different levels, e.g. with sloping channels the channels comprising vertical portions, e.g. U-shaped channels
• H10B 43/10 - EEPROM devices comprising charge-trapping gate insulators characterised by the top-view layout
• H10B 41/10 - Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates characterised by the top-view layout
• H10B 41/27 - Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates characterised by three-dimensional arrangements, e.g. with cells on different height levels with source and drain on different levels, e.g. with sloping channels the channels comprising vertical portions, e.g. U-shaped channels
• H01L 29/786 - Thin-film transistors
• H01L 29/06 - Semiconductor bodies characterised by the shapes, relative sizes, or dispositions of the semiconductor regions
• H01L 29/775 - Field-effect transistors with one-dimensional charge carrier gas channel, e.g. quantum wire FET
• H01L 29/423 - Electrodes characterised by their shape, relative sizes or dispositions not carrying the current to be rectified, amplified or switched
• H01L 29/08 - Semiconductor bodies characterised by the shapes, relative sizes, or dispositions of the semiconductor regions with semiconductor regions connected to an electrode carrying current to be rectified, amplified, or switched and such electrode being part of a semiconductor device which comprises three or more electrodes

Abstract

Provided is an all-electrically-controlled spintronic neuron device, a neuron circuit and a neural network. The neuron device includes: a bottom antiferromagnetic pinning layer; a synthetic antiferromagnetic layer formed on the bottom antiferromagnetic pinning layer; a potential barrier layer formed on the ferromagnetic free layer, wherein a region of the ferromagnetic free layer directly opposite to the potential barrier layer forms a threshold region; a ferromagnetic reference layer formed on the potential barrier layer; wherein the potential barrier layer, the ferromagnetic reference layer and the ferromagnetic free layer form a magnetic tunnel junction; a first antiferromagnetic pinning layer and a second antiferromagnetic pinning layer formed on an exposed region of the ferromagnetic free layer except the region directly opposite the potential barrier layer, and located on two sides of the potential barrier layer; and a first electrode formed on the ferromagnetic reference layer.

IPC Classes  ?

• H10N 52/00 - Hall-effect devices
• H10N 52/85 - Magnetic active materials
• H10N 59/00 - Integrated devices, or assemblies of multiple devices, comprising at least one galvanomagnetic or Hall-effect element covered by groups
• G06N 3/063 - Physical realisation, i.e. hardware implementation of neural networks, neurons or parts of neurons using electronic means

Abstract

A method of preparing a programmable diode, including: forming a tungsten plug by a standard CMOS process; taking the tungsten plug as a lower electrode and depositing a functional layer material such as a ferroelectric film on the tungsten plug; depositing an upper electrode on the functional layer material; and patterning the upper electrode and a functional layer to complete a preparation of the programmable diode. The present disclosure further discloses a ferroelectric memory of a programmable diode prepared by the method of preparing a programmable diode. The method of preparing a programmable diode does not require growing a lower electrode and reduces a complexity of the process. The ferroelectric memory includes a transistor and a programmable diode. This design stores information according to different polarities of the diode, thus a device area may be further reduced and a storage density may be improved.

IPC Classes  ?

• H10B 51/30 - Ferroelectric RAM [FeRAM] devices comprising ferroelectric memory transistors characterised by the memory core region
• H01L 29/861 - Diodes
• H10B 99/00 - Subject matter not provided for in other groups of this subclass
• H01L 29/49 - Metal-insulator semiconductor electrodes
• H01L 21/28 - Manufacture of electrodes on semiconductor bodies using processes or apparatus not provided for in groups
• H01L 29/51 - Insulating materials associated therewith
• H01L 29/78 - Field-effect transistors with field effect produced by an insulated gate
• H01L 29/66 - Types of semiconductor device

Abstract

A photoelectric detection device, including: a vacuum sealed housing, wherein the vacuum sealed housing includes a mounting interface for mounting the photodetector array so as to form a sealed space; the photodetector array has a detection surface facing an outside of the vacuum sealed housing and configured to receive multi-channel measurement optical signals; a photoelectric conversion and synchronous acquisition circuit and a high speed transmission circuit board are placed in the vacuum sealed housing, and the photodetector array is connected to the photoelectric conversion and synchronous acquisition circuit through a signal pin of the photodetector array; the photoelectric conversion and synchronous acquisition circuit is configured to synchronously convert the multi-channel measurement optical signals obtained by the photodetector array into multi-channel digital signals; and the high speed transmission circuit board is configured to perform a serial encoding processing on the converted multi-channel digital signals.

IPC Classes  ?

• G01J 1/44 - Electric circuits
• G01J 1/02 - Photometry, e.g. photographic exposure meter - Details

Abstract

A neuron device including: an antiferromagnetic pinning layer, a first ferromagnetic layer and a spin orbit coupling layer formed on a substrate in sequence; a free layer formed on the spin orbit coupling layer and moving a magnetic domain wall according to a spin orbit torque; a tunneling layer formed on the free layer; a left pinning layer and a right pinning layer formed on two sides of the free layer and having opposite magnetization directions; and a reference layer formed on the tunneling layer; wherein the free layer, the tunneling layer and the reference layer constitute a magnetic tunnel junction, and the magnetic tunnel junction is configured to read neuronal signals. Also provided is a method for preparing a neuron device based on a spin orbit torque.

IPC Classes  ?

• G06N 3/063 - Physical realisation, i.e. hardware implementation of neural networks, neurons or parts of neurons using electronic means
• H01F 10/32 - Spin-exchange-coupled multilayers, e.g. nanostructured superlattices
• H10N 50/85 - Magnetic active materials
• H10N 52/00 - Hall-effect devices

Abstract

Disclosed are a memory device, a method of manufacturing the same, and an electronic apparatus. The memory device includes: first to fourth connection line layers sequentially disposed in a vertical direction relative to a substrate. The first connection line layer includes a plurality of first conductive lines extending parallel in a first direction. One of the second and third connection line layers includes a plurality of conductive lines extending parallel in a second direction intersecting the first direction. The fourth connection line layer includes a plurality of fourth conductive lines extending parallel in a third direction. A memory cell is provided at an intersection of conductive lines. Each memory cell includes first to third transistors stacked in the vertical direction. A fifth connection line layer is provided above the memory cell, and includes a plurality of fifth conductive lines extending in a fourth direction intersecting the third direction.

IPC Classes  ?

• H10B 12/00 - Dynamic random access memory [DRAM] devices

Abstract

Disclosed are a memory device, a method of manufacturing the same, and an electronic apparatus. The memory device includes: first to fourth connection line layers sequentially disposed in a vertical direction, and adjacent connection line layers respectively include conductive lines extending in directions intersected; a plurality of memory cells respectively including first and second transistors stacked. A first active layer of the first transistor includes first and second source/drain regions respectively electrically connected with conductive lines in the first and second connection line layers. A second active layer of the second transistor includes a first source/drain region electrically connected with a gate conductor layer of the first transistor, and a second source/drain region electrically connected with a conductive line in the third connection line layer. A gate conductor layer of the second transistor of each memory cell is electrically connected to a conductive line in the fourth connection line layer.

IPC Classes  ?

• H10B 12/00 - Dynamic random access memory [DRAM] devices

Abstract

The memory circuit structure includes: a storage array, wherein the storage array includes at least two storage units; a decoder connected with a bit line and a word line of the storage array respectively; a programming circuit configured to generate a voltage pulse or a constant current pulse; a polarity switching circuit connected with the programming circuit, and configured to implement a switching between a voltage programming and a current programming of the programming circuit under a set operation and a reset operation; a detection circuit connected with the storage array, and configured to detect a detection signal of a current or a voltage corresponding to the specific storage unit in the storage array and feed back the detection signal to a control unit, wherein the detection signal output by the detection circuit is configured to enable the polarity switching circuit to switch; and the control unit.

IPC Classes  ?

• G11C 13/00 - Digital stores characterised by the use of storage elements not covered by groups , , or

Abstract

A pressure sensor based on zinc oxide nanowires and a method of manufacturing a pressure sensor based on zinc oxide nanowires are provided. The manufacturing method includes: manufacturing a bottom electrode on a substrate; manufacturing a seed layer on the bottom electrode; manufacturing a zinc oxide nanowire layer on the seed layer; manufacturing a support layer on the zinc oxide nanowire layer; and manufacturing a top electrode on the support layer.

IPC Classes  ?

• H10N 30/074 - Forming of piezoelectric or electrostrictive parts or bodies on an electrical element or another base by depositing piezoelectric or electrostrictive layers, e.g. aerosol or screen printing
• G01L 1/16 - Measuring force or stress, in general using properties of piezoelectric devices
• H10N 30/067 - Forming single-layered electrodes of multilayered piezoelectric or electrostrictive parts

Abstract

There are provided a semiconductor device, a method of manufacturing the same, and an electronic device including the device. According to an embodiment, the semiconductor device may include a substrate, and a first device and a second device formed on the substrate. Each of the first device and the second device includes a first source/drain layer, a channel layer and a second source/drain layer stacked on the substrate in sequence, and also a gate stack surrounding a periphery of the channel layer. The channel layer of the first device and the channel layer of the second device are substantially co-planar.

IPC Classes  ?

• H01L 29/78 - Field-effect transistors with field effect produced by an insulated gate
• H01L 21/225 - Diffusion of impurity materials, e.g. doping materials, electrode materials, into, or out of, a semiconductor body, or between semiconductor regions; Redistribution of impurity materials, e.g. without introduction or removal of further dopant using diffusion into, or out of, a solid from or into a solid phase, e.g. a doped oxide layer
• H01L 29/06 - Semiconductor bodies characterised by the shapes, relative sizes, or dispositions of the semiconductor regions
• H01L 29/423 - Electrodes characterised by their shape, relative sizes or dispositions not carrying the current to be rectified, amplified or switched
• H01L 29/786 - Thin-film transistors
• H01L 23/522 - Arrangements for conducting electric current within the device in operation from one component to another including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
• H01L 29/66 - Types of semiconductor device
• H01L 21/8238 - Complementary field-effect transistors, e.g. CMOS
• H01L 21/3065 - Plasma etching; Reactive-ion etching
• H01L 21/223 - Diffusion of impurity materials, e.g. doping materials, electrode materials, into, or out of, a semiconductor body, or between semiconductor regions; Redistribution of impurity materials, e.g. without introduction or removal of further dopant using diffusion into, or out of, a solid from or into a gaseous phase
• H01L 27/092 - Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only the components being field-effect transistors with insulated gate complementary MIS field-effect transistors

Abstract

The present invention relates to the technical field of semiconductors. Disclosed are a three-dimensional integrated circuit and a manufacturing method therefor, used for improving the performance of the integrated circuit when the integrated circuit comprises a power gating circuit. The three-dimensional integrated circuit comprises a substrate, and a front-section circuit, a rear-section metal interconnection layer, and a rear-section power gating circuit that are formed on the substrate; the rear-section metal interconnection layer is formed on the front-section circuit; the rear-section power gating circuit is located in the rear-section metal interconnection layer; and the front-section circuit is electrically connected to a power supply or a ground wire by means of the rear-section metal interconnection layer and the rear-section power gating circuit.

IPC Classes  ?

• H01L 27/06 - Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body including a plurality of individual components in a non-repetitive configuration
• H01L 23/535 - Arrangements for conducting electric current within the device in operation from one component to another including internal interconnections, e.g. cross-under constructions
• H01L 21/8256 - Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using technologies not covered by one of groups , or
• H01L 29/786 - Thin-film transistors
• H01L 29/66 - Types of semiconductor device
• H01L 23/528 - Layout of the interconnection structure

Abstract

Disclosed are a NOR-type memory device, a method of manufacturing the NOR-type memory device, and an electronic apparatus. The NOR-type memory device includes a plurality of device layers. Each device layer includes a first source/drain region and a second source/drain region at opposite ends of the device layer in a vertical direction, and a channel region between the first source/drain region and the second source/drain region; and a gate stack that extends vertically with respect to the substrate. The gate stack includes a gate conductor layer and a memory functional layer disposed between the gate conductor layer and the device layer. A memory cell is defined at an intersection of the gate stack and the device layer. The memory functional layer includes a first layer having a plurality of portions that correspond to the plurality of device layers respectively and are discontinuous with each other in the vertical direction.

IPC Classes  ?

• H10B 41/27 - Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates characterised by three-dimensional arrangements, e.g. with cells on different height levels with source and drain on different levels, e.g. with sloping channels the channels comprising vertical portions, e.g. U-shaped channels
• H10B 43/27 - EEPROM devices comprising charge-trapping gate insulators characterised by three-dimensional arrangements, e.g. with cells on different height levels with source and drain on different levels, e.g. with sloping channels the channels comprising vertical portions, e.g. U-shaped channels
• H10B 51/20 - Ferroelectric RAM [FeRAM] devices comprising ferroelectric memory transistors characterised by the three-dimensional arrangements, e.g. with cells on different height levels

Abstract

Disclosed are a semiconductor device with a ferroelectric or negative capacitance material layer on a sidewall of a gate electrode, a method of manufacturing the semiconductor device, and an electronic apparatus including the semiconductor device. According to embodiments, the semiconductor device may include: a substrate; a gate electrode formed on the substrate; a ferroelectric or negative capacitance material layer formed on a sidewall of the gate electrode; and a source region and a drain region that are located on opposite sides of the gate electrode on the substrate.

IPC Classes  ?

• H01L 29/78 - Field-effect transistors with field effect produced by an insulated gate
• H01L 29/51 - Insulating materials associated therewith
• H01L 29/40 - Electrodes
• H01L 29/66 - Types of semiconductor device

Abstract

A semiconductor device and a method for manufacturing the same. A first electrode layer, a semiconductor layer, and a second electrode layer are sequentially formed on a substrate. Then, a part of the semiconductor layer is removed through etching a sidewall of the semiconductor layer to form a cavity. Afterwards, a channel layer is formed at the cavity, a sidewall of the first electrode layer, and a sidewall of the second electrode layer. The channel layer includes a first channel part located in the cavity and a second channel part located outside the cavity. The first channel part is filled with a dummy gate layer. Then, a part of the dummy gate layer is removed through etching a sidewall of the dummy gate layer with the second channel part serving as a shield. Afterwards, the second channel part and the first channel part, which is in contact with an upper surface and a lower surface of the dummy gate layer, are removed to form a recess. The recess is formed by either the first electrode layer or the second electrode layer, the channel layer, and the dummy gate layer. The recess is filled with a dielectric material to form an isolation sidewall. The formed isolation sidewall can reduce parasitic capacitance of the semiconductor device and improve a performance of the semiconductor device.

IPC Classes  ?

• H01L 29/66 - Types of semiconductor device
• H01L 29/10 - Semiconductor bodies characterised by the shapes, relative sizes, or dispositions of the semiconductor regions with semiconductor regions connected to an electrode not carrying current to be rectified, amplified, or switched and such electrode being part of a semiconductor device which comprises three or more electrodes
• H01L 29/78 - Field-effect transistors with field effect produced by an insulated gate

Abstract

Disclosed are a NOR-type memory device and an electronic apparatus. The NOR-type memory device includes a NOR cell array and a peripheral circuit. The NOR cell array includes: a first substrate; an array of memory cells on the first substrate, wherein each memory cell includes a first gate stack extending vertically with respect to the first substrate and an active region surrounding a periphery of the first gate stack; first bonding pads electrically connected to the first gate stacks; and second bonding pads electrically connected to the active regions. The peripheral circuit includes: a second substrate; peripheral circuit elements on the second substrate; and third bonding pads, wherein at least some of the third bonding pads are electrically connected to the peripheral circuit elements. At least some of the first bonding pads and the second bonding pads are opposite to at least some of the third bonding pads.

IPC Classes  ?

• H10B 80/00 - Assemblies of multiple devices comprising at least one memory device covered by this subclass
• H10B 43/27 - EEPROM devices comprising charge-trapping gate insulators characterised by three-dimensional arrangements, e.g. with cells on different height levels with source and drain on different levels, e.g. with sloping channels the channels comprising vertical portions, e.g. U-shaped channels
• H10B 43/30 - EEPROM devices comprising charge-trapping gate insulators characterised by the memory core region
• H10B 43/40 - EEPROM devices comprising charge-trapping gate insulators characterised by the peripheral circuit region
• H10B 51/20 - Ferroelectric RAM [FeRAM] devices comprising ferroelectric memory transistors characterised by the three-dimensional arrangements, e.g. with cells on different height levels
• H10B 51/30 - Ferroelectric RAM [FeRAM] devices comprising ferroelectric memory transistors characterised by the memory core region
• H10B 51/40 - Ferroelectric RAM [FeRAM] devices comprising ferroelectric memory transistors characterised by the peripheral circuit region
• H01L 25/065 - Assemblies consisting of a plurality of individual semiconductor or other solid state devices all the devices being of a type provided for in the same subgroup of groups , or in a single subclass of , , e.g. assemblies of rectifier diodes the devices not having separate containers the devices being of a type provided for in group
• H01L 25/18 - Assemblies consisting of a plurality of individual semiconductor or other solid state devices the devices being of types provided for in two or more different subgroups of the same main group of groups , or in a single subclass of ,
• H01L 25/00 - Assemblies consisting of a plurality of individual semiconductor or other solid state devices

Abstract

Disclosed are a NOR-type memory device, a method of manufacturing the NOR-type memory device, and an electronic apparatus. The NOR-type memory device may include: a plurality of device layers stacked on a substrate, wherein each device layer includes a first source/drain region and a second source/drain region at opposite ends of the device layer in a vertical direction, and a channel region between the first and second source/drain region; and a gate stack that extends vertically with respect to the substrate to pass through each device layer. The gate stack includes a gate conductor layer and a memory functional layer between the gate conductor layer and the device layer. A memory cell is defined at an intersection of the gate stack and the device layer. A doping concentration in each of the first and second source/drain regions decreases towards the channel region in the vertical direction.

IPC Classes  ?

• H10B 43/27 - EEPROM devices comprising charge-trapping gate insulators characterised by three-dimensional arrangements, e.g. with cells on different height levels with source and drain on different levels, e.g. with sloping channels the channels comprising vertical portions, e.g. U-shaped channels
• H10B 43/10 - EEPROM devices comprising charge-trapping gate insulators characterised by the top-view layout
• H10B 51/10 - Ferroelectric RAM [FeRAM] devices comprising ferroelectric memory transistors characterised by the top-view layout
• H10B 51/20 - Ferroelectric RAM [FeRAM] devices comprising ferroelectric memory transistors characterised by the three-dimensional arrangements, e.g. with cells on different height levels
• H01L 23/522 - Arrangements for conducting electric current within the device in operation from one component to another including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
• H01L 23/528 - Layout of the interconnection structure

Abstract

An SOT-driven field-free switching MRAM and an array thereof. From top to bottom, the SOT-MRAM sequentially includes: a selector (1) configured to turn on or turn off the SOT-MRAM under an action of an external voltage; a magnetic tunnel junction (2), including a ferromagnetic reference layer, a tunneling layer and a ferromagnetic free layer arranged sequentially from top to bottom; and a spin-orbit coupling layer (3) made of one or more selected from heavy metal, doped heavy metal, heavy metal alloy, metal oxide, dual heavy metal layers, semiconductor material, two-dimensional semi-metal material and anti-ferromagnetic material. The spin-orbit coupling layer is configured to generate an in-plane effective field in the ferromagnetic free layer by using the interlayer exchange coupling effect and generate spin-orbit torques by using the spin Hall effect, so as to perform a deterministic data storage in the magnetic tunnel junction (2).

IPC Classes  ?

• H10N 50/20 - Spin-polarised current-controlled devices
• G11C 11/16 - Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using magnetic elements using elements in which the storage effect is based on magnetic spin effect
• H10B 61/00 - Magnetic memory devices, e.g. magnetoresistive RAM [MRAM] devices
• H10N 50/85 - Magnetic active materials
• G06F 7/501 - Half or full adders, i.e. basic adder cells for one denomination

Abstract

The present disclosure discloses a device and a method for testing fatigue characteristics of a selector (210). The device includes: a voltage divider (220) and a counter (103). The voltage divider (220) is connected to a selector (210) to be tested and is configured to divide a voltage for the selector (210) to be tested during a test process. The counter (103) is connected to the selector (210) to be tested and is configured to detect voltage and/or current changes of the selector (210) to be tested.

IPC Classes  ?

• G11C 29/54 - Arrangements for designing test circuits, e.g. design for test [DFT] tools
• G11C 13/00 - Digital stores characterised by the use of storage elements not covered by groups , , or

Abstract

A complementary storage unit and a method of preparing the same, and a complementary memory. The complementary storage unit includes: a control transistor, a pull-up diode and a pull-down diode. The control transistor is configured to control reading and writing of the storage unit. One end of the pull-up diode is connected to a positive selection line, and the other end thereof is connected to a source end of the control transistor, so as to control a high-level input. One end of the pull-down diode is connected to a negative selection line, and the other end thereof is connected to the source end of the control transistor, so as to control a low-level input. The pull-up diode and the pull-down diode are symmetrically arranged in a first direction.

IPC Classes  ?

• G11C 11/4096 - Input/output [I/O] data management or control circuits, e.g. reading or writing circuits, I/O drivers or bit-line switches
• G11C 11/408 - Address circuits
• G11C 11/4094 - Bit-line management or control circuits
• H03K 19/017 - Modifications for accelerating switching in field-effect transistor circuits

Abstract

Provided are a data transmission device and a data transmission method, which are applied to a field of an information technology. The data transmission device includes: a signal conversion module (30) and a signal transmission module (20), wherein the signal conversion module (30) is configured to convert, at a data transmitting end, an electrical signal containing a data information into a magnon signal containing the data information; the signal transmission module (20) is configured to transmit the magnon signal containing the data information to a data receiving end; and the signal conversion module (30) is further configured to convert, at the data receiving end, the magnon signal containing the data information into the electrical signal containing the data information. The data transmission method includes transmitting the data by using the magnon signal, and no voltage or current is required in a process of transmitting the data.

IPC Classes  ?

• G06F 13/40 - Bus structure

Abstract

A semiconductor device and a method for manufacturing the same. The semiconductor device includes: a first gate-all-around (GAA) transistor disposed in the first region, including a first nanowire or nanosheet of at least one first layer, the at least one first layer and the substrate form a first group, among which all pairs of adjacent layers are separated by first distances, respectively; and a second GAA transistor disposed in the second region, including a second nanowire or nanosheet of at least two second layers, the at least two second layers and the substrate form a second group, among which the second layers are separated by second distances, respectively; where a minimum first distance is greater than a maximum second distance, and a quantity of the at least one first layer is less than a quantity of the at least two second layers.

IPC Classes  ?

• H01L 29/786 - Thin-film transistors
• H01L 29/775 - Field-effect transistors with one-dimensional charge carrier gas channel, e.g. quantum wire FET
• H01L 29/66 - Types of semiconductor device
• H01L 29/423 - Electrodes characterised by their shape, relative sizes or dispositions not carrying the current to be rectified, amplified or switched
• H01L 29/06 - Semiconductor bodies characterised by the shapes, relative sizes, or dispositions of the semiconductor regions

Abstract

A nanowire/nanosheet device having a self-aligned isolation portion and a method of manufacturing the same, and an electronic apparatus including the nanowire/nanosheet device are provided. According to embodiments, the nanowire/nanosheet device includes: a substrate; a nanowire/nanosheet spaced apart from a surface of the substrate and extending in a first direction; a gate stack extending in a second direction to surround the nanowire/nanosheet, where the second direction intersects the first direction; a spacer formed on a sidewall of the gate stack; source/drain layers at opposite ends of the nanowire/nanosheet in the first direction and adjoining the nanowire/nanosheet; and a first isolation portion between the gate stack and the substrate, where the first isolation portion is self-aligned with the gate stack.

IPC Classes  ?

• H01L 29/775 - Field-effect transistors with one-dimensional charge carrier gas channel, e.g. quantum wire FET
• H01L 29/06 - Semiconductor bodies characterised by the shapes, relative sizes, or dispositions of the semiconductor regions
• H01L 29/423 - Electrodes characterised by their shape, relative sizes or dispositions not carrying the current to be rectified, amplified or switched
• H01L 29/66 - Types of semiconductor device

Abstract

Provided are a spin orbit torque magnetic random access memory cell, a spin orbit torque magnetic random access memory array and a method for calculating a Hamming distance, wherein the spin orbit torque magnetic random access memory cell includes a magnetic tunnel junction; a first transistor, a drain terminal of the first transistor being connected to a bottom of the magnetic tunnel junction; and a second transistor, a drain terminal of the second transistor being connected to a top of the magnetic tunnel junction.

IPC Classes  ?

• G06F 7/57 - Arithmetic logic units [ALU], i.e. arrangements or devices for performing two or more of the operations covered by groups  or for performing logical operations
• G11C 11/16 - Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using magnetic elements using elements in which the storage effect is based on magnetic spin effect

Abstract

The present disclosure provides an SOT-MRAM memory cell, comprising: a bottom electrode; a magnetic tunnel junction layer located on the bottom electrode; an orbital Hall effect layer located on the magnetic tunnel junction layer; a first transistor having a drain connected to the orbital Hall effect layer; and a second transistor having a drain connected to the bottom electrode. The present disclosure further provides an SOT-MRAM memory, an operation method, and an SOT-MRAM memory array.

IPC Classes  ?

• G11C 11/16 - Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using magnetic elements using elements in which the storage effect is based on magnetic spin effect
• G11C 11/18 - Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using Hall-effect devices

Abstract

A compact vertical semiconductor device and a manufacturing method thereof, and an electronic apparatus including the semiconductor device are provided. According to the embodiments, the vertical semiconductor device may include: a plurality of vertical unit devices stacked on each other, in which the unit devices include respective gate stacks extending in a lateral direction, and each of the gate stacks includes a main body, an end portion, and a connection portion located between the main body and the end portion, and in a top view, a periphery of the connection portion is recessed relative to peripheries of the main body and the end portion; and a contact portion located on the end portion of each of the gate stacks, in which the contact portion is in contact with the end portion.

IPC Classes  ?

• H01L 29/78 - Field-effect transistors with field effect produced by an insulated gate
• H01L 21/8234 - MIS technology
• H01L 27/088 - Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only the components being field-effect transistors with insulated gate
• H01L 29/423 - Electrodes characterised by their shape, relative sizes or dispositions not carrying the current to be rectified, amplified or switched
• H01L 29/45 - Ohmic electrodes

Abstract

The present disclosure relates to the technical field of artificial neuron memory devices, and provides a reconfigurable neuron device based on ion gate regulation and a manufacturing method therefor. The device comprises: a synthetic antiferromagnetic layer, a metal oxide layer, an ionic liquid layer, and a top electrode layer stacked in sequence from bottom to top. The two opposite edges of the bottom end of the synthetic antiferromagnetic layer are provided with a left boundary antiferromagnetic layer and a right boundary antiferromagnetic layer having opposite magnetization directions, and a magnetic tunnel junction for outputting a spike signal is further provided in the middle of the bottom end of the synthetic antiferromagnetic layer. The metal oxide layer, the ionic liquid layer, and the top electrode layer constitute an ion gate, and the ionic liquid layer comprises positive ions and negative ions. When an input voltage is applied to the top electrode layer, oxygen ions in the metal oxide layer move along with the distribution of the positive ions and the negative ions in the ionic liquid layer to adjust the charge accumulation of a top interface of the synthetic antiferromagnetic layer, so as to regulate the leakage motion speed of a magnetic domain wall at the bottom of the synthetic antiferromagnetic layer by means of an RKKY action.

IPC Classes  ?

• H01L 43/00 - Devices using galvano-magnetic or similar magnetic effects; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof
• H01L 43/08 - Magnetic-field-controlled resistors
• H01L 43/12 - Processes or apparatus specially adapted for the manufacture or treatment of these devices or of parts thereof
• G06N 3/063 - Physical realisation, i.e. hardware implementation of neural networks, neurons or parts of neurons using electronic means

Abstract

Provided are a spin orbit torque magnetic random access memory cell, a memory array and a memory, wherein the spin orbit torque magnetic random access memory cell includes: a magnetic tunnel and a selector; the selector is a two-dimensional material based selector; the magnetic tunnel junction is arranged above or below the selector; the magnetic tunnel junction includes an antiferromagnetic layer and a free layer; the free layer is adjacent to the antiferromagnetic layer; when the selector is turned on, the memory cell is conducted, a current generates a spin current which is injected into the free layer, and a magnetization direction of the free layer is switched by the exchange bias effect between the free layer and the antiferromagnetic layer. A deterministic magnetization switching of SOT-MRAM memory cell under zero magnetic field at room temperature may be implemented without an external magnetic field by using the exchange bias effect and applying an optimized bias voltage of the magnetic tunnel junction, so as to achieve a purpose of data writing and implement SOT-MRAM memory cell with double terminal structure.

IPC Classes  ?

• H10B 61/00 - Magnetic memory devices, e.g. magnetoresistive RAM [MRAM] devices
• H10N 52/85 - Magnetic active materials

Abstract

Provided are a symmetric memory cell and a BNN circuit. The symmetric memory cell includes a first complementary structure and a second complementary structure, the second complementary structure being symmetrically connected to the first complementary structure in a first direction, wherein the first complementary structure includes a first control transistor configured to be connected to the second complementary structure, the second complementary structure includes a second control transistor, a drain electrode of the second control transistor and a drain electrode of the first control transistor being symmetrically arranged in the first direction and connected to a bit line, and the symmetric memory cell is configured to store a weight value 1 or 0.

IPC Classes  ?

• G11C 11/4096 - Input/output [I/O] data management or control circuits, e.g. reading or writing circuits, I/O drivers or bit-line switches
• G11C 11/408 - Address circuits
• G11C 11/4094 - Bit-line management or control circuits
• H03K 19/017 - Modifications for accelerating switching in field-effect transistor circuits

Abstract

Disclosed are a NOR-type memory device, a method of manufacturing the NOR-type memory device, and an electronic apparatus including the NOR-type memory device. The NOR-type memory device may include: a first gate stack extending vertically on a substrate, and a gate conductor layer and a memory functional layer; a first semiconductor layer surrounding a periphery of the first gate stack, extending along a sidewall of the first gate stack, and a first source/drain region, a first channel region and a second source/drain region arranged vertically in sequence; a conductive shielding layer surrounding a periphery of the first channel region; and a dielectric layer between the first channel region and the conductive shielding layer. The memory functional layer is located between the first semiconductor layer and the gate conductor layer. A memory cell is defined at an intersection of the first gate stack and the first semiconductor layer.

IPC Classes  ?

• H10B 43/27 - EEPROM devices comprising charge-trapping gate insulators characterised by three-dimensional arrangements, e.g. with cells on different height levels with source and drain on different levels, e.g. with sloping channels the channels comprising vertical portions, e.g. U-shaped channels
• H10B 43/10 - EEPROM devices comprising charge-trapping gate insulators characterised by the top-view layout
• H01L 23/528 - Layout of the interconnection structure
• H10B 51/10 - Ferroelectric RAM [FeRAM] devices comprising ferroelectric memory transistors characterised by the top-view layout
• H10B 51/20 - Ferroelectric RAM [FeRAM] devices comprising ferroelectric memory transistors characterised by the three-dimensional arrangements, e.g. with cells on different height levels
• H01L 29/06 - Semiconductor bodies characterised by the shapes, relative sizes, or dispositions of the semiconductor regions
• H01L 29/775 - Field-effect transistors with one-dimensional charge carrier gas channel, e.g. quantum wire FET
• H01L 29/66 - Types of semiconductor device
• H01L 29/786 - Thin-film transistors
• H01L 29/423 - Electrodes characterised by their shape, relative sizes or dispositions not carrying the current to be rectified, amplified or switched

Abstract

The present disclosure relates to a field of memory technical, and in particular to a magnetoresistive device, a method for changing a resistance state of the magnetoresistive device, and a synapse learning module. The magnetoresistive device includes a top electrode, a ferromagnetic reference layer, a tunneling layer, a ferromagnetic free layer, a spin-orbit coupling layer, and a bottom electrode that are arranged in sequence along a preset direction, where the spin-orbit coupling layer includes a first thickness region and a second thickness region distributed alternately, and a thickness of the first thickness region is different form a thickness of the second thickness region; and the ferromagnetic free layer includes a pinning region, and a position of the pinning region is in one-to-one correspondence with a position of the first thickness region.

IPC Classes  ?

• H10N 50/10 - Magnetoresistive devices
• H10B 61/00 - Magnetic memory devices, e.g. magnetoresistive RAM [MRAM] devices
• H10N 50/85 - Magnetic active materials
• G11C 11/16 - Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using magnetic elements using elements in which the storage effect is based on magnetic spin effect

Abstract

A semiconductor device and a method of manufacturing the same are disclosed. The semiconductor device includes: a substrate and a channel portion. The channel portion includes a first portion including a fin-shaped structure protruding with respect to the substrate and a second portion located above the first portion and spaced apart from the first portion. The second portion includes one or more nanowires or nanosheets spaced apart from each other. Source/drain portions are arranged on two opposite sides of the channel portion in a first direction and in contact with the channel portion. A gate stack extends on the substrate in a second direction intersecting with the first direction, so as to intersect with the channel portion.

IPC Classes  ?

• H01L 29/06 - Semiconductor bodies characterised by the shapes, relative sizes, or dispositions of the semiconductor regions
• H01L 29/423 - Electrodes characterised by their shape, relative sizes or dispositions not carrying the current to be rectified, amplified or switched
• H01L 29/66 - Types of semiconductor device
• H01L 29/775 - Field-effect transistors with one-dimensional charge carrier gas channel, e.g. quantum wire FET
• H01L 29/78 - Field-effect transistors with field effect produced by an insulated gate

Abstract

A metallization stack is provided. The metallization stack may include at least one interconnection line layer and at least one via hole layer arranged alternately on a substrate. At least one pair of adjacent interconnection line layer and via hole layer in the metallization stack includes an interconnection line in the interconnection line layer; and a via hole in the via hole layer. The via hole layer is arranged closer to the substrate than the interconnection line layer, and at least part of the interconnection line extends longitudinally in a first direction, and a sidewall of the at least part of the interconnection line in the first direction is substantially coplanar with at least upper portion of a corresponding sidewall of the via hole under the at least part of the interconnection line.

IPC Classes  ?

• H01L 23/528 - Layout of the interconnection structure
• H01L 21/768 - Applying interconnections to be used for carrying current between separate components within a device
• H01L 23/522 - Arrangements for conducting electric current within the device in operation from one component to another including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body

Abstract

Provided is a cache memory, including: a first field-effect transistor, a field-like spin torque layer underneath a magnetic tunnel junction, an electrode, and a second field-effect transistor sequentially arranged and connected; wherein the first field-effect transistor is configured to provide a writing current and to control the on-off of the writing current through a gate electrode; the field-like spin torque layer is configured to generate field-like spin torques for switching a first ferromagnetic layer of the magnetic tunnel junction; the magnetic tunnel junction includes a first ferromagnetic layer, a tunneling layer, a second ferromagnetic layer and a pinning layer arranged sequentially; the electrode is configured to connect the cache memory with the second field-effect transistor; and the second field-effect transistor is configured to control the on-off of the second field-effect transistor through the gate electrode to read the resistive state of the magnetic tunnel junction.

IPC Classes  ?

• G11C 11/16 - Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using magnetic elements using elements in which the storage effect is based on magnetic spin effect
• H10B 61/00 - Magnetic memory devices, e.g. magnetoresistive RAM [MRAM] devices
• H10N 50/20 - Spin-polarised current-controlled devices
• H10N 50/80 - Constructional details
• H10N 50/85 - Magnetic active materials
• H10N 50/01 - Manufacture or treatment

Abstract

The present invention provides a photolithography device, a gas bath apparatus and a gas bath generator thereof. The gas bath generator comprises a closed annular body. The closed annular body is arranged around a working area. An annular flow channel is formed in the closed annular body. The closed annular body is further provided with circumferentially distributed gas outlets in communication with the annular flow channel. By means of the gas outlets, a closed airflow layer distributed around the working area is generated. The gas bath generator provided by the present invention can be used for a photolithography device and circumferentially arranged around an exposure area of the photolithography device to form a closed airflow layer isolating the exposure area from the outside around the periphery of the exposure area. The present invention solves the problem of how to reduce gas contamination and particle contamination in the silicon wafer microenvironment located in the exposure area of the photolithography device.

IPC Classes  ?

• G03F 7/20 - Exposure; Apparatus therefor

Abstract

The present invention provides a three-dimensional reservoir based on a volatile three-dimensional memristor and a manufacturing method therefor. A storage layer, a selection layer and an electrode layer in each through hole in a three-dimensional reservoir form a memristor, i.e., form a reservoir unit, and a three-dimensional reservoir based on a volatile three-dimensional memristor is formed based on a stack structure and a plurality of through holes. Specifically, in the present invention, virtual nodes generated on the basis of the dynamic characteristics of a three-dimensional memristor are used to construct a three-dimensional reservoir. First, an interfacial memristor is constructed and the volatile characteristics thereof are confirmed by means of electrical tests; a vertical three-dimensional array is prepared on the basis of the volatile memristor, and the dynamic characteristics of the device are adjusted by means of a Schottky barrier, different layers of the three-dimensional reservoir respectively corresponding to reservoirs of different layers. Different reservoirs are constructed by respectively regulating devices of different layers, thereby increasing the richness of the virtual nodes, improving the parallelism and the recognition accuracy of a system, and reducing the area of the system.

IPC Classes  ?

• H01L 27/24 - Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including solid state components for rectifying, amplifying, or switching without a potential-jump barrier or surface barrier

Abstract

Provided are a semiconductor device, a method of manufacturing the semiconductor device, and an electronic apparatus including the semiconductor device. According to the embodiments, the semiconductor device may include: a vertical structure extending in a vertical direction relative to a substrate; and a nanosheet extending from the vertical structure and spaced apart from the substrate in the vertical direction, wherein the nanosheet includes a first portion in a first orientation, and at least one of an upper surface and a lower surface of the first portion is not parallel to a horizontal surface of the substrate.

IPC Classes  ?

• H01L 29/10 - Semiconductor bodies characterised by the shapes, relative sizes, or dispositions of the semiconductor regions with semiconductor regions connected to an electrode not carrying current to be rectified, amplified, or switched and such electrode being part of a semiconductor device which comprises three or more electrodes
• H01L 27/092 - Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only the components being field-effect transistors with insulated gate complementary MIS field-effect transistors
• H01L 29/06 - Semiconductor bodies characterised by the shapes, relative sizes, or dispositions of the semiconductor regions
• H01L 29/423 - Electrodes characterised by their shape, relative sizes or dispositions not carrying the current to be rectified, amplified or switched
• H01L 29/49 - Metal-insulator semiconductor electrodes
• H01L 29/775 - Field-effect transistors with one-dimensional charge carrier gas channel, e.g. quantum wire FET
• H01L 21/8238 - Complementary field-effect transistors, e.g. CMOS
• H01L 29/66 - Types of semiconductor device

Abstract

Disclosed are a vertical semiconductor device having a conductive layer, a method of manufacturing the vertical semiconductor device, and an electronic device including the vertical semiconductor device. According to an embodiment, the semiconductor device may include: a substrate; a first metallic layer, a channel layer and a second metallic layer which are sequentially disposed on the substrate; and a gate stack formed around at least a part of a periphery of the channel layer, wherein each of the first metallic layer, the second metallic layer, and the channel layer is of single crystal structure.

IPC Classes  ?

• H01L 29/423 - Electrodes characterised by their shape, relative sizes or dispositions not carrying the current to be rectified, amplified or switched
• H01L 29/786 - Thin-film transistors
• H01L 29/06 - Semiconductor bodies characterised by the shapes, relative sizes, or dispositions of the semiconductor regions
• H01L 29/66 - Types of semiconductor device
• H01L 29/775 - Field-effect transistors with one-dimensional charge carrier gas channel, e.g. quantum wire FET
• H01L 27/088 - Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only the components being field-effect transistors with insulated gate
• H01L 21/8234 - MIS technology

Abstract

A hardware implementation method and apparatus for a reservoir computing model based on a random resistor array, and an electronic device, which relate to the fields of machine learning and artificial intelligence. The method comprises: acquiring a random weight of a reservoir layer, which is generated on the basis of a resistance-variable device crossbar array; applying a breakdown voltage to the resistance-variable device crossbar array, so as to form a randomly distributed random resistance matrix; converting an input signal into a read voltage signal by means of a circuit of a printed circuit board, and performing, on the basis of the read voltage signal and the random resistance matrix, vector matrix multiplication to determine an output voltage signal; and repeating the step of converting an input signal into a read voltage signal by means of the circuit of the printed circuit board and performing, on the basis of the read voltage signal and the random resistance matrix, vector matrix multiplication to determine an output voltage signal, and then simulating a loop iteration process of the reservoir layer. Therefore, the efficient hardware realization of a large-scale random weight and a reservoir computing model is achieved, and in an edge computing application scenario in which the computing power is limited, the possibility is provided for the efficient hardware realization of the reservoir computing model.

IPC Classes  ?

• G06N 3/063 - Physical realisation, i.e. hardware implementation of neural networks, neurons or parts of neurons using electronic means

Abstract

A method of manufacturing a parallel structure of semiconductor devices includes: disposing a semiconductor stack, which includes source/drain layers disposed vertically in sequence and channel layers therebetween, on a substrate; patterning the semiconductor stack into a predetermined shape to define an active region; forming gate stacks around at least part of peripheries of the channel layers; forming an isolation layer on peripheries of the active region and the gate stack; forming first to third conductive channels on a sidewall of the isolation layer; determining the pre-determined shape and a shape of the gate stacks, such that one of the source/drain layers on two sides of the channel layer passes through the isolation layer to contact the first conductive channel, while the other one passes through the isolation layer to contact the second conductive channel, and the gate stack passes through the isolation layer to contact the third conductive channel.

IPC Classes  ?

• H01L 29/66 - Types of semiconductor device
• H01L 21/77 - Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
• H01L 25/065 - Assemblies consisting of a plurality of individual semiconductor or other solid state devices all the devices being of a type provided for in the same subgroup of groups , or in a single subclass of , , e.g. assemblies of rectifier diodes the devices not having separate containers the devices being of a type provided for in group
• H01L 27/088 - Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only the components being field-effect transistors with insulated gate
• H01L 29/78 - Field-effect transistors with field effect produced by an insulated gate

Abstract

The present invention belongs to the technical field of artificial intelligence, and particularly relates to a method for preparing a reservoir element. The method comprises the following steps: a) sequentially arranging, on a substrate, a bottom electrode layer, a dielectric layer, a resistive layer and a top electrode layer, so as to obtain a reservoir element to be annealed; and b) performing annealing processing on the reservoir element to be annealed, so as to obtain a reservoir element, wherein the temperature of the annealing processing ranges from 300ºC to 700ºC, and the time of the annealing processing ranges from 30s to 100s. In the method provided in the present invention, after being prepared, the reservoir element is subjected to rapid annealing processing, such that defects are re-distributed after rapid annealing, thereby forming a more stable membrane; and a ferroelectric O phase can also be introduced into the membrane. By means of rapid annealing processing, the power consumption of a reservoir element can be effectively reduced, and the computing accuracy can be improved.

IPC Classes  ?

• H01L 45/00 - Solid state devices specially adapted for rectifying, amplifying, oscillating, or switching without a potential-jump barrier or surface barrier, e.g. dielectric triodes; Ovshinsky-effect devices; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof

Abstract

Provided are a memory cell structure, a memory array structure, and a voltage biasing method. The memory cell structure includes: a substrate layer, a well layer and a transistor. The substrate layer is configured to support the memory cell structure; the well layer is embedded in the substrate layer, an upper surface of the well layer is flush with an upper surface of the substrate layer, and a transistor is arranged on the well layer. In the present disclosure, a deep well bias is performed on the memory cell structure, so that the well voltage of the memory cell may be individually biased to a specific voltage, and in combination with the redesigned memory cell array structure, the applied programming voltage mostly falls on the memory cell structure. This reduces the programming voltage of the memory cell, and avoids a breakdown of the selecting transistor due to an excessively large voltage, thereby ensuring a great reliability of the device and a higher efficiency within the area of the memory cell array structure.

IPC Classes  ?

• G11C 13/00 - Digital stores characterised by the use of storage elements not covered by groups , , or

Abstract

Provided in the embodiments of the present application are a semiconductor device and a manufacturing method therefor. The semiconductor device comprises a substrate, a first electrode layer, a functional layer and a second electrode layer, wherein the functional layer is located between the first electrode layer and the second electrode layer, the functional layer comprises a first area, and a second area which surrounds the first area and is of a U-shaped structure, and the orientation of a U-shaped opening of the second area is parallel to the substrate and faces away from the first area, that is, the U-shaped opening faces an outer side; the material of the first area at least comprises germanium; and the second area comprises a U-shaped ferroelectric layer and a U-shaped gate electrode which are sequentially stacked. In the embodiments of the present application, a ferroelectric layer of a U-shaped structure is used as a storage layer of a memory device, and when a gate voltage is kept unchanged, a U-shaped channel can increase an electric field of the ferroelectric layer, thereby increasing a storage window of the whole semiconductor device; and when the storage window of the whole semiconductor device is kept unchanged, the gate voltage can be reduced, thereby reducing the power consumption of the semiconductor device, and improving the performance of the memory device.

IPC Classes  ?

• H01L 29/78 - Field-effect transistors with field effect produced by an insulated gate
• H01L 21/336 - Field-effect transistors with an insulated gate

Abstract

The present application provides a semiconductor device and a manufacturing method therefor. The method comprises: providing a substrate, wherein the substrate is provided with a first source-drain layer, a channel layer and a second source-drain layer that are sequentially stacked, and the periphery of the channel layer is provided with a gate dielectric layer and a gate structure which surround the channel layer in the horizontal direction; forming a spacer layer on the outer side wall of the gate structure; etching the gate structure, so as to reduce the thickness of the gate structure; forming a sacrificial structure covering the gate structure, and a covering layer covering the second source-drain layer, the sacrificial structure and the spacer layer, so that the sacrificial structure is located on the periphery of the second source-drain layer and located on the inner side of the spacer layer; then etching the covering layer to obtain a first contact hole passing through the sacrificial structure, and removing the sacrificial structure at the bottom of the first contact hole to form a gap below the first contact hole; and forming first contact structures in the first contact hole and the gap, thereby realizing self-alignment of the bottoms of the first contact structures and the gate structure, and improving the reliability of a device.

IPC Classes  ?

• H01L 29/423 - Electrodes characterised by their shape, relative sizes or dispositions not carrying the current to be rectified, amplified or switched
• H01L 29/78 - Field-effect transistors with field effect produced by an insulated gate
• H01L 21/336 - Field-effect transistors with an insulated gate

Abstract

Disclosed are a nanowire/sheet device and a manufacturing method therefor, and electronic equipment comprising the nanowire/sheet device. According to embodiments, the nanowire/sheet device comprises: a substrate; a nanowire/sheet spaced apart from the surface of the substrate and extending in a first direction; a source/drain layer located at two opposite ends of the nanowire/sheet in the first direction and connected to the nanowire/sheet; a gate stack extending in a second direction intersecting the first direction to surround the nanowires/sheet; and a first side wall disposed on a sidewall of the gate stack, wherein the first side wall comprises a continuously extending material layer having a first portion along the surface of the nanowire/sheet, a second portion along a sidewall of the source/drain layer facing the gate stack, and a third portion along the sidewall of the gate stack facing the source/drain layer, with a slot or interface between the second portion and the third portion.

IPC Classes  ?

• H01L 29/06 - Semiconductor bodies characterised by the shapes, relative sizes, or dispositions of the semiconductor regions
• H01L 29/78 - Field-effect transistors with field effect produced by an insulated gate
• H01L 21/336 - Field-effect transistors with an insulated gate

Abstract

Provided in the embodiments of the present application are a semiconductor device and a method for manufacturing same. The method comprises: sequentially forming a first electrode layer, a semiconductor layer and a second electrode layer on a substrate; then etching away part of the semiconductor layer from a side wall of the semiconductor layer to form an opening; then forming a channel layer in the opening and on a side wall of the first electrode layer and a side wall of the second electrode layer, wherein the channel layer comprises a first channel portion located in the opening and a second channel portion other than the first channel portion in the opening; filling the first channel portion with a dummy gate layer; then etching away part of the dummy gate layer from a side wall of the dummy gate layer by taking the second channel portion as a mask; then removing the second channel portion and the first channel portion which is in contact with an upper and a lower surface of the dummy gate layer, so as to form a recess formed by the first electrode layer or the second electrode layer, the channel layer and the dummy gate layer; and filling the recess with a dielectric material to form an isolation side wall, wherein the formed isolation side wall can reduce the parasitic capacitance of a semiconductor device and optimize the performance thereof.

IPC Classes  ?

• H01L 29/78 - Field-effect transistors with field effect produced by an insulated gate
• H01L 29/08 - Semiconductor bodies characterised by the shapes, relative sizes, or dispositions of the semiconductor regions with semiconductor regions connected to an electrode carrying current to be rectified, amplified, or switched and such electrode being part of a semiconductor device which comprises three or more electrodes

Abstract

Disclosed are a nanowire/sheet component having a crystal sidewall, a manufacturing method therefor, and an electronic device comprising the nanowire/sheet component. According to an embodiment, a nanowire/sheet component may comprise: a substrate; a nanowire/sheet spaced apart from a surface of the substrate and extending along a first direction; a source/drain layer located at two opposite ends of the nanowire/sheet in the first direction and connected to the nanowire/sheet; a gate stack extending along a second direction intersecting the first direction to surround the nanowire/sheet; and a sidewall disposed on a side wall of the gate stack, the sidewall having substantially the same crystal structure as the nanowire/sheet in at least a part of a region adjacent to the nanowire/sheet.

IPC Classes  ?

• H01L 21/336 - Field-effect transistors with an insulated gate
• H01L 29/06 - Semiconductor bodies characterised by the shapes, relative sizes, or dispositions of the semiconductor regions
• H01L 29/78 - Field-effect transistors with field effect produced by an insulated gate

Abstract

A semiconductor apparatus having a staggered structure, a method of manufacturing a semiconductor apparatus, and an electronic device including the semiconductor apparatus. The semiconductor apparatus includes a first element and a second element on a substrate. The first element and the second element each include a comb-shaped structure. The comb-shaped structure includes a first portion extending in a vertical direction relative to the substrate, and at least one second portion extending from the first portion in a lateral direction relative to the substrate and spaced from the substrate. A height of the second portion of the first element in the vertical direction is staggered with respect to a height of the second portion of the second element in the vertical direction. A material of the comb-shaped structure of the first element is different from a material of the comb-shaped structure of the second element.

IPC Classes  ?

• H01L 29/06 - Semiconductor bodies characterised by the shapes, relative sizes, or dispositions of the semiconductor regions
• H01L 29/786 - Thin-film transistors
• H01L 27/092 - Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only the components being field-effect transistors with insulated gate complementary MIS field-effect transistors
• H01L 29/66 - Types of semiconductor device
• H01L 29/78 - Field-effect transistors with field effect produced by an insulated gate

Abstract

A semiconductor device having a zigzag structure, a method of manufacturing the semiconductor device, and an electronic including the semiconductor device. The semiconductor device may include a semiconductor layer (1031) extending in zigzag in a vertical direction with respect to a substrate (1001). The semiconductor layer (1031) includes one or more first portions disposed in sequence and spaced apart from each other in the vertical direction and second portions respectively disposed on and connected to opposite ends of each first portion. A second portion at one end of each first portion extends from the one end in a direction of leaving the substrate, and a second portion at the other end of the each first portion extends from the other end in a direction of approaching the substrate. First portions adjacent in the vertical direction are connected to each other by the same second portion.

IPC Classes  ?

• H01L 29/786 - Thin-film transistors
• H01L 27/092 - Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only the components being field-effect transistors with insulated gate complementary MIS field-effect transistors
• H01L 29/10 - Semiconductor bodies characterised by the shapes, relative sizes, or dispositions of the semiconductor regions with semiconductor regions connected to an electrode not carrying current to be rectified, amplified, or switched and such electrode being part of a semiconductor device which comprises three or more electrodes
• H01L 29/423 - Electrodes characterised by their shape, relative sizes or dispositions not carrying the current to be rectified, amplified or switched
• H01L 21/8238 - Complementary field-effect transistors, e.g. CMOS
• H01L 29/66 - Types of semiconductor device

Abstract

The present invention relates to a vertical MOSFET device and a manufacturing method therefor and the application thereof. The method comprises: forming, on a substrate, a first silicon layer, a first germanium silicon layer, a second germanium silicon layer, a third germanium silicon layer and a second silicon layer which are vertically stacked from bottom to top, wherein the molar content of germanium in the first germanium silicon layer and the molar content of germanium in the third germanium silicon layer are both greater than the content of germanium in the second germanium silicon layer; performing etching to form a nano-stack structure; selectively etching the first germanium silicon layer and the third germanium silicon layer, so as to form a first groove and a third groove; forming inner side walls of extension regions in the first groove and the third groove; selectively etching the second germanium silicon layer, so as to form a gate groove; forming a dummy gate in the gate groove; forming a source electrode and a drain electrode; forming an active region having a shallow trench isolation layer; and removing the dummy gate, so as to form a gate dielectric layer and a gate electrode. The present invention can effectively control the size of a trench, the sizes of inner side walls of extension regions, the size of a gate electrode, etc., and is applicable to nanosheet or nanowire structures.

IPC Classes  ?

• H01L 21/335 - Field-effect transistors
• H01L 29/06 - Semiconductor bodies characterised by the shapes, relative sizes, or dispositions of the semiconductor regions

Abstract

A memory device and a manufacturing method therefor, which relate to the technical field of semiconductors. The memory device comprises a substrate; a memory unit array, which is located on the substrate and comprises a plurality of memory units, wherein each memory unit comprises a left laminate and a right laminate, which are arranged at an interval in a horizontal direction, the left laminate and the right laminate each comprise a lower isolation layer, a PMOS layer, a first NMOS layer, an upper isolation layer and a second NMOS layer, which are sequentially arranged on the substrate in a stacked manner, the PMOS layer, the first NMOS layer and the second NMOS layer each comprise a first source/drain layer, a channel layer and a second source/drain layer, which are vertically arranged in a stacked manner, and the channel layer is transversely recessed relative to the first source/drain layer and the second source/drain layer; and grid stacks, which are between the first source/drain layer and the second source/drain layer in a vertical direction, and are arranged on two opposite sides of the channel layer, so as to be embedded into transverse recesses of the channel layer.

IPC Classes  ?

• H01L 27/11 - Static random access memory structures
• H01L 21/8244 - Static random access memory structures (SRAM)

Abstract

The invention relates to the technical field of semiconductors. Disclosed are a vertical MOSFET device and a preparation method thereof. The vertical MOSFET device comprises: a substrate; an active region, comprising a first source/drain layer, a channel layer and a second source/drain layer that are sequentially and vertically stacked on the substrate, the periphery of the channel layer being recessed relative to the periphery of the first source/drain layer and the outer periphery of the second source/drain layer; a spacer layer, comprising an upper spacer layer and a lower spacer layer, the upper spacer layer being formed on the lower surface of the second source/drain layer exposed by the recess of the channel layer, the lower spacer layer being formed on the upper surface of the first source/drain layer exposed by the recess of the channel layer, and the upper spacer layer and the lower spacer layer both being in contact with, but not in communication with, a lateral surface of the channel layer; a gate stack, formed at least on the transverse outer periphery of the channel layer and embedded in the groove space between the upper spacer layer and the lower spacer layer.

IPC Classes  ?

• H01L 29/10 - Semiconductor bodies characterised by the shapes, relative sizes, or dispositions of the semiconductor regions with semiconductor regions connected to an electrode not carrying current to be rectified, amplified, or switched and such electrode being part of a semiconductor device which comprises three or more electrodes
• H01L 29/423 - Electrodes characterised by their shape, relative sizes or dispositions not carrying the current to be rectified, amplified or switched
• H01L 29/78 - Field-effect transistors with field effect produced by an insulated gate
• H01L 21/336 - Field-effect transistors with an insulated gate

Abstract

An in-memory computing circuit having reconfigurable logic, including: an input stage and N output stages which are cascaded. The input stage includes 2N STT-MTJs. Each output stage includes STT-MTJs, of which a quantity is equal to a half of a quantity of STT-MTJs in a just previous stage. Two STT-MTJs in the previous stage and one STT-MTJ in the subsequent stage form a double-input single-output in-memory computing unit. Each double-input single-output in-memory computing unit can implement the four logical operations, i.e., NAND, NOR, AND, and OR, under different configurations. Data storage and logical operations can be realized under the same circuit architecture, and reconfigurations among different logic can be achieved.

IPC Classes  ?

• G11C 11/16 - Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using magnetic elements using elements in which the storage effect is based on magnetic spin effect
• H03K 19/20 - Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits characterised by logic function, e.g. AND, OR, NOR, NOT circuits

Abstract

A metal oxide semiconductor field effect transistor (MOSFET), a method for manufacturing MOSFET, and an electronic apparatus including MOSFET are disclosed. The MOSFET include: a vertical channel portion on a substrate; source/drain portions respectively located at upper and lower ends of the channel portion with respect to the substrate; and a gate stack opposite to the channel portion. The channel portion has doping concentration distribution, so that when the MOSFET is an n-type MOSFET (nMOSFET), a threshold voltage of a first portion of the channel portion close to one of the source/drain portions is lower than a threshold voltage of a second portion adjacent to the first portion; or when the MOSFET is a p-type MOSFET (pMOSFET), a threshold voltage of a first portion in the channel portion close to one of the source/drain portions is higher than a threshold voltage of a second portion adjacent to the first portion.

IPC Classes  ?

• H01L 29/10 - Semiconductor bodies characterised by the shapes, relative sizes, or dispositions of the semiconductor regions with semiconductor regions connected to an electrode not carrying current to be rectified, amplified, or switched and such electrode being part of a semiconductor device which comprises three or more electrodes
• H01L 29/04 - Semiconductor bodies characterised by their crystalline structure, e.g. polycrystalline, cubic or particular orientation of crystalline planes
• H01L 29/08 - Semiconductor bodies characterised by the shapes, relative sizes, or dispositions of the semiconductor regions with semiconductor regions connected to an electrode carrying current to be rectified, amplified, or switched and such electrode being part of a semiconductor device which comprises three or more electrodes
• H01L 29/66 - Types of semiconductor device

Abstract

The present invention relates to a semiconductor storage unit structure and a preparation method therefor and use thereof, and a semiconductor memory. The semiconductor storage unit structure comprises a substrate, a first transistor layer, an isolation layer and a second transistor layer, wherein the first transistor layer comprises a first stacked structure formed by a first source electrode, a first channel and a first drain electrode which are arranged in a stacked manner from bottom to top, and a first gate electrode located on a side wall of the first stacked structure; and the second transistor layer comprises: a second stacked structure formed by a second drain electrode, a second channel and a second source electrode which are arranged in a stacked manner from bottom to top, and a second gate electrode located on a side wall of the second stacked structure. At least part of the side wall of the second drain electrode is in direct contact with the first gate electrode. The present invention provides a 2T0C-type DRAM unit with an improved structure, has the advantages of vertical stacking integration, a high integration level, low electric leakage, a short refreshing time, etc., and has significant advantages compared with existing 2T0C-type DRAMs.

IPC Classes  ?

• H01L 27/108 - Dynamic random access memory structures
• H01L 27/06 - Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body including a plurality of individual components in a non-repetitive configuration

Abstract

A storage device and a method for manufacturing same, and an electronic device comprising a storage device. The storage device comprises a substrate, a storage unit array on the substrate, and a plurality of word lines, which extend in a first direction, on the substrate. The storage unit array comprises a plurality of storage units, which are arranged in rows in the first direction and in columns in a second direction. Each storage unit comprises: an active region, which extends in a third direction, and comprises a vertical stack of a first source/drain layer, a channel layer and a second source/drain layer; and a gate stack, which is located between the first source/drain layer and the second source/drain layer in a vertical direction, and sandwiches the channel layer between at least two opposite sides of the channel layer. First source/drain layers in active regions of each column are continuous, so as to form a bit line, which extends continuously in a zigzag in the second direction. Each word line extends in the first direction, so as to intersect with active regions in a corresponding row, and is electrically connected to the gate stack on two opposite sides of the channel layer of each storage unit.

IPC Classes  ?

• H01L 27/108 - Dynamic random access memory structures

Abstract

A two-dimensional material-based selector includes: a stack unit, wherein the stack unit has a metal-two-dimensional semiconductor-metal structure comprising a two-dimensional semiconductor layer, and metal layers arranged on an upper surface and a lower surface of the two-dimensional semiconductor layer, respectively. The number of the stack units is N, where N≥1. In each stack unit, a Schottky contact is formed on two metal-two-dimensional conductor interfaces, and the stack unit includes two Schottky diode structures connected in reverse series in response to the two-dimensional material-based selector being turned on. Alternatively, the number of the stack units is M, where M≥2. In each stack unit, a Schottky contact and an Ohmic contact are formed the two metal-two-dimensional conductor interfaces, respectively. The M stack units include M Schottky diode structures connected in reverse series in response to the two-dimensional material-based selector being turned on.

IPC Classes  ?

• H10B 61/00 - Magnetic memory devices, e.g. magnetoresistive RAM [MRAM] devices
• G11C 11/16 - Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using magnetic elements using elements in which the storage effect is based on magnetic spin effect

Abstract

Disclosed are a semiconductor device having a U-shaped structure, a method of manufacturing the semiconductor device, and an electronic including the semiconductor device. According to an embodiment, the semiconductor device may include: a first fin and a second fin disposed opposite to each other, wherein the first fin and the second fin extend in a vertical direction with respect to a substrate; a connection nanosheet connecting a bottom end of the first fin to a bottom end of a second fin to form a U-shaped structure, wherein the connection nanosheet is spaced apart from a top surface of the substrate.

IPC Classes  ?

• H01L 29/775 - Field-effect transistors with one-dimensional charge carrier gas channel, e.g. quantum wire FET
• H01L 27/088 - Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only the components being field-effect transistors with insulated gate
• H01L 29/423 - Electrodes characterised by their shape, relative sizes or dispositions not carrying the current to be rectified, amplified or switched
• H01L 29/06 - Semiconductor bodies characterised by the shapes, relative sizes, or dispositions of the semiconductor regions
• H01L 29/66 - Types of semiconductor device

Abstract

A memory device, a manufacturing method therefor, and an electronic device comprising the memory device. The memory device may comprise: a substrate; a plurality of word lines on the substrate extending in a first direction; a plurality of bit lines on the substrate extending in a second direction perpendicular to the first direction; and a memory cell array on the substrate comprising a plurality of memory cells electrically connected to corresponding word lines and bit lines, respectively. Each memory cell may comprise: an active region extending in a third direction inclined with respect to the first direction and comprising a vertical stack of a first source/drain layer, a channel layer, and a second source/drain layer; and gate stacks provided between the first source/drain layer and the second source/drain layer in a vertical direction and provided on the opposite sides of the channel layer in a fourth direction orthogonal to the third direction, so as to sandwich the channel layer. A corresponding word line of each memory cell extends across the memory cell in the first direction to be in contact with and electrically connected to the gate stacks on the opposite sides of the memory cell.

IPC Classes  ?

• H01L 27/108 - Dynamic random access memory structures

Abstract

The present disclosure provides a memory cell, comprising: a stack layer, stacked on a substrate, and comprising: a plurality of channel holes running through the stack layer and part of the substrate, wherein at least one second laminated material layer in the stack layer after the plurality of channel holes are formed is etched to form an annular limiting structure; a gate dielectric layer, located on the surfaces of the plurality of channel holes which are etched to form the annular limiting structure; a channel layer, located on the surface of the gate dielectric layer; and a resistive layer, located on the surface of the channel layer corresponding to the annular limiting structure. A gate voltage applied to the at least one second laminated material layer and a bit line pulse signal connected to the channel layer are controlled, a resistance state of the resistive layer is changed, and a reading, writing or erasing operation of the memory cell on the resistive layer is implemented. The present disclosure further provides a preparation method for the memory cell, and a three-dimensional memory and an operation method therefor.

IPC Classes  ?

• H01L 27/24 - Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including solid state components for rectifying, amplifying, or switching without a potential-jump barrier or surface barrier
• G11C 16/04 - Erasable programmable read-only memories electrically programmable using variable threshold transistors, e.g. FAMOS

Abstract

Disclosed in the present invention is a correction method for a surface plasma photolithographic pattern, comprising: forming multiple test patterns on a test mask, each test pattern at least being represented by a first test parameter and a second test parameter related to the first test parameter; exposing a photoresist layer by using the test mask containing the test patterns to form multiple photoresist patterns, each photoresist pattern at least being represented by a first exposure parameter and a second exposure parameter related to the first exposure parameter; establishing a first data table on the basis of a correspondence between the first test parameters and second test parameters of the test patterns and the first exposure parameters and second exposure parameters of the photoresist patterns; processing the first data table according to the first exposure parameters to obtain a second data table; and correcting second test parameters of multiple design patterns on the basis of the second data table to obtain corrected design patterns, and using the corrected design patterns to manufacture a mask for exposure.

IPC Classes  ?

• H01L 21/027 - Making masks on semiconductor bodies for further photolithographic processing, not provided for in group or
• G03F 7/20 - Exposure; Apparatus therefor

Abstract

The present invention provides a storage cell, comprising: a channel layer array comprising N channel layers, the N channel layers being vertically provided on a substrate in a first direction, a tunneling layer and a storage layer being sequentially provided outside the N channel layers, and N being a positive integer; N heat conduction cores respectively located in the N channel layers and penetrating through the substrate; and a thermocouple array comprising a thermocouple word line layer growing on the substrate in a negative direction of the first direction and N thermocouple layers located on the thermocouple word line layer, the N thermocouple layers being connected to the N heat conduction cores in a one-to-one correspondence mode. A first potential difference is applied between the thermocouple word line layer and a part of the thermocouple layers in the N thermocouple layers, and the heat conduction core connected to the part of the thermocouple layers is heated, such that the channel layer and the storage layer corresponding to the heat conduction core are respectively kept at a first preset temperature and a second preset temperature under the heat insulation effect of the tunneling layer. The present invention further provides a three-dimensional memory and an operation method therefor.

IPC Classes  ?

• H01L 23/34 - Arrangements for cooling, heating, ventilating or temperature compensation
• H01L 27/11582 - Electrically programmable read-only memories; Multistep manufacturing processes therefor with charge-trapping gate insulators, e.g. MNOS or NROM characterised by three-dimensional arrangements, e.g. with cells on different height levels with source and drain on different levels, e.g. with sloping channels the channels comprising vertical portions, e.g. U-shaped channels
• H01L 27/1157 - Electrically programmable read-only memories; Multistep manufacturing processes therefor with charge-trapping gate insulators, e.g. MNOS or NROM characterised by the memory core region with cell select transistors, e.g. NAND
• H01L 27/11556 - Electrically programmable read-only memories; Multistep manufacturing processes therefor with floating gate characterised by three-dimensional arrangements, e.g. with cells on different height levels with source and drain on different levels, e.g. with sloping channels the channels comprising vertical portions, e.g. U-shaped channels
• H01L 27/11524 - Electrically programmable read-only memories; Multistep manufacturing processes therefor with floating gate characterised by the memory core region with cell select transistors, e.g. NAND
• G11C 16/04 - Erasable programmable read-only memories electrically programmable using variable threshold transistors, e.g. FAMOS
• G11C 16/26 - Sensing or reading circuits; Data output circuits

Abstract

Provided in the embodiments of the present application are a ferroelectric tunnel junction device and a manufacturing method therefor. The ferroelectric tunnel junction device comprises a first electrode, a dielectric layer, a ferroelectric layer and a second electrode, which are sequentially stacked, wherein the thickness of the ferroelectric layer is less than five nanometers. The thickness of the ferroelectric layer is relatively thin, such that a relatively large tunneling current can be provided for the device, and the relatively thin ferroelectric layer can also increase depolarization field strength in the ferroelectric tunnel junction device, accelerate depolarization and reduce a data holding capability, so as to obtain a volatile data storage device. The volatile ferroelectric tunnel junction device can be applied to a reservoir computing network system. A plurality of polarization currents that are collected by the ferroelectric tunnel junction device during a running process are used as virtual nodes of a reservoir computing network system, and data can be input into the plurality of virtual nodes in parallel, that is, the data can be processed in parallel by the reservoir computing network system based on the ferroelectric tunnel junction device, such that the calculation of a neural network model is efficiently performed, and the requirement of the neural network model for efficient training is met.

IPC Classes  ?

• H01L 45/00 - Solid state devices specially adapted for rectifying, amplifying, oscillating, or switching without a potential-jump barrier or surface barrier, e.g. dielectric triodes; Ovshinsky-effect devices; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof

Abstract

Provided are a semiconductor device, a method of manufacturing the semiconductor device, and an electronic apparatus including the semiconductor device. According to the embodiments, the semiconductor device may include: a nanosheet stack layer on a substrate including a plurality of nanosheets spaced apart from each other in a vertical direction relative to the substrate, wherein at least one of the plurality of nanosheets includes a first portion in a first orientation, and at least one of an upper surface and a lower surface of the first portion is not parallel to a horizontal surface of the substrate.

IPC Classes  ?

• H01L 29/06 - Semiconductor bodies characterised by the shapes, relative sizes, or dispositions of the semiconductor regions
• H01L 29/08 - Semiconductor bodies characterised by the shapes, relative sizes, or dispositions of the semiconductor regions with semiconductor regions connected to an electrode carrying current to be rectified, amplified, or switched and such electrode being part of a semiconductor device which comprises three or more electrodes
• H01L 29/66 - Types of semiconductor device
• H01L 29/786 - Thin-film transistors
• H01L 29/775 - Field-effect transistors with one-dimensional charge carrier gas channel, e.g. quantum wire FET
• H01L 27/092 - Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only the components being field-effect transistors with insulated gate complementary MIS field-effect transistors
• H01L 21/8238 - Complementary field-effect transistors, e.g. CMOS

Abstract

Provided is a photoetching quality optimization method, comprising: determining, on the basis of a characteristic matrix method and the Bloch's theorem, a stray item of a wave function introduced from the roughness of the surface of a metal film layer (S101); inputting the stray item of the wave function into a photoetching quality deviation mathematical model for calculation simulation, thereby obtaining an effect analysis curve of the roughness of the metal film layer on the photoetching quality, the effect analysis curve representing an effect result of the roughness of the metal film layer on the photoetching quality (S102); and according to the effect result, reducing the roughness of the surface of the metal film layer and/or providing a metal-dielectric multilayer film structure between a mask above a metal-dielectric unit and air so as to optimize the photoetching quality of the metal-dielectric unit (S103). Provided are a photoetching quality optimization apparatus (1400), an electronic device (1500), a computer-readable storage medium, and a computer program product.

IPC Classes  ?

• G06F 30/23 - Design optimisation, verification or simulation using finite element methods [FEM] or finite difference methods [FDM]
• G06F 17/16 - Matrix or vector computation
• G03F 7/20 - Exposure; Apparatus therefor

Abstract

A mask parameter optimization method, comprising: acquiring a test pattern, a light source parameter, and an initial mask parameter, wherein the initial mask parameter comprises a mask thickness and an initial mask side wall angle; generating a plurality of candidate mask parameters according to the initial mask side wall angle in the initial mask parameter, the plurality of candidate mask parameters comprising different mask side wall angles and the same mask thickness; obtaining an imaging contrast ratio of each candidate mask parameter on the basis of the test pattern and the light source parameter; and selecting an optimal mask side wall angle from the plurality of candidate mask parameters according to the imaging contrast ratio. By optimizing the mask parameter of a multilayer film lens structure, the imaging contrast ratio is significantly improved, and the imaging resolution is improved.

IPC Classes  ?

• G03F 1/00 - Originals for photomechanical production of textured or patterned surfaces, e.g. masks, photo-masks or reticles; Mask blanks or pellicles therefor; Containers specially adapted therefor; Preparation thereof
• G03F 1/70 - Adapting basic layout or design of masks to lithographic process requirements, e.g. second iteration correction of mask patterns for imaging
• G03F 7/20 - Exposure; Apparatus therefor

Abstract

An analytic method and device for quantitatively calculating line edge roughness in a plasma ultra-diffraction photoetching process, related to the field of semiconductor manufacturing. The method comprises: determining a theoretical point spread function of a light source on the basis of field intensity distribution data of the light source at an opening of a focusing element in plasma ultra-diffraction photoetching (101); determining a plurality of transverse point width values of a point mapping graph on the basis of the point mapping graph (102); respectively determining an actual point spread function corresponding to the plurality of transverse point width values on the basis of the theoretical point spread function and the plurality of transverse point width values (103); determining an actual line spread function of a line graph on the basis of an attenuation constant and the actual point spread function (104); and determining a line edge roughness theoretical analysis formula of the plasma ultra-diffraction photoetching on the basis of a line edge roughness change value, the exposure dose of the line graph, the near-field photoresist contrast, and the graph logarithmic slope relationship of the line graph (109). The analysis method greatly improves the actual applicability of the surface plasma ultra-diffraction photoetching technology.

IPC Classes  ?

• G03F 7/20 - Exposure; Apparatus therefor

Abstract

Embodiments of the present application provide a fabrication method for a semiconductor device. A photolithographic coating is formed on a structure to be led out. The photolithographic coating comprises a first film layer, a photolithographic film layer and a second film layer. The refractive indexes of the first film layer and the second film layer are both smaller than 1, so that the photolithographic coating forms an optical structure having a relatively high reflection coefficient. The photolithographic coating is exposed by using light of a target wavelength and a mask. The structure is reflected by the photolithographic coating. The structure is used as a mask for imaging to the photolithographic film layer; meanwhile, the pattern of the mask is also imaged to the photolithographic film layer. That is, the patterns of the structure and the mask are both imaged to a target region of the photolithographic film layer, and the target region corresponds to the structure, which achieves the self-alignment of a pattern layer of the structure and a pattern layer in which a contact hole is located. The target region only corresponds to the structure in an overlapping region in which the patterns of the structure and the mask are simultaneously imaged on the photolithographic film layer during one exposure process, which may improve the alignment accuracy between different pattern layers and reduce alignment errors.

IPC Classes  ?

• H01L 21/027 - Making masks on semiconductor bodies for further photolithographic processing, not provided for in group or

Abstract

Embodiments of the present application provide a manufacturing method for a semiconductor device. A photoetching coating is formed on a structure to be led out, the photoetching coating comprises a first film layer, a photoetching film layer and a second film layer, and the refractive indexes of the first film layer and the second film layer are both smaller than 1, so that the photoetching coating forms an optical structure having a relatively high reflection coefficient; the photoetching coating is exposed by utilizing light having a first wavelength, and the structure to be led out is reflected by the photoetching coating; the structure to be led out is used as a mask for imaging to a first area of the photoetching film layer, the photoetching coating is exposed by using light having a second wavelength and the mask, and the pattern of the mask is imaged to a second area of the photoetching film layer, wherein an overlapping area of the first area and the second area is a leading-out area, and the leading-out area corresponds to the structure to be led out. Self-alignment of the layer of the structure to be led out and the layer where a contact hole is located is achieved, and only the overlapping area of imaging on the photoetching film layer in two exposures can correspond to the structure to be led out, so that the alignment precision between different layers can be improved, and alignment errors are reduced.

IPC Classes  ?

• H01L 21/027 - Making masks on semiconductor bodies for further photolithographic processing, not provided for in group or
• H01L 21/311 - Etching the insulating layers
• H01L 21/768 - Applying interconnections to be used for carrying current between separate components within a device