An apparatuses, systems, and techniques of a fault resilient transaction handling device for a virtualized system. A request to initiate a transaction involving a direct memory access (DMA) operation to access data associated with one or more guests is received at a device connected to a computing system that hosts the one or more guests. A page fault associated with execution of the DMA operation of the transaction is detected. A transaction fault handling protocol that is to be initiated to address the detected page fault is selected from a set of transaction fault handling protocols. The selected transaction fault handling protocol is caused to be performed to address the detected page fault.
A source network device may transmit a lock request including a request for a network element to allocate resources in association with an operation of a reduction tree. The source network device may transmit collision information associated with the lock request in response to receiving a lock failure notification indicating that one or more network elements have failed to allocate the resources. A network element may receive, from one or more child nodes, lock requests defined for a data-reduction operation associated with a data-reduction flow. The network element may propagate a received lock request to a parent node. A root network device may transmit a lock command to network elements of a reduction tree. The lock command includes a request for an allocation of resources. The root network device may transmit collision information associated with the lock command in response to receiving a lock failure notification.
G06F 9/46 - Dispositions pour la multiprogrammation
G06F 9/06 - Dispositions pour la commande par programme, p.ex. unités de commande utilisant des programmes stockés, c. à d. utilisant un moyen de stockage interne à l'équipement de traitement de données pour recevoir ou conserver les programmes
G06F 9/52 - Synchronisation de programmes; Exclusion mutuelle, p.ex. au moyen de sémaphores
3.
CVD SYSTEM WITH SUBSTRATE CARRIER AND ASSOCIATED MECHANISMS FOR MOVING SUBSTRATE THERETHROUGH
A substrate carrier and a mechanism for moving the substrate carrier through a chemical vapor deposition system are provided. The substrate carrier includes a cylindrical housing having an interior surface. A plurality of plurality of shelves fixed to the interior surface, each shelf configured to support at least one substrate. The substrate carrier may include a connector configured to engage the substrate carrier with the mechanism. The mechanism may include a moveable arm and a motor configured to actuate the moveable arm. The moveable arm may include an actuating member connected to the motor and configured to move the moveable arm between a retracted state and an extended state. The moveable arm may be configured to operate in a chamber having a first pressure and a first temperature and the motor may be configured to operate in an environment having a second pressure.
H01L 21/677 - Appareils spécialement adaptés pour la manipulation des dispositifs à semi-conducteurs ou des dispositifs électriques à l'état solide pendant leur fabrication ou leur traitement; Appareils spécialement adaptés pour la manipulation des plaquettes pendant la fabrication ou le traitement des dispositifs à semi-conducteurs ou des dispositifs électriques à l'état solide ou de leurs composants pour le transport, p.ex. entre différents postes de travail
C23C 16/00 - Revêtement chimique par décomposition de composés gazeux, ne laissant pas de produits de réaction du matériau de la surface dans le revêtement, c. à d. procédés de dépôt chimique en phase vapeur (CVD)
4.
CVD SYSTEM WITH FLANGE ASSEMBLY FOR FACILITATING UNIFORM AND LAMINAR FLOW
A first and a second flange assembly configured for facilitating uniform and laminar flow in a system are provided. The first flange assembly includes a first flange body configured to introduce a gas into a chamber. The first flange assembly includes a plurality of outlet tubes disposed on an interior surface of the first flange body and a plurality of inlet tubes disposed on an exterior surface of the first flange body and in fluid communication with the plurality of outlet tubes. The second flange assembly includes a second flange body configured to remove the gas from the chamber. The second flange assembly includes a plurality of through holes extending from an interior surface to an exterior surface of the second flange body and a plurality of exit tubes extending from the exterior surface of the second flange body and in fluid communication with the plurality of through holes.
C23C 16/455 - Revêtement chimique par décomposition de composés gazeux, ne laissant pas de produits de réaction du matériau de la surface dans le revêtement, c. à d. procédés de dépôt chimique en phase vapeur (CVD) caractérisé par le procédé de revêtement caractérisé par le procédé utilisé pour introduire des gaz dans la chambre de réaction ou pour modifier les écoulements de gaz dans la chambre de réaction
C23C 16/44 - Revêtement chimique par décomposition de composés gazeux, ne laissant pas de produits de réaction du matériau de la surface dans le revêtement, c. à d. procédés de dépôt chimique en phase vapeur (CVD) caractérisé par le procédé de revêtement
C30B 25/14 - Moyens d'introduction et d'évacuation des gaz; Modification du courant des gaz réactifs
C01B 32/186 - Préparation par dépôt chimique en phase vapeur [CVD]
H01L 21/20 - Dépôt de matériaux semi-conducteurs sur un substrat, p.ex. croissance épitaxiale
5.
PROCESS FOR LOCALIZED REPAIR OF GRAPHENE-COATED LAMINATION STACKS AND PRINTED CIRCUIT BOARDS
Processes for localized lasering of a lamination stack and graphene-coated printed circuit board (PCB) are disclosed. An example PCB may include a lamination stack, post-lamination, that may further include a core, an adhesive layer, and at least one graphene-metal structure. A top layer of graphene of the graphene-metal structure may have never been grown before the lamination process or may have been removed post-lamination such that a portion of the top layer of graphene is missing. The localized lasering process described herein may grow (for the first time) or re-grow the graphene layer of the exposed portion of the metal layer without adverse effects to the rest of the lamination stack or PCB and while promoting a uniform layer of graphene on the top surface. A process of growing graphene through application of molecular layer and a self-assembled monolayer (SAM), are also described herein.
Processes for creating a two-dimensional-target structure are disclosed. An example process to create a two-dimensional-target structure may include the process of providing two-dimensional material grown on an initial substrate to create a two-dimensional-substrate structure; applying the two-dimensional-substrate structure to a target substrate via an adhesion promoter to create a lamination stack; applying a lamination process to the lamination stack; and then removing the initial substrate from the lamination stack, post-lamination, to create the two-dimensional-target structure. The two-dimensional-target structure may then be used in such rigid or flexible electronic devices and/or non-standard devices as the target substrate may be rigid or flexible and/or translucent in contrast to the initial substrate first used to grow the two-dimensional material.
B32B 37/00 - Procédés ou dispositifs pour la stratification, p.ex. par polymérisation ou par liaison à l'aide d'ultrasons
H01L 21/02 - Fabrication ou traitement des dispositifs à semi-conducteurs ou de leurs parties constitutives
B82B 3/00 - Fabrication ou traitement des nanostructures par manipulation d’atomes ou de molécules, ou d’ensembles limités d’atomes ou de molécules un à un comme des unités individuelles
H01L 21/20 - Dépôt de matériaux semi-conducteurs sur un substrat, p.ex. croissance épitaxiale
7.
PROCESS FOR LAMINATING GRAPHENE-COATED PRINTED CIRCUIT BOARDS
Processes for laminating a graphene-coated printed circuit board (PCB) are disclosed. An example laminated PCB may include a lamination stack that may include an inner core, an adhesive layer, and at least one graphene-metal structure. Pressure and heat—which may be applied under vacuum or controlled gas atmosphere–may be applied to the lamination stack, after all materials have been placed. The graphene of the graphene-metal structure is designed to promote high frequency performance and heat management within the PCB.
B32B 9/00 - Produits stratifiés composés essentiellement d'une substance particulière non couverte par les groupes
B32B 3/26 - Produits stratifiés caractérisés essentiellement par le fait qu'une des couches comporte des discontinuités ou des rugosités externes ou internes, ou bien qu'une des couches est de forme générale non plane; Produits stratifiés caractérisés essentiellement par des particularismes de forme caractérisés par une couche comportant des cavités ou des vides internes
B32B 7/12 - Liaison entre couches utilisant des adhésifs interposés ou des matériaux interposés ayant des propriétés adhésives
B32B 37/12 - Procédés ou dispositifs pour la stratification, p.ex. par polymérisation ou par liaison à l'aide d'ultrasons caractérisés par l'usage d'adhésifs
B32B 15/04 - Produits stratifiés composés essentiellement de métal comprenant un métal comme seul composant ou comme composant principal d'une couche adjacente à une autre couche d'une substance spécifique
Processes for laminating a conductive-lubricant coated Printed Circuit Board (PCB) are disclosed. An example laminated PCB may include a lamination stack that may further include a core, an adhesive layer, and at least one graphene-metal structure or at least one hexagonal Boron Nitride metal (h-BN-metal) structure. The materials of the PCB may change in accordance with the invention described herein, including the materials of the core, the materials of the conductive-lubricant coatings, or the metal layers of the conductive-lubricant-metal structures. Doping processes for each change in materials used are also described herein. The conductive-lubricant of the conductive-lubricant-metal structure will promote high frequency performance and heat management within the PCB. Furthermore, a removal process of those materials post-lamination is described herein to promote protection of materials and subsequent removal of protective layers without breakage or tearing.
B32B 9/00 - Produits stratifiés composés essentiellement d'une substance particulière non couverte par les groupes
B32B 7/12 - Liaison entre couches utilisant des adhésifs interposés ou des matériaux interposés ayant des propriétés adhésives
B32B 37/12 - Procédés ou dispositifs pour la stratification, p.ex. par polymérisation ou par liaison à l'aide d'ultrasons caractérisés par l'usage d'adhésifs
B32B 15/04 - Produits stratifiés composés essentiellement de métal comprenant un métal comme seul composant ou comme composant principal d'une couche adjacente à une autre couche d'une substance spécifique
A network device (100) includes multiple ports (102, 104), multiple buffer slices (106), a controller (101), and buffer control circuitry (112, 114). The multiple ports are configured to communicate packets over a network. The multiple buffer slices are linked respectively to the multiple ports. The controller is configured to allocate a group of two or more of the buffer slices to a selected port among the ports. The buffer control circuitry is configured to buffer the packets, communicated via the selected port, in the group of the buffer slices, using zero-copy buffering.
H04L 49/9005 - Dispositions de mémoires tampon en utilisant une allocation dynamique de l'espace des mémoires tampon
H04L 47/283 - Commande de flux; Commande de la congestion par rapport à des considérations temporelles en réponse à des retards de traitement, p.ex. causés par une gigue ou un temps d'aller-retour [RTT]
H04L 67/568 - Stockage temporaire des données à un stade intermédiaire, p.ex. par mise en antémémoire
A computer system (100) includes a volatile memory and at least one processor (102). The volatile memory includes a protected storage segment (PSS - 112) configured to store firmware-authentication program code for authenticating firmware of the computer system. The at least one processor is configured to receive a trigger to switch to a given version of the firmware, to obtain, in response to the trigger, a privilege to access the PSS, to authenticate the given version of the firmware by executing the firmware-authentication program code from the PSS, to switch to the given version of the firmware upon successfully authenticating the given version, and to take an alternative action upon failing to authenticate the given version.
G06F 21/57 - Certification ou préservation de plates-formes informatiques fiables, p.ex. démarrages ou arrêts sécurisés, suivis de version, contrôles de logiciel système, mises à jour sécurisées ou évaluation de vulnérabilité
11.
EFFICIENT PARALLELIZED COMPUTATION OF A BENES NETWORK CONFIGURATION
A routing controller (30) includes an interface (68) and multiple processors (60). The interface is configured to receive a permutation (76) defining requested interconnections between N input ports and N output ports of a Benes network (24). The Benes network includes multiple 2-by-2 switches (42), and is reducible in a plurality of nested subnetworks associated with respective nesting levels, down to irreducible subnetworks including a single 2-by-2 switch. The multiple processors are configured to collectively determine a setting of the 2-by-2 switches that implements the received permutation, including determining sub-settings for two or more subnetworks of a given nesting level in parallel, and to configure the multiple 2-by-2 switches of the Benes network in accordance with the determined setting.
An optoelectronic transmitter (10) includes an electro-optic modulator (12), digital driving circuitry (14), and feedback circuitry (30). The electro-optic modulator is configured to modulate an optical signal in response to an electrical drive signal. The digital driving circuitry is coupled to the electro-optical modulator and is configured to generate the electrical drive signal. The feedback circuitry is configured to measure a quantity indicative of a power level of the modulated optical signal produced by the electro-optic modulator, and to adapt a supply voltage to the digital driving circuitry in response to the measured quantity.
H04B 10/50 - Systèmes de transmission utilisant des ondes électromagnétiques autres que les ondes hertziennes, p.ex. les infrarouges, la lumière visible ou ultraviolette, ou utilisant des radiations corpusculaires, p.ex. les communications quantiques Émetteurs
Various embodiments provide a method for fabricating a couplable electro-optical device. In an example embodiment, the method includes fabricating at least one raw electro- optical device on a substrate; applying lens material to a working stamp; aligning the substrate and the working stamp; pressing the substrate onto the lens material until the distance between the substrate and the working stamp is a predetermined distance; and curing the lens material to form an integrated lens secured to the at least one electro-optical device on the substrate. An anti-reflective coating layer may be optionally applied on top of the molded lens. The couplable electro-optical device may be incorporated into a receiver, transmitter, and/or transceiver using passive alignment to align the couplable electro-optical device to an optical fiber.
YISSUM RESEARCH DEVELOPMENT COMPANY OF THE HEBREW UNIVERSITY LTD (Israël)
Inventeur(s)
Patronas, Ioannis (giannis)
Zahavi, Eitan
Schapira, Michael
Mentovich, Elad
Abrégé
A method for distributed allocation of data paths in an optical network (100) including optical switches (30, 32, 130) connected by optical links (44, 140), includes receiving a request for a data path for connecting a source node (10) and a destination node (20). In in response to the request, one or more queries are sent, the queries corresponding to one or more candidate optical circuits that connect the source node and the destination node, the queries requesting one or more processors (230) to configure the optical switches along the candidate optical circuits to reserve optical channels on the optical links of the candidate optical circuits for the requested data path. An optical circuit is identified from among the candidate optical circuits, in which all the optical channels for the requested data path have been reserved successfully. The requested data path is established over the identified optical circuit.
H04L 12/721 - Procédures de routage, p.ex. routage par le chemin le plus court, routage par la source, routage à état de lien ou routage par vecteur de distance
H04L 12/729 - Sélection d’un chemin avec bande passante ou débit adéquat
Apparatuses, systems, and associated methods of manufacturing are described that provide a dynamic data interconnect and networking cable configuration. The dynamic data interconnect includes a substrate, transmitters supported on the substrate configured to generate signals, and receivers supported on the substrate configured to receive signals. The dynamic data interconnect further includes a number of connection pads that receive data cables attached thereto and a number of transmission lanes that operably couple the transmitters and receivers to the connection pads. The dynamic data interconnect further includes transmission circuitry in communication with each of the transmitters and receivers such that, in an operational configuration, the transmission circuitry determines a transmission state of the dynamic data interconnect and selectively disables operation of at least a portion of the transmitters or at least a portion of the receivers.
Apparatuses, systems, and associated methods of manufacturing are described that provide an optical interposer and associated communication system. An example optical interposer includes a substrate having a first end that receives a first optical fiber welded thereto and a second end that receives a plurality of photonic integrated circuits (PICs) attached thereto. The interposer further includes an optical waveguide network defined by the substrate that provides optical communication between the first welded optical fiber and the plurality of PICs. The optical waveguide network also includes optical redistribution elements supported by the substrate. In an operational configuration, the optical interposer receives a first input optical signal from the first welded optical fiber, and the plurality of optical redistribution elements successively split the first input optical signal such that a plurality of output optical signals is directed to the plurality of PICs.
G02B 6/12 - OPTIQUE ÉLÉMENTS, SYSTÈMES OU APPAREILS OPTIQUES - Détails de structure de dispositions comprenant des guides de lumière et d'autres éléments optiques, p.ex. des moyens de couplage du type guide d'ondes optiques du genre à circuit intégré
G02B 6/122 - Elements optiques de base, p.ex. voies de guidage de la lumière
G02B 6/125 - Courbures, branchements ou intersections
G02B 6/42 - Couplage de guides de lumière avec des éléments opto-électroniques
G02B 6/43 - Dispositions comprenant une série d'éléments opto-électroniques et d'interconnexions optiques associées
G02B 6/28 - Moyens de couplage optique ayant des bus de données, c. à d. plusieurs guides d'ondes interconnectés et assurant un système bidirectionnel par nature en mélangeant et divisant les signaux
An optoelectronic device (20) includes thin film structures (56) disposed on a semiconductor substrate (54) and patterned to define components of an integrated drive circuit, which is configured to generate a drive signal. A back end of line (BEOL) stack (42) of alternating metal layers (44, 46) and dielectric layers (50) is disposed over the thin film structures. The metal layers include a modulator layer (48), which contains a plasmonic waveguide (36, 99, 105) and a plurality of electrodes (30, 32, 34, 96, 98, 106), which apply a modulation to surface plasmons polaritons (SPPs) propagating in the plasmonic waveguide in response to the drive signal. A plurality of interconnect layers are patterned to connect the thin film structures to the electrodes. An optical input coupler (38, 82) is configured to couple light into the modulator layer, whereby the light is modulated by the modulation of the SPPs, and an optical output coupler (38, 82) is configured to couple the modulated light out of the modulator layer.
G02F 1/225 - Dispositifs ou dispositions pour la commande de l'intensité, de la couleur, de la phase, de la polarisation ou de la direction de la lumière arrivant d'une source lumineuse indépendante, p.ex. commutation, ouverture de porte ou modulation; Optique non linéaire pour la commande de l'intensité, de la phase, de la polarisation ou de la couleur par interférence dans une structure de guide d'ondes optique
G02F 1/01 - Dispositifs ou dispositions pour la commande de l'intensité, de la couleur, de la phase, de la polarisation ou de la direction de la lumière arrivant d'une source lumineuse indépendante, p.ex. commutation, ouverture de porte ou modulation; Optique non linéaire pour la commande de l'intensité, de la phase, de la polarisation ou de la couleur
18.
CONSOLIDATING MULTIPLE ELECTRICAL DATA SIGNALS INTO AN OPTICAL DATA SIGNAL ON A MULTI-CHIP MODULE USING ASIC FOR CONTROLLING A PHOTONICS TRANSCEIVER
A multi-chip module (MCM - 10) includes a substrate (11), one or more photonic chips (14) disposed on the substrate, and an electronic chip (12) disposed on the substrate. The one or more photonic chips include one or more optical channels (22), which are configured to guide propagating optical signals, and two or more photonic modulator-segments (18) coupled to each of the optical channels, each photonic modulator-segment configured to modulate the propagating optical signals responsively to digitally modulated driving electrical signals provided thereto. The electronic chip is configured to generate the digitally modulated driving electrical signals on multiple different lanes (16) of the electronic chip, synchronize the driving electrical signals on the multiple lanes to a same clock, separately control respective phases of the driving electrical signals, fine-tune the voltages of the driving electrical signals on the multiple lanes, and drive the photonic modulator-segments on the photonic chips with the synchronized and phase-controlled driving electrical signals.
A passive dual polarization unit and coherent transceiver and/or receiver including one or more passive dual polarization units are provided. An example passive dual polarization unit includes a polarization splitter configured to split an input signal into a TE mode and TM mode signals; TE/TM splitters each designed to split the TE/TM mode signals into first TE/TM signals and second TE/TM signals; a first TE signal polarization rotation component for receiving the first TE signal and providing a third TM signal having the same magnitude and time dependence as the first TE signal; a first TM signal polarization rotation component for receiving the first TM signal and providing a third TE signal having the same magnitude and time dependence as the first TM signal; and TE/TM couplers that couple the second TE/TM signals and the third TE/TM signals to generate output TE/TM signals.
H04B 10/2569 - Dispositions spécifiques à la transmission par fibres pour réduire ou éliminer la distorsion ou la dispersion due à la dispersion modale de polarisation [PMD]
A semiconductor device assembly (10) includes a multi-layer printed circuit board (PCB - 40), a thermoelectric cooler (TEC - 30), a chip (22), and packaged integrated circuitry (IC - 28). The multi-layer PCB includes a lateral heat conducting path (60) formed in a recessed area (44) of the PCB. The TEC and the chip are disposed on the PCB, side-by-side to one another over the lateral heat conducting path. The TEC is configured to evacuate heat from the chip via the lateral heat conducting path, and to dissipate the evacuated heat via a first end of a heat sink (33) in thermal contact with the TEC. The packaged IC is disposed on an un-recessed area of the PCB, wherein the packaged IC is configured to dissipate heat via a second end of the heat sink that is in thermal contact with the packaged IC.
YISSUM RESEARCH DEVELOPMENT COMPANY OF THE HEBREW UNIVERSITY LTD. (Israël)
Inventeur(s)
Aharon, Eran
Marom, Dan Mark
Bakopoulos, Paraskevas
Mentovich, Elad
Abrégé
An optical switching device (20) includes a substrate (39) and first and second optical waveguides (23, 25) having respective first and second tapered ends (62, 64), which are fixed on the substrate in mutual proximity one to another. A pair of electrodes (36, 38) is disposed on the substrate with a gap therebetween. A cantilever beam (32) is disposed on the substrate within the gap and configured to deflect transversely between first and second positions within the gap in response to a potential applied between the electrodes. A third optical waveguide (21) is mounted on the cantilever beam and has a third tapered end (60) disposed between the first and second tapered ends of the first and second waveguides, so that the third tapered end is in proximity with the first tapered end when the cantilever beam is in the first position and is in proximity with the second tapered end when the cantilever beam is in the second position.
G02B 6/122 - Elements optiques de base, p.ex. voies de guidage de la lumière
G02B 6/125 - Courbures, branchements ou intersections
G02B 6/35 - Moyens de couplage optique comportant des moyens de commutation
G02B 6/12 - OPTIQUE ÉLÉMENTS, SYSTÈMES OU APPAREILS OPTIQUES - Détails de structure de dispositions comprenant des guides de lumière et d'autres éléments optiques, p.ex. des moyens de couplage du type guide d'ondes optiques du genre à circuit intégré
An optical interconnect device and the method of fabricating it are described. The device includes an in-plane laser cavity transmitting a light beam along a first direction, a Franz Keldysh (FK) optical modulator transmitting the light beam along the first direction, a mode- transfer module including a tapered structure disposed after the FK optical modulator along the first direction to enlarge the spot size of the light beam to match an external optical fiber and a universal coupler controlling the light direction. The tapered structure can be made linear or non- linear along the first direction. The universal coupler passes the laser light to an in-plane external optical fiber if the fiber is placed along the first direction, or it is a vertical coupler in the case that the external optical fiber is placed perpendicularly to the substrate surface. The coupler is coated with highly reflective material.
G02B 6/12 - OPTIQUE ÉLÉMENTS, SYSTÈMES OU APPAREILS OPTIQUES - Détails de structure de dispositions comprenant des guides de lumière et d'autres éléments optiques, p.ex. des moyens de couplage du type guide d'ondes optiques du genre à circuit intégré
G02B 6/122 - Elements optiques de base, p.ex. voies de guidage de la lumière
Computing apparatus (22) includes a host processor (30), which runs a virtual machine monitor (VMM) (40), which supports a plurality of virtual machines (38) and includes a cryptographic security software module (54). A network interface controller (NIC) (32) links the host processor to a network (28) so as to transmit and receive data packets from and to the virtual machines and includes a cryptographic security hardware logic module (44), which when invoked by the VMM, applies the cryptographic security protocol to the data packets while maintaining a state context of the protocol with respect to each of the virtual machines. Upon encountering an exception in applying the cryptographic security protocol, the NIC transfers the data packet, together with the state context of the cryptographic security protocol with respect to the given virtual machine, to the cryptographic security software module for processing.
A network interface controller (30) that is connected to a host (34) and a packet communications network. The network interface controller (30) includes electrical circuitry configured as a packet processing pipeline (72) with a plurality of stages (76, 78, 80, 82). It is determined in the network interface controller (30) that at least a portion of the stages (76, 78, 80, 82) of the pipeline (72) are acceleration-defined stages (78, 80). Packets are processed in the pipeline (72) by transmitting data to an accelerator (74) from the acceleration-defined stages (78, 80), performing re- spective acceleration tasks (86, 90) on the transmitted data in the accelerator (74), and returning processed data from the accelerator (74) to receiving stages (80, 82) of the pipeline (72).
Apparatus (36) for data communications includes a host interface (64) and a network interface (62), which receives from a packet communication network (24) data, packets containing video data comprising interleaved words (82, 84) of luminance data and chrominance data. In one embodiment, packet processing circuitry (66) separates the luminance data from the chrominance data and writes the luminance data, via the host interface, to a luminance buffer (58) in the host memory (38) while writing the chrominance data, via the host interface, to at least one chrominance buffer (60) in the memory, separate from the luminance buffer. In another embodiment, in which the video data include data words of more than eight bits, the packet processing circuitry writes the video data to at least one buffer while justifying the video data in the memory so that the video data with respect to successive pixels in the sequence are byte-aligned in the buffer.
H04N 9/64 - Circuits pour le traitement de signaux de couleur
H04N 19/00 - Procédés ou dispositions pour le codage, le décodage, la compression ou la décompression de signaux vidéo numériques
H04N 19/117 - Filtres, p.ex. pour le pré-traitement ou le post-traitement
H04N 19/136 - Caractéristiques ou propriétés du signal vidéo entrant
H04N 19/132 - Procédés ou dispositions pour le codage, le décodage, la compression ou la décompression de signaux vidéo numériques utilisant le codage adaptatif caractérisés par l’élément, le paramètre ou la sélection affectés ou contrôlés par le codage adaptatif Échantillonnage, masquage ou troncature d’unités de codage, p.ex. ré-échantillonnage adaptatif, saut de trames, interpolation de trames ou masquage de coefficients haute fréquence de transformée
H04N 19/186 - Procédés ou dispositions pour le codage, le décodage, la compression ou la décompression de signaux vidéo numériques utilisant le codage adaptatif caractérisés par l’unité de codage, c. à d. la partie structurelle ou sémantique du signal vidéo étant l’objet ou le sujet du codage adaptatif l’unité étant une couleur ou une composante de chrominance
H04N 21/23 - Traitement de contenu ou de données additionnelles; Opérations élémentaires de serveur; Intergiciel de serveur
H04N 21/60 - Distribution sélective de contenu, p.ex. télévision interactive ou vidéo à la demande [VOD] - Détails de la communication entre serveur et client
26.
METHOD AND APPARATUS FOR OPTICAL COUPLING OF OPTICAL SIGNALS FOR A PHOTONIC INTEGRATED CIRCUIT
An optical coupler and method of assembly are described that provide efficient coupling from the photonic integrated circuit (PIC) waveguide layer to external components, such as optical fibers, VCSELs, photodetectors, and gain blocks, among others. The optical coupler includes a PIC that can be supported by-a printed circuit board, an optoelectronic transducer supported by the PIC that can convert between optical signals and corresponding electrical signals, and a coupled waveguide assembly. The coupled waveguide assembly includes a low-index waveguide, a high-index waveguide, and a reflective surface that changes a pathway of the optical signals to direct the optical signals from the optoelectronic transducer into the low-index waveguide or from the low-index waveguide into the optoelectronic transducer.
An apparatus (20) includes a Silicon Photonics (SiP) device (24, 94) and a ferrule (28, 102), The SiP device includes multiple optical waveguides (36, 106). The ferrule includes multiple optical fibers (68, 114) for exchanging optical signals with the respective optical waveguides of the SiP device. In some embodiments, an array (32) of micro-lenses (48) is configured to couple the optical signals between the optical waveguides of the SiP device and the respective optical fibers of the ferrule. In some embodiments, a polymer layer (98) is placed between the SiP device and the ferrule, and includes multiple polymer-based Spot-Size Converters (SSCs - 110, 118) that are configured to couple the optical signals between the optical waveguides of the SiP device and the respective optical fibers of the ferrule.
Above a prescribed mounting surface on the surface (22A) of a flexible wiring substrate (22), a press plate (28) for a flexible wiring substrate is provided at a position right below a first heat dissipation block (24) and a press sheet (26) in order to press the mounting surface toward a bottom cover (12). The press plate (28) for a flexible wiring substrate (28) has five protrusions (28PA, 28PB) that are aligned with each other. Respective protrusions (28PA, 28PB) are formed so as to intersect with an electroconductive pattern (22ACP) at a prescribed interval.
A method of communication includes receiving, in a network interface device (26), first and second requests from an initiator process (22) running on an initiator host (24) to transmit, respectively, first and second data to first and second target processes (28, 34) running on one or more target nodes (14, 16), via a packet network (18). A single dynamically-connected initiator context is allocated for serving both the first and second requests. A first connect packet referencing the dynamically-connected (DC) initiator context is directed to the first target process so as to open a first dynamic connection with the first target process, followed by transmission of the first data over the first dynamic connection. The first dynamic connection is closed after the transmission of the first data, and a second connect packet is transmitted so as to open a second dynamic connection with the second target process, followed by transmission of the second data.
H04L 12/28 - Réseaux de données à commutation caractérisés par la configuration des liaisons, p.ex. réseaux locaux [LAN Local Area Networks] ou réseaux étendus [WAN Wide Area Networks]
brevets
