One or more examples relate to voltage level shifting. An example apparatus (100) may include first and second inputs (102, 104), an output (106), and a circuit. The first and second inputs may receive compliments (VIN+, VIN-) of a signal represented by first voltage levels. The output may provide the signal represented by second voltage levels. The circuit may change voltage levels utilized to represent the signal from first voltage levels to second voltage levels. The circuit may include cross-coupled first high voltage switches (HV MP1, HV MP2), a pair of series coupled switches (114, 116), and a pair of voltage clamping switches (108, 110). The cross-coupled first high voltage switches may selectively couple the output to a high voltage node (Vnode) responsive to a high voltage level of the signal. The pair of series coupled switches may comprising respective second high voltage switches, and the pair of series coupled switches may selectively couple the output to a first voltage supply. The pair of voltage clamping switches may increase OFF-resistance of the respective second high voltage switches of the pair of series coupled switches responsive to a low voltage level at the respective input.
An apparatus having a substrate having first and second substrate contacts; a chip having a front-side chip contact and first and second back-side chip contacts, the front-side chip contact electrically connected to the first substrate contact; a chiplet having a chiplet contact electrically connected the first back-side chip contact; and a lead electrically connected to the second back-side chip contact and electrically connected to the second substrate contact.
3.
SWITCHING DATA BASED ON A BUS IDENTIFIER AND A DEVICE IDENTIFIER
One or more examples relate to an apparatus to switch data based on a bus identifier and a device identifier. Such an apparatus may include an upstream port for a respective peripheral component interconnect express (PCIe)-compliant communicative connection with a host; a downstream port for a respective PCIe-compliant communicative connection with an endpoint; and a switching logic. The switching logic may store a bus identifier and a device identifier for the endpoint; and switch data at least partially responsive to the bus identifier and the device identifier of the endpoint.
4.
APPARATUS AND METHOD FOR ACTIVE INDUCTOR MODULATION
An active inductor modulator circuit is provided. The active inductor modulator circuit may include a circuit to receive an input signal and provide an output signal at an output terminal of the circuit based on a clock signal, a modulated active inductor coupled to the circuit to improve a time delay between the input signal and the provided output signal, and a modulation clock circuit to generate a delayed clock signal to enable the modulated active inductor prior to a transition of the output signal from a first logic state to a second logic state.
One or more examples relate, generally to supply voltage based or temperature based fine control of a tunable oscillator of a PLL. An associated method includes: receiving one or more values indicative of temperature or supply voltage of a phase-locked loop (PLL); setting a digital fine-tuning control code to an initialization code, the initialization code at least partially based on the received one or more values indicative of temperature or supply voltage of the PLL, wherein the digital fine-tuning control code for setting a number of tuning-elements within a fine bank of a tunable oscillator; and starting, with the set digital fine-tuning control code, a process to set an initial frequency of the oscillator at or close to a target frequency. The process may be a calibration process performed before initially acquiring lock or re-acquiring lock.
H03L 7/099 - Commande automatique de fréquence ou de phase; Synchronisation utilisant un signal de référence qui est appliqué à une boucle verrouillée en fréquence ou en phase - Détails de la boucle verrouillée en phase concernant principalement l'oscillateur commandé de la boucle
H03L 1/00 - Stabilisation du signal de sortie du générateur contre les variations de valeurs physiques, p.ex. de l'alimentation en énergie
H03L 1/02 - Stabilisation du signal de sortie du générateur contre les variations de valeurs physiques, p.ex. de l'alimentation en énergie contre les variations de température uniquement
6.
AUTOMATIC USB3 HUB FOR DETECTING AND CHANGING LINK SPEED
A USB control method comprising: counting errors encountered by a USB connection; comparing a number of counted errors to an error count threshold within a set time frame (404); identifying a port speed configuration for the USB connection (408); and changing the port speed configuration for the USB connection to a slower port speed configuration than the identified port speed configuration (414)
One or more examples relate, generally, to providing timing signals to gate drivers of a converter. An example apparatus for providing timing signals to gate drivers of a converter includes a circuit that includes a timing input, and a plurality of outputs. The timing input may receive an incoming timing signal. The plurality of outputs may couple to a respective plurality of gate drivers to control an output voltage of a converter. The circuit may provide respective timing signals, at respective ones of the plurality of outputs at least partially responsive to the incoming timing signal, the respective timing signals synchronized such that like edges of the respective timing signals coincide.
H02M 3/158 - Transformation d'une puissance d'entrée en courant continu en une puissance de sortie en courant continu sans transformation intermédiaire en courant alternatif par convertisseurs statiques utilisant des tubes à décharge avec électrode de commande ou des dispositifs à semi-conducteurs avec électrode de commande utilisant des dispositifs du type triode ou transistor exigeant l'application continue d'un signal de commande utilisant uniquement des dispositifs à semi-conducteurs avec commande automatique de la tension ou du courant de sortie, p.ex. régulateurs à commutation comprenant plusieurs dispositifs à semi-conducteurs comme dispositifs de commande finale pour une charge unique
H02M 1/08 - Circuits spécialement adaptés à la production d'une tension de commande pour les dispositifs à semi-conducteurs incorporés dans des convertisseurs statiques
H02M 1/088 - Circuits spécialement adaptés à la production d'une tension de commande pour les dispositifs à semi-conducteurs incorporés dans des convertisseurs statiques pour la commande simultanée de dispositifs à semi-conducteurs connectés en série ou en parallèle
H03K 17/28 - Modifications pour introduire un retard avant commutation
H03K 17/64 - Commutation ou ouverture de porte électronique, c. à d. par d'autres moyens que la fermeture et l'ouverture de contacts caractérisée par l'utilisation de composants spécifiés par l'utilisation, comme éléments actifs, de dispositifs à semi-conducteurs les dispositifs étant des transistors bipolaires à charges inductives
An apparatus includes two PHY circuits, each including a PHY transmitter circuit and connected to a universal serial bus (USB)-C connector. The apparatus includes a USB circuit to issue a receiver detect signal through one of the PHY transmitters circuit to the USB-C connector, issue another receiver detect signal through the other PHY transmitter circuit to the USB-C connector, determine which receiver detect signal resulted in a termination in a USB-C element, and consequently determine an orientation of a USB plug connected between the apparatus and the USB-C element.
A metal-insulator-metal (MIM) capacitor module includes an outer electrode, an insulator, an inner electrode, an outer electrode extension structure, an inner electrode contact element, and an outer electrode contact element. The outer electrode includes a plurality of vertically-extending outer electrode sidewalls. The insulator is formed in an opening defined by the vertically-extending outer electrode sidewalls, and includes a plurality of vertically-extending insulator sidewalls. The inner electrode formed in an interior opening defined by the insulator. The outer electrode extension structure extends laterally from a particular vertically-extending outer electrode sidewall. The inner electrode contact element and outer electrode contact element are formed in a metal layer. The inner electrode contact element is electrically connected to the inner electrode, and the outer electrode contact element is electrically connected to the outer electrode extension structure.
H01L 23/522 - Dispositions pour conduire le courant électrique à l'intérieur du dispositif pendant son fonctionnement, d'un composant à un autre comprenant des interconnexions externes formées d'une structure multicouche de couches conductrices et isolantes inséparables du corps semi-conducteur sur lequel elles ont été déposées
H01L 49/02 - Dispositifs à film mince ou à film épais
10.
METAL-INSULATOR-METAL (MIM) CAPACITOR MODULE WITH DIELECTRIC SIDEWALL SPACER
A metal-insulator-metal (MIM) capacitor includes a bottom electrode cup, an insulator cup, and a top electrode. The bottom electrode cup includes a laterally-extending bottom electrode cup base, and a bottom electrode cup sidewall extending upwardly from the laterally-extending bottom electrode cup base. The insulator cup is formed in an opening defined by the bottom electrode cup, and includes a laterally-extending insulator cup base formed over the laterally-extending bottom electrode cup base, and an insulator cup sidewall extending upwardly from the laterally-extending insulator cup base. A dielectric sidewall spacer is located between the insulator cup sidewall and the bottom electrode cup sidewall. The top electrode is formed in an opening defined by the insulator cup.
This description relates, generally, to protecting a circuit from an input voltage. Various examples include an apparatus including one or more circuits to draw current from, or provide current to, a pair of connectors for an input circuit. The connectors may be for electrical coupling to first and second terminals of a twisted pair. The one or more circuits may be at least partially responsive to positive and negative biasing signals. The apparatus may additionally include an operational amplifier to generate the positive and negative biasing signals. The operational amplifier may include: a first input terminal at least partially responsive to a reference voltage and a second input terminal at least partially responsive to a common-mode voltage of the input circuit. Related systems and methods are also disclosed.
A device with one-time-programmable (OTP) memory, boot code, volatile memory, and non- volatile memory. Boot code may use information in OTP to authenticate code of an implicit owner of the electronic device; receive a first create owner container request; create a first owner container comprising a first signed data image; store the first owner container; and use the first signed data image to authenticate first executable code associated with the first owner. Boot code may transfer ownership from the first owner to a second owner, including authenticating a signed transfer of ownership command using a key stored in the first owner container and creating a second owner container comprising a second signed data image associated with the second owner; storing the second owner container; revoking the first owner container; and using the second signed data image to authenticate second executable code associated with the second owner of the electronic device.
G06F 21/57 - Certification ou préservation de plates-formes informatiques fiables, p.ex. démarrages ou arrêts sécurisés, suivis de version, contrôles de logiciel système, mises à jour sécurisées ou évaluation de vulnérabilité
Disclosed are systems, methods, and devices for communicating a source of a 10SPE wake. Such a communication may be performed over a low-pin count hardware interface of a 10SPE physical layer (PHY) module having a split arrangement. A controller side of a 10SPE PHY may perform a local or remote 10SPE wake forward in response to a communicated source of a wake. Also disclosed is a digital interface for operatively coupling a PHY controller to PHY transceiver over a low-pin count connection, where the digital interface includes circuitry for checking the integrity of circuitry of the digital interface. Also disclosed is a PHY transceiver of a 10SPE PHY, where the transceiver includes a circuitry for controlling a starting polarity of frames.
An electronic device may have a plurality of defined life cycle stages and a one-time-programmable (OTP) memory comprising a plurality of life cycle bits, wherein respective bit patterns of the life cycle bits may correspond with respective life cycle stages of the defined life cycle stages. The electronic device may also have a boot code stored in read only memory and executable by a processor to receive a request to transition from a current life cycle stage to a next life cycle stage and, in response to the received request, automatically generate a bit pattern corresponding to the next life cycle stage of the plurality of defined life cycle stages and program the bit pattern corresponding to the next life cycle stage of the plurality of defined life cycle stages in the OTP memory during a time when the OTP memory is not user-accessible.
G06F 21/71 - Protection de composants spécifiques internes ou périphériques, où la protection d'un composant mène à la protection de tout le calculateur pour assurer la sécurité du calcul ou du traitement de l’information
G06F 21/62 - Protection de l’accès à des données via une plate-forme, p.ex. par clés ou règles de contrôle de l’accès
15.
INITIATING SOFTAP MODE PROVISIONING OF WIFI DEVICE VIA CUSTOM DATA FIELD
One or more examples relate to a method, which includes sending, from a provisioner WiFi device to a provisionee WiFi device in an idle mode, a probe request frame including a random data in a custom data field; powering up the provisionee WiFi device in a SoftAp mode at least partially responsive to receiving the probe request frame; sending, from the provisioner WiFi device to the provisionee WiFi device in the SoftAp mode, a further probe request frame including the random data in a custom data field; sending, from the provisionee WiFi device in the SoftAp mode to the provisioner WiFi device, a probe response frame; establishing a secure WiFi connection between the provisioner WiFi device and the provisionee WiFi device utilizing passphrases respectively generated by the provisioner WiFi device and the provisionee WiFi device; and sending provisioning data, from the provisioner WiFi device to the provisionee WiFi device in SoftAp mode, via the secure WiFi connection.
A system and method of testing an integrated circuit provide a first clock signal to a first flip-flop with an output to a functional circuit, provide a second clock signal to a second flip-flop with an input from the functional circuit, wherein the second flip-flip has a minimum hold time, provide a test input to the first flip-flop, observe a signal propagation time through the functional circuit, determine the signal propagation time is less than the minimum hold time of the second flip-flop, and increasing a timing separation by adding a unit of delay to the first clock signal or subtracting a unit of delay from the second clock signal.
G01R 31/3193 - Matériel de test, c. à d. circuits de traitement de signaux de sortie avec une comparaison entre la réponse effective et la réponse connue en l'absence d'erreur
A device having a digital-to-analog converter (DAC) data generator circuit to perform a function upon an event and generate digital DAC data based on the function and the event, and a DAC circuit to generate an analog waveform signal from the digital DAC data.
An apparatus includes a sampling circuit (204) to sample input from a sensor circuit (202). The input includes a cosine coil waveform and a sine coil waveform. The sampling circuit is to generate a cosine coil sampled data stream and a sine coil sampled data stream. The apparatus includes an adjustment circuit (206) to, based upon a characterization of the sensor circuit, delay the cosine coil sampled data stream or the sine coil sampled data stream.
G01D 5/20 - Moyens mécaniques pour le transfert de la grandeur de sortie d'un organe sensible; Moyens pour convertir la grandeur de sortie d'un organe sensible en une autre variable, lorsque la forme ou la nature de l'organe sensible n'imposent pas un moyen de conversion déterminé; Transducteurs non spécialement adaptés à une variable particulière utilisant des moyens électriques ou magnétiques influençant la valeur d'un courant ou d'une tension en faisant varier l'inductance, p.ex. une armature mobile
G01D 3/02 - Dispositions pour la mesure prévues pour les objets particuliers indiqués dans les sous-groupes du présent groupe avec dispositions pour changer ou corriger la fonction de transfert
19.
REDUCING ERROR IN ESTIMATED ANGULAR POSITION OF A ROTOR OF A MOTOR
Sensorless field-oriented control (FOC) of permanent magnet synchronous motor (PMSM) using saliency based estimator is generating an error due to the sensitivity in the calculation of error in estimated angular position to q-axis current due to effects of stator magnetic saliency. The solution is to generate An error correction signal combined with the estimation to generate a correct signal
An apparatus is disclosed that includes a common drain, a common source, and a common gate, respectively, of the power semiconductor device, and paralleled transistor cells of the power semiconductor device. In various examples, a configuration of a gate structure of a first respective transistor cell coupled with the common gate is different than a configuration of a gate structure of a second respective transistor cell coupled with the common gate. Alternatively or additionally, in various examples, a configuration of a structure coupled between a first portion of the paralleled transistor cells and the common gate is different than a configuration of a structure coupled between the second portion of the paralleled transistor cells and the common gate.
An apparatus and method including a command input to receive a command with a macro identifier from a channel processor, a macro memory storing a plurality of flash control commands, each comprising a corresponding duration and a corresponding plurality of target control values to control a flash target; and a second finite state machine comprising a plurality of control outputs each corresponding to control inputs on the flash target, wherein in response to a received command, the first finite state machine locates in the macro memory a sequence of flash control commands associated with the macro identifier and sequentially outputs the flash control commands to the second finite state machine; and wherein the second finite state machine drives each of the plurality of control outputs based on corresponding values in the first flash control command for the duration specified in the current flash control command.
An electronic device includes a transaction host, first and second peripherals, memory, an access control register, and first and second access controllers. The memory stores access control identifier management instructions, a first task related to the first peripheral, and a first bitmask indicating respective access settings for the first and second peripherals for performing the first task. The access control register includes a first access control identifier for the first peripheral and a second access control identifier for the second peripheral. The transaction host executes the access control identifier management instructions to program the first and second access control identifiers based on the first bitmask, and subsequently executes the first task. The first and second access controllers control access to the first and second peripherals, respectively, based on the respective first and second access control identifiers programmed based on the first bitmask.
G06F 21/85 - Protection des dispositifs de saisie, d’affichage de données ou d’interconnexion dispositifs d’interconnexion, p.ex. les dispositifs connectés à un bus ou les dispositifs en ligne
23.
METAL-INSULATOR-METAL (MIM) CAPACITOR INCLUDING AN INSULATOR CUP AND LATERALLY-EXTENDING INSULATOR FLANGE
A metal-insulator-metal (MIM) capacitor includes a bottom electrode cup, an insulator, and a top electrode. The bottom electrode cup includes a laterally-extending bottom electrode cup base and a bottom electrode cup sidewall extending upwardly from the laterally-extending bottom electrode cup base. The insulator includes an insulator cup formed in an opening defined by the bottom electrode cup, and an insulator flange extending laterally outwardly from the insulator cup sidewall and extending laterally over an upper surface of the bottom electrode cup sidewall. The top electrode is formed in an opening defined by the insulator cup. The top electrode is insulated from the upper surface of the bottom electrode cup sidewall by the insulator flange.
H01L 23/522 - Dispositions pour conduire le courant électrique à l'intérieur du dispositif pendant son fonctionnement, d'un composant à un autre comprenant des interconnexions externes formées d'une structure multicouche de couches conductrices et isolantes inséparables du corps semi-conducteur sur lequel elles ont été déposées
H01L 49/02 - Dispositifs à film mince ou à film épais
24.
METAL-INSULATOR-METAL (MIM) CAPACITOR MODULE INCLUDING A CUP-SHAPED STRUCTURE WITH A ROUNDED CORNER REGION
A metal-insulator-metal (MIM) capacitor includes a bottom electrode cup, an insulator, and a top electrode. The bottom electrode cup includes a laterally-extending bottom electrode cup base and a bottom electrode cup sidewall extending upwardly from the laterally-extending bottom electrode cup base. The insulator includes an insulator cup formed in an opening defined by the bottom electrode cup, and a rounded insulator flange extending laterally outwardly and curving upwardly from the insulator cup, the rounded insulator flange covering an upper surface of the bottom electrode cup sidewall. The top electrode is formed in an opening defined by the insulator cup. The top electrode is insulated from the upper surface of the bottom electrode cup sidewall by the rounded insulator flange.
H01L 23/522 - Dispositions pour conduire le courant électrique à l'intérieur du dispositif pendant son fonctionnement, d'un composant à un autre comprenant des interconnexions externes formées d'une structure multicouche de couches conductrices et isolantes inséparables du corps semi-conducteur sur lequel elles ont été déposées
H01L 49/02 - Dispositifs à film mince ou à film épais
25.
ELECTRONIC DEVICE INCLUDING ACCESS CONTROL IDENTIFIERS FOR CONTROLLING ACCESS TO PERIPHERALS
G06F 21/85 - Protection des dispositifs de saisie, d’affichage de données ou d’interconnexion dispositifs d’interconnexion, p.ex. les dispositifs connectés à un bus ou les dispositifs en ligne
Examples may include an apparatus including a circuit coupled between a supply line, a return line, and a terminal. The circuit may provide an oscillating signal to the terminal. The circuit may include a first switch to couple the supply line with the terminal. The circuit may also include a second switch to couple the return line with the terminal. The circuit may also include a first inductor coupled between the first switch and the terminal. The circuit may also include a second inductor coupled between the second switch and the terminal. The circuit may also include a first diode coupled between the return line and an internal node of the first switch and the first inductor. The circuit may also include a second diode coupled between the supply line and an internal node of the second switch and the second inductor. Related systems and methods are also disclosed.
H02P 27/08 - Dispositions ou procédés pour la commande de moteurs à courant alternatif caractérisés par le type de tension d'alimentation utilisant une tension d’alimentation à fréquence variable, p.ex. tension d’alimentation d’onduleurs ou de convertisseurs utilisant des convertisseurs de courant continu en courant alternatif ou des onduleurs avec modulation de largeur d'impulsions
H02M 1/12 - Dispositions de réduction des harmoniques d'une entrée ou d'une sortie en courant alternatif
H02M 7/537 - Transformation d'une puissance d'entrée en courant continu en une puissance de sortie en courant alternatif sans possibilité de réversibilité par convertisseurs statiques utilisant des tubes à décharge avec électrode de commande ou des dispositifs à semi-conducteurs avec électrode de commande utilisant des dispositifs du type triode ou transistor exigeant l'application continue d'un signal de commande utilisant uniquement des dispositifs à semi-conducteurs, p.ex. onduleurs à impulsions à un seul commutateur
27.
VERIFICATION OF OFF-CHIP COMPUTER-READABLE INSTRUCTIONS AND RELATED SYSTEMS, METHODS, AND APPARATUSES
An apparatus may comprise an off-chip data storage device and a semiconductor device package including processing circuitry and an on-chip memory device, the off-chip data storage device including master data and portions of the computer-readable instructions. The processing circuitry may retrieve a master data that includes a digital signature that may be used to verify the master data and a hash table that may include hash information for others of the portions. The processing circuitry may also verify the master instructions responsive to the digital signature, retrieve a portion, calculate a hash value of the retrieved portion, and determine whether the calculated hash value correlates to hash information of the hash table.
G06F 21/79 - Protection de composants spécifiques internes ou périphériques, où la protection d'un composant mène à la protection de tout le calculateur pour assurer la sécurité du stockage de données dans les supports de stockage à semi-conducteurs, p.ex. les mémoires adressables directement
G06F 21/54 - Contrôle des usagers, programmes ou dispositifs de préservation de l’intégrité des plates-formes, p.ex. des processeurs, des micrologiciels ou des systèmes d’exploitation au stade de l’exécution du programme, p.ex. intégrité de la pile, débordement de tampon ou prévention d'effacement involontaire de données par ajout de routines ou d’objets de sécurité aux programmes
G06F 21/57 - Certification ou préservation de plates-formes informatiques fiables, p.ex. démarrages ou arrêts sécurisés, suivis de version, contrôles de logiciel système, mises à jour sécurisées ou évaluation de vulnérabilité
28.
SYSTEMS AND METHODS FOR MANAGING INTERRUPT PRIORITY LEVELS
G06F 9/48 - Lancement de programmes; Commutation de programmes, p.ex. par interruption
G06F 13/26 - Gestion de demandes d'interconnexion ou de transfert pour l'accès au bus d'entrée/sortie utilisant l'interruption avec commande prioritaire
A computer system includes a non-transitory computer-readable memory to store (a) a vector table including an exception vector pointing to an exception handler and (b) a vector fail address of a vector fetch bus error handler, and a processor to identify an exception, initiate an exception vector fetch in response to the identified exception to read the exception vector from the vector table, identify a vector fetch bus error associated with the exception vector fetch, access the vector fail address of the vector fetch bus error handler in response to the vector fetch bus error, and execute the vector fetch bus error handler.
G06F 11/10 - Détection ou correction d'erreur par introduction de redondance dans la représentation des données, p.ex. en utilisant des codes de contrôle en ajoutant des chiffres binaires ou des symboles particuliers aux données exprimées suivant un code, p.ex. contrôle de parité, exclusion des 9 ou des 11
One or more examples relate, generally, to an apparatus. The apparatus includes a charged particle source and a charged particle pointer. The charged particle pointer urges charged particles emitted by the charged particle source in a predetermined direction. The charged particle pointer comprises a repeller, and an isolator positioned along a path extending from the repeller in the predetermined direction.
An article of manufacture includes a non-transitory machine-readable medium. The medium includes instructions that cause a processor to execute a shift instruction. The shift instruction is to cause a source data in memory to be shifted left or shifted right. The shift instruction is to include a source parameter and a bit size parameter. The processor is to execute the shift instruction through a shift of a first source word of the source data by the bit size parameter to yield a first intermediate word, a shift of a second source word of the source data by the bit size parameter to yield a second intermediate word and a first set of shifted-out bits, and through execution of a logical OR operation on the first intermediate word and the first set of shifted-out bits to yield a first result word.
An article of manufacture includes a non-transitory machine-readable medium. The medium includes instructions. The instructions, when read and executed by a processor, cause the processor to determine that a first input instruction in a code stream to be executed is to perform a read-modify-write operation, determine that the first input instruction is to target a memory location, and, based on a determination that the first input instruction is to perform the read-modify-write operation and the determination that the first input instruction is to target the memory location, convert the first input instruction to a second input instruction to target the memory location with a mask to cause an atomic operation to implement the read-modify-write operation.
One or more examples relate to an apparatus includes an error detector, an oscillator, an analog proportional path, and a digital integral path. The oscillator includes an analog proportional input, a digital integral input, and an analog integral input. The analog proportional path to provide a control signal for the analog proportional input of the oscillator. The digital integral path to provide a control for the digital integral input and the analog integral input of the oscillator. A first signal path of an interface includes a direct coupling between the digital phase detector and integrator and the digital integral input of the oscillator. A second signal path of the interface includes a digital-to-analog converter (DAC) with a filtered delta-sigma modulator (DSM) input between the digital phase detector and integrator and the analog integral input of the oscillator
H03L 7/093 - Commande automatique de fréquence ou de phase; Synchronisation utilisant un signal de référence qui est appliqué à une boucle verrouillée en fréquence ou en phase - Détails de la boucle verrouillée en phase concernant principalement l'agencement de détection de phase ou de fréquence y compris le filtrage ou l'amplification de son signal de sortie utilisant des caractéristiques de filtrage ou d'amplification particulières dans la boucle
H03L 7/099 - Commande automatique de fréquence ou de phase; Synchronisation utilisant un signal de référence qui est appliqué à une boucle verrouillée en fréquence ou en phase - Détails de la boucle verrouillée en phase concernant principalement l'oscillateur commandé de la boucle
34.
METHOD AND APPARATUS FOR CARRYING CONSTANT BIT RATE (CBR) CLIENT SIGNALS
A method and apparatus in which a data stream generated by a previous network node, a cumulative phase offset report (CPOR) and a client rate report (CRR) are received. A counter accumulating a PHY-scaled stream clock (IPSCk) is sampled at a nominal sampling period (Tps) to obtain a cumulative PHY-scaled count (CPSC). A PHY-scaled stream phase offset (PSPO) is calculated that indicates phase difference between a PHY-scaled stream nominal bit count (LPSD) and an incoming PHY-scaled count delta (IPSD), where IPSD indicates CPSC increment between successive CPSC samples. The data stream is demultiplexed to obtain CBR carrier streams that include a previous network node CPOR (CPOR-P) and a previous network node CPO (CPO-P). A CPO is calculated that is a function of CPO-P and the PSPO. CPO-P is replaced with the calculated CPO. The CBR carrier streams are multiplexed into intermediate-network-node data streams that are transmitted from the intermediate-network-node.
H04J 3/16 - Systèmes multiplex à division de temps dans lesquels le temps attribué à chacun des canaux au cours d'un cycle de transmission est variable, p.ex. pour tenir compte de la complexité variable des signaux, pour adapter le nombre de canaux transmis
H04L 47/38 - Commande de flux; Commande de la congestion en adaptant le codage ou le taux de compression
H04L 65/60 - Diffusion en flux de paquets multimédias
35.
SYSTEM AND METHOD FOR A STORAGE CONTROLLER CARD WITH REDUNDANT BOOT STORAGE
An storage controller and method for providing a respective first and a second solid-state memory interface to control a first and a second flash memory, a RAID controller coupled to the first and second solid-state memory interface, the RAID controller presenting a single boot device to a CPU and synchronizing writes to made to the boot device to both of the first and second solid-state memories, the RAID controller providing a plurality of data storage ports to be coupled to at least three data storage drives wherein the RAID controller is to present a unified data device to the CPU.
A flyback converter to receive an input voltage and provide an output voltage is provided, and may include a transformer having a primary winding and secondary winding, a primary switch coupled to the primary winding, a synchronous rectifier device coupled to the secondary winding, and a secondary side control circuit to turn on the synchronous rectifier device by outputting a control signal at a first amplitude, subsequently modify the control signal to maintain a voltage across the synchronous rectifier device substantially constant until a predicted time that precedes a current in the synchronous rectifier device reaching substantially zero, subsequently turn off the synchronous rectifier device based on the voltage across the synchronous rectifier device reaching substantially zero, and subsequently turn on the synchronous rectifier device by outputting the control signal at a second amplitude, before the primary switch is turned on. The second amplitude is less than the first amplitude.
H02M 1/00 - APPAREILS POUR LA TRANSFORMATION DE COURANT ALTERNATIF EN COURANT ALTERNATIF, DE COURANT ALTERNATIF EN COURANT CONTINU OU VICE VERSA OU DE COURANT CONTINU EN COURANT CONTINU ET EMPLOYÉS AVEC LES RÉSEAUX DE DISTRIBUTION D'ÉNERGIE OU DES SYSTÈMES D'ALI; TRANSFORMATION D'UNE PUISSANCE D'ENTRÉE EN COURANT CONTINU OU COURANT ALTERNATIF EN UNE PUISSANCE DE SORTIE DE CHOC; LEUR COMMANDE OU RÉGULATION - Détails d'appareils pour transformation
H02M 3/335 - Transformation d'une puissance d'entrée en courant continu en une puissance de sortie en courant continu avec transformation intermédiaire en courant alternatif par convertisseurs statiques utilisant des tubes à décharge avec électrode de commande ou des dispositifs à semi-conducteurs avec électrodes de commande pour produire le courant alternatif intermédiaire utilisant des dispositifs du type triode ou transistor exigeant l'application continue d'un signal de commande utilisant uniquement des dispositifs à semi-conducteurs
H02M 1/08 - Circuits spécialement adaptés à la production d'une tension de commande pour les dispositifs à semi-conducteurs incorporés dans des convertisseurs statiques
A computer-implemented method (1200) is provided including instantiating an object of an analog information model object class definition (1204) defining a net interface to a digital circuit simulator, and a plurality of analog circuit properties. The method includes connecting the net interface of the data structure (1206) to a first net defined in a digital circuit simulation and identifying all other instances of the AIM object class definition connected to the first net defined in the digital circuit simulation (1208) of a simulated digital circuit and determining an analog voltage at and current through the first net based on the analog circuit properties of all instances (1210) connected to the first net (1212).
G06F 30/367 - Vérification de la conception, p.ex. par simulation, programme de simulation avec emphase de circuit intégré [SPICE], méthodes directes ou de relaxation
G06F 30/31 - Saisie informatique, p.ex. éditeurs spécifiquement adaptés à la conception de circuits
G06F 30/38 - Conception de circuits au niveau mixte des signaux analogiques et numériques
Vapor cells may include a body including a cavity within the body. A first substrate bonded to a second substrate at an interface within the body, at least one of the first substrate, the second substrate, or an interfacial material between the first and second substrates may define at least one recess or pore in a surface. A smalltest dimension of the at least one recess or pore may be about 500 microns or less, as measured in a direction parallel to at least one surface of the first substrate partially defining the cavity.
G04F 5/14 - Appareils pour la production d'intervalles de temps prédéterminés, utilisés comme étalons utilisant des horloges atomiques
H03L 7/26 - Commande automatique de fréquence ou de phase; Synchronisation utilisant comme référence de fréquence les niveaux d'énergie de molécules, d'atomes ou de particules subatomiques
39.
SYSTEM AND METHOD FOR ENHANCING FLASH CHANNEL UTILIZATION
An apparatus and method for dispatching flash commands. The apparatus includes a plurality of queues, wherein each queue comprises an input to receive a flash command, an output to send a flash command, and an empty signal output to signal when the queue is empty, wherein each queue is assigned a unique, ordered priority. The apparatus includes a selector comprising a plurality of flash command inputs, a flash command output to a flash target, and a selection input, wherein each flash command input is coupled to a corresponding queue output. The apparatus includes an arbiter comprising inputs receiving each queue empty signal and receiving a lock bit from the flash command output of the selector and comprising a selection output coupled to the selection input of the selector. The flash command comprises a lock bit and a plurality of control bits to output to control inputs on a flash target.
A device includes (a) an integrated inductor having an inductor wire and (b) a metal interconnect arrangement, both formed in an integrated circuit layer stack of alternating metal layers and via layers. At least a portion of the inductor wire is defined by an inductor element stack including multiple metal layer inductor elements formed in multiple respective metal layers, and multiple via layer inductor elements formed in multiple respective via layers and conductively connected to the metal layer inductor elements. Each via layer inductor element has a length of at least 1 µm in each of two lateral directions orthogonal to each other and perpendicular to the vertical direction. The metal interconnect arrangement includes metal layer interconnect elements formed in the respective metal layers, and interconnect vias formed in the respective via layers.
H01L 23/522 - Dispositions pour conduire le courant électrique à l'intérieur du dispositif pendant son fonctionnement, d'un composant à un autre comprenant des interconnexions externes formées d'une structure multicouche de couches conductrices et isolantes inséparables du corps semi-conducteur sur lequel elles ont été déposées
H01L 23/528 - Configuration de la structure d'interconnexion
41.
SYSTEM FOR MANAGING ACCESS TO A MEMORY RESOURCE BY MULTIPLE USERS
A system (e.g., NVMe controller) for managing access to a memory resource by multiple users may include memory storing function queue categorizations for function queues associated with each user, and circuitry to store and execute a multi-user arbitration algorithm that arbitrates access to the memory resource by the multiple users. The function queue categorizations assign a function category to each function queue associated with each user. The multi-user arbitration algorithm includes (a) selecting an intra-user winning function queue for each respective user by performing an intra-user function queue arbitration of the function queues associated with the respective user based on the function queue categorizations associated with the arbitrated function queues, (b) selecting an inter-user winning function queue by performing an inter-user function queue arbitration of the intra-user winning function queues selected for the multiple users, and (c) serving a function from the inter-user winning function queue to the memory resource.
A device includes an integrated inductor and metal interconnect formed in an integrated circuit (IC) structure. The integrated inductor includes an inductor wire having a portion defined by an inductor element stack including (a) a metal layer inductor element formed in a metal layer in the IC structure and (b) a multi-component via layer inductor element formed in a via layer in the IC structure vertically adjacent the metal layer, and conductively connected to the metal layer inductor element. The multi-component via layer inductor element includes a via layer inductor element cup-shaped component formed from a first metal, and a via layer inductor element fill component formed from a second metal in an opening defined by the via layer inductor element cup-shaped component. The metal interconnect includes a metal layer interconnect element formed in the metal layer, and an interconnect via formed in the via layer from the first metal.
H01L 23/522 - Dispositions pour conduire le courant électrique à l'intérieur du dispositif pendant son fonctionnement, d'un composant à un autre comprenant des interconnexions externes formées d'une structure multicouche de couches conductrices et isolantes inséparables du corps semi-conducteur sur lequel elles ont été déposées
H01L 23/528 - Configuration de la structure d'interconnexion
H01L 23/532 - Dispositions pour conduire le courant électrique à l'intérieur du dispositif pendant son fonctionnement, d'un composant à un autre comprenant des interconnexions externes formées d'une structure multicouche de couches conductrices et isolantes inséparables du corps semi-conducteur sur lequel elles ont été déposées caractérisées par les matériaux
43.
SYSTEM AND METHOD FOR FLEXIBLY CROSSING PACKETS OF DIFFERENT PROTOCOLS
An apparatus and method coupling a first and a second data bus comprising selectors for routing first bus egress lanes to egress memories, each egress memory coupled to one second bus egress lane, where the second bus has more egress lanes than the first. Each egress memory corresponds to one second bus egress lane. A first FSM selecting which first bus egress lane to load into each egress memory synchronous with the first bus clock. A second FSM outputting egress memory values to the second bus synchronous with the second bus clock. A set of ingress memories, each memory coupled to one second bus ingress lane and to an input of each ingress selector. A third FSM loading the ingress memories synchronous with the second bus clock. A fourth FSM selecting which ingress memory to route to each first bus ingress lane synchronous with the first bus clock.
One or more examples relate, generally, to an orientation of a rotor. Some examples relate to an apparatus. The apparatus may include sample-accumulation logic to generate, over a time duration, a value indicative of inductance at least partially responsive to a probe signal provided to a stator of a motor. The apparatus may also include a probe-current discriminator to generate a further value indicative of an orientation of a rotor of the motor at least partially responsive to the generated value. The apparatus may also include update logic to update a process variable of a control loop at least partially responsive to a state of the further value.
H02P 6/18 - Dispositions de circuits pour détecter la position sans éléments séparés pour détecter la position
H02P 6/185 - Dispositions de circuits pour détecter la position sans éléments séparés pour détecter la position utilisant la détection par inductance, p.ex. excitation par impulsion
45.
DEVICES INCLUDING CAPACITOR COUPLING POWER PATH TO GROUND PATH AND ASSOCIATED COMPONENTS AND SYSTEMS
The device may include a core. The device may include built-up layers arranged over the core. The device may also include a ground path disposed in a first built-up layer of the built-up layers. The device may also include a power path disposed in a second built-up layer of the built-up layers. The device may also include a multi-terminal capacitor on a top layer of the built-up layers. The multi-terminal capacitor may be coupled to the ground path and the power path through respective vias passing through the built-up layers. The respective vias may be arranged to alternate such that respective vias coupled to the power path neighbor a respective via coupled to the ground path.
H01L 23/50 - Dispositions pour conduire le courant électrique vers le ou hors du corps à l'état solide pendant son fonctionnement, p.ex. fils de connexion ou bornes pour des dispositifs à circuit intégré
A curvature compensated bandgap circuit that is capable of matching best-in-class two (2) parts-per-million performance without over-temperature trimming. This improves performance metrics for precision voltage reference products without requiring individual device tuning during production thereof. A core bandgap circuit comprises a main operational amplifier having a second order bowed voltage response over temperature. A ptat circuit is coupled to the core bandgap circuit to provide a sigmoidal third order shape for the bandgap voltage.
G05F 3/30 - Régulateurs utilisant la différence entre les tensions base-émetteur de deux transistors bipolaires fonctionnant à des densités de courant différentes
A state machine motor controller (SMMC) interface comprises a plurality of states which defines a unique set of poles/ motor phase /phases energized. Digital sensors capture the start of overlap of rotor poles with stator poles. The state change occurs when a rotor pole starts overlapping with a stator pole. The number of states depends on the number of phases and the design of the motor. The SMMC has up to four inputs to accept rotational information from digital sensors and can control motors having up to 16 states. A sequencer is used to keep track of state changes and provides a next state depending on forward/reverse direction setting and braking setting. A counter provides rotational speed based upon the number of clock pulses per time period for a state change. The sequencer checks for a faulty sensor(s) and generates a fault interrupt therefrom.
G01D 5/245 - Moyens mécaniques pour le transfert de la grandeur de sortie d'un organe sensible; Moyens pour convertir la grandeur de sortie d'un organe sensible en une autre variable, lorsque la forme ou la nature de l'organe sensible n'imposent pas un moyen de conversion déterminé; Transducteurs non spécialement adaptés à une variable particulière utilisant des moyens électriques ou magnétiques produisant des impulsions ou des trains d'impulsions utilisant un nombre variable d'impulsions dans un train
H02P 25/092 - Convertisseurs spécialement adaptés pour la commande des moteurs à réluctance
Examples disclosed herein relate generally to providing frames at a network port. Some examples relate to an apparatus. The apparatus may include a network port to directly couple the apparatus to a switch. The apparatus may also include a transmission logic to provide a frame at the network port at a time slot of a switch-associated cycle time. The transmission logic may provide the frame at the time slot at least partially responsive to an offset value and a port number. Related devices, systems and methods are also disclosed.
H04Q 9/00 - Dispositions dans les systèmes de commande à distance ou de télémétrie pour appeler sélectivement une sous-station à partir d'une station principale, sous-station dans laquelle un appareil recherché est choisi pour appliquer un signal de commande ou
G05B 19/418 - Commande totale d'usine, c.à d. commande centralisée de plusieurs machines, p.ex. commande numérique directe ou distribuée (DNC), systèmes d'ateliers flexibles (FMS), systèmes de fabrication intégrés (IMS), productique (CIM)
A method and apparatus for embedding a microprocessor in a programmable logic device (PLD), where the microprocessor has a logic unit that can operate in two modes. A first mode is a general purpose mode running at least one general purpose process related to the PLD, and a second mode is a fixed function mode emulating a fixed function for use by logic configured into a fabric of the PLD (fabric). A memory unit is coupled to the logic unit and to the fabric, and the fabric is operable for transferring signals with the logic unit in relation to the fixed function.
An apparatus and method for scheduling memory requests including receiving a plurality of requests having a type and associating each request of the received plurality of requests with a corresponding target, which is associated with one channel of a plurality of channels. The method assigning a priority to each request, assigning a utilization cost to each request based on the request's target and request type, and queueing each request of the plurality of requests for scheduling. The method selecting a first request of the received plurality of requests to be scheduled based on its priority, scheduling the first request for processing at a time when the first request utilization cost is less than or equal to a current value of a dynamic utilization counter, and debiting the dynamic utilization counter by the first request utilization cost.
A timing device includes an oven having a chamber, a crystal oscillator disposed in the chamber that generates a clock signal, and one or more sensors to generate operational characteristic signals indicative of respective operational characteristics of the crystal oscillator or the oven. The timing device includes a plurality of I/O connections and an IC device. The IC device includes processing logic to generate information that indicates how the generated clock signal is to be modified and a modulator coupled to the processing logic and the crystal oscillator. The modulator modulates the generated clock signal in relation to the information to generate a modulated clock signal indicative of the one or more operational characteristics of the crystal oscillator or the oven. The modulator outputs the modulated clock signal over a single one of the plurality of I/O connections.
H03B 5/00 - Production d'oscillation au moyen d'un amplificateur comportant un circuit de réaction entre sa sortie et son entrée
F24C 7/08 - Disposition ou montage des dispositifs de commande ou de sécurité
H03L 1/02 - Stabilisation du signal de sortie du générateur contre les variations de valeurs physiques, p.ex. de l'alimentation en énergie contre les variations de température uniquement
H03L 1/04 - Stabilisation du signal de sortie du générateur contre les variations de valeurs physiques, p.ex. de l'alimentation en énergie contre les variations de température uniquement - Détails structurels destinés à maintenir la température constante
H05B 1/02 - Dispositions de commutation automatique spécialement adaptées aux appareils de chauffage
An electronic device includes a first interposer, a first integrated circuit (IC) device affixed to the first interposer, a second interposer, and a second IC device affixed to the second interposer. The second interposer is bonded to the first interposer. The first interposer includes first interposer circuitry and a first connection element electrically connected to the first interposer circuitry. The second interposer includes second interposer circuitry and a second connection element electrically connected to the second interposer circuitry. The second connection element is bonded to the first connection element to define a connection element pair. The connection element pair provides an electrical connection between the first interposer circuitry and the second interposer circuitry.
H01L 23/538 - Dispositions pour conduire le courant électrique à l'intérieur du dispositif pendant son fonctionnement, d'un composant à un autre la structure d'interconnexion entre une pluralité de puces semi-conductrices se trouvant au-dessus ou à l'intérieur de substrats isolants
H01L 23/498 - Connexions électriques sur des substrats isolants
H01L 21/48 - Fabrication ou traitement de parties, p.ex. de conteneurs, avant l'assemblage des dispositifs, en utilisant des procédés non couverts par l'un uniquement des groupes
H01L 25/065 - Ensembles consistant en une pluralité de dispositifs à semi-conducteurs ou d'autres dispositifs à l'état solide les dispositifs étant tous d'un type prévu dans le même sous-groupe des groupes , ou dans une seule sous-classe de , , p.ex. ensembles de diodes redresseuses les dispositifs n'ayant pas de conteneurs séparés les dispositifs étant d'un type prévu dans le groupe
A method and apparatus for decoding in which a first failed decode operation is performed on raw bit values of a FEC block by a LDPC decoder. When the FEC block is determined to be a trapped block an updated LLR map is generated; a FEC block is determined to be a trapped block, if the number of unsatisfied check nodes, i.e. the syndrome weight, is less than a threshold; the updated LLR map and either the raw bit values of the FEC block or a failed-decode-output- block from a previous failed decode operation on the trapped block are provided to the LDPC decoder; a decode operation of the LDPC decoder is performed using the updated LLR map on the bit values of the FEC block or the failed-decode-output-block from the previous failed decode operation; and the generating, the providing and the performing are repeated until the decode operation is successful or until a predetermined number of trapped-block-decoding iterations have been performed. When the decode operation is successful in decoding the FEC block the codeword is output.
H03M 13/11 - Détection d'erreurs ou correction d'erreurs transmises par redondance dans la représentation des données, c.à d. mots de code contenant plus de chiffres que les mots source utilisant un codage par blocs, c.à d. un nombre prédéterminé de bits de contrôle ajouté à un nombre prédéterminé de bits d'information utilisant plusieurs bits de parité
G06F 11/10 - Détection ou correction d'erreur par introduction de redondance dans la représentation des données, p.ex. en utilisant des codes de contrôle en ajoutant des chiffres binaires ou des symboles particuliers aux données exprimées suivant un code, p.ex. contrôle de parité, exclusion des 9 ou des 11
54.
INTEGRATED CIRCUIT PACKAGE MODULE INCLUDING A BONDING SYSTEM
An integrated circuit package module includes an integrated circuit package device including a contact element, and a bonding system formed on the integrated circuit package device. The bonding system includes a bonding system substrate and a bonding element formed in the bonding system substrate and conductively coupled to the contact element of the integrated circuit package device. The bonding element includes (a) a conduction component conductively connected to the contact element, the conduction component formed from a first metal having a first melting point, and (b) a bonding component formed from a second metal having a second melting point lower than the first melting point of the first metal.
H01L 23/485 - Dispositions pour conduire le courant électrique vers le ou hors du corps à l'état solide pendant son fonctionnement, p.ex. fils de connexion ou bornes formées de couches conductrices inséparables du corps semi-conducteur sur lequel elles ont été déposées formées de structures en couches comprenant des couches conductrices et isolantes, p.ex. contacts planaires
H01L 23/498 - Connexions électriques sur des substrats isolants
H01L 21/60 - Fixation des fils de connexion ou d'autres pièces conductrices, devant servir à conduire le courant vers le ou hors du dispositif pendant son fonctionnement
55.
INTRODUCTION AND DETECTION OF ERRONEOUS STOP CONDITION IN A SINGLE UART
A universal asynchronous receiver/transmitter includes a transmission register to include information to be transmitted, a receive register to include information received, a frame error checking circuit to evaluate contents of the receive register for a frame error, and control logic. The control logic is to route the contents of the transmission register to the receive register. The control logic is to, during transmission of the contents of the transmission register through the reprogrammable pin to the receive register, modify a bit inversion register to yield modified contents to be provided to the receive register. The modified contents are to cause a frame error. The control logic is to determine whether the frame error checking circuit detected the frame error.
G06F 11/22 - Détection ou localisation du matériel d'ordinateur défectueux en effectuant des tests pendant les opérations d'attente ou pendant les temps morts, p.ex. essais de mise en route
G06F 13/38 - Transfert d'informations, p.ex. sur un bus
H04L 1/24 - Tests pour s'assurer du fonctionnement correct
An apparatus comprising: a support structure; and a first electrically-conductive material arranged at the support structure to define a first continuous path for first electrical current to flow between a first location and a second location, the first continuous path comprising: a first path portion defining a first generally-clockwise path for the first electrical current to flow around a first axis, the first path portion including a first inner-circumferential portion and a first outer-circumferential portion, the first inner-circumferential portion located closer to a central axis than the first outer-circumferential portion, a radius of curvature of the first inner-circumferential portion being greater than a radius of curvature of the first outer-circumferential portion; and a second path portion defining a first generally-counter-clockwise path for the first electrical current to flow around a second axis, the first path portion and the second path portion circumferentially arranged around the central axis. Related devices, systems and methods are also disclosed.
G01D 5/20 - Moyens mécaniques pour le transfert de la grandeur de sortie d'un organe sensible; Moyens pour convertir la grandeur de sortie d'un organe sensible en une autre variable, lorsque la forme ou la nature de l'organe sensible n'imposent pas un moyen de conversion déterminé; Transducteurs non spécialement adaptés à une variable particulière utilisant des moyens électriques ou magnétiques influençant la valeur d'un courant ou d'une tension en faisant varier l'inductance, p.ex. une armature mobile
57.
INTEGRATED CIRCUIT STRUCTURE INCLUDING A METAL-INSULATOR-METAL (MIM) CAPACITOR MODULE AND A THIN-FILM RESISTOR (TFR) MODULE
An integrated circuit structure including a metal-insulator-metal (MIM) capacitor module and a thin-film resistor (TFR) module is provided. The MIM capacitor module includes a bottom electrode base formed in a lower metal layer, a bottom electrode formed in a dielectric region between the lower metal layer and an upper metal layer, an insulator formed over the bottom electrode, and a top electrode formed in the upper metal layer over the insulator. The bottom electrode includes a cup-shaped bottom electrode component and a bottom electrode fill component formed in an interior opening defined by the cup-shaped bottom electrode component. The TFR module includes a pair of metal heads formed in the dielectric region and a resistor element connected across the pair of metal heads. Each metal head includes a cup-shaped head component and a head fill component formed in an interior opening defined by the cup-shaped head component.
H01L 27/06 - Dispositifs consistant en une pluralité de composants semi-conducteurs ou d'autres composants à l'état solide formés dans ou sur un substrat commun comprenant des éléments de circuit passif intégrés avec au moins une barrière de potentiel ou une barrière de surface le substrat étant un corps semi-conducteur comprenant une pluralité de composants individuels dans une configuration non répétitive
H01L 27/07 - Dispositifs consistant en une pluralité de composants semi-conducteurs ou d'autres composants à l'état solide formés dans ou sur un substrat commun comprenant des éléments de circuit passif intégrés avec au moins une barrière de potentiel ou une barrière de surface le substrat étant un corps semi-conducteur comprenant une pluralité de composants individuels dans une configuration non répétitive les composants ayant une région active en commun
H01L 49/02 - Dispositifs à film mince ou à film épais
A metal-insulator-metal (MIM) capacitor module is provided. The MIM capacitor module includes a bottom electrode base formed in a lower metal layer, a bottom electrode conductively coupled to the bottom electrode base, a planar insulator formed over the bottom electrode, and a top electrode formed in an upper metal layer over the insulator. The bottom electrode includes a cup-shaped bottom electrode component and a bottom electrode fill component formed in an interior opening defined by the cup-shaped bottom electrode component.
H01L 49/02 - Dispositifs à film mince ou à film épais
H01L 23/522 - Dispositions pour conduire le courant électrique à l'intérieur du dispositif pendant son fonctionnement, d'un composant à un autre comprenant des interconnexions externes formées d'une structure multicouche de couches conductrices et isolantes inséparables du corps semi-conducteur sur lequel elles ont été déposées
59.
RECEPTION OF SIGNALS FOR RANGING, TIMING, AND DATA TRANSFER
A device is disclosed. The device may include an antenna, which antenna may receive a ranging signal encoding timing information for one or more of positioning, navigation, and timing. The ranging signal may include a first pulse of a pulse group, a second pulse of the pulse group, and an inter-pulse interval between a start of the first pulse and a start of the second pulse. The device may include a processor, which processor may identify a transmitter of the ranging signal at least partially responsive to the inter-pulse interval.
G01S 1/04 - Radiophares ou systèmes de balisage émettant des signaux ayant une ou des caractéristiques pouvant être détectées par des récepteurs non directionnels et définissant des directions, situations ou lignes de position déterminées par rapport aux émetteu; Récepteurs travaillant avec ces systèmes utilisant les ondes radioélectriques - Détails
G01S 1/24 - Systèmes pour déterminer une direction ou une ligne de position en comparant les temps de transit de signaux synchronisés provenant d'antennes non directionnelles ou de systèmes d'antennes séparés, c. à d. systèmes à différence de parcours les signaux synchronisés étant des impulsions ou des modulations équivalentes des ondes porteuses et les temps de transit étant comparés par mesure de la différence des temps d'arrivée d'une partie repérée des signaux de modulations
60.
TRANSMISSION OF SIGNALS FOR RANGING, TIMING, AND DATA TRANSFER
A method is disclosed. In various examples, the method may include receiving an instruction for generating a signal that comprises a ranging signal and a data signal, and transmitting the signal at least partially responsive to the instruction. In various examples the signal may be transmitted via a terrestrial transmitter for transmitting radio waves having encoded messaging information and timing information for one or more of positioning, navigation and timing. In various examples, the signal may include a pulse group comprising a first pulse having a first start time; and a second pulse having a second start time. The second start time may be an integer number of inter-pulse intervals plus an encoding delay after the first start time. The encoding delay may encode data.
G01S 1/24 - Systèmes pour déterminer une direction ou une ligne de position en comparant les temps de transit de signaux synchronisés provenant d'antennes non directionnelles ou de systèmes d'antennes séparés, c. à d. systèmes à différence de parcours les signaux synchronisés étant des impulsions ou des modulations équivalentes des ondes porteuses et les temps de transit étant comparés par mesure de la différence des temps d'arrivée d'une partie repérée des signaux de modulations
G01S 1/04 - Radiophares ou systèmes de balisage émettant des signaux ayant une ou des caractéristiques pouvant être détectées par des récepteurs non directionnels et définissant des directions, situations ou lignes de position déterminées par rapport aux émetteu; Récepteurs travaillant avec ces systèmes utilisant les ondes radioélectriques - Détails
61.
RECEPTION OF SIGNALS FOR RANGING, TIMING, AND DATA TRANSFER
A device is disclosed. In one or more examples, the device may include an antenna to receive a signal comprising a ranging signal and a data signal. The signal may encode timing information for one or more of positioning, navigation, and timing. The signal may include a first pulse having a first start time and a second pulse having a second start time. The second start time may be an integer number of inter-pulse intervals plus an encoding delay after the first start time. The encoding delay may encode data. The device may include a processor to obtain the data responsive to the encoding delay.
G01S 1/04 - Radiophares ou systèmes de balisage émettant des signaux ayant une ou des caractéristiques pouvant être détectées par des récepteurs non directionnels et définissant des directions, situations ou lignes de position déterminées par rapport aux émetteu; Récepteurs travaillant avec ces systèmes utilisant les ondes radioélectriques - Détails
G01S 1/24 - Systèmes pour déterminer une direction ou une ligne de position en comparant les temps de transit de signaux synchronisés provenant d'antennes non directionnelles ou de systèmes d'antennes séparés, c. à d. systèmes à différence de parcours les signaux synchronisés étant des impulsions ou des modulations équivalentes des ondes porteuses et les temps de transit étant comparés par mesure de la différence des temps d'arrivée d'une partie repérée des signaux de modulations
62.
TRANSMISSION OF SIGNALS FOR RANGING, TIMING, AND DATA TRANSFER
A method is disclosed. In various examples, the method may include receiving an instruction for generating a signal comprising a ranging signal and a data signal. The method may also include transmitting, via a terrestrial transmitter for transmitting radio waves having encoded messaging information and timing information for one or more of positioning, navigation and timing, the signal at least partially responsive to the instruction. The signal may include a pulse group comprising a number of ranging pulses and a number of data pulses subsequent to the number of ranging pulses. Respective ones of the number of data pulses may have a phase of either a positive-going phase or a negative-going phase. Information may be encoded using the either positive-going phases or negative-going phases of the data pulses.
G01S 1/04 - Radiophares ou systèmes de balisage émettant des signaux ayant une ou des caractéristiques pouvant être détectées par des récepteurs non directionnels et définissant des directions, situations ou lignes de position déterminées par rapport aux émetteu; Récepteurs travaillant avec ces systèmes utilisant les ondes radioélectriques - Détails
G01S 1/24 - Systèmes pour déterminer une direction ou une ligne de position en comparant les temps de transit de signaux synchronisés provenant d'antennes non directionnelles ou de systèmes d'antennes séparés, c. à d. systèmes à différence de parcours les signaux synchronisés étant des impulsions ou des modulations équivalentes des ondes porteuses et les temps de transit étant comparés par mesure de la différence des temps d'arrivée d'une partie repérée des signaux de modulations
63.
RECEPTION OF SIGNALS FOR RANGING, TIMING, AND DATA TRANSFER
A device is disclosed. In one or more examples, the device may include an antenna to receive a signal encoding timing information for one or more of positioning, navigation, and timing. The signal may include a pulse group comprising a number of ranging pulses and a number of data pulses subsequent to the number of ranging pulses. Respective ones of the number of data pulses may have a phase of either a positive-going phase or a negative-going phase. Data may be encoded using the either positive-going phases or negative-going phases of the data pulses. The device may include a processor to decode the data at least partially responsive to the phases of the respective ones of the number of data pulses.
G01S 1/04 - Radiophares ou systèmes de balisage émettant des signaux ayant une ou des caractéristiques pouvant être détectées par des récepteurs non directionnels et définissant des directions, situations ou lignes de position déterminées par rapport aux émetteu; Récepteurs travaillant avec ces systèmes utilisant les ondes radioélectriques - Détails
G01S 1/24 - Systèmes pour déterminer une direction ou une ligne de position en comparant les temps de transit de signaux synchronisés provenant d'antennes non directionnelles ou de systèmes d'antennes séparés, c. à d. systèmes à différence de parcours les signaux synchronisés étant des impulsions ou des modulations équivalentes des ondes porteuses et les temps de transit étant comparés par mesure de la différence des temps d'arrivée d'une partie repérée des signaux de modulations
A method of forming a via is provided. A lower metal element is formed, and a first patterned photoresist is used to form a sacrificial element over the lower metal element. A dielectric region including a dielectric element projection extending upwardly above the sacrificial element is formed. A second patterned photoresist including a second photoresist opening is formed, wherein the dielectric element projection is at least partially located in the second photoresist opening. A dielectric region trench opening is etched in the dielectric region. The sacrificial element is removed to define a via opening extending downwardly from the dielectric region trench opening. The dielectric region trench opening and the via opening are filled to define (a) an upper metal element in the dielectric region trench opening and (b) a via in the via opening, wherein the via extends downwardly from the upper metal element.
An electronic device includes an integrated circuit package including a die mounted on a die carrier, a mold structure at least partially encapsulating the mounted die, and a heat transfer chimney formed on the die. The heat transfer chimney extends at least partially through the mold structure to transfer heat away from the die. The heat transfer chimney is formed from a thermally conductive compound including thermally conductive nanoparticles.
H01L 23/367 - Refroidissement facilité par la forme du dispositif
H01L 23/373 - Refroidissement facilité par l'emploi de matériaux particuliers pour le dispositif
H01L 23/433 - Pièces auxiliaires caractérisées par leur forme, p.ex. pistons
H01L 23/29 - Capsulations, p.ex. couches de capsulation, revêtements caractérisées par le matériau
H01L 23/31 - Capsulations, p.ex. couches de capsulation, revêtements caractérisées par leur disposition
H01L 23/552 - Protection contre les radiations, p.ex. la lumière
H01L 23/556 - Protection contre les radiations, p.ex. la lumière contre les rayons alpha
H01L 23/00 - DISPOSITIFS À SEMI-CONDUCTEURS NON COUVERTS PAR LA CLASSE - Détails de dispositifs à semi-conducteurs ou d'autres dispositifs à l'état solide
H01L 25/065 - Ensembles consistant en une pluralité de dispositifs à semi-conducteurs ou d'autres dispositifs à l'état solide les dispositifs étant tous d'un type prévu dans le même sous-groupe des groupes , ou dans une seule sous-classe de , , p.ex. ensembles de diodes redresseuses les dispositifs n'ayant pas de conteneurs séparés les dispositifs étant d'un type prévu dans le groupe
66.
INDUCTIVE ANGULAR-POSITION SENSORS, AND RELATED DEVICES, SYSTEMS, AND METHODS
Examples disclosed herein relate generally to inductive angular-position sensors. An example apparatus may include a support structure, a first inductive angular-position sensor, a second inductive angular-position sensor, and a shield. The first inductive angular-position sensor may include a respective first sense coil arranged at a first portion of the support structure. The respective first sense coil may at least partially circumscribe an axis. The second inductive angular-position sensor may include a respective first sense coil arranged opposite the first sense coil of the first inductive angular-position sensor at a second portion of the support structure. The first sense coil of the first inductive angular-position sensor may at least partially circumscribe the axis. The shield may be arranged between the first sense coil of the first inductive angular-position sensor and the first sense coil of the second inductive angular-position sensor.
G01D 5/20 - Moyens mécaniques pour le transfert de la grandeur de sortie d'un organe sensible; Moyens pour convertir la grandeur de sortie d'un organe sensible en une autre variable, lorsque la forme ou la nature de l'organe sensible n'imposent pas un moyen de conversion déterminé; Transducteurs non spécialement adaptés à une variable particulière utilisant des moyens électriques ou magnétiques influençant la valeur d'un courant ou d'une tension en faisant varier l'inductance, p.ex. une armature mobile
67.
DETERMINING ALLOCATION OF LANES OF A PERIPHERAL-COMPONENT‑INTERCONNECT-EXPRESS PORT TO LINKS
Examples disclosed herein include a method including transmitting, via respective lanes of a number of lanes of a peripheral component interconnect express (PCIe) port, a respective lane identifier. The method may also include receiving, via the respective lanes of the number of lanes of the PCIe port, respective further lane identifiers. The method may also include determining which of the number of lanes to allocate to a link for communicating with a device coupled to the PCIe port at least partially responsive to the respective further lane identifiers. The method may also include allocating the determined lanes of the number of lanes to the link. Related devices and systems are also disclosed
An operational amplifier includes a pre-amplifier circuit, a first trim circuit, and a second trim circuit. The pre-amplifier circuit is to include a differential pair and receive an input voltage. The first trim circuit is to produce an offset voltage correction current and provide the offset voltage correction current to the pre-amplifier circuit to correct an offset of the operational amplifier. The second trim circuit is to produce a common mode voltage (VCM) correction current, provide the VCM voltage correction current to the pre-amplifier circuit, and cause the VCM correction current to have a non-zero value to reduce a correction caused by the offset voltage correction current when the input voltage is within a mid voltage input range. The pre-amplifier circuit is to apply the offset correction current and the VCM correction current to output signals of the differential pair.
A feedback mechanism about a state of a transmission of a packet over a wireless medium is disclosed. In one or more examples, a wireless stack determines a state of a transmission of wireless packets that correspond to the network packet and infers a state of transmission of the network packet based on such a determination. The wireless stack informs a network stack about the state of transmission of the network packet.
H04L 1/16 - Dispositions pour détecter ou empêcher les erreurs dans l'information reçue en utilisant un canal de retour dans lesquelles le canal de retour transporte des signaux de contrôle, p.ex. répétition de signaux de demande
H04L 1/18 - Systèmes de répétition automatique, p.ex. systèmes Van Duuren
Various examples relate to adjustable light sources. An example may include an apparatus including a light source to adjustably emit light toward a region of interest at least partially responsive to a control signal. The apparatus may also include a sensor to generate a signal indicative of an intensity of light sensed by the sensor in the region of interest. The apparatus may also include a wireless-communication equipment to broadcast a value that represents the intensity of light received by the sensor. The wireless-communication equipment may also receive a broadcast of a further value that represents an intensity of light in a further region of interest. The apparatus may also include a processor to adjust the control signal at least partially responsive to the further value. Related devices, systems and methods are also disclosed.
H05B 47/20 - Circuits pour faire fonctionner des sources lumineuses en général, c. à d. où le type de source lumineuse n'est pas important pour la protection
H05B 47/155 - Commande coordonnée de plusieurs sources lumineuses
H05B 47/11 - Commande de la source lumineuse en réponse à des paramètres détectés en détectant la luminosité ou la température de couleur de la lumière ambiante
H05B 47/19 - Commande de la source lumineuse par télécommande via une transmission sans fil
71.
OBJECT DETECTION IN WIRELESS CHARGING SYSTEMS AND RELATED SYSTEMS, METHODS, AND DEVICES
Foreign object detection for wireless power transmission and related systems, methods, and devices are disclosed. A controller for a wireless power transmitter is to determine a transmit coil voltage potential at a transmit coil of the wireless power transmitter, determine an input power provided to the wireless power transmitter, determine a transmitter power loss, and determine a transmitted power of the wireless power transmitted to the wireless power receiver based, at least in part, on the input power and the transmitter power loss. The controller is also to compute a power loss responsive to the transmitted power and a received power indicated by the wireless power receiver, and determine that a foreign object is detected responsive to a determination that the power loss is greater than a predetermined threshold
H02J 50/40 - Circuits ou systèmes pour l'alimentation ou la distribution sans fil d'énergie électrique utilisant plusieurs dispositifs de transmission ou de réception
H02J 50/60 - Circuits ou systèmes pour l'alimentation ou la distribution sans fil d'énergie électrique sensibles à la présence d’objets étrangers, p.ex. détection d'êtres vivants
Various examples may include an apparatus including a memory to store ingressing data or egressing data, a timer to generate a timing signal responsive to a user-configurable time interval, and a circuit to move the ingressing data or the egressing data from the memory at least partially responsive to the timing signal generated by the timer. Various examples may include a method including receiving a data packet at a network-facing interface, writing data of the data packet into a memory, receiving a timing signal, and responsive to the timing signal, providing the data from the memory at a device-facing interface. Various examples may include a method including receiving data at a device-facing interface, writing the data to a memory, receiving a timing signal, and responsive to the timing signal, providing a data packet including the data at a network-facing interface. Related devices, systems and methods are also disclosed.
H04L 49/35 - Interrupteurs spécialement adaptés à des applications spécifiques
H04L 49/60 - Commutateurs définis sous forme de logiciel
H04L 67/12 - Protocoles spécialement adaptés aux environnements propriétaires ou de mise en réseau pour un usage spécial, p.ex. les réseaux médicaux, les réseaux de capteurs, les réseaux dans les véhicules ou les réseaux de mesure à distance
73.
CONTROL OF A REGENERATIVE BRAKE FOR A MOTOR SYSTEM AND RELATED SYSTEMS, METHODS, AND DEVICES
A controller for a motor system includes an input terminal to receive a signal indicating a speed of an electric motor and a regenerative brake current interpolator to indicate a brake current to be applied to the electric motor responsive to the speed of the electric motor. Values of the brake current vary with variation of the speed of the electric motor.
B60L 7/06 - Freinage dynamo-électrique par résistance pour véhicules propulsés par moteurs à courant alternatif
B60L 7/14 - Freinage dynamo-électrique par récupération pour véhicules propulsés par moteurs à courant alternatif
B60L 15/02 - Procédés, circuits ou dispositifs pour commander la propulsion des véhicules à traction électrique, p.ex. commande de la vitesse des moteurs de traction en vue de réaliser des performances désirées; Adaptation sur les véhicules à traction électrique de l'installation de commande à distance à partir d'un endroit fixe, de différents endroits du véhicule ou de différents véhicules d'un même train caractérisés par la forme du courant utilisé dans le circuit de commande
B60L 15/06 - Procédés, circuits ou dispositifs pour commander la propulsion des véhicules à traction électrique, p.ex. commande de la vitesse des moteurs de traction en vue de réaliser des performances désirées; Adaptation sur les véhicules à traction électrique de l'installation de commande à distance à partir d'un endroit fixe, de différents endroits du véhicule ou de différents véhicules d'un même train caractérisés par la forme du courant utilisé dans le circuit de commande utilisant un courant alternatif sensiblement sinusoïdal
B60L 15/20 - Procédés, circuits ou dispositifs pour commander la propulsion des véhicules à traction électrique, p.ex. commande de la vitesse des moteurs de traction en vue de réaliser des performances désirées; Adaptation sur les véhicules à traction électrique de l'installation de commande à distance à partir d'un endroit fixe, de différents endroits du véhicule ou de différents véhicules d'un même train pour la commande du véhicule ou de son moteur en vue de réaliser des performances désirées, p.ex. vitesse, couple, variation programmée de la vitesse
B60L 7/18 - Freinage dynamo-électrique par récupération commandant l'effet de freinage
74.
TECHNIQUES FOR CONTROLLING VAPOR PRESSURE OF SUBJECT MATERIALS IN VAPOR CELLS AND RELATED METHODS
Methods of using vapor cells may involve providing a vapor cell including a body defining a cavity within the body. At least a portion of at least one surface of the vapor cell within the cavity may include at least one pore having an average dimension of about 500 microns or less, as measured in a direction parallel to the at least one surface. A vapor pressure of a subject material within the cavity may be controlled utilizing the at least one pore by inducing an exposed surface of a subject material in a liquid state within the at least one pore to have a shape different than a shape the exposed surface of the subject material in a liquid state would have on a flat, nonporous surface.
G04F 5/14 - Appareils pour la production d'intervalles de temps prédéterminés, utilisés comme étalons utilisant des horloges atomiques
H03L 7/26 - Commande automatique de fréquence ou de phase; Synchronisation utilisant comme référence de fréquence les niveaux d'énergie de molécules, d'atomes ou de particules subatomiques
A damascene method for manufacturing a thin film resistor (TFR) module is provided. A pair of heads are formed spaced apart from each other. A dielectric region is deposited over the pair of heads, and an opening extending over both heads is formed in the dielectric region. A TFR layer is deposited over the dielectric region and extending into the opening to define a cup-shaped TFR layer structure including (a) a laterally-extending TFR element base conductively connected to both heads and (b) vertical ridges extending upwardly from the laterally-extending TFR element base. A high density plasma (HDP) ridge removal process is performed to remove or shorten the vertical ridges from the cup-shaped TFR layer structure, thereby defining a TFR element having removed or shorted vertical ridges. The removal or shortening of the vertical ridges may improve the temperature coefficient of resistance (TCR) characteristic of the TFR element.
A system for managing a virtual meeting (e.g., video conference) includes memory storing a video conference application and at least one processor to execute the video conference application to generate a virtual meeting view for a first attendee including multiple attendee video streams arranged according to a virtual attendee arrangement specifying positions of the attendee video streams relative to each other in the virtual meeting view, receive second attendee audio data associated with a second attendee video stream, identify a particular video stream position specified by the virtual attendee arrangement, determine differential stereo effect data corresponding with the particular video stream position, and apply the differential stereo effect data to the second attendee audio data to provide differential audio signals on different audio channels output to the first attendee to create a stereo sound effect corresponding with the particular video stream position.
An integrated circuit device includes an anti-fuse device. The anti-fuse device includes a cup-shaped bottom anti-fuse electrode, a cup-shaped anti-fuse insulator formed in an opening defined by the cup-shaped bottom anti-fuse electrode, and a top anti-fuse electrode formed in an opening defined by the cup-shaped anti-fuse insulator. A thickness of the cup-shaped anti-fuse insulator is less than 200Å.
G11C 17/16 - Mémoires mortes programmables une seule fois; Mémoires semi-permanentes, p.ex. cartes d'information pouvant être replacées à la main dans lesquelles le contenu est déterminé en établissant, en rompant ou en modifiant sélectivement les liaisons de connexion par une modification définitive de l'état des éléments de couplage, p.ex. mémoires PROM utilisant des liaisons électriquement fusibles
G11C 17/18 - Circuits auxiliaires, p.ex. pour l'écriture dans la mémoire
H01L 23/525 - Dispositions pour conduire le courant électrique à l'intérieur du dispositif pendant son fonctionnement, d'un composant à un autre comprenant des interconnexions externes formées d'une structure multicouche de couches conductrices et isolantes inséparables du corps semi-conducteur sur lequel elles ont été déposées avec des interconnexions modifiables
G11C 17/04 - Mémoires mortes programmables une seule fois; Mémoires semi-permanentes, p.ex. cartes d'information pouvant être replacées à la main utilisant des éléments capacitifs
A CAN bus transmitter has an input to receive a transmit data signal, and CANH and CANL outputs coupled to a CAN bus. The CAN bus transmitter comprises a plurality of CAN driver circuits having inputs coupled through delay circuits with their CANH and CANL outputs in common and connected to the CAN bus. Matching of Cgs capacitances between devices of the CANH and CANL legs provides substantially synchronized changes in the CANH and CANL output logic levels upon a change in the input logic level. Variable delaying of the input logic level changes to each of the plurality of CAN driver circuits reduces emission of unwanted signals from the CAN bus.
H04L 12/413 - Réseaux à ligne bus avec commande décentralisée avec accès aléatoire, p.ex. accès multiple avec détection de porteuse et détection de collision (CSMA-CD)
H04B 1/48 - Commutation transmission-réception dans des circuits pour connecter l'émetteur et le récepteur à une voie de transmission commune, p.ex. par l'énergie de l'émetteur
H04L 7/00 - Dispositions pour synchroniser le récepteur avec l'émetteur
A UART includes a transmission register, a receive register, a virtual remappable pin, a parity error check circuit to evaluate contents of the receive register for a parity error, and control logic to determine contents of the transmission register. The contents include underlying data and a parity bit based thereupon. The control logic is to route the contents through the first virtual remappable pin to the receive register. The control logic is to, before reception of the entire contents at the receive register, cause modified contents to be provided to the receive register. The modified contents are to cause a parity error. The modified contents are to include different underlying data or a different parity bit than the contents of the transmission register. The control logic is to determine whether the parity error check circuit detected the parity error.
H04L 1/00 - Dispositions pour détecter ou empêcher les erreurs dans l'information reçue
H03M 13/37 - Méthodes ou techniques de décodage non spécifiques à un type particulier de codage prévu dans les groupes
H03M 13/00 - Codage, décodage ou conversion de code pour détecter ou corriger des erreurs; Hypothèses de base sur la théorie du codage; Limites de codage; Méthodes d'évaluation de la probabilité d'erreur; Modèles de canaux; Simulation ou test des codes
80.
SYSTEM AND METHOD FOR PERFORMING RATE ADAPTATION AND MULTIPLEXING OF CONSTANT BIT RATE (CBR) CLIENT DATA FOR TRANSMISSION OVER A METRO TRANSPORT NETWORK (MTN)
A system and method for performing rate adaptation and multiplexing of constant bit rate (CBR) client data for transmission over a Metro Transport Network (MTN) by defining a plurality of plurality of generic mapping procedure (GMP) thread frames for a respective stream of two or more streams of 64B/66B-encoded blocks of CR client data, defining a plurality of pseudo-Ethernet packets, mapping the plurality of GMP thread frames into consecutive pseudo-Ethernet packets, assembling a stream of GMP multiplexing frames comprising the consecutive pseudo-Ethernet packets, inserting a fixed number of idle blocks between the consecutive pseudo-Ethernet packets of the stream of GMP multiplexing frames and inserting an MTN path overhead (POH) frame into the stream of GMP multiplexing frames to generate a stream of GMP multiplexing rate adapted frames.
H04J 3/07 - Dispositions de synchronisation utilisant le bourrage d'impulsions pour les systèmes à débits d'informations différents ou variables
H04J 3/16 - Systèmes multiplex à division de temps dans lesquels le temps attribué à chacun des canaux au cours d'un cycle de transmission est variable, p.ex. pour tenir compte de la complexité variable des signaux, pour adapter le nombre de canaux transmis
81.
SYSTEM AND METHOD FOR PERFORMING RATE ADAPTATION OF CONSTANT BIT RATE (CBR) CLIENT DATA WITH A FIXED NUMBER OF IDLE BLOCKS FOR TRANSMISSION OVER A METRO TRANSPORT NETWORK (MTN)
A system and method for performing rate adaptation of constant bit rate (CBR) client data for transmission over a Metro Transport Network (MTN) by defining a plurality of pseudo-Ethernet packets at a source node, assembling a plurality of Generic Mapping Procedure (GMP) frames by mapping a plurality of blocks from a stream of encoded blocks of CBR client data, a plurality of pad blocks, and GMP overhead into consecutive pseudo-Ethernet packets of the plurality of pseudo- Ethernet packets, inserting a fixed number of idle blocks between one or more of the consecutive pseudo-Ethernet packets and inserting an MTN path overhead (POH) frame that is aligned to the plurality of GMP frames to generate a plurality of rate adapted GMP frames for transmission over the MTN to an intermediate node or a sink node.
H04J 3/07 - Dispositions de synchronisation utilisant le bourrage d'impulsions pour les systèmes à débits d'informations différents ou variables
H04J 3/16 - Systèmes multiplex à division de temps dans lesquels le temps attribué à chacun des canaux au cours d'un cycle de transmission est variable, p.ex. pour tenir compte de la complexité variable des signaux, pour adapter le nombre de canaux transmis
82.
SYSTEM AND METHOD FOR PERFORMING RATE ADAPTATION OF CONSTANT BIT RATE (CBR) CLIENT DATA WITH A VARIABLE NUMBER OF IDLE BLOCKS FOR TRANSMISSION OVER A METRO TRANSPORT NETWORK (MTN)
A system and method for performing rate adaptation of constant bit rate (CBR) client data for transmission over a Metro Transport Network (MTN) by defining a plurality of pseudo-Ethernet packets at a source node, assembling a plurality of Generic Mapping Procedure (GMP) frames by mapping a plurality of blocks from a stream of encoded blocks of CBR client data, a plurality of pad blocks, and GMP overhead into consecutive pseudo-Ethernet packets of the plurality of pseudo-Ethernet packets, inserting a variable number of idle blocks between one or more of the consecutive pseudo-Ethernet packets and inserting an MTN path overhead (POH) frame that is aligned to the plurality of GMP frames to generate a plurality of rate adapted GMP frames for transmission over the MTN to an intermediate node or a sink node.
H04J 3/07 - Dispositions de synchronisation utilisant le bourrage d'impulsions pour les systèmes à débits d'informations différents ou variables
H04J 3/16 - Systèmes multiplex à division de temps dans lesquels le temps attribué à chacun des canaux au cours d'un cycle de transmission est variable, p.ex. pour tenir compte de la complexité variable des signaux, pour adapter le nombre de canaux transmis
83.
TEMPERATURE SENSOR INTEGRATED IN A TRANSISTOR ARRAY
A temperature sensor integrated in a transistor array, e.g., metal–oxide–semiconductor field-effect transistor (MOSFET) array, is provided. The integrated temperature sensor may include a doped well region formed in a substrate (e.g., SiC substrate), a resistor gate formed over the doped well region, first and second sensor terminals conductively coupled to the doped well region on opposite sides of the resistor gate. The integrated temperature sensor includes a gate driver to apply a voltage to the resistor gate that affects a resistance of the doped well region below the resistor gate, and temperature analysis circuitry to determine a resistance of a conductive path passing through the doped well region, and determine a temperature associated with the transistor array.
G01K 7/16 - Mesure de la température basée sur l'utilisation d'éléments électriques ou magnétiques directement sensibles à la chaleur utilisant des éléments résistifs
H01L 29/78 - Transistors à effet de champ l'effet de champ étant produit par une porte isolée
H01L 27/02 - Dispositifs consistant en une pluralité de composants semi-conducteurs ou d'autres composants à l'état solide formés dans ou sur un substrat commun comprenant des éléments de circuit passif intégrés avec au moins une barrière de potentiel ou une barrière de surface
A method and apparatus for measuring an unknown impedance. The apparatus comprises a first input to receive a first signal generated by a first portion of a sensor circuit, the first portion comprising an unknown impedance and a first known resistance, the unknown impedance to vary based upon a phenomenon to be measured by the sensor circuit. The apparatus also comprises a second input to receive a second signal generated by a second portion of the sensor circuit, the second portion of the sensor circuit comprising a known impedance and a second known resistance. And the apparatus comprises control logic to, based on a difference in time at which each of the first input and the second input reach a reference voltage, determine a measurement of the sensor circuit.
G01D 5/00 - Moyens mécaniques pour le transfert de la grandeur de sortie d'un organe sensible; Moyens pour convertir la grandeur de sortie d'un organe sensible en une autre variable, lorsque la forme ou la nature de l'organe sensible n'imposent pas un moyen de conversion déterminé; Transducteurs non spécialement adaptés à une variable particulière
Resistive random access memory (RRAM) cells, for example conductive bridging random access memory (CBRAM) cells and oxygen vacancy-based RRAM (OxRRAM) cells are provided. An RRAM cell may include a metal-insulator-metal (MIM) structure formed between adjacent metal interconnect layers or between a silicided active layer (e.g., including MOSFET devices) and a first metal interconnect layer. The MIM structure of the RRAM cell may be formed by a damascene process including forming a tub opening in a dielectric region, forming a cup-shaped bottom electrode in the tub opening, forming a cup-shaped insulator in an interior opening defined by the cup-shaped bottom electrode, and forming a top electrode in an interior opening defined by the cup-shaped insulator. The cup-shaped bottom electrode, or a component thereof (in the case of a multi-layer bottom electrode) may be formed concurrently with interconnect vias, e.g., by deposition of tungsten or other conformal metal.
H01L 45/00 - Dispositifs à l'état solide spécialement adaptés pour le redressement, l'amplification, la production d'oscillations ou la commutation, sans barrière de potentiel ni barrière de surface, p.ex. triodes diélectriques; Dispositifs à effet Ovshinsky; Procédés ou appareils spécialement adaptés à la fabrication ou au traitement de ces dispositifs ou de leurs parties constitutives
86.
CARBON NANOTUBE (CNT) MEMORY CELL ELEMENT AND METHODS OF CONSTRUCTION
Carbon nanotube (CNT) memory cell elements and methods of forming CNT memory cell elements are provided. A CNT memory cell may comprise a CNT memory cell element, e.g., in combination with a transistor. A CNT memory cell element (202) includes a metal/CNT layer/metal (M/CNT/M) structure (220, 222, 224) formed between adjacent metal interconnect layers (Mx, Mx+i) or between a silicided active layer (e.g., including MOSFET devices) and a metal interconnect layer. The M/CNT/M structure is formed by a process including forming a tub opening (213) in a dielectric region (208), forming a cup-shaped bottom electrode (220) in the tub opening, forming a cup-shaped CNT layer (222) in an interior opening defined by the cup-shaped bottom electrode, and forming a top electrode (224) in an interior opening defined by the cup-shaped CNT layer.
H01L 45/00 - Dispositifs à l'état solide spécialement adaptés pour le redressement, l'amplification, la production d'oscillations ou la commutation, sans barrière de potentiel ni barrière de surface, p.ex. triodes diélectriques; Dispositifs à effet Ovshinsky; Procédés ou appareils spécialement adaptés à la fabrication ou au traitement de ces dispositifs ou de leurs parties constitutives
87.
FERROELECTRIC RANDOM ACCESS MEMORY (FRAM) CAPACITORS AND METHODS OF CONSTRUCTION
Ferroelectric random access memory (FRAM) capacitors and methods of forming FRAM capacitors are provided. An FRAM capacitor may be formed between adjacent metal interconnect layers or between a silicided active layer (e.g., including MOSFET devices) and a first metal interconnect layer. The FRAM capacitor may be formed by a damascene process including forming a tub opening in a dielectric region, forming a cup-shaped bottom electrode, forming a cup-shaped ferroelectric element in an interior opening defined by the cup-shaped bottom electrode, and forming a top electrode in an interior opening defined by the cup-shaped ferroelectric element. The FRAM capacitor may form a component of an FRAM memory cell. For example, an FRAM memory cell may include one FRAM capacitor and one transistor (1T1C configuration) or two FRAM capacitors and two transistor (2T2C configuration).
H01L 27/11507 - Mémoires mortes programmables électriquement; Procédés de fabrication à étapes multiples de ces dispositifs avec condensateurs ferro-électriques de mémoire caractérisées par la région noyau de mémoire
H01L 49/02 - Dispositifs à film mince ou à film épais
88.
A LINK MONITOR FOR A SWITCH HAVING A PCIE-COMPLIANT INTERFACE, AND RELATED SYSTEMS, DEVICES, AND METHODS
Some embodiments relate to a link monitor for a switch having a PCIe-compliant interface. Some embodiments relate to an apparatus including a Peripheral Component Interconnect Express (PCIe)-compliant interface provided at a PCIe domain of a switch. The apparatus may also include a link monitor provided at a switching fabric of the switch that supports the PCIe domain of the switch. The link monitor to observe a factor-changing event of a state of a fabric link and obtain a value at least partially responsive to a weight computation, the weight computation for a factor associated with the factor-changing event. Related devices, systems and methods are also disclosed.
An apparatus for inductive linear-position sensing is disclosed. An apparatus may include a support structure and an electrically conductive material defining a continuous path for electrical current to flow between a first location and a second location. The continuous path may include: a first path portion defining a first spiraling path for the electrical current to flow in a clockwise direction around a first axis; a second path portion laterally spaced from the first path portion and defining a second spiraling path for the electrical current to flow in a counter-clockwise direction around a second axis; a first coupling portion coupling an inner portion of the first path portion to an inner portion of the second path portion; and a second coupling portion coupling an outer portion of the second path portion to an outer portion of the first path portion. Related systems, devices, and methods are also disclosed.
G01D 5/20 - Moyens mécaniques pour le transfert de la grandeur de sortie d'un organe sensible; Moyens pour convertir la grandeur de sortie d'un organe sensible en une autre variable, lorsque la forme ou la nature de l'organe sensible n'imposent pas un moyen de conversion déterminé; Transducteurs non spécialement adaptés à une variable particulière utilisant des moyens électriques ou magnétiques influençant la valeur d'un courant ou d'une tension en faisant varier l'inductance, p.ex. une armature mobile
90.
PROVISIONING HEADLESS WIFI DEVICES AND RELATED SYSTEMS, METHODS AND DEVICES
One or more examples of systems, methods and devices are disclosed for provisioning a headless WiFi device. A method may include: inferring a channel identifier of a desired WiFi router access point, establishing a communication link with a provisioning WiFi device utilizing the channel identifier, and establishing a communication link with the WiFi router access point utilizing a channel identifier provided by the provisioning WiFi device.
System and method for analyzing CXL flits at read bypass detection logic (115) to identify bypass memory read requests (108) and transmitting the identified bypass memory read requests (108) over a read request bypass path (120) directly to a transaction/ application layer (135) of the CXL memory controller (100), wherein the read request bypass path (120) does not include an arbitration/ multiplexing layer (125) and a link layer (130) of the CXL memory controller (100), thereby reducing the latency inherent in a CXL memory controller (100).
A method for memory protection includes receiving a burst-write instruction that includes data and a burst-write address. The data are segmented into a plurality of data blocks. One or more bits of the burst-write address, or a hash of the burst-write address are concatenated to respective data blocks to obtain data-and-write-address-bit (DWAB) segments. A SECDED ECC is executed on respective DWAB segments to generate a corresponding plurality of sets of parity bits (DWAB-PB). Respective DWAB-PB are concatenated to the corresponding data block to generate corresponding forward-error-correction (FEC) blocks, none of the FEC blocks including the burst-write address or the hash of the burst-write address. A burst-write command and a respective portion of a respective FEC block is sent to respective memory devices during a plurality of beats until all of the beats of the burst-write have been sent.
G06F 11/10 - Détection ou correction d'erreur par introduction de redondance dans la représentation des données, p.ex. en utilisant des codes de contrôle en ajoutant des chiffres binaires ou des symboles particuliers aux données exprimées suivant un code, p.ex. contrôle de parité, exclusion des 9 ou des 11
93.
METHOD AND APPARATUS FOR PERFORMING A READ OF A FLASH MEMORY USING PREDICTED RETENTION-AND-READ-DISTURB-COMPENSATED THRESHOLD VOLTAGE SHIFT OFFSET VALUES
A method for performing a read of a flash memory includes storing configuration files for a plurality of RRD-compensating RNNs. A current number of PE cycles for a flash memory are identified and TVSO values are identified corresponding to the current number of PE cycles. A current retention time and a current number of read disturbs for the flash memory are identified. The configuration file of the RRD-compensating RNN corresponding to the current number of PE cycles, the current retention time and current number of read disturbs is selected and is loaded into a neural network engine to form an RNN core in the neural network engine. A neural network operation of the RNN core is performed to predict RRD-compensated TVSO values. The input to the neural network operation includes the identified TVSO values. A read of the flash memory is performed using the predicted RRD-compensated TVSO values.
G11C 11/56 - Mémoires numériques caractérisées par l'utilisation d'éléments d'emmagasinage électriques ou magnétiques particuliers; Eléments d'emmagasinage correspondants utilisant des éléments d'emmagasinage comportant plus de deux états stables représentés par des échelons, p.ex. de tension, de courant, de phase, de fréquence
G11C 16/26 - Circuits de détection ou de lecture; Circuits de sortie de données
G11C 16/34 - Détermination de l'état de programmation, p.ex. de la tension de seuil, de la surprogrammation ou de la sousprogrammation, de la rétention
G11C 29/02 - Détection ou localisation de circuits auxiliaires défectueux, p.ex. compteurs de rafraîchissement défectueux
A method for outlier management at a flash controller includes testing a flash memory device to identify one or more outlier blocks of the flash memory device. Hyperparameters for a DNN are loaded into a training circuit. Test reads of the one or more outlier blocks are performed and a number of errors in the test reads is identified. The DNN is trained using a mini-batch training process and using the identified number of errors in the test reads and is tested to determine whether the trained DNN meets a training error threshold. The performing, the identifying, the training and the testing are repeated until the trained DNN meets the training error threshold to identify parameters of an outlier-block DNN. A neural network operation is performed using the identified parameters to predict a set of TVSO values. A read is performed using the set of predicted TVSO values.
G11C 29/44 - Indication ou identification d'erreurs, p.ex. pour la réparation
G11C 29/02 - Détection ou localisation de circuits auxiliaires défectueux, p.ex. compteurs de rafraîchissement défectueux
G11C 29/50 - Test marginal, p.ex. test de vitesse, de tension ou de courant
G11C 16/34 - Détermination de l'état de programmation, p.ex. de la tension de seuil, de la surprogrammation ou de la sousprogrammation, de la rétention
Object detection in wireless power systems and related system, methods, and devices are disclosed. A controller for a wireless power transmitter includes a measurement voltage potential input terminal and a processing core. The processing core is to determine an average of peak to peak amplitude differences present in sampled measurement voltage potentials for each of the plurality of transmit coils, determine a lowest average of the peak to peak amplitude differences, and select a transmit coil corresponding to the lowest average of the peak to peak amplitude differences to transmit wireless power to a receive coil of a wireless power receiver. A wireless power system includes a tank circuit selectively including any one of a plurality of transmit coils.
H02J 50/12 - Circuits ou systèmes pour l'alimentation ou la distribution sans fil d'énergie électrique utilisant un couplage inductif du type couplage à résonance
H02J 50/40 - Circuits ou systèmes pour l'alimentation ou la distribution sans fil d'énergie électrique utilisant plusieurs dispositifs de transmission ou de réception
96.
AMPLIFYING A DIFFERENTIAL VOLTAGE SIGNAL COMPONENT OF A VOLTAGE ACROSS A RESISTOR
One or more examples relate to an apparatus to amplify differential voltage signal components of voltage across a resistor. Such an apparatus may include a resistor; a differential amplification circuit operatively coupled with the resistor to amplify a differential voltage signal component of a voltage across the resistor; and an operative coupling between the resistor and the differential amplification circuit to pass the differential voltage signal component and isolate a common mode voltage signal component of the voltage across the resistor.
A method for meeting quality of service (QoS) requirements in a flash controller that includes one or more instruction queues and a neural network engine. A configuration file for a QoS neural network is loaded into the neural network engine. A current command is received at the instruction queue(s). Feature values corresponding to commands in the instruction queue(s) are identified and are loaded into the neural network engine. A neural network operation of the QoS neural network is performed using as input the identified feature values to predict latency of the current command. The predicted latency is compared to a first latency threshold. When the predicted latency exceeds the first latency threshold one or more of the commands in the instruction queue(s) are modified. The commands are not modified when the predicted latency does not exceed the latency threshold. A next command in the instruction queue(s) is then performed.
A logic cell for a programmable logic integrated circuit apparatus includes a K-input lookup table (LUT) circuit having a primary output Y, wherein Y is any function of K inputs, and at least one additional output (F). A carry circuit receives the outputs of the LUT and a carry‑in input CI. The carry circuit generates a sum output S and a carry‑out output CO. The carry circuit can be configured to provide S = CI and select CO from the set {0, 1, F}. The carry circuit can alternatively be configured to provide S = EXOR(Y, CI) and select CO from the set {0, 1, F}. The carry circuit can alternatively be configured to provide S = EXOR(Y, CI) and CO = CI if Y=q or to select CO from the set {0, 1, F} if Y≠q, where q is a pre-determined value (e.g., such as 0 or 1).
A method and apparatus for estimating signal related delays in a PLD design is disclosed. The PLD design is modeled in relation to one or more stages, each of the stages including a driver and one or more receivers coupled to the driver with a wiring tree. The modeling is based on a selected set of parameters that include: slope related delays associated with the driver; a delay related to a layout of the wiring tree; and a parameter related to a slope transfer from a previous driver input. A predetermined set of values for each of the selected parameters are accessed; the estimated signal related delays are computed for each of the modeled stages; and are written to a computer-readable storage medium.
G06F 30/367 - Vérification de la conception, p.ex. par simulation, programme de simulation avec emphase de circuit intégré [SPICE], méthodes directes ou de relaxation
G06F 119/12 - Analyse temporelle ou optimisation temporelle
100.
SPEAKER IN A MULT-SPEAKER SYSTEM ADJUSTING ITS SPEAKER SETTINGS
Examples disclosed herein include a speaker comprising: a group of microphones; and a processor to: determine a first speaker-channel identifier for a multi-speaker system at least partially responsive to a first tone captured at the group of microphones; determine a position of a source of the captured first tone relative to the speaker at least partially responsive to position information derived from the captured first tone; determine a second speaker-channel identifier at least partially responsive to the first speaker-channel identifier and the position of the source of the captured first tone; and determine speaker settings at least partially responsive to the second speaker- channel identifier. Further, disclosed herein is a method comprising: capturing a first tone exhibiting a first tone frequency; associating the captured first tone with a first speaker-channel identifier; determining a relative position of a source of the captured first tone at least partially responsive to a position information derived from the captured first tone; determining a second speaker-channel identifier at least partially responsive to the relative position and the first speaker-channel identifier; and determining speaker settings at least partially responsive to the second speaker-channel identifier.
H04R 1/40 - Dispositions pour obtenir la fréquence désirée ou les caractéristiques directionnelles pour obtenir la caractéristique directionnelle désirée uniquement en combinant plusieurs transducteurs identiques
brevets
