The invention provides a direct memory access (DMA) controller. The DMA controller has an address register, a data register and transfer circuitry for transferring data over a bus of a computing system. The DMA controller is configured to use the transfer circuitry to read data over the bus from a memory location having a first memory address, wherein the data comprises a second memory address, and store the second memory address in the address register, and use the transfer circuitry to transfer data over the bus between a memory location having the second memory address, or having a memory address derived from the second memory address, and the data register.
G06F 13/28 - Gestion de demandes d'interconnexion ou de transfert pour l'accès au bus d'entrée/sortie utilisant le transfert par rafale, p.ex. acces direct à la mémoire, vol de cycle
G06F 12/14 - Protection contre l'utilisation non autorisée de mémoire
A configurable radio frequency receiver is provided. The receiver has at least one low noise amplifier; an oscillator arrangement for producing a plurality of signals having a first number or a second number of separate phases; and multiple mixer modules having inputs connected to an output of the low noise amplifier. The receiver has a configurable resistor network. The receiver is configured such that it can operate in a first mode with said plurality of signals having said first number of phases or a second mode with said plurality of signals having said second number of phases. The configurable resistor network enables the receiver to operate in the first mode in a first configuration, and the second mode in a second configuration. The mixer modules are employed during the operation of the first mode and the second mode.
A radio receiver device is disclosed. The radio receiver device is configured to receive a radio signal comprising a data packet, said data packet comprising a first portion comprising an encoded bit sequence and including information specific to the data packet and a second portion comprising an encoded bit sequence and comprising corresponding information specific to the data packet. The radio receiver device is configured to calculate a correlation metric using the first portion and the second portion; and to estimate a carrier frequency offset between the radio signal and the radio receiver device using the correlation metric.
A receiver apparatus for receiving an OFDM radio signal comprising a first plurality of subcarrier-symbols, modulated on a corresponding plurality of subcarriers, and a second plurality of subcarrier-symbols, modulated on the corresponding plurality of subcarriers, to generate first and second bit sequences, the first bit sequence being an interleaved version of the second bit sequence according to a predetermined interleave function. Soft-output decoder logic generates a first soft-bit sequence for the first plurality of subcarrier-symbols, and a second soft-bit sequence for the second plurality of subcarrier-symbols. Combiner logic combines the soft-bit sequences, with the soft-bit sequences either both in an interleaved state or both in a non-interleaved state, by combining a respective soft-bit having a bit position in the first soft-bit sequence with a respective soft-bit having a same bit position in the second soft-bit sequence. Hard-output decoder logic outputs a hard-bit sequence representing the transmitted bit sequence.
An integrated-circuit device comprises a resettable source register in a first reset domain. A destination circuit, outside the first reset domain, is arranged to sample an output of the resettable source register. A digital logic module causes a central reset controller to output a reset-warning signal in response to receiving a request to reset first reset domain, and to reset the first domain after a predetermined delay period from outputting the reset-warning signal.
A receiver apparatus is configured to receive a radio-frequency signal comprising a first subcarrier comprising first subcarrier symbols and a second subcarrier comprising second subcarrier symbols, wherein the first subcarrier symbols and the second subcarrier symbols both encode a same bit sequence in a respective first subcarrier symbol and a second subcarrier symbol. Soft-output decoder logic calculates respective log-likelihood ratios for each of the first subcarrier symbols and generates a first output sequence comprising the respective log-likelihood ratios calculated for the first subcarrier symbols and similarly generates a second output sequence. Combiner logic combines the output sequences by adding or subtracting a respective log-likelihood ratio with a respective log-likelihood ratio calculated for the respective second subcarrier symbol to obtain a combined log-likelihood ratio for a respective bit of the bit sequence, and outputs a combined output sequence comprising a respective combined log-likelihood ratio for each bit of the bit sequence.
There is provided a method of testing an RF transceiver circuit and an RF transceiver circuit arranged to be operable in a test mode comprising a transmitter circuit portion and a receiver circuit portion, the receiver circuit portion including a mixer. The method involves the transmitter circuit portion generating a modulated signal and the receiver circuit portion receiving a continuous radio frequency wave. The mixer mixes the modulated signal with a signal derived from the continuous radio frequency wave to produce an output. A remainder of the receiver circuit portion processes the output of the mixer.
H04B 17/17 - Détection de contre-performance ou d’exécution défectueuse, p.ex. déviations de réponse
H04B 1/403 - Circuits utilisant le même oscillateur pour générer à la fois la fréquence de l’émetteur et la fréquence de l’oscillateur local du récepteur
A control portion for controlling an amplifier portion of a transmitter device is provided. The amplifier portion is arranged to amplify a radio signal with a transmission gain based at least partially on a gain control signal and having a nominal gain relationship between the gain control signal and the transmission gain. The control portion is arranged to determine a desired transmission gain, to determine one or more operating conditions, to calculate a gain control signal for causing the amplifier portion to apply the desired transmission gain, taking into account the nominal gain relationship and the one or more operating conditions, and to output said gain control signal. The gain control signal is different to a gain control signal calculated based only on the nominal gain relationship.
A radio transmitter is configured to operate in accordance with a first predetermined OFDM radio protocol. The transmitter reserves, within a timeslot with a predetermined timeslot duration, a reserved set of time-frequency resource units not available for an OFDM data channel defined by the first protocol. The transmitter allocates, within the timeslot, an allocated set of R time-frequency resource units for the OFDM data channel defined by the first protocol, wherein a number M of time-frequency resource units are included in both the allocated set and the reserved set, wherein the value R is such that R>N and R−M≤N, where N is a predetermined maximum number of time-frequency resource units that can be used to carry the data channel. The transmitter then transmits data indicative of the allocated set of R time-frequency resource units and data indicative of the reserved set of time-frequency resource units.
A digital radio transmitter device operates in accordance with a predetermined communication protocol that defines a default inter-frame spacing. The device has a minimum inter-frame spacing that is shorter than said default inter-frame spacing. The device is configured to: transmit a first data packet indicating that the device is able to support an inter-frame spacing shorter than said default inter-frame spacing; receive a second data packet from a peer device after said default inter-frame spacing; if said second data packet indicates that said peer device is able to support an inter-frame spacing shorter than said default inter-frame spacing, transmit a third data packet using an inter-frame spacing shorter than said default inter-frame spacing; and if said second data packet does not indicate that said peer device is able to support an inter-frame spacing shorter than said default inter-frame spacing, transmit said third packet using said default inter-frame spacing.
An integrated-circuit chip and method of operating said chip is provided. The integrated-circuit chip includes multiple processors, a system memory and a main system bus for carrying data between each of the processors and the system memory. The chip also has debug logic, a debug port for communicating with the debug logic from outside the chip and a debug connection that connects the debug logic to the main system bus. A power management system is also included for controlling the power supplied to each of a number of power domains on the chip. The debug logic and each of the processors are in different respective power domains. The debug logic is configured to send a debug instruction to any of the processors. The debug instruction is communicated over the debug connection and over the main system bus.
An amplitude regulator circuit portion is arranged to supply a current to an inverter in an oscillator circuit. The regulator monitors a voltage at the input terminal of the inverter and varies the current supplied to the inverter in response to the monitored voltage. The amplitude regulator comprises first, second, and third PMOS transistors, and first and second NMOS transistors and is arranged such that an input node is connected to the input terminal of the inverter, a respective gate terminal of each of the first and second NMOS transistors, and a respective drain terminal of the first NMOS and first PMOS transistors. The amplitude regulator also comprises a back-bias circuit portions arranged to vary a back-bias voltage at a back-gate terminal of the second NMOS transistor, to vary a threshold voltage, where the threshold voltage of the second NMOS transistor is lower than that of the first NMOS transistor.
H03B 5/36 - Production d'oscillation au moyen d'un amplificateur comportant un circuit de réaction entre sa sortie et son entrée l'élément déterminant la fréquence étant un résonateur électromécanique un résonateur piézo-électrique l'élément actif de l'amplificateur comportant un dispositif semi-conducteur
H03B 5/04 - Modifications du générateur pour compenser des variations dans les grandeurs physiques, p.ex. alimentation, charge, température
According to an aspect, there is provided a first radio device for performing the following. The first radio device causes wireless transmission of one or more first advertising messages at one or more advertising radio frequencies using a connectionless mode of the first radio device. The radio device receives, for at least one first advertising message, a first scan request from a second radio device and transmits, for each first scan request, a first scan response to the second radio device. Based on one or more received first scan requests, the first radio device performs bi-directional channel sounding with the second radio device at one or more sounding radio frequencies. The first radio device receives, from the second radio device, at least one first message comprising information on second channel sounding measurements and transmits. to the second radio device, at least one second message comprising information on first channel sounding measurements performed by the first radio device.
H04W 4/80 - Services utilisant la communication de courte portée, p.ex. la communication en champ proche, l'identification par radiofréquence ou la communication à faible consommation d’énergie
H04W 8/00 - Gestion de données relatives au réseau
There is disclosed an electronic device and a method of operating an electronic device. It has peripherals which each have one or more event outputs or task inputs, connected to a peripheral interconnect. The device also has a controller for configuring the peripheral interconnect and a memory, which are communicatively coupled to a bus system. The peripheral interconnect receives configuration data from the controller, which selectively connects peripheral event outputs and task inputs. The controller uses the bus system to access a sequence of instructions in a script stored in the memory. Each instruction in the sequence identifies a peripheral task input, event output and a second peripheral event output. Each subsequent instruction in the sequence is implemented in response to detecting an event signalled from the second peripheral event output identified by the preceding instruction in the sequence.
G06F 13/12 - Commande par programme pour dispositifs périphériques utilisant des matériels indépendants du processeur central, p.ex. canal ou processeur périphérique
An integrated circuit device includes an n-bit register comprising: a plurality of latches and at least one flip-flop, and clock gating circuitry, which includes a clock signal coupled to the latches and the flip-flop. Each latch comprises a latch gating terminal configured to receive a gating signal, wherein a respective latch is configured to receive the gating signal that either corresponds to the clock signal or is determined according to a logical operation including the clock signal such that a transparency for each respective latch is controlled in dependence upon a level of the gating signal. The integrated circuit device is configured to operate in a scan test mode, wherein during a scan shift operation, an input signal terminal of the flip-flop is configured to receive a test input signal and the flip-flop is configured to load the test input signal to an output signal terminal of the flip-flop.
An electronic device comprises an oscillator circuit portion comprising an inverter and a crystal oscillator connected between the input and output terminals of the inverter. An amplitude regulator circuit portion is arranged to supply a current to the inverter. The amplitude regulator monitors a voltage at the input of the inverter and varies the current supplied to the inverter in response to the monitored voltage. The amplitude regulator comprises a trimmable resistor arranged such that the voltage at the input of the inverter is set to an operating point when the supply current is equal to a threshold value, the operating point being at least partly determined by the selected resistance of the resistor. A current monitor is arranged to monitor the current supplied to the inverter during operation and to determine therefrom whether the voltage at the input terminal of the inverter is within a predetermined range.
H03B 5/36 - Production d'oscillation au moyen d'un amplificateur comportant un circuit de réaction entre sa sortie et son entrée l'élément déterminant la fréquence étant un résonateur électromécanique un résonateur piézo-électrique l'élément actif de l'amplificateur comportant un dispositif semi-conducteur
A circuit portion comprises a DCDC converter that provides current to one of a plurality of loads at a time. A controller detects when a voltage across an under-supplied load of the plurality of loads is below a first threshold. Channel logic circuitry provides current from the converter to the under-supplied load in response to the controller detecting that the voltage is below the first threshold. A voltage regulator provides current to the under-supplied load when the voltage is below a second threshold.
H02M 3/157 - Transformation d'une puissance d'entrée en courant continu en une puissance de sortie en courant continu sans transformation intermédiaire en courant alternatif par convertisseurs statiques utilisant des tubes à décharge avec électrode de commande ou des dispositifs à semi-conducteurs avec électrode de commande utilisant des dispositifs du type triode ou transistor exigeant l'application continue d'un signal de commande utilisant uniquement des dispositifs à semi-conducteurs avec commande automatique de la tension ou du courant de sortie, p.ex. régulateurs à commutation avec commande numérique
H02M 3/158 - Transformation d'une puissance d'entrée en courant continu en une puissance de sortie en courant continu sans transformation intermédiaire en courant alternatif par convertisseurs statiques utilisant des tubes à décharge avec électrode de commande ou des dispositifs à semi-conducteurs avec électrode de commande utilisant des dispositifs du type triode ou transistor exigeant l'application continue d'un signal de commande utilisant uniquement des dispositifs à semi-conducteurs avec commande automatique de la tension ou du courant de sortie, p.ex. régulateurs à commutation comprenant plusieurs dispositifs à semi-conducteurs comme dispositifs de commande finale pour une charge unique
H02M 1/00 - APPAREILS POUR LA TRANSFORMATION DE COURANT ALTERNATIF EN COURANT ALTERNATIF, DE COURANT ALTERNATIF EN COURANT CONTINU OU VICE VERSA OU DE COURANT CONTINU EN COURANT CONTINU ET EMPLOYÉS AVEC LES RÉSEAUX DE DISTRIBUTION D'ÉNERGIE OU DES SYSTÈMES D'ALI; TRANSFORMATION D'UNE PUISSANCE D'ENTRÉE EN COURANT CONTINU OU COURANT ALTERNATIF EN UNE PUISSANCE DE SORTIE DE CHOC; LEUR COMMANDE OU RÉGULATION - Détails d'appareils pour transformation
A common-mode feedback circuit for a fully differential amplifier comprises first (MB), second (MTP), and third (MTN) transistors, each having a respective drain, source, gate, and back-gate terminals. The drain terminal of the first transistor (MB) and the gate terminals of the first, second, and third transistors (MB, MTP, MTN) are connected together at a bias current terminal. The drain terminals of the second and third transistors are connected together at a tail current terminal. The source terminals of the first, second, and third transistors are connected together. The back-gate terminal of the first transistor (MB) is arranged to receive a common-mode reference voltage input (VCM), the back-gate terminal of the second transistor (MTP) is arranged to receive a positive output voltage (VP) from the fully differential amplifier, and the back-gate terminal of the third transistor (MTN) is arranged to receive a negative output voltage (VN) from the fully differential amplifier.
A constant-gm current source, arranged to generate a supply current for a Pierce oscillator. First and second transistors have source terminals connected to first and second supply rails, respectively, and drain terminals connected together and to the gate terminal of the first transistor. Third and fourth transistors have source terminals connected to the first and second supply rails, respectively, and drain terminals are connected together and to the gate terminal of the fourth transistor. An output portion varies the supply current in response to a voltage at the drain terminals of the third and fourth transistors. The gate terminals of the first and third transistors are connected together, and the gate terminals of the second and fourth transistors are connected together. An auto-calibration transistor has its source terminal connected to the first supply rail and its drain terminal connected to the source terminal of the first transistor.
H03B 5/04 - Modifications du générateur pour compenser des variations dans les grandeurs physiques, p.ex. alimentation, charge, température
H03B 5/36 - Production d'oscillation au moyen d'un amplificateur comportant un circuit de réaction entre sa sortie et son entrée l'élément déterminant la fréquence étant un résonateur électromécanique un résonateur piézo-électrique l'élément actif de l'amplificateur comportant un dispositif semi-conducteur
A circuit portion is provided which includes an energy harvesting device producing a DC output; a DC-DC converter having an input connected to the DC output of the energy harvesting device; an output for connection to a load; and a monitoring module including a non-ohmic semiconductor element. The monitoring module is arranged to derive information relating to an output current flowing from the DC-DC converter by measuring a current through the non-ohmic semiconductor element. The monitoring module is arranged to adjust one or more parameters of the DC-DC converter based on the information relating to said output current flowing from the DC-DC converter.
H02M 3/158 - Transformation d'une puissance d'entrée en courant continu en une puissance de sortie en courant continu sans transformation intermédiaire en courant alternatif par convertisseurs statiques utilisant des tubes à décharge avec électrode de commande ou des dispositifs à semi-conducteurs avec électrode de commande utilisant des dispositifs du type triode ou transistor exigeant l'application continue d'un signal de commande utilisant uniquement des dispositifs à semi-conducteurs avec commande automatique de la tension ou du courant de sortie, p.ex. régulateurs à commutation comprenant plusieurs dispositifs à semi-conducteurs comme dispositifs de commande finale pour une charge unique
H02M 1/00 - APPAREILS POUR LA TRANSFORMATION DE COURANT ALTERNATIF EN COURANT ALTERNATIF, DE COURANT ALTERNATIF EN COURANT CONTINU OU VICE VERSA OU DE COURANT CONTINU EN COURANT CONTINU ET EMPLOYÉS AVEC LES RÉSEAUX DE DISTRIBUTION D'ÉNERGIE OU DES SYSTÈMES D'ALI; TRANSFORMATION D'UNE PUISSANCE D'ENTRÉE EN COURANT CONTINU OU COURANT ALTERNATIF EN UNE PUISSANCE DE SORTIE DE CHOC; LEUR COMMANDE OU RÉGULATION - Détails d'appareils pour transformation
H02M 3/157 - Transformation d'une puissance d'entrée en courant continu en une puissance de sortie en courant continu sans transformation intermédiaire en courant alternatif par convertisseurs statiques utilisant des tubes à décharge avec électrode de commande ou des dispositifs à semi-conducteurs avec électrode de commande utilisant des dispositifs du type triode ou transistor exigeant l'application continue d'un signal de commande utilisant uniquement des dispositifs à semi-conducteurs avec commande automatique de la tension ou du courant de sortie, p.ex. régulateurs à commutation avec commande numérique
H02M 3/06 - Transformation d'une puissance d'entrée en courant continu en une puissance de sortie en courant continu sans transformation intermédiaire en courant alternatif par convertisseurs statiques utilisant des résistances ou des capacités, p.ex. diviseur de tension
A transmitter device includes a power supply, a power supply assessment module, a transmission power assessment module, and a data transmission module. The power assessment module assesses the present power delivery capability of the power supply. The transmission power assessment module assesses the power required for successful data transmission to an external communication party. The transmitter device compares the present power delivery capability to the power required for successful data transmission. If the comparison indicates that the present power delivery capability of the power supply is such that the power supply is able to supply sufficient power for successful data transmission, the transmitter device initiates data communication. If the comparison indicates that the present power delivery capability of the power supply is such that the power supply is not able to supply sufficient power for successful data transmission, the transmitter device does not initiate data communication.
A circuit portion is provided which includes an energy harvesting device producing a DC output; an inductor-less capacitor-based DC-DC converter, having an input connected to the DC output of the energy harvesting device; an output connected to a battery; and a voltage limiting module. The voltage limiting module includes a voltage sensor arranged to measure a voltage representative of a voltage at the battery and is arranged to limit a voltage provided by the DC-DC converter if the voltage representative of the voltage at the battery exceeds a threshold.
H02J 7/00 - Circuits pour la charge ou la dépolarisation des batteries ou pour alimenter des charges par des batteries
H01M 10/48 - Accumulateurs combinés à des dispositions pour mesurer, tester ou indiquer l'état des éléments, p.ex. le niveau ou la densité de l'électrolyte
H01M 10/42 - Procédés ou dispositions pour assurer le fonctionnement ou l'entretien des éléments secondaires ou des demi-éléments secondaires
H02J 50/00 - Circuits ou systèmes pour l'alimentation ou la distribution sans fil d'énergie électrique
A bootloader comprises software instructions for execution by a processor of an electronic processing device. The bootloader comprises an interpreter for interpreting a boot script stored in a memory of the processing device, and an integrity checker for checking the integrity of boot scripts stored in the memory. The bootloader comprises instructions for using the integrity checker to check the integrity of a first boot script of a plurality of boot scripts stored in the memory. The bootloader also comprises instructions for using the integrity checker to check the integrity of a second boot script of the plurality of boot scripts stored in the memory, independently of the integrity of the first boot script. The interpreter comprises instructions for interpreting a control-flow command in the first boot script, the control-flow command conditionally or unconditionally causing the bootloader to start interpreting commands from the second boot script.
G06F 21/57 - Certification ou préservation de plates-formes informatiques fiables, p.ex. démarrages ou arrêts sécurisés, suivis de version, contrôles de logiciel système, mises à jour sécurisées ou évaluation de vulnérabilité
An electronic device comprises a synchronisation system that receives a signal clocked by a first clock signal having a first frequency and receives a second clock signal having said first frequency, but offset in phase from the first clock signal. The signal is delayed by an adjustable delay period. It is determined whether, following a logic transition in the delayed signal, the next clock edge received is an active edge or is a non-active edge. A calibration controller increases the delay period when the next clock edge is a non-active edge and maintains or decreases the delay period when the next clock edge is an active edge, or decreases the delay period when the next clock edge is an active edge and maintains or increases the delay period when the next clock edge is a non-active edge.
H03K 5/26 - Circuits présentant plusieurs entrées et une sortie pour comparer des impulsions ou des trains d'impulsions entre eux en ce qui concerne certaines caractéristiques du signal d'entrée, p.ex. la pente, l'intégrale la caractéristique étant la durée, l'intervalle, la position, la fréquence ou la séquence
H03L 7/08 - Commande automatique de fréquence ou de phase; Synchronisation utilisant un signal de référence qui est appliqué à une boucle verrouillée en fréquence ou en phase - Détails de la boucle verrouillée en phase
A method of operating a digital radio receiver is provided as follows: a) receiving a radio signal comprising a symbol sequence; b) selecting a portion of the symbol sequence; c) determining a first error between the selected portion of the symbol sequence and a first predetermined symbol sequence using a difference metric; d) determining a set of second errors between the selected portion of the symbol sequence and a respective set of second predetermined symbol sequences, each formed by prepending different length portions of a predetermined preamble symbol sequence to a beginning of the first predetermined symbol sequence; and e) determining a minimum error from the first error and the set of second errors. If the first error is not the minimum error, a different portion of the symbol sequence is selected. Otherwise, a following portion of the symbol sequence is decoded to produce a data payload.
H04L 1/00 - Dispositions pour détecter ou empêcher les erreurs dans l'information reçue
H04L 27/144 - Circuits de démodulation; Circuits récepteurs avec démodulation utilisant les propriétés spectrales du signal reçu, p.ex. en utilisant des éléments sélectifs de la fréquence ou sensibles à la fréquence
H03M 13/41 - Estimation de séquence, c.à d. utilisant des méthodes statistiques pour la reconstitution des codes originaux utilisant l'algorithme de Viterbi ou des processeurs de Viterbi
A processing apparatus has a processor comprising a plurality of deferred-push processor registers and processor-register control circuitry. The processor-register control circuitry comprises a plurality of status registers, each status register corresponding to a different respective deferred-push register. The processor-register control circuitry is configured to: detect a write of a new value to a register of the deferred-push registers; and determine whether the status register for the deferred-push register has a first value, indicative of an unsaved status for the deferred-push register. The processor-control circuitry is configured, when the status register has the first value, to: read a current value from the deferred-push register before the writing of the new value to the deferred-push register completes; write the current value to a memory; and set the status register for the deferred-push register to a second value, indicative of a saved status for the deferred-push register.
An apparatus for demodulating a frequency-modulated signal comprises a joint frequency-offset & modulation-index estimator, and a signal demodulator. The joint estimator receives data representative of a preamble portion of the signal, modulated with predetermined preamble data. It jointly determines a frequency-offset estimate and a modulation-index estimate by using an optimization process that minimizes a cost function that is a function of the received data and that is parameterised by a frequency-offset parameter and by a modulation-index parameter. The signal demodulator receives data representative of a message portion of the signal, modulated with message data, and uses the frequency-offset estimate to demodulate the message.
H04L 27/144 - Circuits de démodulation; Circuits récepteurs avec démodulation utilisant les propriétés spectrales du signal reçu, p.ex. en utilisant des éléments sélectifs de la fréquence ou sensibles à la fréquence
A hardware accelerator comprises a direct memory access (DMA) system and an array of processing elements (PEs). Each PE comprises two data inputs and two data outputs and can perform a selectable logical or arithmetic operation. The array comprises configurable interconnects for selectively connecting outputs of the PEs to inputs of the PEs. A first data buffer comprises two or more first-edge cyclic registers, for connecting the DMA system to selected data inputs at a first edge of the PE array. A second data buffer comprises two or more second-edge linear or cyclic shift registers, for connecting selected data outputs of a second edge of the PE array to the DMA system.
A method of, and apparatus for, demodulating a frequency-modulated signal. The method comprises: for each of a plurality of templates, performing a respective cross-correlation operation between the template and data representative of the frequency-modulated signal, each template comprising data representative of a signal that is frequency-modulated with predetermined preamble data using a different respective modulation index; generating frequency-offset data from one or more of the cross-correlation operations, the frequency-offset data being representative of a difference between a reference frequency and a carrier frequency of the frequency-modulated signal; determining a respective peak correlation-coefficient value from each of the cross-correlation operations; identifying a highest peak correlation-coefficient value in the determined peak correlation-coefficient values; determining a modulation index estimate in dependence on which template produced the highest peak correlation-coefficient value; and using the frequency-offset data and the modulation index estimate to demodulate at least a portion of the frequency-modulated signal.
H04L 27/156 - Circuits de démodulation; Circuits récepteurs avec démodulation utilisant les propriétés temporelles du signal reçu, p.ex. détectant la largeur de l'impulsion
A receiver comprises a matched filter bank, decision logic and a frequency offset estimator. The matched filter bank comprises an input for receiving data representative of a frequency- or phase-modulated signal. The decision logic generates a sequence of demodulated symbol values from outputs of the matched filter bank. The frequency offset estimator determines a first phase value from a first output and a second phase value from a second output of the matched filter bank, the second output being offset from the first by L symbol periods. It also determines a phase adjustment value from an L-symbol subsequence within the sequence of demodulated symbol values, each subsequence value being determined from values output by the matched filter bank between the first and second outputs. It estimates a frequency offset based on the difference between the first phase value plus the phase adjustment value, and the second phase value.
A current limiting circuit portion for limiting an output current of an electronic device includes an input voltage line for receiving an input voltage and a trimming circuit portion. The trimming circuit portion includes a resistive part providing a first resistance that is configurable based on one or more resistance control signals applied thereto, and a condition-tracking part connected in series with the resistive part that includes a condition-tracking transistor, the condition-tracking part providing a second resistance that is dependent on temperature and the input voltage.
G05F 1/565 - Régulation de la tension ou de l'intensité là où la variable effectivement régulée par le dispositif de réglage final est du type continu utilisant des dispositifs à semi-conducteurs en série avec la charge comme dispositifs de réglage final sensible à une condition du système ou de sa charge en plus des moyens sensibles aux écarts de la sortie du système, p.ex. courant, tension, facteur de puissance
G05F 1/595 - Dispositifs à semi-conducteurs connectés en série
G05F 1/575 - Régulation de la tension ou de l'intensité là où la variable effectivement régulée par le dispositif de réglage final est du type continu utilisant des dispositifs à semi-conducteurs en série avec la charge comme dispositifs de réglage final caractérisé par le circuit de rétroaction
An asynchronous circuit portion for sampling an input signal is provided. The circuit portion comprises a sampling circuit portion arranged to sample the input signal to generate a sanitized output signal corresponding to the input signal; a comparison circuit portion arranged to compare the sanitized output signal with the input signal and to generate a change signal if the sanitized output signal does not correspond to the input signal; and a control circuit portion arranged to trigger the sampling circuit portion to sample the input signal to generate an updated sanitized output signal, in response to the change signal.
H03L 7/14 - Commande automatique de fréquence ou de phase; Synchronisation utilisant un signal de référence qui est appliqué à une boucle verrouillée en fréquence ou en phase - Détails de la boucle verrouillée en phase pour assurer une fréquence constante quand la tension d'alimentation ou la tension de correction fait défaut
H03L 7/085 - Commande automatique de fréquence ou de phase; Synchronisation utilisant un signal de référence qui est appliqué à une boucle verrouillée en fréquence ou en phase - Détails de la boucle verrouillée en phase concernant principalement l'agencement de détection de phase ou de fréquence y compris le filtrage ou l'amplification de son signal de sortie
H03K 19/21 - Circuits OU EXCLUSIF, c. à d. donnant un signal de sortie si un signal n'existe qu'à une seule entrée; Circuits à COÏNCIDENCES, c. à d. ne donnant un signal de sortie que si tous les signaux d'entrée sont identiques
According to an aspect, there is provided a finite state machine repair circuitry comprising: at least one control unit, and at least one memory for storing instructions to be executed by the at least one control unit, wherein the at least one memory and the instructions are configured to, with the at least one control unit, cause the finite state machine repair circuitry at least to perform: causing overriding at least one of one or more input and/or output signals of a finite state machine circuit by corresponding one or more override signals generated by the finite state machine repair circuitry so as to a form a channel mimicking operation of said finite state machine circuit.
G06F 30/398 - Vérification ou optimisation de la conception, p.ex. par vérification des règles de conception [DRC], vérification de correspondance entre géométrie et schéma [LVS] ou par les méthodes à éléments finis [MEF]
A radio device comprises a radio transceiver, a resonator, a temperature measurement unit, a frequency synthesiser and a processing system. A temperature signal from the temperature measurement unit, representative of a measured temperature of the resonator, is used to determine an estimated frequency offset for the resonator at the measured temperature using a model stored in a memory of the processing system that relates frequency offset to temperature. A periodic signal from the resonator is provided to the frequency synthesizer, which, in dependence on the estimated frequency offset, is used to generate a periodic local signal. The radio transceiver receives a radio signal comprising a periodic component at a received signal frequency. An error value representative of a difference between the received signal frequency and a frequency of the periodic local signal is determined and used to update one or more parameters of the model stored in the memory.
H04B 1/38 - TRANSMISSION - Détails des systèmes de transmission non caractérisés par le milieu utilisé pour la transmission Émetteurs-récepteurs, c. à d. dispositifs dans lesquels l'émetteur et le récepteur forment un ensemble structural et dans lesquels au moins une partie est utilisée pour des fonctions d'émission et de réception
H03L 1/02 - Stabilisation du signal de sortie du générateur contre les variations de valeurs physiques, p.ex. de l'alimentation en énergie contre les variations de température uniquement
H03L 7/197 - Synthèse de fréquence indirecte, c. à d. production d'une fréquence désirée parmi un certain nombre de fréquences prédéterminées en utilisant une boucle verrouillée en fréquence ou en phase en utilisant un diviseur de fréquence ou un compteur dans la boucle une différence de temps étant utilisée pour verrouiller la boucle, le compteur comptant entre des nombres variables dans le temps ou le diviseur de fréquence divisant par un facteur variable dans le temps, p.ex. pour obtenir une division de fréquence
A method of operating a display system consisting of a plurality of light emitting diodes (LEDs) is disclosed. The LEDs are arranged in a plurality of groups and an integrated circuit provides power to the LEDs through a plurality of output pins connected to respective groups. The integrated circuit selectively determines the states of the output pins to illuminate the groups of LEDs in a repeating sequence such that each group is illuminated for a time dependent on a number of groups and a compensation factor. The compensation factor is dependent on at least a number of LEDs in the group.
A radio-frequency modulator apparatus comprises a baseband stage, a mixer stage and a radio-frequency stage. The baseband stage comprises: an input line for receiving an input current representative of a baseband input signal, a baseband transistor that passes some or all of the input current between a first and a second terminal thereof, an electrical connection between the input line and a control terminal of the baseband transistor, and an output line connected to said control terminal. The mixer stage receives a signal from the baseband stage and mixes it with a radio-frequency local-oscillator signal to generate a radio-frequency mixed signal. The radio-frequency stage receives the radio-frequency mixed signal, applies the radio-frequency mixed signal to a control terminal of a radio-frequency transistor causing it to pass a radio-frequency output current between a first and a second terminal thereof, and outputs the radio-frequency output current as an output signal.
H03D 7/12 - Transfert de modulation d'une porteuse à une autre, p.ex. changement de fréquence au moyen de dispositifs à semi-conducteurs ayant plus de deux électrodes
An Orthogonal Frequency-Division Multiplexing digital radio transmitter is arranged to transmit a data packet comprising a plurality of Orthogonal Frequency-Division Multiplexing symbols. At least one of the symbols comprises a plurality of demodulation reference signals in a first plurality of frequency sub-carriers of the symbol. The transmitter is arranged to transmit a physical control channel at least partly distributed among a remainder of frequency sub-carriers of the symbol according to a calculated distribution. The transmitter calculates the distribution by arranging the remainder of frequency sub-carriers in a two-dimensional matrix such that said remainder of frequency sub-carriers have indices which are sequential in a first dimension and have a common increment in a second dimension, and allocating a second plurality of the remainder of frequency sub-carriers to the physical control channel sequentially in the second direction.
A time delay circuit comprising a plurality of differential delay cells each having a respective time delay and being arranged in series. Each delay cell comprises first and second inverter sub-cells, each comprising a respective PMOS transistor and an NMOS transistor arranged in series such that their respective drain terminals are connected at a drain node. Each of the transistors has a back-gate terminal and is arranged such that a respective voltage applied to said back-gate terminal linearly controls its respective threshold voltage. The back-gate terminal of the PMOS transistor in each inverter sub-cell is connected to the drain node of the other sub-cell and/or the back-gate terminal of the NMOS transistor in each inverter sub-cell is connected to the drain node of the other sub-cell. A control signal varies the time delay of the delay cell by adjusting a voltage supplied to a back-gate terminal of a transistor.
H03K 5/134 - Dispositions ayant une sortie unique et transformant les signaux d'entrée en impulsions délivrées à des intervalles de temps désirés utilisant une chaîne de dispositifs actifs de retard avec des transistors à effet de champ
A method of digital radio communication between a central device and a peripheral device. The peripheral device transmits a repeated burst of advertising packets on a primary physical channel, each packet comprising an advertising field indicating an availability to form a connection. The advertising field comprises an address identifying the peripheral device. The peripheral device transmits a subsequent advertising packet on an auxiliary channel. The central device receives a packet from the burst of packets, decodes the advertising field and compares the address to one or more desired connection addresses to determine whether to initiate a connection to the peripheral device. If the address matches a desired connection address, the central device initiates a connection to the peripheral device. If the address does not match a desired connection address, the central device resumes listening for further advertising packets.
H04W 8/00 - Gestion de données relatives au réseau
H04W 28/18 - Négociation des paramètres de télécommunication sans fil
H04W 28/24 - Négociation de l'agrément du niveau de service [SLA Service Level Agreement]; Négociation de la qualité de service [QoS Quality of Service]
A method of operating a digital radio transmitter device in accordance with a predetermined communication protocol defining a transmission timing tolerance. The method comprises: transmitting a plurality of first periodic transmissions in accordance with said predetermined communication protocol having a first period and an inherent timing uncertainty less than said transmission timing tolerance; performing a plurality of second periodic actions with a second period wherein said first and second periods are equal to each other or an integer multiple of each other; and adjusting a timing of one or more of the first periodic transmissions by an amount greater than said inherent timing uncertainty but less than or equal to a difference between said inherent timing uncertainty and said transmission timing tolerance so as to change said first period temporarily by an amount less than or equal to said transmission timing tolerance, thereby changing an offset between said first transmissions and said second actions.
A method and system for moving data from a source memory to a destination memory by a processor are disclosed. The processor has a plurality of registers and the source memory stores a sequence of instructions that include one or more load instructions and one or more store instructions. The processor moves the load instructions from the source memory to the destination memory. Then, the processor initiates execution of the load instructions from the destination memory in order to load the data from the source memory to one or more registers in the processor. Execution then returns to the sequence of instructions stored in the source memory, and the processor stores the data from the registers to the destination memory.
A method and system for moving data from a source memory to a destination memory by a processor is disclosed herein. The destination memory stores a sequence of instructions and the sequence of instructions comprises one or more load instructions and one or more store instructions. The processor initially moves the one or more store instructions from the destination memory to the source memory. The processor then executes the one or more load instructions from the destination memory. On executing the one or more load instructions, the data is loaded from the source memory to at least one register in the processor. The processor further initiates execution of the one or more store instructions stored in the source memory. On executing the one or more store instructions from the source memory, the processor stores the data from the at least one register to the destination memory.
A circuit portion for a radio transceiver comprises: a power amplifier for use when the transceiver operates in a transmission mode, a low-noise amplifier for use when the transceiver operates in a reception mode, a voltage control circuit portion, and a transformer. The transformer comprises a primary winding with a terminal for connecting to an antenna, and a secondary winding comprising a first terminal, a second terminal and a third terminal located between the first and second terminals. The power amplifier is connected to the secondary winding, the low-noise amplifier is connected to both the primary and secondary windings and the voltage control circuit portion is connected to the third terminal of the secondary winding. The voltage control circuit portion applies a first voltage to the third terminal when the transceiver operates in the transmission mode and applies a second, different voltage when the transceiver operates in the reception mode.
H03L 7/099 - Commande automatique de fréquence ou de phase; Synchronisation utilisant un signal de référence qui est appliqué à une boucle verrouillée en fréquence ou en phase - Détails de la boucle verrouillée en phase concernant principalement l'oscillateur commandé de la boucle
H04B 1/18 - Circuits d'entrée, p.ex. pour le couplage à une antenne ou à une ligne de transmission
H04B 1/38 - TRANSMISSION - Détails des systèmes de transmission non caractérisés par le milieu utilisé pour la transmission Émetteurs-récepteurs, c. à d. dispositifs dans lesquels l'émetteur et le récepteur forment un ensemble structural et dans lesquels au moins une partie est utilisée pour des fonctions d'émission et de réception
44.
RADIO TRANSMITTER APPARATUS WITH CRYPTOGRAPHIC ENGINE
An integrated-circuit radio transmitter chip comprises a transmitter, a cryptographic engine and control circuitry for the cryptographic engine. The cryptographic engine performs a cryptographic operation by receiving input data, performing a first process to generate first result data and a second process to generate second result data. The first and second result data are used to generate output data. In response to determining that the transmitter is active, the control circuity controls the cryptographic engine to perform the first process and prevents the cryptographic engine from performing the second process while the transmitter is active. The control circuitry controls the cryptographic engine to perform the second process in response to determining that the transmitter is not active.
H04L 9/32 - Dispositions pour les communications secrètes ou protégées; Protocoles réseaux de sécurité comprenant des moyens pour vérifier l'identité ou l'autorisation d'un utilisateur du système
A system for synchronizing communications in a radio ranging process involves transmitting calibration signals according to a predetermined schedule of nominal transmission times. Timing offsets are determined. A start time is determined for a transmission of a ranging signal. The start time is earlier than a nominal start time of the ranging signal by at least the largest timing offset. Another system for synchronization involves a radio device transmitting a calibration signal to a second radio device and receiving a calibration response signal from the second radio device. A time-of-flight value is determined in dependence on a time of departure of the calibration signal and a time of arrival of the calibration response signal. A ranging signal is transmitted at a time determined in dependence on the determined time-of-flight value. A ranging response signal is received and processed to determine a range value.
A radio receiver comprises a matched filter bank and a decision unit. The matched filter bank has a plurality of filter modules for generating correlation-strength data from a sampled radio signal, each filter module being configured to cross-correlate the sampled signal with data representing a respective filter sequence. The decision unit is configured to use the correlation-strength data to generate a sequence of decoded symbols from the sampled signal. The matched filter bank and/or decision unit are configured to determine the value of each symbol in the sequence in part based on the value of a respective earlier decoded symbol from the sequence of decoded symbols.
An electronic device comprising a system on chip and an external module. The system on chip includes a plurality of internal subsystems and a power management system including a plurality of internal voltage regulators which supply power to the plurality of internal subsystems. Each of the internal voltage regulators has an associated current limiter. The external module includes at least one external voltage regulator which can provide power to at least one of the internal subsystems. The power management system during a start-up phase enables the internal voltage regulators and the current limiters and in a subsequent phase determines an externally powered set of the internal subsystems, disables the corresponding internal voltage regulators, and disables the current limiters associated with the internal subsystems not externally powered.
G06F 1/32 - Moyens destinés à économiser de l'énergie
G06F 1/3206 - Surveillance d’événements, de dispositifs ou de paramètres initiant un changement de mode d’alimentation
G06F 1/3296 - Gestion de l’alimentation, c. à d. passage en mode d’économie d’énergie amorcé par événements Économie d’énergie caractérisée par l'action entreprise par diminution de la tension d’alimentation ou de la tension de fonctionnement
A radio receiver device determines whether a digital radio signal includes a predetermined cyclic preamble. An input portion samples the digital radio signal and generates a plurality of samples for storage in a buffer. A first autocorrelator correlates first and second subsets of the samples to generate a first correlation metric, the second subset having been stored in the buffer earlier than said first subset by an even integer multiple of half of the preamble period. A second autocorrelator correlates first and third subsets of the plurality of samples to generate a second correlation metric, the third subset having been stored in the buffer earlier than said first subset by an odd integer multiple of half of the preamble period. A processing portion calculates a difference between the correlation metrics and determines that the radio signal includes the predetermined cyclic preamble when the difference is greater than a threshold value.
An oscillator arrangement is provided, comprising a relaxation oscillator having an active state and an inactive state; a bias current circuit portion arranged to provide a bias current to the relaxation oscillator during said active state; and an electronic switch arranged to isolate said relaxation oscillator from the bias current circuit portion when in said inactive state. The oscillator arrangement is arranged to store an internal voltage value associated with said bias current and the bias current circuit portion is arranged to use the stored internal voltage value to generate the bias current when the oscillator is started up from the inactive state to the active state.
H03B 5/24 - Elément déterminant la fréquence comportant résistance, et soit capacité, soit inductance, p.ex. oscillateur à glissement de phase l'élément actif de l'amplificateur étant un dispositif à semi-conducteurs
H03K 3/014 - Modifications du générateur pour assurer le démarrage des oscillations
H03K 4/501 - Génération d'impulsions ayant comme caractéristique essentielle une pente définie ou des parties en gradins à forme triangulaire en dents de scie utilisant comme éléments actifs des dispositifs à semi-conducteurs dans laquelle la tension en dents de scie est produite à travers un condensateur le début de la période de retour étant déterminé par l'amplitude de la tension à travers le condensateur, p.ex. avec un comparateur
A clock selector circuit receives a first input clock signal (CLK1) having a first frequency, and a second input clock signal (CLK2) having a second frequency. A phase difference detector is configured to detect when a phase difference occurs, over time, between the first input clock signal (CLK1) and the second input clock signal (CLK2), determined using when a clock edge crosses zero, and to signal this zero crossing to switching circuitry. The switching circuitry is configured, in response to receiving a zero-crossing signal from the phase difference detector, to detect an edge of opposite type to the predetermined type in the first input clock signal (CLK1) or in the second input clock signal (CLK2), and, in response to detecting said edge of opposite type, to switch an output clock signal (CLK_OUT) between the first input clock signal (CLK1) and the second input clock signal (CLK2).
H03K 3/00 - Circuits pour produire des impulsions électriques; Circuits monostables, bistables ou multistables
H03K 5/135 - Dispositions ayant une sortie unique et transformant les signaux d'entrée en impulsions délivrées à des intervalles de temps désirés par l'utilisation de signaux de référence de temps, p.ex. des signaux d'horloge
G06F 1/08 - Générateurs d'horloge ayant une fréquence de base modifiable ou programmable
H03K 5/26 - Circuits présentant plusieurs entrées et une sortie pour comparer des impulsions ou des trains d'impulsions entre eux en ce qui concerne certaines caractéristiques du signal d'entrée, p.ex. la pente, l'intégrale la caractéristique étant la durée, l'intervalle, la position, la fréquence ou la séquence
A method of operating a radio receiver device comprises receiving a plurality of signals with a plurality of corresponding frequencies; applying respective gains to each of the plurality of signals; and storing the gain applied to each signal and its corresponding frequency. The method comprises subsequently receiving a further signal with a further frequency; and applying a further gain to the further signal. The further gain is determined using at least one of the stored gains according to a difference between the further frequency and at least one of the plurality of corresponding frequencies.
Analog to digital conversion circuitry has an input sampling buffer, which has an input sampling capacitor for sampling an analog signal. The conversion circuitry also has a successive-approximation-register analog to digital converter (SAR-ADC) which converts the sampled analog signal to a digital signal. The input sampling buffer has an amplifier and a gain-control capacitor, and has an amplification configuration and an error-feedback configuration. In the amplification configuration, the input sampling capacitor is coupled to the amplifier and gain-control capacitor, with the gain-control capacitor connected in feedback with the amplifier, for applying gain to the sampled analog signal. In the error-feedback configuration, the gain-control capacitor is decoupled from the input sampling capacitor and receives a residue voltage from the SAR-ADC, such that the level of the analog signal determined in the amplification configuration varies depending on the residue voltage received onto the gain-control capacitor in the error-feedback configuration.
According to an aspect, there is provided an apparatus comprising: a bulk-controlled switch circuit comprising a first transistor coupled to a load and having a source coupled to a source voltage and a drain coupled to a drain voltage, a second transistor and a third transistor coupled, in parallel with the first transistor, to one another in series between the source voltage and the drain voltage, wherein a bulk of the first transistor is coupled with bulks of the second transistor and the third transistor, wherein a gate of the second transistor is coupled to the source voltage via a first impedance circuit and a gate of the third transistor is coupled to the drain voltage via a second impedance circuit to form a comparator switch controlled by the source voltage and the drain voltage and to dynamically switch a greater one of the source voltage and the drain voltage to the load; a first current generator circuit and a second current generator circuit; a first current mirror circuit biased by the first current generator circuit, responsive to the source voltage, and configured to trigger the second transistor to couple the source voltage to the load when the source voltage is above the drain voltage; a second current mirror circuit biased by the second current generator circuit, responsive to the drain voltage, and configured to trigger the third transistor to couple the drain voltage to the load when the drain voltage is above the source voltage.
H02M 3/156 - Transformation d'une puissance d'entrée en courant continu en une puissance de sortie en courant continu sans transformation intermédiaire en courant alternatif par convertisseurs statiques utilisant des tubes à décharge avec électrode de commande ou des dispositifs à semi-conducteurs avec électrode de commande utilisant des dispositifs du type triode ou transistor exigeant l'application continue d'un signal de commande utilisant uniquement des dispositifs à semi-conducteurs avec commande automatique de la tension ou du courant de sortie, p.ex. régulateurs à commutation
H02M 3/158 - Transformation d'une puissance d'entrée en courant continu en une puissance de sortie en courant continu sans transformation intermédiaire en courant alternatif par convertisseurs statiques utilisant des tubes à décharge avec électrode de commande ou des dispositifs à semi-conducteurs avec électrode de commande utilisant des dispositifs du type triode ou transistor exigeant l'application continue d'un signal de commande utilisant uniquement des dispositifs à semi-conducteurs avec commande automatique de la tension ou du courant de sortie, p.ex. régulateurs à commutation comprenant plusieurs dispositifs à semi-conducteurs comme dispositifs de commande finale pour une charge unique
H01L 27/02 - Dispositifs consistant en une pluralité de composants semi-conducteurs ou d'autres composants à l'état solide formés dans ou sur un substrat commun comprenant des éléments de circuit passif intégrés avec au moins une barrière de potentiel ou une barrière de surface
H03K 17/687 - Commutation ou ouverture de porte électronique, c. à d. par d'autres moyens que la fermeture et l'ouverture de contacts caractérisée par l'utilisation de composants spécifiés par l'utilisation, comme éléments actifs, de dispositifs à semi-conducteurs les dispositifs étant des transistors à effet de champ
A circuit portion comprising a clock domain is disclosed. A first clock is arranged to clock components in the clock domain. An analogue to digital converter is clocked by a second clock with a duty cycle. The second clock is derived from the first clock. The analogue to digital converter is arranged to output a feedback signal upon finishing a conversion of a sample, and the feedback signal is arranged to control the duty cycle.
H03M 1/38 - Valeur analogique comparée à des valeurs de référence uniquement séquentiellement, p.ex. du type à approximations successives
H03K 19/17736 - Circuits logiques, c. à d. ayant au moins deux entrées agissant sur une sortie; Circuits d'inversion utilisant des éléments spécifiés utilisant des circuits logiques élémentaires comme composants disposés sous forme matricielle - Détails structurels des ressources de routage
j to select a subset from the plurality of subsets. Timing or frequency synchronization information for the radio apparatus is determined from the peaks of the selected subset.
A method of mediating a read transaction from a transaction source domain having a first bus width to a transaction target domain having a second bus width less than the first bus width. The method includes receiving first and second read transactions associated with a first and second transaction ID, separating each read transaction into a plurality of sub-transactions, which have the second bus width. The method further includes sending a sub-transaction of each plurality of sub-transactions to the transaction target domain and receiving first data associated with the first transaction ID and second data associated with the second transaction ID, storing the first data in a first storage element assigned to a first list, storing the second data in a second storage element assigned to a second list; and reading out data to the transaction source domain from the first list and the second list independently of each other.
A radio apparatus is configured to correlate signal data with stored synchronization data to generate synchronization correlation data. The signal data represents a received radio-frequency signal that encodes a data frame having a synchronization preamble comprising a plurality of instances of a predetermined synchronization sequence. The stored synchronization data represents the predetermined synchronization sequence. The synchronization correlation data is generated by correlating signal data representing the synchronization preamble with the stored synchronization data. While generating the synchronization correlation data, the radio apparatus identifies a first set of one or more peaks in the synchronization correlation data, and determines first synchronization information from the first set of one or more peaks. After generating more of the synchronization correlation data, the radio apparatus identifies a second set of one or more peaks in the synchronization correlation data, and determines second synchronization information from the second set of one or more peaks.
According to an aspect, there is provided a solution for providing an access to a slave unit. An address from a master unit trying to access a slave unit is received (400). The received address is mapped (402) to a slave address. Default access permissions are associated (404) to the master-slave connection. Additional access permissions associated with the master unit and the slave address are determined (406). The master-slave connection is enabled (408) if additional access permissions allow the master unit to access the slave, otherwise the connection is rejected.
An electronic device comprises a bridge configured to transfer data bus transactions from a transaction source domain having a first bus width to a transaction target domain having a second bus width less than the first bus width. The bridge comprises a first interface configured to receive a transaction from the transaction source domain, where the transaction has a first transaction burst length. A converter logic is configured such that when a transaction is received via the first interface, the converter logic splits the transaction into a plurality of second transactions each having a respective second transaction burst length, wherein the plurality of second transactions have the second bus width. A second interface is configured to send the plurality of second transactions to the transaction target domain.
G06F 13/28 - Gestion de demandes d'interconnexion ou de transfert pour l'accès au bus d'entrée/sortie utilisant le transfert par rafale, p.ex. acces direct à la mémoire, vol de cycle
G06F 9/46 - Dispositions pour la multiprogrammation
G06F 13/362 - Gestion de demandes d'interconnexion ou de transfert pour l'accès au bus ou au système à bus communs avec commande d'accès centralisée
An integrated-circuit device comprises a physical-unclonable-function (PUF) unit, a secure module, and an interconnect system communicatively coupled to the PUF unit and to the secure module. The device transfers a PUF key from the PUF unit to the secure module, over the interconnect system. In order to do this, the secure module generates a random value. The secure module then sends the random value to the PUF unit. The PUF unit then performs a bitwise XOR operation between the received random value and the PUF key, to generate a masked value. The PUF unit then transfers the masked value over the interconnect system to the secure module. The secure module then unmasks the PUF key by performing a bitwise XOR operation between the received masked value and the random value.
H04L 9/32 - Dispositions pour les communications secrètes ou protégées; Protocoles réseaux de sécurité comprenant des moyens pour vérifier l'identité ou l'autorisation d'un utilisateur du système
An electronic device has an amplifier having an amplifier input terminal and an amplifier output terminal, the amplifier output terminal being connected to the device output terminal. An input capacitor is connected between the device input terminal and the amplifier input terminal. A feedback capacitor is connected between the amplifier output terminal and the amplifier input terminal. A switchable capacitor has a first terminal connected to the amplifier input terminal and a second terminal connected to a respective first terminal of each of a first switch and a second switch. The first switch has its second terminal connected to the device input terminal. The second switch has its second terminal connected to the amplifier output terminal. In this arrangement, the switchable capacitor can be switched between forming part of the input path of the amplifier or the feedback path of the amplifier.
An RF amplifier comprises a first ‘transconductance’ transistor (NCS) arranged to receive an RF input voltage (RFIN) at its gate terminal. A second ‘cascode’ transistor (NCG) has its source terminal connected to the drain terminal of the first transistor (NCS) at a node (MID). A feedback circuit portion is configured to measure a node voltage at the node (MID), to determine an average of the node voltage, to compare said average node voltage to a predetermined reference voltage (VBCG), and to generate a control voltage (CGGATE) dependent on the difference between the average node voltage and the predetermined reference voltage (VBCG). The feedback circuit portion applies the control voltage (CGGATE) to the gate terminal of the second transistor (NCG).
H03F 1/22 - Modifications des amplificateurs pour réduire l'influence défavorable de l'impédance interne des éléments amplificateurs par utilisation de couplage dit "cascode", c. à d. étage avec cathode ou émetteur à la masse suivi d'un étage avec grille ou base à la masse respectivement
H03F 3/195 - Amplificateurs à haute fréquence, p.ex. amplificateurs radiofréquence comportant uniquement des dispositifs à semi-conducteurs dans des circuits intégrés
H03F 1/02 - Modifications des amplificateurs pour augmenter leur rendement, p.ex. étages classe A à pente glissante, utilisation d'une oscillation auxiliaire
63.
START-UP CIRCUIT FOR REFERENCE VOLTAGE/CURRENT GENERATOR
This document describes a start-up circuit for a self-biasing generator providing a reference voltage or a reference current, the start-up circuit comprising: an impedance circuit; means for coupling, in response to a start-up signal input to the start-up circuit, the impedance circuit to a bias voltage line of a current mirror circuit of the self-biasing generator, thereby inducing current to flow in the self-biasing generator and starting the self-biasing generator; a bypass current source coupled to the current mirror circuit and to the impedance, wherein the bypass current source is configured to be driven by a current in the current mirror circuit and to supply current to the impedance in proportion to the current in the current mirror circuit, thereby limiting the current induced to the self-biasing generator by the start-up circuit.
G05F 3/20 - Régulation de la tension ou du courant là où la tension ou le courant sont continus utilisant des dispositifs non commandés à caractéristiques non linéaires consistant en des dispositifs à semi-conducteurs en utilisant des combinaisons diode-transistor
buf); b) connecting the resonator to a second, lower, voltage for a second pulse period to discharge the resonator at least partially; and repeating steps a) and b) at a rate corresponding to the resonance of the resonator and with a phase corresponding to the resonance of the resonator, so as to maintain the resonance of the resonator.
H03B 5/36 - Production d'oscillation au moyen d'un amplificateur comportant un circuit de réaction entre sa sortie et son entrée l'élément déterminant la fréquence étant un résonateur électromécanique un résonateur piézo-électrique l'élément actif de l'amplificateur comportant un dispositif semi-conducteur
H03L 7/099 - Commande automatique de fréquence ou de phase; Synchronisation utilisant un signal de référence qui est appliqué à une boucle verrouillée en fréquence ou en phase - Détails de la boucle verrouillée en phase concernant principalement l'oscillateur commandé de la boucle
H03B 5/06 - Modifications du générateur pour assurer l'amorçage des oscillations
H03B 5/02 - Production d'oscillation au moyen d'un amplificateur comportant un circuit de réaction entre sa sortie et son entrée - Détails
H03B 5/32 - Production d'oscillation au moyen d'un amplificateur comportant un circuit de réaction entre sa sortie et son entrée l'élément déterminant la fréquence étant un résonateur électromécanique un résonateur piézo-électrique
This document describes a solution for low-power voltage regulation. According to an aspect, there is provided an apparatus comprising: a supply voltage regulator circuit configured to regulate a power supply voltage of a circuit; a comparator circuit coupled to the power supply voltage and configured to sample the power supply voltage, to compare the sampled power supply voltage with a reference voltage and, if the sampled power supply voltage is below the reference voltage, to enable the supply voltage regulator circuit to charge the power supply voltage, wherein the comparator is switched on and off in response to a clock signal; and a clock signal generator circuit configured to generate the clock signal.
G05F 1/56 - Régulation de la tension ou de l'intensité là où la variable effectivement régulée par le dispositif de réglage final est du type continu utilisant des dispositifs à semi-conducteurs en série avec la charge comme dispositifs de réglage final
A method is disclosed for producing an output clock signal with a target frequency using an oscillator circuit portion configured to receive a control value and produce an output clock signal with a frequency dependent on the control value. In one embodiment, the method comprises providing a first control value to the oscillator circuit portion corresponding to the target frequency, so as to cause the oscillator circuit portion to produce the output clock signal with a first frequency, comparing the output clock signal with a reference clock signal having a reference frequency to determine an offset between the first frequency and the target frequency, and providing a second control value to the oscillator circuit portion that differs from the first control value by a magnitude calculated with reference to the determined offset, to cause the oscillator circuit portion to produce the output clock signal with a second frequency.
A circuit portion comprises a load circuit portion and a bias circuit portion. The load circuit portion comprises a load transistor. The bias circuit portion comprises a replica transistor matched to the load transistor and connected to the load transistor at a node such that when a current flows through the replica transistor, a current proportional to the current through the replica transistor flows through the load transistor. The bias circuit portion also comprises a current input for receiving an input current, a supply voltage input for receiving a supply voltage, and a feedback loop arranged to: adjust a voltage at the node connecting the replica transistor and the load transistor such that the replica transistor conducts a current proportional to the input current, and counteract variations in the voltage at the node connecting the replica transistor and the load transistor arising from changes in the supply voltage.
H03K 3/353 - Générateurs caractérisés par le type de circuit ou par les moyens utilisés pour produire des impulsions par l'utilisation, comme éléments actifs, de transistors à effet de champ avec réaction positive interne ou externe
A microcontroller comprises a processor and a memory. The memory comprises a first-stage bootloader, a first second-stage bootloader, a second second-stage bootloader region, and an application region for storing an application. The processor is configured to execute instructions from the first-stage bootloader when the microcontroller is reset. The first-stage bootloader comprises instructions for transferring execution from the first-stage bootloader to the active second-stage bootloader, which comprises instructions for transferring execution to an address in the application region, and for causing the processor to write a replacement second-stage bootloader to whichever of the first and second second-stage bootloader regions is not the active region. The first-stage bootloader comprises instructions for detecting the replacement second-stage bootloader in whichever of the first and second second-stage bootloader regions is not the active region and for transferring execution to the replacement second-stage bootloader when the microcontroller is next reset.
A handshake circuit portion for performing a handshake procedure to facilitate data reception by an associated circuit portion is provided. The handshake circuit portion comprises a request signal input for detecting a request signal from a further handshake circuit portion associated with a further circuit portion, an acknowledge signal output for asserting an acknowledge signal for the further handshake circuit portion, and a blocking signal input for detecting a blocking signal from the associated circuit portion. The handshake circuit portion is arranged to detect a request signal via the request signal input, determine if a blocking signal is present on the blocking signal input, and if a blocking signal is not present on the blocking signal input, respond to the request signal by asserting an acknowledge signal via the acknowledge signal output.
G06F 21/85 - Protection des dispositifs de saisie, d’affichage de données ou d’interconnexion dispositifs d’interconnexion, p.ex. les dispositifs connectés à un bus ou les dispositifs en ligne
An integrated-circuit device comprising first and second radio systems. The first radio system comprises a first processor coupled to a first program memory and a first radio. The second radio system comprises a second processor coupled to a second program memory and a second radio. The device further comprises inter-processor communication (IPC) circuitry coupled to the first and second processors, for providing an IPC channel between the first and second processors. First software, stored in the first program memory for execution by the first processor comprises instructions for causing the first processor, in response to receiving a signal from the first radio, to send an electrical signal over the IPC channel to the second processor for causing second software stored in the second program memory to cause the second processor to send a command to the second radio.
According to an aspect, there are provided an apparatus and a method for providing an access to a memory circuit. A read enable input initializing a wait state counter configured to count a predetermined number of clock cycles is received (200) and the wait state counter output is monitored. A memory ready signal output is received (202) from the memory circuit at a synchronizer input and the output signal of the synchronizer is monitored. An ON-state data ready signal is provided (204) when either the wait state counter has elapsed, or the output signal of the synchronizer is in ON-state.
A microcontroller system comprising a master microcontroller unit, a further module and a general purpose input/output. In a first state the general purpose input/output is controlled by the master microcontroller unit and in a second state the general purpose input/output is controlled by the further module. The master microcontroller unit is arranged to transmit a selection signal which changes the state of the general purpose input/output.
A digital radio receiver receives an encoded digital radio signal comprising a plurality of bits. The receiver determines a plurality of soft bits representing estimates of the bits and stores the soft bits in a rate de-matching buffer. The receiver calculates a first linear combination of soft bits from a first subset of the buffer and a second linear combination of soft bits from a second subset of the buffer. The receiver calculates a ratio between the first and second linear combinations and compares the ratio to an expected value. The receiver then determines its operational state based on the comparison.
A device comprising: a transceiver operable in a first or second mode and configured to receive packets from a remote device, each packet comprising an indication of whether or not the remote device has a further packet to transmit, wherein: in the first mode the transceiver: (i) sends a polling message in response to receiving the indication of a further packet for transmission; and (ii) listens for that further packet; and in the second mode the transceiver: (i) does not send a polling message in response to receiving the indication of a further packet for transmission; and (ii) listens for packets regardless of whether a received packet indicates that there is a further packet to transmit or not; and a controller configured to monitor an activity level for the transceiver and cause the transceiver to operate in the first or second mode in dependence on the activity level.
A method of encoding a variable, which may have a plurality of different states, using an integrated circuit comprising a physical unclonable function module. The method comprises using the physical unclonable function module to generate a fingerprint value deterministically dependent on one or more physical fabrication properties of the integrated circuit; generating a first encoding value using the fingerprint value; generating a second encoding value using the fingerprint value; and encoding said variable using said encoding values.
H04L 9/32 - Dispositions pour les communications secrètes ou protégées; Protocoles réseaux de sécurité comprenant des moyens pour vérifier l'identité ou l'autorisation d'un utilisateur du système
A clock selector circuit includes a first input for receiving a reference clock signal having a reference frequency, a second input for receiving an offset clock signal having an offset frequency, a clock output for outputting the reference or offset clock signal, and switching circuitry. The switching circuitry includes a switching input and sign detector circuitry that outputs a sign signal indicating whether the reference clock signal is leading the offset clock signal in phase. In response to receiving a switching signal, the switching circuitry detects when like edges of the reference clock signal and the offset clock signal are aligned to within a predetermined tolerance, with the new signal leading the current signal if the offset frequency is lower than the reference frequency, or with the new clock signal trailing the current clock signal if not. In response, the switching circuitry switches to outputting the new clock signal.
H03K 5/135 - Dispositions ayant une sortie unique et transformant les signaux d'entrée en impulsions délivrées à des intervalles de temps désirés par l'utilisation de signaux de référence de temps, p.ex. des signaux d'horloge
G06F 1/08 - Générateurs d'horloge ayant une fréquence de base modifiable ou programmable
H03K 4/02 - Génération d'impulsions ayant comme caractéristique essentielle une pente définie ou des parties en gradins avec parties en gradins, p.ex. en forme d'escalier
77.
RADIO APPARATUS FOR COMMUNICATING DIGITAL AUDIO STREAMS
A radio receiver apparatus comprises radio circuitry for receiving a sequence of radio data packets, transmitted at regular intervals, wherein the sequence of radio data packets encodes a digital audio stream and each radio data packet encodes a respective number of audio samples from the digital audio stream. The apparatus also comprises a digital audio interface for outputting audio samples from the received digital audio stream, a controllable oscillator arranged to control an output rate at which the audio samples are output from the digital audio interface, and a timer. The apparatus also comprises control logic, configured to use the timer to measure an interval between receiving each of a pair of the radio data packets, and to control the oscillator to vary the output rate incrementally, in a number of steps, while outputting the audio samples from one radio data packet. The number of steps, or the size of each step, or both, depends on the measured interval.
This document discloses a power leakage sensor for a circuit, comprising: a power switch controller circuit coupled with at least one power switch for the digital circuit, the power switch controller configured to control the at least one power switch, to monitor power supply of the digital circuit, and to perform the following: a. in response to the detecting that the power supply to the circuit is powered on, output a power-off signal to the at least one power switch; and b. in response to the measured power supply metric falling below a threshold in response to the power-off signal, output a power-on signal to the at least one power switch. The power leakage sensor further comprises a frequency counter circuit configured to count a frequency of executing steps a. and b., the frequency indicating a proportion of power leakage in the digital circuit.
This document discloses a solution for controlling refreshing of memory resources of a dynamic random access memory. According to an aspect, there is disclosed an apparatus for a radio device, comprising: a dynamic random access memory circuit; a memory allocator configured to allocate memory resources from the dynamic random access memory circuit and to determine unallocated memory resources; a radio modem configured to communicate with the memory allocator in order to gain memory resources from the dynamic random access memory circuit; a memory refresh circuit configured to refresh the memory resources of the dynamic random access memory circuit; and a controller configured to determine, on the basis of a state change signal received from a radio modem of the radio device, that the radio modem is in an idle state and, in response to said determining, to control the memory refresh circuit to disable said refresh of the unallocated memory resources.
A radio system comprises a radio transmitter apparatus and a radio receiver apparatus. The radio transmitter apparatus is configured to transmit a continuous-wave radio-frequency signal having a first frequency. The radio receiver apparatus comprises: an antenna for receiving the continuous-wave radio-frequency signal; a local oscillator for generating a periodic signal at a second frequency which differs from the first frequency by a frequency offset; a mixer for mixing the received continuous-wave radio-frequency signal with the periodic signal to generate a down-mixed signal; and a processor or other circuitry configured to generate frequency-offset data from the down-mixed signal, wherein the frequency-offset data is representative of an estimate of the frequency offset. The processor or other circuitry is configured to use the frequency-offset data to generate DC-offset data representative of an estimate of a DC offset component of the down-mixed signal.
A local oscillator buffer circuit comprises a complementary common-source stage comprising a first p-channel transistor (MCSP) and a first n-channel transistor (MCSN), arranged such that their respective gate terminals are connected together at a first input node, and their respective drain terminals of each of is connected together at a buffer output node. A complementary source-follower stage comprises a second p-channel transistor (MSFP) and a second n-channel transistor (MSFN), arranged such that their respective gate terminals are connected together at a second input node, and their respective source terminals are connected together at the buffer output node.
H03B 5/24 - Elément déterminant la fréquence comportant résistance, et soit capacité, soit inductance, p.ex. oscillateur à glissement de phase l'élément actif de l'amplificateur étant un dispositif à semi-conducteurs
H04B 1/403 - Circuits utilisant le même oscillateur pour générer à la fois la fréquence de l’émetteur et la fréquence de l’oscillateur local du récepteur
H03F 3/30 - Amplificateurs push-pull à sortie unique; Déphaseurs pour ceux-ci
H03F 3/193 - Amplificateurs à haute fréquence, p.ex. amplificateurs radiofréquence comportant uniquement des dispositifs à semi-conducteurs comportant des dispositifs à effet de champ
82.
ANALYZING THE FREQUENCY STABILITY OF RADIO TRANSCEIVER APPARATUS
A method for analyzing a frequency stability of a radio transceiver device comprises receiving a first succession of unmodulated radio-frequency signals of different frequencies from a radio transceiver apparatus. For each unmodulated radio-frequency signal, a respective time series of phase-offset values is determined, each phase-offset value being representative of a difference between a phase of the respective received unmodulated radio-frequency signal and a phase of a respective reference signal. The time series of phase-offset values is processed to determine a respective signal-phase-offset value for each unmodulated radio-frequency signal. A frequency-stability value, representative of a frequency stability of the radio transceiver apparatus, is calculated as a function representative of statistical variation in the signal-phase-offset values determined for the first succession of unmodulated radio-frequency signals.
An apparatus has a radio for communicating with LTE networks using a first access technology and for communicating with LTE networks using a second access technology. The apparatus is configured to access an identity-data memory storing received identity data. The apparatus includes an access-technology-identification memory for storing access-technology identification information that identifies an access technology associated with identity data stored in the identity-data memory. The apparatus registers with an LTE cellular network, using a selected access technology. The apparatus processes the access-technology identification information to determine whether the identity data stored in the identity-data memory is associated with the selected access technology, and, when it is associated, sends the identity data to the LTE network.
A method for determining a distance between an initiator radio transceiver and a reflector radio transceiver is provided. The method comprises the initiator radio transceiver transmitting a first radio signal at a first transmission time and the reflector radio transceiver receiving the first radio signal at a first reception time. The reflector transceiver samples the first radio signal using a sampling clock signal having a sampling period and determines a first reception-time value at a temporal resolution that is finer than the sampling period, including a fractional component representative of a fraction of the sampling period. The reflector transceiver transmits a second radio signal at a second transmission time that is offset from the sampling clock signal by an amount that depends on said fractional component so as to provide a predetermined dwell time that is determined to an accuracy finer than the sampling period. The initiator radio transceiver receives the second radio signal at a second reception time and determines a distance value representative of a distance between the initiator radio transceiver and the reflector radio transceiver.
G01S 13/82 - Systèmes utilisant la reradiation d'ondes radio, p.ex. du type radar secondaire; Systèmes analogues dans lesquels des signaux de type continu sont transmis
G01S 5/02 - Localisation par coordination de plusieurs déterminations de direction ou de ligne de position; Localisation par coordination de plusieurs déterminations de distance utilisant les ondes radioélectriques
A method of determining a distance between a radio frequency device and a target is disclosed in which the radio frequency device receives a radio frequency signal from the target. The method comprises determining a time domain channel response from the received radio frequency signal, determining an amplitude of a largest peak in the time domain channel response, determining an amplitude of a second, earlier, peak in the time domain channel response, comparing the second peak amplitude to a threshold based on the largest peak amplitude, identifying the largest peak as a shortest path peak if the second peak amplitude is less than the threshold, identifying the second peak as a shortest path peak if the second peak amplitude is greater than the threshold, and calculating the distance between the radio frequency device and the target based on a time corresponding to the shortest path peak.
A method of digital radio communication between a first device and a second device is disclosed. An advertising packet is transmitted between first and second devices, wherein the packet includes a first address and a data portion. Additionally, an encryption key is transmitted between the devices. The first device generates a second address by encrypting an identity value derived from part of the first address using the encryption key and the data portion. The result is encrypted to generate second portion of the second address. The first device then transmits a connection request including the second address. The second device decrypts the second portion and uses the encryption key to determine correspondence with the first portion. If said correspondence is determined, the second device decrypts the first portion using at least the encryption key and compares it to an expected identity value derived from the first address.
H04W 12/0471 - Gestion des clés, p.ex. par architecture d’amorçage générique [GBA] sans l’utilisation d’un nœud de réseau fiable comme ancre de confiance Échange de clés
According to an aspect, there is provided a first radio device comprising means for performing the following. The first radio device transmits, using a connectionless mode, an advertising message. Subsequently, the first radio device receives, from a second radio device at a second reception time instance measured by the first radio device using the connectionless mode, a scan request. The first radio device transmits, to the second radio device, the scan response using the connectionless mode. Finally, the first radio device performs an auxiliary activity involving wireless communication between the first and second radio devices. The performing of the auxiliary activity is initiated at a first starting time defined to occur at a pre-defined time interval following an anchor point corresponding to the second reception time instance or to a subsequent timestamp generated in response to the receiving of the scan request at the second reception time instance.
A computer system configured to enable communication between two or more virtual platforms is disclosed. The computer system comprises a physical processor configured to run the two or more virtual platforms. The computer system further comprises a memory. The memory comprises one or more separate memory portions allocated to each of the two or more virtual platforms, wherein within at least one memory portion allocated to one of the virtual platform a predefined range of addresses is configured as a shared device memory, the shared device memory being accessible by all the virtual platforms. Firmware running on a first virtual platform is configured to transfer a data packet from the first virtual platform to one or more further virtual platforms via the shared device memory.
G06F 9/455 - Dispositions pour exécuter des programmes spécifiques Émulation; Interprétation; Simulation de logiciel, p.ex. virtualisation ou émulation des moteurs d’exécution d’applications ou de systèmes d’exploitation
G06F 12/02 - Adressage ou affectation; Réadressage
A circuit portion comprises a DCDC converter that is configured to charge and discharge an inductor according to a duty cycle to provide current to an output load. A duty module is configured to determine the duty cycle such that the DCDC converter will output a target current. A duty limiter module is configured to cause the inductor to discharge early if the determined duty cycle exceeds a threshold.
H02M 3/158 - Transformation d'une puissance d'entrée en courant continu en une puissance de sortie en courant continu sans transformation intermédiaire en courant alternatif par convertisseurs statiques utilisant des tubes à décharge avec électrode de commande ou des dispositifs à semi-conducteurs avec électrode de commande utilisant des dispositifs du type triode ou transistor exigeant l'application continue d'un signal de commande utilisant uniquement des dispositifs à semi-conducteurs avec commande automatique de la tension ou du courant de sortie, p.ex. régulateurs à commutation comprenant plusieurs dispositifs à semi-conducteurs comme dispositifs de commande finale pour une charge unique
H02M 1/00 - APPAREILS POUR LA TRANSFORMATION DE COURANT ALTERNATIF EN COURANT ALTERNATIF, DE COURANT ALTERNATIF EN COURANT CONTINU OU VICE VERSA OU DE COURANT CONTINU EN COURANT CONTINU ET EMPLOYÉS AVEC LES RÉSEAUX DE DISTRIBUTION D'ÉNERGIE OU DES SYSTÈMES D'ALI; TRANSFORMATION D'UNE PUISSANCE D'ENTRÉE EN COURANT CONTINU OU COURANT ALTERNATIF EN UNE PUISSANCE DE SORTIE DE CHOC; LEUR COMMANDE OU RÉGULATION - Détails d'appareils pour transformation
A circuit portion comprises a DCDC converter that provides current from an output to a plurality of loads. Channel logic circuitry is configured to provide current from the output of the converter to each load according to a cyclical sequence, wherein each cycle has a duration that is divided equally into a plurality of time slots. The channel logic circuitry is configured to provide current to each load for one or more discrete time slots. The number of time slots is greater than the number of loads so that at least two output loads receive current for different numbers of time slots in a cycle.
H02M 3/158 - Transformation d'une puissance d'entrée en courant continu en une puissance de sortie en courant continu sans transformation intermédiaire en courant alternatif par convertisseurs statiques utilisant des tubes à décharge avec électrode de commande ou des dispositifs à semi-conducteurs avec électrode de commande utilisant des dispositifs du type triode ou transistor exigeant l'application continue d'un signal de commande utilisant uniquement des dispositifs à semi-conducteurs avec commande automatique de la tension ou du courant de sortie, p.ex. régulateurs à commutation comprenant plusieurs dispositifs à semi-conducteurs comme dispositifs de commande finale pour une charge unique
H02M 1/00 - APPAREILS POUR LA TRANSFORMATION DE COURANT ALTERNATIF EN COURANT ALTERNATIF, DE COURANT ALTERNATIF EN COURANT CONTINU OU VICE VERSA OU DE COURANT CONTINU EN COURANT CONTINU ET EMPLOYÉS AVEC LES RÉSEAUX DE DISTRIBUTION D'ÉNERGIE OU DES SYSTÈMES D'ALI; TRANSFORMATION D'UNE PUISSANCE D'ENTRÉE EN COURANT CONTINU OU COURANT ALTERNATIF EN UNE PUISSANCE DE SORTIE DE CHOC; LEUR COMMANDE OU RÉGULATION - Détails d'appareils pour transformation
H02M 3/157 - Transformation d'une puissance d'entrée en courant continu en une puissance de sortie en courant continu sans transformation intermédiaire en courant alternatif par convertisseurs statiques utilisant des tubes à décharge avec électrode de commande ou des dispositifs à semi-conducteurs avec électrode de commande utilisant des dispositifs du type triode ou transistor exigeant l'application continue d'un signal de commande utilisant uniquement des dispositifs à semi-conducteurs avec commande automatique de la tension ou du courant de sortie, p.ex. régulateurs à commutation avec commande numérique
A radio device receives data from a base station that transmits a first radio signal, carrying a first data block, in a first time window, and a second radio signal, also carrying the first data block, in a different, second time window. The radio device comprises first and second antennas, receive circuitry, and a switch for selectively connecting the receive circuitry to the first antenna or to the second antenna. It is configured to sample the first radio signal, received by the first antenna in the first time window, to generate first sampled data; disconnect the first antenna from the receive circuitry and connect the second antenna; sample the second radio signal, received by the second antenna in the second time window, to generate second sampled data; and use both the first sampled data and the second sampled data to decode the first data block.
H04B 7/08 - Systèmes de diversité; Systèmes à plusieurs antennes, c. à d. émission ou réception utilisant plusieurs antennes utilisant plusieurs antennes indépendantes espacées à la station de réception
H04B 7/06 - Systèmes de diversité; Systèmes à plusieurs antennes, c. à d. émission ou réception utilisant plusieurs antennes utilisant plusieurs antennes indépendantes espacées à la station d'émission
H04L 1/00 - Dispositions pour détecter ou empêcher les erreurs dans l'information reçue
A radio device sends a random-access request message to a base station and receives a random-access response message from the base station. A plurality of data transport blocks are thereafter transmitted in a first direction between the radio device and the base station, but the radio device does not send a connection-setup complete message to the base station until all of the plurality of data transport blocks having been transmitted.
A low noise amplifier comprising a first transconductance amplifier arranged to receive an input voltage at its input terminal and to generate an output current at its output terminal. A second transconductance amplifier is arranged such that its input terminal is connected to the input terminal of the first transconductance amplifier, and such that the output terminal of the second transconductance amplifier is connected to the input terminal of the second transconductance amplifier via a capacitive feedback network (C1).
H03F 1/26 - Modifications des amplificateurs pour réduire l'influence du bruit provoqué par les éléments amplificateurs
H03F 1/22 - Modifications des amplificateurs pour réduire l'influence défavorable de l'impédance interne des éléments amplificateurs par utilisation de couplage dit "cascode", c. à d. étage avec cathode ou émetteur à la masse suivi d'un étage avec grille ou base à la masse respectivement
H03F 1/56 - Modifications des impédances d'entrée ou de sortie, non prévues ailleurs
A digital radio communication system comprises a central device and a peripheral device arranged to operate in accordance with a predetermined communication protocol. The central and peripheral devices are both arranged to: transmit data packets over a plurality of available radio channels having different frequencies; receive the data packets transmitted by the other respective device; and perform data integrity checks on the data packets received. At least one of the central and peripheral devices is arranged to assign a dynamic channel rating to one or more of said radio channels based on an outcome of at least some of the data integrity checks.
H04W 4/80 - Services utilisant la communication de courte portée, p.ex. la communication en champ proche, l'identification par radiofréquence ou la communication à faible consommation d’énergie
H04L 1/20 - Dispositions pour détecter ou empêcher les erreurs dans l'information reçue en utilisant un détecteur de la qualité du signal
A method of communication over a cellular telecommunications network using an electronic device comprises communicating a session control signal between the electronic device and the cellular telecommunications network on a first radio channel provided by the cellular telecommunications network. The session control signal comprises identification data that identifies a remote party. The cellular telecommunications network uses the identification data to establish an IP-based communication session with the remote party. Content data for the IP-based communication session is communicated between the electronic device and the cellular telecommunications network on a second radio channel provided by the cellular telecommunications network.
An integrated-circuit device comprises a source register in a reset domain, a destination circuit outside the reset domain, and a reset checking circuit. The checking circuit comprises a buffer outside the reset domain for receiving data values output by the source register, a reset detector, and reset checking logic. The checking logic detects a new data value output by the source register, checks whether a reset of the reset domain has been detected, and contingently outputs a control signal for controlling whether the destination circuit receives the new data value from the buffer. The reset detector signals whether a reset has been detected by using a feedback path to hold a predetermined value in a resettable latch until the latch receives a reset signal, and to hold a different value in the latch after receiving a reset signal.
An integrated circuit device has a processor, a software-trace message handling system, a software-trace message sink peripheral, and a hardware interconnect system. The interconnect system is capable of directing software-trace messages from the processor to the software-trace message handling system, and of directing software-trace messages from the processor to the software-trace message sink peripheral. The software-trace message sink peripheral can present an interconnect delay to the processor, when receiving a software-trace message from the processor, that is equal to or substantially equal to an interconnect delay that the software-trace message handling system would have presented to the processor if the software-trace message handling system were to have received the software-trace message.
G06F 1/3296 - Gestion de l’alimentation, c. à d. passage en mode d’économie d’énergie amorcé par événements Économie d’énergie caractérisée par l'action entreprise par diminution de la tension d’alimentation ou de la tension de fonctionnement
G06F 13/36 - Gestion de demandes d'interconnexion ou de transfert pour l'accès au bus ou au système à bus communs
A radio receiver of a radio communication system is configured to tune to a radio channel by generating a periodic signal, mixing the periodic signal with radio signals received from a radio transmission system and passing the mixed signal through a channel filter. The radio receiver receives, from the radio transmission system, an OFDM data signal modulated on a set of OFDM subcarriers within the tuned channel. The channel filter has a passband that is wider than the channel bandwidth of the tuned channel such that the filter passes i) said OFDM data signal, ii) an in-channel reference signal, and iii) an out-of-channel reference signal. The radio receiver comprises channel estimation logic configured to use both reference signals to calculate a channel estimate for an OFDM subcarrier within the tuned channel.
H03B 5/06 - Modifications du générateur pour assurer l'amorçage des oscillations
H03B 5/32 - Production d'oscillation au moyen d'un amplificateur comportant un circuit de réaction entre sa sortie et son entrée l'élément déterminant la fréquence étant un résonateur électromécanique un résonateur piézo-électrique
H03L 5/02 - Commande automatique de la tension, du courant ou de la puissance de la puissance
H03B 5/36 - Production d'oscillation au moyen d'un amplificateur comportant un circuit de réaction entre sa sortie et son entrée l'élément déterminant la fréquence étant un résonateur électromécanique un résonateur piézo-électrique l'élément actif de l'amplificateur comportant un dispositif semi-conducteur
An integrated-circuit device comprises first and second peripherals, connected to a processor via a bus system, a peripheral interconnect that is separate from the bus system, wake up logic, a configuration memory and a power controller. In response to a change of state, the first peripheral generates event signals that are output to the peripheral interconnect. The peripheral interconnect provides the event signal to the second peripheral, which initiates tasks in response. The first peripheral, second peripheral and the wake-up logic are in a first, second and third power domain respectively. The power controller provides power to the third power domain whenever the first or second power domain is powered up. The wake-up logic detects an event signal from the first peripheral and, if it determines that the second peripheral is configured to initiate a task in response, it instructs the power controller to power up the second peripheral.
brevets
