Abstract

The present invention relates to a processing apparatus (100) for processing component carrier structures (210). The processing apparatus (100) comprises a handler (110) configured for loading a component carrier structure (210), for supplying the component carrier structure (210) to a processing chamber (101), and for unloading the component carrier structure (210) after processing in the processing chamber (101); and the processing chamber (101) configured for processing the component carrier structure (210) and having an integrated dryer device (102) for drying the component carrier structure (210) before the handler (110) removes the component carrier structure (210) from the processing chamber (101).

IPC Classes  ?

• H05K 3/00 - Apparatus or processes for manufacturing printed circuits
• H05K 3/22 - Secondary treatment of printed circuits

Abstract

A method for a reliability assessment of an electronic component carrier or a package comprising an electronic component carrier (1). The method comprises: providing a global simulation model of the component carrier or package (1), wherein a predetermined number of geometric properties of the component carrier or package (1) and of its constituent parts made of different materials and of physical properties of materials used in said constituent parts are defined as independent variables in a parameter space of the global simulation model; and wherein the global simulation model is configured to receive input data including a point in the parameter space and is configured to output data indicative of resulting geometric and/or physical properties within a global volume of the resulting component carrier or package (1). The method comprises running a simulation of the global simulation model and identifying, in its output data, boundary conditions for a plurality of local sub-portions (2) of the component carrier or package (1). The method further comprises providing at least one data-based local model for said local sub- portions (2), each data-based local model being trained to receive said boundary conditions as input data and provide a criticality value indicative of a reliability of the respective local sub-portion (2) as output data; running the at least one local data-based model for each of said local sub-portions (2) and identifying, in the respective output data, those local sub-portions (2) whose criticality value is above at least one predetermined threshold.

IPC Classes  ?

• G06F 30/17 - Mechanical parametric or variational design
• G06F 30/23 - Design optimisation, verification or simulation using finite element methods [FEM] or finite difference methods [FDM]
• G06F 30/27 - Design optimisation, verification or simulation using machine learning, e.g. artificial intelligence, neural networks, support vector machines [SVM] or training a model
• G06F 119/02 - Reliability analysis or reliability optimisation; Failure analysis, e.g. worst case scenario performance, failure mode and effects analysis [FMEA]
• G06F 113/18 - Chip packaging
• G06F 115/12 - Printed circuit boards [PCB] or multi-chip modules [MCM]

Abstract

There is described a component carrier (100), wherein the component carrier (100) comprises: i) a stack (101) comprising at least one electrically conductive layer structure (104) and/or at least one electrically insulating layer structure (102), ii) an electronic component (110) embedded in the stack (101); and iii) a thermal structure (120), configured to dissipate thermal energy produced by the electronic component (110) towards and beyond a main surface (105) of the stack (101), wherein the thermal structure (120) comprises: iiia) a base structure (121) mounted on and/or at least partially embedded in the stack (101), in particular flush with one of the layer structures (102, 104) of the stack (101), and iiib) a plurality of protrusions (125), protruding from the base structure (121), and extending beyond the main surface (105) of the stack (101).

IPC Classes  ?

• H01L 23/367 - Cooling facilitated by shape of device
• H01L 23/433 - Auxiliary members characterised by their shape, e.g. pistons
• H05K 1/18 - Printed circuits structurally associated with non-printed electric components
• H05K 3/00 - Apparatus or processes for manufacturing printed circuits
• H01L 21/48 - Manufacture or treatment of parts, e.g. containers, prior to assembly of the devices, using processes not provided for in a single one of the groups
• H01L 23/13 - Mountings, e.g. non-detachable insulating substrates characterised by the shape
• H01L 23/498 - Leads on insulating substrates
• H01L 23/538 - Arrangements for conducting electric current within the device in operation from one component to another the interconnection structure between a plurality of semiconductor chips being formed on, or in, insulating substrates
• H01L 23/00 - SEMICONDUCTOR DEVICES NOT COVERED BY CLASS - Details of semiconductor or other solid state devices

Abstract

An electronic device (100) which comprises a three-dimensionally non-planar mold body (102) defining at least part of one of a non-planar side surface (104) and an opposed non-planar side surface (106) of the electronic device (100), an electrically conductive structure (114) provided on one of said non-planar side surface (104) and said opposing non-planar side surface (106), and at least one electric entity (108) at least partially inside of the three-dimensionally non-planar mold body (102).

IPC Classes  ?

• H01L 23/00 - SEMICONDUCTOR DEVICES NOT COVERED BY CLASS - Details of semiconductor or other solid state devices
• H05K 5/06 - Hermetically-sealed casings
• H01L 21/56 - Encapsulations, e.g. encapsulating layers, coatings

Abstract

A package includes a component carrier having a stack with at least one electrically conductive layer structure and/or at least one electrically insulating layer structure, a cavity in the stack, an active electronic component in the cavity, and a functional filling medium filling at least part of the cavity. The functional filling medium extends to an external surface of the stack for defining an output surface and configured to transmit at least one output of the active electronic component toward the output surface.

IPC Classes  ?

• H01L 23/552 - Protection against radiation, e.g. light
• H01L 21/48 - Manufacture or treatment of parts, e.g. containers, prior to assembly of the devices, using processes not provided for in a single one of the groups
• H01L 21/56 - Encapsulations, e.g. encapsulating layers, coatings
• H01L 23/00 - SEMICONDUCTOR DEVICES NOT COVERED BY CLASS - Details of semiconductor or other solid state devices
• H01L 23/29 - Encapsulation, e.g. encapsulating layers, coatings characterised by the material
• H01L 23/31 - Encapsulation, e.g. encapsulating layers, coatings characterised by the arrangement
• H01L 23/367 - Cooling facilitated by shape of device
• H01L 23/498 - Leads on insulating substrates

Abstract

The present invention relates to a packing apparatus (100), a method of automatically packing component carriers (201) in a packing apparatus (100), a component carrier pack and a system. The packing apparatus (100) comprises a gating arrangement (110) configured for allowing only component carriers (201) to proceed with packing which meet at least one predefined gating criterion; a tracing arrangement (120) configured for tracing the component carriers (201) during processing by the packing apparatus (100); and a packing unit (130) for packing the traced component carriers (201), which meet the at least one predefined gating criterion, to a component carrier pack (102).

IPC Classes  ?

• G05B 19/418 - Total factory control, i.e. centrally controlling a plurality of machines, e.g. direct or distributed numerical control (DNC), flexible manufacturing systems (FMS), integrated manufacturing systems (IMS), computer integrated manufacturing (CIM)

Abstract

There is described an integrated circuit, IC, substrate (100), comprising: i) a reinforced fiber-free dielectric material (110); ii) a bridge element (120) comprising: iia) at least two electrically conductive terminals (121a, 121b), iib) an electrical interconnection (125) that electrically interconnects the at least two electrically conductive terminals (121a, 121b), and iic) a dielectric protection material (122) that encapsulates the electrical interconnection (125), wherein the bridge element (120) is embedded in the reinforced fiber-free dielectric material (110), so that at least two components (140a, 140b), when surface mounted to a first main surface (101) of the IC substrate (100), are electrically connected to the at least two electrically conductive terminals (121a, 121b), respectively; and iii) a redistribution layer, RDL, structure (130), arranged at a second main surface (102) of the IC substrate (100) being opposite to the first main surface (101), and electrically connectable by further electrical interconnections (105) to the at least two components (140a, 140b).

IPC Classes  ?

• H01L 23/538 - Arrangements for conducting electric current within the device in operation from one component to another the interconnection structure between a plurality of semiconductor chips being formed on, or in, insulating substrates
• H05K 3/46 - Manufacturing multi-layer circuits

Abstract

An electronic device includes a component carrier having a stack with at least one electrically conductive layer structure and/or at least one electrically insulating layer structure, an electronic component on and/or in the stack, and a cooling member with a fluid cooling unit at least partially therein. The component carrier and the cooling member are connected by a connection structure. The connection structure comprises thermal interface material which contributes to a heat removal from the electronic component to the cooling unit.

IPC Classes  ?

• H05K 7/20 - Modifications to facilitate cooling, ventilating, or heating

Abstract

There is described a method of processing a metal-containing fluid (101), the method comprising: i) providing the metal-containing fluid (101) that comprises at least one metal in a first oxidation state; ii) performing a membrane electrolysis (110), thereby oxidizing the metal from the first oxidation state to a second oxidation state to obtain an oxidized metal-containing fluid (102); and thereafter iii) streaming the oxidized metal-containing fluid (102) through an ion exchange device (120), thereby separating the metal in the second oxidation state from the oxidized metal-containing fluid (102) to obtain a processed metal-containing fluid (105).

IPC Classes  ?

• C02F 1/42 - Treatment of water, waste water, or sewage by ion-exchange
• C02F 1/467 - Treatment of water, waste water, or sewage by electrochemical methods by electrolysis by electrochemical disinfection
• C22B 3/42 - Treatment or purification of solutions, e.g. obtained by leaching by ion-exchange extraction
• C25C 1/06 - Electrolytic production, recovery or refining of metals by electrolysis of solutions of iron group metals, refractory metals or manganese
• C02F 101/20 - Heavy metals or heavy metal compounds
• C02F 101/22 - Chromium or chromium compounds, e.g. chromates
• C02F 103/16 - Nature of the water, waste water, sewage or sludge to be treated from metallurgical processes, i.e. from the production, refining or treatment of metals, e.g. galvanic wastes

Abstract

A component carrier includes: i) a first layer stack (comprising at least one first electrically conductive layer structure and/or at least one first electrically insulating layer structure, ii) a component embedded in the first layer stack, where a main surface of the component is essentially flush with an outer main surface of the first layer stack iii) a second layer stack comprising at least one second electrically conductive layer structure and/or at least one second electrically insulating layer structure, and iv) a thermally conductive block embedded in the second layer stack. The layer stacks are connected with each other so that a thermal path from the embedded component via the thermally conductive block up to an exterior surface of the component carrier has a minimum thermal conductivity of at least 7 W/mK, in particular at least 40 W/mK. Further, a method of manufacturing the component carrier is described.

IPC Classes  ?

• H05K 1/02 - Printed circuits - Details
• H05K 1/18 - Printed circuits structurally associated with non-printed electric components
• H05K 3/30 - Assembling printed circuits with electric components, e.g. with resistor

Abstract

The invention relates to a method for estimating a conversion degree value (α) of a polymeric material, wherein the method comprises the steps of: heating the polymeric material with a predetermined heating rate (β); acquisition of at least one first measured value from the polymeric material at a current temperature (T), the first measured value relating to a specific kind of the conversion degree; determination of a fixed value (QI) associated with the reciprocal temperature (1/T) and the heating rate (β), the fixed value (QI) being independent from the conversion degree value (α) of said polymeric material; and estimation of the conversion degree value (α) of the polymeric material based on the first measured value and the fixed value (QI).

IPC Classes  ?

• G01N 25/48 - Investigating or analysing materials by the use of thermal means by investigating the development of heat, i.e. calorimetry, e.g. by measuring specific heat, by measuring thermal conductivity on solution, sorption, or a chemical reaction not involving combustion or catalytic oxidation
• G01N 33/44 - Resins; Plastics; Rubber; Leather

Abstract

The invention relates to a method for estimating a viscosity curve of a polymeric material, the method comprising: acquiring viscosity values of the polymeric material at different temperatures (T) under different heating rates (0); determining at least one viscosity curve of the polymeric material depending on the measured viscosities for each heating rate (0); splitting the viscosity curves into at least one determined melting curve and at least one determined curing curve per determined viscosity curve; determining at least one fitted melting curve per determined melting curve; determining at least one fitted curing curve per determined curing curve; and estimating the viscosity curve of the polymeric material by combining the fitted melting curve and the fitted curing curve.

IPC Classes  ?

• G01N 11/00 - Investigating flow properties of materials, e.g. viscosity or plasticity; Analysing materials by determining flow properties
• G01N 33/44 - Resins; Plastics; Rubber; Leather

Abstract

The invention relates to a method for estimating a conversion degree value (α) of a polymeric material, wherein the method comprises the steps of: heating the polymeric material with a predetermined heating rate (β); acquisition of at least one first measured value from the polymeric material at a current temperature (T), the first measured value relating to a specific kind of the conversion degree; determination of a fixed value (QI) associated with the reciprocal temperature (1/T) and the heating rate (β), the fixed value (QI) being independent from the conversion degree value (α) of said polymeric material; and estimation of the conversion degree value (α) of the polymeric material based on the first measured value and the fixed value (QI).

IPC Classes  ?

• G01N 25/48 - Investigating or analysing materials by the use of thermal means by investigating the development of heat, i.e. calorimetry, e.g. by measuring specific heat, by measuring thermal conductivity on solution, sorption, or a chemical reaction not involving combustion or catalytic oxidation
• G01N 33/44 - Resins; Plastics; Rubber; Leather

Abstract

The invention relates to a method to define a production and/or application and/or use of a polymeric material, comprising the steps of: estimation of a convention degree value (α) of the polymeric material based on at least one first measured value from the polymeric material relating to the kind of conversion degree and based on a fixed value (QI) associated with a respective reciprocal temperature (1/T) and a heating rate (β) of the specific polymeric material, the fixed value (QI) being independent from the conversion degree value (α) of the polymeric material, and definition of the production and/or the application and/or the use of the polymeric material use based on the estimated conversion degree value (α).

IPC Classes  ?

• G16C 60/00 - Computational materials science, i.e. ICT specially adapted for investigating the physical or chemical properties of materials or phenomena associated with their design, synthesis, processing, characterisation or utilisation

Abstract

There is described a method of manufacturing component carriers in a component carrier manufacture plant (100), the method comprising: i) providing a process fluid (101) to a component carrier manufacture process (HO); ii) manufacturing the component carriers (110), thereby producing a heavy metal waste fluid (102); and iii) processing the heavy metal waste fluid (102) by at least one treatment step to a) obtain a processed fluid (101, 105) with drinking water quality and/or b) stream the processed fluid (105) as the process fluid (101) back to the component carrier manufacture process (100), thereby providing a closed process water cycle.

IPC Classes  ?

• C02F 9/00 - Multistage treatment of water, waste water or sewage
• C02F 1/28 - Treatment of water, waste water, or sewage by sorption
• C02F 1/42 - Treatment of water, waste water, or sewage by ion-exchange
• C02F 1/68 - Treatment of water, waste water, or sewage by addition of specified substances, e.g. trace elements, for ameliorating potable water
• C02F 101/20 - Heavy metals or heavy metal compounds
• C02F 103/16 - Nature of the water, waste water, sewage or sludge to be treated from metallurgical processes, i.e. from the production, refining or treatment of metals, e.g. galvanic wastes
• C02F 103/34 - Nature of the water, waste water, sewage or sludge to be treated from the chemical industry not provided for in groups

Abstract

A carrier assembly (100) is provided, which comprises (i) a component carrier (101); (ii) a component (110) in or on the component carrier (101); (iii) a signal conductive element (120) provided on a component surface (111) of said component (110); and (iv) a shielding conductive structure 130, which is at least partially embedded in the component carrier (101) and which at least partially surrounds said signal conductive element (120).

IPC Classes  ?

• H05K 1/02 - Printed circuits - Details
• H05K 1/11 - Printed elements for providing electric connections to or between printed circuits
• H05K 1/18 - Printed circuits structurally associated with non-printed electric components

Abstract

There is described a component carrier (100), comprising: i) a stack (101) comprising at least one electrically insulating layer structure (102) and/or at least one electrically conductive layer structure (104); ii) a cavity (120), at least partially provided in the stack (101) and delimited by a plurality of sidewalls (121), iii) a metallic shielding structure (125) in the cavity (120), wherein the metallic shielding structure (125) at least partially covers the plurality of sidewalls (121); and iv) a dielectric element (150) arranged in the cavity (120), wherein the dielectric element (150) comprises a material having a dielectric constant, Dk, of two or more.

IPC Classes  ?

• H01P 3/06 - Coaxial lines
• H01P 3/12 - Hollow waveguides
• H01P 3/16 - Dielectric waveguides, i.e. without a longitudinal conductor

Abstract

An electronic package having a base structure; a layer stack formed over the base structure; and a component embedded at least partially within the base structure and/or within the layer stack. The layer stack has a decoupling layer structure, the decoupling layer structure with a decoupling material having a Young Modulus being smaller than 1 GPa.

IPC Classes  ?

• H01L 23/373 - Cooling facilitated by selection of materials for the device
• H01L 23/492 - Bases or plates
• H01L 23/00 - SEMICONDUCTOR DEVICES NOT COVERED BY CLASS - Details of semiconductor or other solid state devices
• H01L 21/56 - Encapsulations, e.g. encapsulating layers, coatings

Abstract

A component carrier (100) which comprises a stack (102) comprising at least one electrically conductive layer structure (104) and at least one electrically insulating layer structure (106), wherein the at least one electrically insulating layer structure (106) comprises at least one design layer structure (108, 110) having a stamped surface profile, and a component (112) being embedded in the stack (102) and being at least partially covered by the at least one design layer structure (108, 110).

IPC Classes  ?

• H05K 1/18 - Printed circuits structurally associated with non-printed electric components
• H05K 3/46 - Manufacturing multi-layer circuits

Abstract

A package (100), wherein the package (100) comprises a component carrier (102) comprising at least one electrically conductive layer structure (104) and/or at least one electrically insulating layer structure (106), and an optical chip (108) and an electric chip (110) being functionally coupled with each other and being embedded side-by-side in the component carrier (102) so that a signal path (112) between the optical chip (108) and the electric chip (110) is within a horizontal plane.

IPC Classes  ?

• G02B 6/42 - Coupling light guides with opto-electronic elements
• H01L 21/56 - Encapsulations, e.g. encapsulating layers, coatings
• H01L 23/16 - Fillings or auxiliary members in containers, e.g. centering rings
• H01L 23/31 - Encapsulation, e.g. encapsulating layers, coatings characterised by the arrangement
• H01L 25/16 - Assemblies consisting of a plurality of individual semiconductor or other solid state devices the devices being of types provided for in two or more different main groups of groups , or in a single subclass of , , e.g. forming hybrid circuits

Abstract

A component carrier which includes a stack having at least one electrically conductive layer structure and/or at least one electrically insulating layer structure, a first electronic component and a second electronic component arranged in the stack, a first block and a second block arranged in the stack below the first electronic component and the second electronic component, and a third block and a fourth block arranged in the stack above the first electronic component and the second electronic component, wherein said blocks are thermally conductive.

IPC Classes  ?

• H01L 23/538 - Arrangements for conducting electric current within the device in operation from one component to another the interconnection structure between a plurality of semiconductor chips being formed on, or in, insulating substrates
• H01L 23/00 - SEMICONDUCTOR DEVICES NOT COVERED BY CLASS - Details of semiconductor or other solid state devices
• H01L 25/07 - Assemblies consisting of a plurality of individual semiconductor or other solid state devices all the devices being of a type provided for in the same subgroup of groups , or in a single subclass of , , e.g. assemblies of rectifier diodes the devices not having separate containers the devices being of a type provided for in group
• H01L 25/00 - Assemblies consisting of a plurality of individual semiconductor or other solid state devices
• H01L 23/373 - Cooling facilitated by selection of materials for the device

Abstract

The invention provides a package (100) with a component carrier, an interposer and a component and a method of manufacturing the same, the package (100) which comprises a component carrier (102), an interposer (104) arranged on the component carrier (102) and having a laminated interposer stack comprising electrically conductive vertical through connections (108) and electrically conductive horizontal structures (110) in a dielectric matrix (112), and at least one component (114) arranged on the interposer (104), wherein at least one of the component carrier (102) and the at least one component (114) is directly connected to exposed horizontal structures (110) of the interposer (104).

IPC Classes  ?

• H01L 21/48 - Manufacture or treatment of parts, e.g. containers, prior to assembly of the devices, using processes not provided for in a single one of the groups
• H01L 23/538 - Arrangements for conducting electric current within the device in operation from one component to another the interconnection structure between a plurality of semiconductor chips being formed on, or in, insulating substrates
• H01L 25/065 - Assemblies consisting of a plurality of individual semiconductor or other solid state devices all the devices being of a type provided for in the same subgroup of groups , or in a single subclass of , , e.g. assemblies of rectifier diodes the devices not having separate containers the devices being of a type provided for in group
• H01L 21/683 - Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components for supporting or gripping
• H01L 23/31 - Encapsulation, e.g. encapsulating layers, coatings characterised by the arrangement
• H01L 23/498 - Leads on insulating substrates

Abstract

The disclosure relates to a device and a computer implemented method for identifying a contaminant in a printed circuit board (PCB) production line using an elemental analysis technique, preferably energy-dispersive X-ray spectroscopy (EDX) by comparing the elemental composition and carbon-oxygen ratio of the contaminant to the elemental composition and carbon-oxygen ratios of reference samples. In the comparison, the elemental composition is expressed as a first and a second value and the ratio of carbon-oxygen ratios as a third value. The method also comprises calculating a similarity score between the contaminant and each of the reference samples based on the first, second and third values. The aim is to trace the source of contamination in the production line and to take corrective action.

IPC Classes  ?

• G16C 20/20 - Identification of molecular entities, parts thereof or of chemical compositions

Abstract

A component carrier which includes a stack having at least one electrically conductive layer structure, at least one electrically insulating layer structure, and a recess being at least partially formed in the stack, optionally having an electrically conductive coating, and being configured as waveguide, wherein a plurality of edges delimiting the recess are formed by electrically conductive material of the at least one electrically conductive layer structure and/or of the optional electrically conductive coating.

IPC Classes  ?

• H05K 1/02 - Printed circuits - Details
• H05K 3/46 - Manufacturing multi-layer circuits

Abstract

The present application provides a package (100) and its manufacturing method. The package (100) comprises a core (102) having at least one through hole (104) delimited by a wall surface which is at least partially covered with at least one electrically conductive plating material (106), a first layer stack (108) on one main surface of the core (102), and a second layer stack (110) on an opposing other main surface of the core (102), wherein the first layer stack (108) has electrically conductive elements (112) with a higher integration density than further electrically conductive elements (114) with a lower integration density of the second layer stack (110), and wherein the further electrically conductive elements (114) comprise at least one cylindrical vertical electrically conductive connection element (116) for contributing to the formation of an electrically conductive connection interface (118) at a main surface of the second layer stack (110) facing away from the core (102).

IPC Classes  ?

• H01L 21/48 - Manufacture or treatment of parts, e.g. containers, prior to assembly of the devices, using processes not provided for in a single one of the groups
• H01L 21/683 - Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components for supporting or gripping
• H01L 23/498 - Leads on insulating substrates
• H01L 23/538 - Arrangements for conducting electric current within the device in operation from one component to another the interconnection structure between a plurality of semiconductor chips being formed on, or in, insulating substrates

Abstract

A component carrier includes a stack having at least one electrically conductive layer structure and at least one electrically insulating layer structure. At least one of the at least one electrically insulating layer structure(s) has at least partly tapered through holes filled substantially completely with an electrically conductive filling. The at least one electrically conductive layer structure and the electrically conductive filling are made of the same material. Different ones of the through holes of one electrically insulating layer structure are tapering in opposite directions.

IPC Classes  ?

• H01L 23/48 - Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads or terminal arrangements
• H01L 23/00 - SEMICONDUCTOR DEVICES NOT COVERED BY CLASS - Details of semiconductor or other solid state devices

Abstract

It is described a component carrier (100), wherein the component carrier (100) comprises: i) a stack (101) comprising at least one electrically conductive layer structure (104) and/or at least one electrically insulating layer structure (102); ii) a first electronic switch component (110) and a second electronic switch component (120) embedded side-by-side in the stack (101); and iii) a capacitor device (130), electrically connected in parallel to the first electronic switch component (110) and the second electronic switch component (120); wherein the capacitor device (130) is assembled, in particular surface-mounted, to the stack (101), so that the first electronic switch component (110) and the second electronic switch component (120) are at least partially arranged below the capacitor device (130) in a direction (z) perpendicular to the directions of main extension (x, y) of the component carrier (100).

IPC Classes  ?

• H05K 1/18 - Printed circuits structurally associated with non-printed electric components
• H05K 1/02 - Printed circuits - Details
• H05K 1/11 - Printed elements for providing electric connections to or between printed circuits

Abstract

A package (100) which comprises an inorganic core (102) having at least one through hole (104), and at least one organic board (108) comprising an at least partially organic dielectric matrix (106) and at least one electrically conductive vertical through connection (110) extending vertically through the at least partially organic dielectric matrix (106), wherein the at least one organic board (108) is at least partially embedded in the at least one through hole (104), and wherein an electric connection between a top side and a bottom side of the inorganic core (102) is established by the at least one vertical through connection (110).

IPC Classes  ?

• H01L 23/538 - Arrangements for conducting electric current within the device in operation from one component to another the interconnection structure between a plurality of semiconductor chips being formed on, or in, insulating substrates
• H05K 3/00 - Apparatus or processes for manufacturing printed circuits

Abstract

There is described a radio frequency, RF, module (100), comprising: i) a stack (101) comprising at least one electrically conductive layer structure (104) and/or at least one electrically insulating layer structure (102); and ii) a RF front-end functionality (115) that is integrated in the stack (101). Further, an RF arrangement, a manufacture method and a use are described.

IPC Classes  ?

• H05K 1/02 - Printed circuits - Details
• H05K 1/03 - Use of materials for the substrate
• H05K 1/18 - Printed circuits structurally associated with non-printed electric components
• H05K 3/46 - Manufacturing multi-layer circuits

Abstract

There is described a component carrier (100), comprising: i) a stack (101) comprising at least one electrically insulating layer structure (102) and/or at least one electrically conductive layer structure (104); ii) at least one signal element (150), wherein the signal element (150) protrudes from the outermost layer structure (102, 104) of the stack (101); and iii) a surrounding material (140) arranged on the outermost layer structure (102, 104) of the stack (101) and at least partially surrounding the at least one signal element (150). The signal element (150) comprises a dielectric material and comprises a permittivity that is different, in particular higher, than a permittivity of a medium that directly surrounds the at least one signal element (150).

IPC Classes  ?

• H01Q 9/04 - Resonant antennas
• H01Q 21/06 - Arrays of individually energised antenna units similarly polarised and spaced apart

Abstract

A component carrier includes a stack with at least one electrically insulating layer structure and/or at least one electrically conductive layer structure, and a component having one or more pads and at least one dielectric layer on at least one main surface of the component. The at least one dielectric layer does not extend beyond the main surface in a lateral direction. The dielectric layer at least partially covers one or more pads of the component. In addition, at least one electrically conductive contact extends through at least one opening in the dielectric layer up to at least one of the pads.

IPC Classes  ?

• H01L 23/538 - Arrangements for conducting electric current within the device in operation from one component to another the interconnection structure between a plurality of semiconductor chips being formed on, or in, insulating substrates
• H01L 23/31 - Encapsulation, e.g. encapsulating layers, coatings characterised by the arrangement
• H01L 23/373 - Cooling facilitated by selection of materials for the device
• H01L 23/00 - SEMICONDUCTOR DEVICES NOT COVERED BY CLASS - Details of semiconductor or other solid state devices
• H01L 21/48 - Manufacture or treatment of parts, e.g. containers, prior to assembly of the devices, using processes not provided for in a single one of the groups
• H01L 21/56 - Encapsulations, e.g. encapsulating layers, coatings

Abstract

A package (100) which comprises an integrated circuit substrate (102) having an exposed substrate pad (104) and having an exposed substrate dielectric (106), and an electronic component (108) having an integrated circuit (136), having an exposed component pad (110) and having an exposed component dielectric (112), wherein the integrated circuit substrate (102) is connected with the electronic component (108) so that there is a direct physical contact between the substrate pad (104) and the component pad (110) and so that there is a direct physical contact between the substrate dielectric (106) and the component dielectric (112).

IPC Classes  ?

• H01L 23/485 - Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads or terminal arrangements consisting of lead-in layers inseparably applied to the semiconductor body consisting of layered constructions comprising conductive layers and insulating layers, e.g. planar contacts
• H01L 23/498 - Leads on insulating substrates
• H01L 21/60 - Attaching leads or other conductive members, to be used for carrying current to or from the device in operation

Abstract

An integrated circuit substrate (100) for surface mounting an integrated circuit component (102) thereon, wherein the integrated circuit substrate (100) comprises a support structure (104) having at least one hole, and at least two functional inlays (108) placed inside said at least one hole side by side, wherein a pitch (D) at an integrated circuit component mounting side (140) of the integrated circuit substrate (100) is not more than 150 μm.

IPC Classes  ?

• H01L 21/48 - Manufacture or treatment of parts, e.g. containers, prior to assembly of the devices, using processes not provided for in a single one of the groups
• H01L 23/498 - Leads on insulating substrates
• H05K 1/18 - Printed circuits structurally associated with non-printed electric components

Abstract

An integrated circuit substrate (100) for surface mounting an integrated circuit component (102) thereon, wherein the integrated circuit substrate (100) comprises a central section (104), and at least two vertically stacked functional volume sections (106) in the central section (104), wherein a pitch (D) at an integrated circuit component mounting side (108) of the integrated circuit substrate (100) is not more than 150 μm.

IPC Classes  ?

• H01L 23/498 - Leads on insulating substrates

Abstract

The present invention provides a component carrier (1) comprising a stack (2) comprising at least one electrically conductive layer structure (3) and at least one electrically insulating layer structure (4); a first component (5) embedded in the stack (2); a second component (6) mounted on the first component (5) and in a cavity (7) which is delimited by an interface surface (8) of the stack (2); and an electrically insulating filling (9) which at least partially fills the cavity (7) and extends up to the interface surface (8) and thereby forms an interface with at least one of the at least one electrically insulating layer structure (4).

IPC Classes  ?

• H01L 23/538 - Arrangements for conducting electric current within the device in operation from one component to another the interconnection structure between a plurality of semiconductor chips being formed on, or in, insulating substrates

Abstract

There is described a component carrier (100) comprising: i) a stack (110) comprising at least one electrically insulating layer structure (102) and at least one electrically conductive layer structure (104); ii) a cavity (120) formed in the stack (110); iii) an electrically insulating material layer (130) arranged in the stack (110), at least partially defining the bottom of the cavity (120); and iv) a metal layer (140) arranged in the stack (110) below the electrically insulating material layer (130); The bottom of the cavity (120) comprises a bottom surface encircled by the sidewalls (121) of the cavity (120), and a peripheral recess (131) is formed on the bottom of the cavity (120).

IPC Classes  ?

• H05K 3/46 - Manufacturing multi-layer circuits
• H05K 3/00 - Apparatus or processes for manufacturing printed circuits
• H05K 1/14 - Structural association of two or more printed circuits
• H05K 1/02 - Printed circuits - Details
• H05K 1/18 - Printed circuits structurally associated with non-printed electric components

Abstract

It is described a method of manufacturing a component carrier, the method comprising: i) providing a component carrier (100) with at least one electrically insulating layer structure and/or at least one electrically conductive layer structure; ii) forming a protection layer (150) on the component carrier (100), so that a first portion (130) of the surface of the component carrier (100) is covered with the protection layer (150), and a second portion (140) of the surface of the component carrier (100) is not covered with the protection layer (150); iii) performing a component carrier manufacture step with respect to the second portion (140); and afterwards iv) removing the protection layer (150) from the first portion (130) using a pressurized fluid.

IPC Classes  ?

• H05K 3/00 - Apparatus or processes for manufacturing printed circuits
• H05K 3/28 - Applying non-metallic protective coatings

Abstract

Described herein is a component carrier, wherein the component carrier comprises a stack comprising a plurality of electrically conductive layer structures and at least one electrically insulating layer structure, wherein a first of said electrically conductive layer structures comprises a first surface where a first plurality of conductive nanowires is connected and a second of said electrically conductive layer structures comprises a second surface where a second plurality of conductive nanowires is connected, wherein said first and second surfaces and said first and second pluralities of nanowires are configured to at least partially connect the nanowires of the first plurality of nanowires with the respective nanowires of the second plurality of nanowires.

IPC Classes  ?

• H05K 3/46 - Manufacturing multi-layer circuits
• H05K 1/02 - Printed circuits - Details

Abstract

It is described a component carrier (100) comprising: i) a stack comprising at least one electrically insulating layer structure (102) and at least one electrically conductive layer structure (104); ii) a first metal trace (110) comprising a rough surface (111); and iii) a second metal trace (120) arranged adjacent to the first metal trace (110), comprising a smooth surface (121). The component carrier (100) is configured to guide high-frequency, HF, and or high speed signals through the second metal trace (120).

IPC Classes  ?

• H05K 1/02 - Printed circuits - Details
• H05K 3/38 - Improvement of the adhesion between the insulating substrate and the metal
• H05K 3/10 - Apparatus or processes for manufacturing printed circuits in which conductive material is applied to the insulating support in such a manner as to form the desired conductive pattern
• H05K 3/28 - Applying non-metallic protective coatings

Abstract

A component carrier includes a laminated stack having electrically insulating layer structures and electrically conductive layer structures; and an electrically insulating cap structure selectively covering an optical waveguide at an exterior surface of the laminated stack. A method for manufacturing a component carrier is also disclosed.

IPC Classes  ?

• G02B 6/42 - Coupling light guides with opto-electronic elements

Abstract

Described herein are a component carrier, wherein the component carrier comprises: a stack comprising a plurality of electrically conductive layer structures and at least one electrically insulating layer structure, wherein at least two of said electrically conductive layer structures are connected through a plurality of (electrical) conductive nanowires.

IPC Classes  ?

• H05K 1/11 - Printed elements for providing electric connections to or between printed circuits
• H05K 1/18 - Printed circuits structurally associated with non-printed electric components

Abstract

A carrier assembly may include a first carrier sub-assembly, said first carrier sub-assembly having an elongated shape and comprising at least one electrically conductive layer structure and at least one electrically insulating layer structure, said at least one electrically conductive layer structure extending up to a first area provided on one of two extremities of the elongated shape, wherein a first plurality of conductive nanowires is provided on said first area, and a second carrier sub-assembly, said second carrier sub-assembly comprising at least one electrically conductive layer structure and at least one electrically insulating layer structure, said at least one electrically conductive layer structure comprising a second area, wherein a second plurality of conductive nanowires is provided on that second area.

IPC Classes  ?

• H05K 1/02 - Printed circuits - Details
• H05K 1/14 - Structural association of two or more printed circuits
• H05K 3/46 - Manufacturing multi-layer circuits

Abstract

An inlay for a component carrier includes a gas-permeable porous layer structure, an upper layer structure, arranged on the gas-permeable porous layer structure, the upper layer structure defining a cavity such that a portion of the gas-permeable porous layer structure is exposed and an upper metal layer structure arranged on the upper layer structure. A component carrier with the inlay and manufacturing methods of the inlay and the component carrier are described.

IPC Classes  ?

• H05K 1/18 - Printed circuits structurally associated with non-printed electric components
• H05K 1/03 - Use of materials for the substrate
• H05K 1/02 - Printed circuits - Details
• H05K 3/46 - Manufacturing multi-layer circuits
• H05K 3/00 - Apparatus or processes for manufacturing printed circuits

Abstract

An inductor inlay, a component carrier, and methods for manufacturing the inductor inlay and the component carrier. The inductor inlay has a magnetic layer stack of interconnected magnetic layers and an electrically conductive structure embedded in the magnetic stack. The electrically conductive structure is configured as an inductor element with a coil-like shape. A component carrier includes a stack with at least one electrically conductive layer structure and at least one electrically insulating layer structure and the inductor inlay with the magnetic layer stack with interconnected magnetic layers and the electrically conductive structure embedded in the magnetic layer stack. Methods for manufacturing the inductor inlay and component carrier are further described.

IPC Classes  ?

• H01F 27/29 - Terminals; Tapping arrangements
• H01F 17/00 - Fixed inductances of the signal type

Abstract

A component carrier includes a stack with electrically conductive layer structures, at least one electrically insulating layer structure, and a magnetic inlay embedded in the stack. The electrically conductive layer structures form at least part of an electrically conductive coil structure surrounding at least part of the magnetic inlay. The coil structure includes at least one vertical segment with at least one plated slot filled with electrically conductive material.

IPC Classes  ?

• H01F 27/28 - Coils; Windings; Conductive connections
• H01F 27/24 - Magnetic cores

Abstract

A component carrier includes a stack with electrically conductive layer structures and at least one electrically insulating layer structure. The electrically conductive layer structures have a higher density connection region and a lower density connection region, and a first component and a second component which are surface-mounted on the stack. The first component and the second component are electrically coupled with each other by the higher density connection region.

IPC Classes  ?

• H01L 23/498 - Leads on insulating substrates
• H01L 25/065 - Assemblies consisting of a plurality of individual semiconductor or other solid state devices all the devices being of a type provided for in the same subgroup of groups , or in a single subclass of , , e.g. assemblies of rectifier diodes the devices not having separate containers the devices being of a type provided for in group
• H01L 25/18 - Assemblies consisting of a plurality of individual semiconductor or other solid state devices the devices being of types provided for in two or more different subgroups of the same main group of groups , or in a single subclass of ,
• H01L 23/00 - SEMICONDUCTOR DEVICES NOT COVERED BY CLASS - Details of semiconductor or other solid state devices
• H01L 21/48 - Manufacture or treatment of parts, e.g. containers, prior to assembly of the devices, using processes not provided for in a single one of the groups
• H01L 25/00 - Assemblies consisting of a plurality of individual semiconductor or other solid state devices

Abstract

A component carrier includes a stack with at least one electrically insulating layer structure and electrically conductive layer structures some of which have a first density of trace structures and a second density of connection structures, and a further stack with at least one further electrically insulating layer structure and further electrically conductive layer structures some of which have a third density of further trace structures and a fourth density of further connection structures. A first component is applied to the stack and a second component is embedded in the further stack. The connection structures are respectively connected to the further connection structures. The first density of trace structures is lower than the third density of further trace structures. The stack and the further stack are connected with each other by the connection structures and by the further connection structures. The first component is connected to the second component.

IPC Classes  ?

• H05K 1/11 - Printed elements for providing electric connections to or between printed circuits
• H05K 1/18 - Printed circuits structurally associated with non-printed electric components
• H05K 3/42 - Plated through-holes
• H05K 3/34 - Assembling printed circuits with electric components, e.g. with resistor electrically connecting electric components or wires to printed circuits by soldering

Abstract

A coreless component carrier includes a stack with at least two electrically conductive layer structures and at least one electrically insulating layer structure, vias that vertically interconnect the electrically conductive layer structures in the stack, and protruding portions that protrude from the outermost electrically conductive layer structure of the stack beyond the upper main surface of the stack. The vias include an electrically conductive material and taper in the same direction. Methods for manufacturing the coreless component carrier are also disclosed.

IPC Classes  ?

• H05K 1/11 - Printed elements for providing electric connections to or between printed circuits
• H05K 1/02 - Printed circuits - Details
• H05K 3/46 - Manufacturing multi-layer circuits

Abstract

A component carrier includes a carrier body formed of a plurality of electrically conductive layer structures and/or electrically insulating layer structures, a metal surface structure coupled to the carrier body and a metal body directly on the metal surface structure formed by additive manufacturing. The metal body is arranged directly on the metal surface structure without material and layers in between.

IPC Classes  ?

• B22F 10/28 - Powder bed fusion, e.g. selective laser melting [SLM] or electron beam melting [EBM]
• B22F 10/47 - Structures for supporting workpieces or articles during manufacture and removed afterwards characterised by structural features
• B22F 10/64 - Treatment of workpieces or articles after build-up by thermal means
• B33Y 80/00 - Products made by additive manufacturing
• B33Y 10/00 - Processes of additive manufacturing

Abstract

A component carrier includes a stack having at least one electrically conductive layer structure and/or at least one electrically insulating layer structure, a component including a terminal made of a first electrically conductive material and being embedded in the stack, a recess in the stack exposing at least a part of the terminal, an interface structure on the at least partially exposed terminal and an electrically conductive structure on the interface structure made of a second electrically conductive material.

IPC Classes  ?

• H05K 1/18 - Printed circuits structurally associated with non-printed electric components
• H05K 1/11 - Printed elements for providing electric connections to or between printed circuits
• H05K 3/10 - Apparatus or processes for manufacturing printed circuits in which conductive material is applied to the insulating support in such a manner as to form the desired conductive pattern
• H05K 3/30 - Assembling printed circuits with electric components, e.g. with resistor
• H05K 3/40 - Forming printed elements for providing electric connections to or between printed circuits

Abstract

A package (100) which comprises an inorganic carrier body (102) having a cavity (104), an organic integrated circuit substrate (106) embedded in the cavity (104) of the carrier body (102), and a redistribution structure (108) formed partially on and/or above the carrier body (102) and partially on and/or in the integrated circuit substrate (106).

IPC Classes  ?

• H01L 23/538 - Arrangements for conducting electric current within the device in operation from one component to another the interconnection structure between a plurality of semiconductor chips being formed on, or in, insulating substrates

Abstract

A component carrier, including a stack having at least one electrically conductive layer structure and at least one electrically insulating layer structure, a cavity in the stack, an inlay substrate at least partially embedded in the cavity. The inlay substrate includes a component and an IC substrate stacked one above the other, a first redistribution structure that electrically connects the component to a first component carrier main surface, and a second redistribution structure that electrically connects the IC substrate to a second component carrier main surface opposed to the first component carrier main surface.

IPC Classes  ?

• H01L 23/00 - SEMICONDUCTOR DEVICES NOT COVERED BY CLASS - Details of semiconductor or other solid state devices
• H01R 12/52 - Fixed connections for rigid printed circuits or like structures connecting to other rigid printed circuits or like structures
• H01L 25/065 - Assemblies consisting of a plurality of individual semiconductor or other solid state devices all the devices being of a type provided for in the same subgroup of groups , or in a single subclass of , , e.g. assemblies of rectifier diodes the devices not having separate containers the devices being of a type provided for in group
• H01L 25/18 - Assemblies consisting of a plurality of individual semiconductor or other solid state devices the devices being of types provided for in two or more different subgroups of the same main group of groups , or in a single subclass of ,
• H01L 25/16 - Assemblies consisting of a plurality of individual semiconductor or other solid state devices the devices being of types provided for in two or more different main groups of groups , or in a single subclass of , , e.g. forming hybrid circuits
• H01L 21/48 - Manufacture or treatment of parts, e.g. containers, prior to assembly of the devices, using processes not provided for in a single one of the groups
• H01L 21/56 - Encapsulations, e.g. encapsulating layers, coatings
• H01L 23/538 - Arrangements for conducting electric current within the device in operation from one component to another the interconnection structure between a plurality of semiconductor chips being formed on, or in, insulating substrates
• H01L 23/31 - Encapsulation, e.g. encapsulating layers, coatings characterised by the arrangement

Abstract

A module includes a component carrier including a stack having at least one electrically conductive layer structure and at least one electrically insulating layer structure. A semiconductor-based bridging component having a redistribution structure is embedded in the stack. An electronic component is mounted on the component carrier and being partially electrically connected with the semiconductor-based component and partially electrically connected with another element of the component carrier or the module.

IPC Classes  ?

• H01L 23/538 - Arrangements for conducting electric current within the device in operation from one component to another the interconnection structure between a plurality of semiconductor chips being formed on, or in, insulating substrates
• H01L 25/16 - Assemblies consisting of a plurality of individual semiconductor or other solid state devices the devices being of types provided for in two or more different main groups of groups , or in a single subclass of , , e.g. forming hybrid circuits
• H01L 25/065 - Assemblies consisting of a plurality of individual semiconductor or other solid state devices all the devices being of a type provided for in the same subgroup of groups , or in a single subclass of , , e.g. assemblies of rectifier diodes the devices not having separate containers the devices being of a type provided for in group
• H10B 80/00 - Assemblies of multiple devices comprising at least one memory device covered by this subclass
• H01L 23/00 - SEMICONDUCTOR DEVICES NOT COVERED BY CLASS - Details of semiconductor or other solid state devices
• H01L 23/498 - Leads on insulating substrates
• H01L 21/48 - Manufacture or treatment of parts, e.g. containers, prior to assembly of the devices, using processes not provided for in a single one of the groups

Abstract

A component carrier includes a stack including at least one electrically conductive layer structure and at least one electrically insulating layer structure and a component connected to the stack. The component has a planar redistribution layer at a main surface thereof.

IPC Classes  ?

• H05K 1/18 - Printed circuits structurally associated with non-printed electric components
• H05K 3/30 - Assembling printed circuits with electric components, e.g. with resistor

Abstract

An antenna radiation module for assembling to an antenna inlay for a component carrier or to a component carrier. The module includes a dielectric layer structure and an antenna radiation layer structure. The antenna radiation layer structure is embedded in the first dielectric layer structure. Further, an antenna inlay, a component carrier, and a manufacturing method are described.

IPC Classes  ?

• H01Q 1/52 - Means for reducing coupling between antennas; Means for reducing coupling between an antenna and another structure
• H01Q 9/04 - Resonant antennas
• H01Q 1/40 - Radiating elements coated with, or embedded in, protective material

Abstract

The invention pertains to a method for the bonding of a component embedded into a printed circuit board exhibiting the following steps: Provision of a core exhibiting at least one insulating layer and at least one conductor layer applied to the insulating layer, Embedding of at least one component into a recess of the insulating layer, wherein the contacts of the component are essentially situated in the plane of an outer surface of the core exhibiting the at least one conductor layer, Application of a photoimageable resist onto the one outer surface of the core on which the component is arranged, while filling the spaces between the contacts of the component, Clearing of end faces of the contacts and of the areas of the conductor layer covered by the photoimageable resist by exposing and developing the photoimageable resist, by application of a semi-additive process, deposition of a layer of conductor material onto the cleared end faces of the contacts and the cleared areas of the conductor layer and formation of a conductor pattern on at least the one outer surface of the core on which the component is arranged, as well as the interconnecting paths between the contacts and the conductor pattern, and Removal of the areas of the conductor layer not belonging to the conductor pattern.

IPC Classes  ?

• H05K 3/06 - Apparatus or processes for manufacturing printed circuits in which the conductive material is applied to the surface of the insulating support and is thereafter removed from such areas of the surface which are not intended for current conducting or shielding the conductive material being removed chemically or electrolytically, e.g. by photo-etch process
• H05K 3/00 - Apparatus or processes for manufacturing printed circuits

Abstract

A method for manufacturing a component carrier includes i) providing a metal layer, in particular a copper layer; ii) forming a film on the metal layer; iii) patterning the film in order to expose a part of the metal layer; iv) carrying out a first etch, thereby thinning the film and removing a further part of the exposed metal layer; and thereafter v) carrying out a second etch, thereby forming at least one metal trace that is spatially separated from the metal layer. A component carrier made by the method is further described.

IPC Classes  ?

• H05K 3/06 - Apparatus or processes for manufacturing printed circuits in which the conductive material is applied to the surface of the insulating support and is thereafter removed from such areas of the surface which are not intended for current conducting or shielding the conductive material being removed chemically or electrolytically, e.g. by photo-etch process
• H05K 1/02 - Printed circuits - Details

Abstract

A component carrier having a stack with at least one electrically conductive layer structure and at least one electrically insulating layer structure; an opening located at least partially in the stack; and a fill material which is located within the opening. The fill material is a photosensitive material, wherein at least a part of the photosensitive material has undergone a hardening treatment with electromagnetic radiation. A method for manufacturing such a component carrier is further described.

IPC Classes  ?

• H05K 1/02 - Printed circuits - Details
• H05K 1/11 - Printed elements for providing electric connections to or between printed circuits
• H05K 3/06 - Apparatus or processes for manufacturing printed circuits in which the conductive material is applied to the surface of the insulating support and is thereafter removed from such areas of the surface which are not intended for current conducting or shielding the conductive material being removed chemically or electrolytically, e.g. by photo-etch process

Abstract

A component carrier includes a stack with at least one electrically conductive layer structure and at least one electrically insulating layer structure, and a microwave structure embedded at least partially in the stack. The microwave structure configured for exciting a microwave propagation mode and having at least two stack pieces being interconnected with each other at an electrically conductive connection interface.

IPC Classes  ?

• H05K 1/02 - Printed circuits - Details

Abstract

A method for manufacturing a component carrier includes i) providing a metal layer, in particular a copper layer; ii) forming a film on the metal layer; iii) patterning the film in order to expose a part of the metal layer; iv) carrying out a first etch, thereby thinning the film and removing a further part of the exposed metal layer; and thereafter v) carrying out a second etch, thereby forming at least one metal trace that is spatially separated from the metal layer. A component carrier made by the method is further described.

IPC Classes  ?

• H01L 23/31 - Encapsulation, e.g. encapsulating layers, coatings characterised by the arrangement
• H05K 1/18 - Printed circuits structurally associated with non-printed electric components
• H05K 3/00 - Apparatus or processes for manufacturing printed circuits
• H01L 21/56 - Encapsulations, e.g. encapsulating layers, coatings
• H01L 31/0203 - Containers; Encapsulations
• H01L 33/48 - SEMICONDUCTOR DEVICES NOT COVERED BY CLASS - Details thereof characterised by the semiconductor body packages
• G02B 6/42 - Coupling light guides with opto-electronic elements

Abstract

A method of manufacturing a component carrier (100), wherein the method comprises stamping a surface profile in a design layer (102), forming an electrically conductive seed layer (118) on the stamped design layer (102), forming a patterned electroplating protection structure (106) on portions of the seed layer (118) apart from indentations (108) of the profiled design layer (102), and electroplating an electroplating structure (110) selectively on or above portions of the seed layer (118) exposed with respect to the electroplating protection structure (106).

IPC Classes  ?

• C25D 1/00 - Electroforming
• C23F 1/00 - Etching metallic material by chemical means
• C25D 5/02 - Electroplating of selected surface areas
• C25D 5/00 - Electroplating characterised by the process; Pretreatment or after-treatment of workpieces
• B41K 1/00 - Portable hand-operated devices without means for supporting or locating the articles to be stamped, i.e. hand stamps; Inking devices or other accessories therefor
• B31F 1/07 - Embossing
• C25D 7/12 - Semiconductors
• C23F 1/02 - Local etching

Abstract

The present invention relates to a method of manufacturing a layer structure (101) for a component carrier (100). According to the method, a carrier layer (102) is provided. An imprint resist layer (104) is added onto the carrier layer (102) and predefined structures forming at least one recess (105) are stamped into the imprint resist layer (104) by a predefined stamp, wherein the recess (105) defines a filling structure (108) in or on the carrier layer (102). In the filling structure (108) at least one of an electrically insulating material (113) and an electrically conductive material (202) is filled.

IPC Classes  ?

• G03F 7/00 - Photomechanical, e.g. photolithographic, production of textured or patterned surfaces, e.g. printed surfaces; Materials therefor, e.g. comprising photoresists; Apparatus specially adapted therefor
• H01L 23/538 - Arrangements for conducting electric current within the device in operation from one component to another the interconnection structure between a plurality of semiconductor chips being formed on, or in, insulating substrates
• H05K 3/10 - Apparatus or processes for manufacturing printed circuits in which conductive material is applied to the insulating support in such a manner as to form the desired conductive pattern

Abstract

A method of manufacturing a component carrier (100), wherein the method comprises stamping a surface profile in a design layer (102), forming a metallic base structure (122, 122') in at least one indentation (108) of the profiled design layer (102) at least partially by electroplating, and electroplating an electroplating structure (110) in the at least one indentation (108) on or above the metallic base structure (122, 122'),

IPC Classes  ?

• H05K 3/46 - Manufacturing multi-layer circuits
• H05K 3/28 - Applying non-metallic protective coatings
• H05K 1/18 - Printed circuits structurally associated with non-printed electric components

Abstract

A coreless component carrier includes (a) a stack with at least one electrically conductive layer structure and at least one electrically insulating layer structure; and (b) a component embedded in the stack. At least one electrically insulating layer structure includes a reinforced layer structure, which is arranged at an outer main surface of the stack. Further described is a method for manufacturing such a coreless component carrier and preferably simultaneously a further coreless component carrier of the same type.

IPC Classes  ?

• H05K 1/18 - Printed circuits structurally associated with non-printed electric components
• H01L 21/48 - Manufacture or treatment of parts, e.g. containers, prior to assembly of the devices, using processes not provided for in a single one of the groups
• H01L 21/683 - Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components for supporting or gripping
• H01L 23/00 - SEMICONDUCTOR DEVICES NOT COVERED BY CLASS - Details of semiconductor or other solid state devices
• H01L 23/31 - Encapsulation, e.g. encapsulating layers, coatings characterised by the arrangement
• H01L 23/498 - Leads on insulating substrates
• H01L 25/065 - Assemblies consisting of a plurality of individual semiconductor or other solid state devices all the devices being of a type provided for in the same subgroup of groups , or in a single subclass of , , e.g. assemblies of rectifier diodes the devices not having separate containers the devices being of a type provided for in group
• H05K 1/03 - Use of materials for the substrate
• H05K 3/46 - Manufacturing multi-layer circuits

Abstract

A component carrier includes a stack with at least one electrically conductive layer structure, at least one electrically insulating layer structure, and a hole in the stack having a first hole portion covered with metal and having a second hole portion not covered with metal, wherein the second hole portion is defined by an anti-plating dielectric structure and an electroless plateable separation barrier.

IPC Classes  ?

• H05K 3/42 - Plated through-holes
• H01L 23/498 - Leads on insulating substrates
• H01L 21/48 - Manufacture or treatment of parts, e.g. containers, prior to assembly of the devices, using processes not provided for in a single one of the groups
• H05K 1/11 - Printed elements for providing electric connections to or between printed circuits
• H05K 1/03 - Use of materials for the substrate
• H05K 3/06 - Apparatus or processes for manufacturing printed circuits in which the conductive material is applied to the surface of the insulating support and is thereafter removed from such areas of the surface which are not intended for current conducting or shielding the conductive material being removed chemically or electrolytically, e.g. by photo-etch process
• H05K 3/10 - Apparatus or processes for manufacturing printed circuits in which conductive material is applied to the insulating support in such a manner as to form the desired conductive pattern

Abstract

A component carrier includes a layer stack with at least one electrically insulating layer structure and/or at least one electrically conductive layer structure, at least one opening in the layer stack, a first curable dielectric element arranged at least partially on the opening, and a second curable dielectric element arranged adjacent to the first curable dielectric element, so that there is an interface region in between. A part of the first curable dielectric element extends partially into the opening.

IPC Classes  ?

• H05K 1/03 - Use of materials for the substrate
• H05K 1/02 - Printed circuits - Details
• H05K 3/46 - Manufacturing multi-layer circuits

Abstract

A method includes forming a layer stack with at least one electrically insulating layer structure and at least one patterned electrically conductive layer structure on a temporary carrier, the layer stack includes a lower surface adjoining the temporary carrier and an upper surface opposite to the lower surface; mounting a first component at the upper surface; placing a first frame structure at the upper surface, the first frame structure surrounding at least partially the first component; covering the first component with a first coating material, the first coating material spatially extending at least partially into voids at or within the first frame structure and into voids at or within the layer stack; and removing the temporary carrier. The lower surface of the layer stack is an even surface. The opposite upper surface of the layer stack is an uneven surface. An electronic package can be manufactured with the described method.

IPC Classes  ?

• H01L 23/00 - SEMICONDUCTOR DEVICES NOT COVERED BY CLASS - Details of semiconductor or other solid state devices
• H01L 23/498 - Leads on insulating substrates
• H01L 25/065 - Assemblies consisting of a plurality of individual semiconductor or other solid state devices all the devices being of a type provided for in the same subgroup of groups , or in a single subclass of , , e.g. assemblies of rectifier diodes the devices not having separate containers the devices being of a type provided for in group
• H01L 23/522 - Arrangements for conducting electric current within the device in operation from one component to another including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body

Abstract

A method of manufacturing a component carrier includes laser drilling a blind hole in a layer stack, and subsequently extending the blind hole to a through hole by etching. A component carrier includes an electrically insulating layer structure, an electrically conductive layer structure directly on an electrically insulating layer structure, and a tapering through hole extending through the electrically conductive layer structure and through the electrically insulating layer structure with a lateral overhang of the electrically conductive layer structure beyond the electrically insulating layer structure at the tapering through hole of not more than 20% of a maximum diameter of the tapering through hole.

IPC Classes  ?

• H05K 3/00 - Apparatus or processes for manufacturing printed circuits
• H05K 3/42 - Plated through-holes
• H05K 1/11 - Printed elements for providing electric connections to or between printed circuits

Abstract

A component carrier includes a stack having at least one horizontal electrically conductive layer structure, at least one electrically insulating layer structure, a semiconductor component embedded in the stack, and at least one vertical via being laterally offset from the semiconductor component. The at least one horizontal electrically conductive layer structure electrically connects the vertical via to a bottom main surface of the semiconductor component. The component carrier is configured for a current flow from the vertical via to the horizontal electrically conductive layer structure, from the horizontal electrically conductive layer structure to the bottom main surface of the semiconductor component, from the bottom main surface of the semiconductor component to an upper main surface of the semiconductor component, and from the upper surface of the semiconductor component to the outside of the component carrier.

IPC Classes  ?

• H05K 1/18 - Printed circuits structurally associated with non-printed electric components
• H05K 1/02 - Printed circuits - Details
• H05K 1/11 - Printed elements for providing electric connections to or between printed circuits
• H05K 3/40 - Forming printed elements for providing electric connections to or between printed circuits

Abstract

A component carrier for carrying at least one electronic component includes (a) a plurality of electrically conductive layers; (b) a plurality of electrically insulating layers; and (c) a thermoplastic structure. The electrically conductive layers, the electrically insulating layers, and the thermoplastic structure form a laminate. Further, a method for manufacturing such a component carrier and an electronic apparatus including such a component carrier are provided.

IPC Classes  ?

• H05K 1/02 - Printed circuits - Details
• H05K 1/18 - Printed circuits structurally associated with non-printed electric components
• H05K 3/00 - Apparatus or processes for manufacturing printed circuits
• H05K 3/46 - Manufacturing multi-layer circuits

Abstract

A component carrier includes a stack with at least one electrically conductive layer structure and/or at least one electrically insulating layer structure. The at least one electrically conductive layer structure includes a first trace. A tapering trench is formed in the at least one electrically insulating layer structure beside and below the first trace. A method of manufacturing the component carrier is also described.

IPC Classes  ?

• H05K 1/02 - Printed circuits - Details
• H05K 3/00 - Apparatus or processes for manufacturing printed circuits
• H01L 23/13 - Mountings, e.g. non-detachable insulating substrates characterised by the shape
• H01L 23/498 - Leads on insulating substrates
• H01L 21/48 - Manufacture or treatment of parts, e.g. containers, prior to assembly of the devices, using processes not provided for in a single one of the groups
• H01P 3/08 - Microstrips; Strip lines

Abstract

A method of manufacturing a component carrier includes forming a poorly adhesive structure on at least one layer structure, thereafter removing part of the poorly adhesive structure to thereby define a lateral limit of the poorly adhesive structure, thereafter attaching at least one further layer structure to the at least one layer structure and to the poorly adhesive structure, and forming a cavity by removing material of the at least one further layer structure above the poorly adhesive structure.

IPC Classes  ?

• H05K 3/46 - Manufacturing multi-layer circuits
• H05K 1/11 - Printed elements for providing electric connections to or between printed circuits
• H05K 1/02 - Printed circuits - Details
• H05K 3/00 - Apparatus or processes for manufacturing printed circuits
• H05K 3/30 - Assembling printed circuits with electric components, e.g. with resistor

Abstract

A component carrier includes a stack with at least one electrically conductive layer structure and at least one electrically insulating layer structure. At least one electrically insulating layer structure has at least partly tapering through holes filled substantially completely with an electrically conductive filling. The at least one electrically conductive layer structure and the electrically conductive filling are made of the same material. In addition, different ones of the through holes of one electrically insulating layer structure are tapering in opposite directions.

IPC Classes  ?

• H05K 1/02 - Printed circuits - Details
• H05K 1/11 - Printed elements for providing electric connections to or between printed circuits
• H01L 23/498 - Leads on insulating substrates
• H01L 21/48 - Manufacture or treatment of parts, e.g. containers, prior to assembly of the devices, using processes not provided for in a single one of the groups

Goods & Services

Apparatus and instruments for conducting, switching, transforming, accumulating, regulating or controlling electricity; printed circuit boards for the connecting and/or carrying of electric and electronic sub-assemblies, components, elements and/or modules; printed circuits; integrated circuits; printed circuit boards incorporating integrated circuits; circuit boards provided with integrated circuits; component insertion apparatus for printed circuit boards; masks for production of integrated circuits, namely, reticles and photomasks used in lithographic production of integrated circuits; ion implant systems for doping semiconductor materials; control facilities for electronic component parts and components Retail services, namely, manufacturing, processing, sale and delivery of finished and semi-finished information technology equipment Scientific and technological services, namely, design, engineering, research, development, simulation and testing relating to apparatus and instruments for conducting, switching, transforming, accumulating, regulating or controlling electricity, printed circuit boards for the connecting and/or carrying of electric and electronic sub-assemblies, components, elements and/or modules, printed circuits, integrated circuits, printed circuit boards incorporating integrated circuits, circuit boards provided with integrated circuits; scientific and technological services, namely, design, engineering research, development and testing relating to component insertion apparatus for printed circuit boards, masks for production of integrated circuits, photomasks, ion implant systems, control facilities for electronic component parts and components, soldering apparatus, electric, to dive and surge soldering baths, photolithographic systems, etching devices, etching machines, machines for use in the manufacture of electrical and electronic circuitry; development of electric and electronic component parts, components, modules and appliances; technological consultancy in relation to the development and production of electric and electronic component parts, components, modules and appliances; design of printed circuit boards; design of integrated circuits; technical consultancy in the design of machinery for electronic circuitry manufacture; technical data analysis

Abstract

A component carrier assembly includes a first component carrier having a first electrically insulating layer structure and a via in the first electrically insulating layer structure, where the via is at least partially filled with electrically conductive material and where an upper part of the via extends beyond an outer main surface of the first component carrier; and a second component carrier having a second electrically insulating layer structure, and an electrically conductive adhesive material that is at least partially embedded in the second electrically insulating layer structure. The first component carrier and the second component carrier are interconnected and the upper part of the via at least partially penetrates into the electrically conductive adhesive material.

IPC Classes  ?

• H05K 1/14 - Structural association of two or more printed circuits
• H05K 1/11 - Printed elements for providing electric connections to or between printed circuits
• H05K 3/12 - Apparatus or processes for manufacturing printed circuits in which conductive material is applied to the insulating support in such a manner as to form the desired conductive pattern using printing techniques to apply the conductive material
• H05K 3/46 - Manufacturing multi-layer circuits
• H05K 3/18 - Apparatus or processes for manufacturing printed circuits in which conductive material is applied to the insulating support in such a manner as to form the desired conductive pattern using precipitation techniques to apply the conductive material
• H05K 3/36 - Assembling printed circuits with other printed circuits

Abstract

A component carrier intermediate product includes a first electrically-insulating layer structure; an at least partially uncured and patterned second electrically-insulating layer structure having recesses, wherein the recesses are filled by an electrically-conductive material; and a component carrier section arranged on the at least partially uncured and patterned second electrically-insulating layer structure.

IPC Classes  ?

• H05K 3/46 - Manufacturing multi-layer circuits

Abstract

A magnetic inlay for a component carrier includes a magnetic matrix and an electrically conductive structure embedded horizontally in the magnetic matrix. The electrically conductive structure is configured as an inductive element. The magnetic inlay is configured so that, depending on the geometrical properties of the electrically conductive structure, a specific inductance value is provided for the magnetic inlay.

IPC Classes  ?

• H05K 1/16 - Printed circuits incorporating printed electric components, e.g. printed resistor, capacitor, inductor
• H01F 17/00 - Fixed inductances of the signal type
• H01F 27/28 - Coils; Windings; Conductive connections
• H01F 41/04 - Apparatus or processes specially adapted for manufacturing or assembling magnets, inductances or transformers; Apparatus or processes specially adapted for manufacturing materials characterised by their magnetic properties for manufacturing cores, coils or magnets for manufacturing coils
• H05K 1/11 - Printed elements for providing electric connections to or between printed circuits
• H05K 3/46 - Manufacturing multi-layer circuits

Abstract

A magnetic inlay includes a magnetic matrix and a plurality of electrically conductive vertical through connections extending vertically through the magnetic matrix. Further, a component carrier including the magnetic inlay and a method of manufacturing said magnetic inlay are described.

IPC Classes  ?

• H05K 1/16 - Printed circuits incorporating printed electric components, e.g. printed resistor, capacitor, inductor
• H01F 27/28 - Coils; Windings; Conductive connections
• H01F 41/04 - Apparatus or processes specially adapted for manufacturing or assembling magnets, inductances or transformers; Apparatus or processes specially adapted for manufacturing materials characterised by their magnetic properties for manufacturing cores, coils or magnets for manufacturing coils

Abstract

A component carrier includes a stack with at least one electrically insulating layer structure, a structured electrically conductive layer assembled to the stack, where a part of the structured electrically conductive layer is configured as an inductive element, and a magnetic matrix embedded in the stack. The magnetic matrix at least partially surrounds the inductive element. Further, a manufacturing method is described.

IPC Classes  ?

• H05K 1/18 - Printed circuits structurally associated with non-printed electric components
• H05K 1/11 - Printed elements for providing electric connections to or between printed circuits
• H05K 3/10 - Apparatus or processes for manufacturing printed circuits in which conductive material is applied to the insulating support in such a manner as to form the desired conductive pattern
• H01F 27/28 - Coils; Windings; Conductive connections
• H01F 27/32 - Insulating of coils, windings, or parts thereof
• H01F 41/04 - Apparatus or processes specially adapted for manufacturing or assembling magnets, inductances or transformers; Apparatus or processes specially adapted for manufacturing materials characterised by their magnetic properties for manufacturing cores, coils or magnets for manufacturing coils
• H01F 41/12 - Insulating of windings

Abstract

A component carrier includes a stack including at least one electrically conductive layer structure and/or at least one electrically insulating layer structure, a magnetic element assembled to the stack, and a dielectric layer structure on the stack. The magnetic element includes an embedded inductive element. The dielectric layer structure at least partially surrounds the magnetic element. Further, a manufacturing method and a use of photo-imaging are described.

IPC Classes  ?

• H05K 1/16 - Printed circuits incorporating printed electric components, e.g. printed resistor, capacitor, inductor
• H01F 17/00 - Fixed inductances of the signal type
• H05K 1/09 - Use of materials for the metallic pattern
• H05K 3/12 - Apparatus or processes for manufacturing printed circuits in which conductive material is applied to the insulating support in such a manner as to form the desired conductive pattern using printing techniques to apply the conductive material

Abstract

A component carrier includes a stack having at least one electrically conductive layer structure and/or at least one electrically insulating layer structure and a magnetic element assembled to the stack. The magnetic element includes a magnetic matrix and an inductive element. The inductive element is at least partially enclosed by the magnetic matrix, so that an electric current flow direction through the inductive element is essentially in a horizontal direction with respect to the stack. Further, a magnetic inlay and a manufacturing method are described.

IPC Classes  ?

• H05K 5/00 - Casings, cabinets or drawers for electric apparatus

Abstract

A component carrier (100) which comprises a stack (102) comprising at least one electrically conductive layer structure (104) and/or at least one electrically insulating layer structure (106), and a photosensitive adhesion promoter (108) on or above the stack (102), wherein only a sub-portion (110) of the photosensitive adhesion promoter (108) is photoactivated, and electrically conductive material (112) selectively on said sub-portion (110) of the photosensitive adhesion promoter (108).

IPC Classes  ?

• H05K 3/18 - Apparatus or processes for manufacturing printed circuits in which conductive material is applied to the insulating support in such a manner as to form the desired conductive pattern using precipitation techniques to apply the conductive material
• H05K 3/38 - Improvement of the adhesion between the insulating substrate and the metal
• H05K 3/24 - Reinforcing of the conductive pattern

Abstract

A component carrier includes a layer body with at least one electrically conductive layer structure and/or at least one electrically insulating layer structure, a component embedded in the layer body, and at least one galvanic connection stack at least partially on at least part of at least one main surface of the layer body. At least one of a bottom main surface and a top main surface of the embedded component is electrically connected to the at least one galvanic connection stack.

IPC Classes  ?

• H05K 1/18 - Printed circuits structurally associated with non-printed electric components
• H05K 1/09 - Use of materials for the metallic pattern

Abstract

A component carrier includes (a) a base structure having a surface with a surface profile; (b) a first dielectric layer formed on the surface of the base structure and (c) a second dielectric layer formed on the first dielectric layer. The first dielectric layer has a first main surface with a first surface profile. The first main surface faces away from the surface of the base structure. The first surface profile corresponds to the surface profile of the base structure. The second dielectric layer includes a second main surface with a second surface profile. The second main surface faces away from the surface of the base structure. The second surface profile differs from the surface profile of the base structure. A manufacturing method uses an auxiliary sheet for pressing the first dielectric layer on the main surface. The auxiliary sheet is removed before pressing the second dielectric layer.

IPC Classes  ?

• H05K 1/03 - Use of materials for the substrate
• H05K 1/02 - Printed circuits - Details
• H05K 3/46 - Manufacturing multi-layer circuits

Abstract

A method of manufacturing a component carrier includes: (i) embedding a poorly adhesive structure in a stack, wherein the stack comprises at least one electrically conductive layer structure and/or at least one electrically insulating layer structure; (ii) forming a cavity in the stack by removing a stack piece, wherein the stack piece is in part delimited by the poorly adhesive structure; and (iii) selectively exposing a bottom of the cavity by partially removing the poorly adhesive structure. A corresponding component carrier includes analogous features.

IPC Classes  ?

• H01L 23/31 - Encapsulation, e.g. encapsulating layers, coatings characterised by the arrangement
• H01L 21/48 - Manufacture or treatment of parts, e.g. containers, prior to assembly of the devices, using processes not provided for in a single one of the groups
• H01L 23/538 - Arrangements for conducting electric current within the device in operation from one component to another the interconnection structure between a plurality of semiconductor chips being formed on, or in, insulating substrates
• H01L 23/00 - SEMICONDUCTOR DEVICES NOT COVERED BY CLASS - Details of semiconductor or other solid state devices
• H05K 1/18 - Printed circuits structurally associated with non-printed electric components
• H05K 3/34 - Assembling printed circuits with electric components, e.g. with resistor electrically connecting electric components or wires to printed circuits by soldering

Abstract

A component carrier includes a core with a dielectric body, a component embedded at least partially in the core, a first dielectric layer being arranged at a bottom side of the core and of the component, and a second dielectric layer being arranged at a top side of the core and of the component. A gap around the component in the core is filled adjacent to the bottom side with material of the first dielectric layer and is filled adjacent to the top side with material of the second dielectric layer.

IPC Classes  ?

• H01L 21/673 - Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components using specially adapted carriers
• H01L 21/683 - Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components for supporting or gripping

Abstract

A component carrier which includes a stack with at least one electrically conductive layer structure and/or at least one electrically insulating layer structure, a high-frequency component embedded in the stack. At least one waveguide is integrated in the stack. A transmission line and a coupling element configured transmit a signal between the high-frequency component and the at least one waveguide. A transmission and/or reception unit wirelessly transmits and/or receives one or more signals.

IPC Classes  ?

• G01S 7/03 - RADIO DIRECTION-FINDING; RADIO NAVIGATION; DETERMINING DISTANCE OR VELOCITY BY USE OF RADIO WAVES; LOCATING OR PRESENCE-DETECTING BY USE OF THE REFLECTION OR RERADIATION OF RADIO WAVES; ANALOGOUS ARRANGEMENTS USING OTHER WAVES - Details of systems according to groups , , of systems according to group - Details of HF subsystems specially adapted therefor, e.g. common to transmitter and receiver
• H05K 1/02 - Printed circuits - Details
• H05K 1/11 - Printed elements for providing electric connections to or between printed circuits
• G01S 7/02 - RADIO DIRECTION-FINDING; RADIO NAVIGATION; DETERMINING DISTANCE OR VELOCITY BY USE OF RADIO WAVES; LOCATING OR PRESENCE-DETECTING BY USE OF THE REFLECTION OR RERADIATION OF RADIO WAVES; ANALOGOUS ARRANGEMENTS USING OTHER WAVES - Details of systems according to groups , , of systems according to group

Abstract

It is described a method of processing an etching waste medium from circuit board and/or substrate manufacture, the method comprising: i) providing a medium to be processed (11), being the etching waste medium, in particular from an etching process (150), wherein the medium to be processed (11) comprises a metal salt to be processed and an acid (15); ii) processing the medium to be processed (11) in an ion exchange process (145), so that the metal salt to be processed is exchanged by a metal salt, and a metal salt containing medium (10) is obtained from the medium to be processed (11); hereby a) streaming a first process cycle (170) through the ion exchange process (145), wherein the first process cycle (170) is a first closed loop that yields substantially only elementary metal (50); and b) streaming a second process cycle (180) through the ion exchange process (140), wherein the second process cycle (180) is a second closed loop that yields substantially only purified water (188) and/or a metal-depleted salt concentrate (186b).

IPC Classes  ?

• C25D 21/18 - Regeneration of process solutions of electrolytes
• C25D 21/22 - Regeneration of process solutions by ion-exchange
• C25C 3/00 - Electrolytic production, recovery or refining of metals by electrolysis of melts
• C25D 21/14 - Controlled addition of electrolyte components
• C22B 3/42 - Treatment or purification of solutions, e.g. obtained by leaching by ion-exchange extraction
• C22B 7/00 - Working-up raw materials other than ores, e.g. scrap, to produce non-ferrous metals or compounds thereof
• C23F 1/46 - Regeneration of etching compositions
• C25C 1/02 - Electrolytic production, recovery or refining of metals by electrolysis of solutions of light metals
• C25C 1/08 - Electrolytic production, recovery or refining of metals by electrolysis of solutions of iron group metals, refractory metals or manganese of nickel or cobalt
• C25C 1/12 - Electrolytic production, recovery or refining of metals by electrolysis of solutions of copper
• C25C 1/14 - Electrolytic production, recovery or refining of metals by electrolysis of solutions of tin
• C25C 1/16 - Electrolytic production, recovery or refining of metals by electrolysis of solutions of zinc, cadmium or mercury
• C25C 1/20 - Electrolytic production, recovery or refining of metals by electrolysis of solutions of noble metals
• C25D 21/20 - Regeneration of process solutions of rinse-solutions
• C25D 3/38 - Electroplating; Baths therefor from solutions of copper

Abstract

A component carrier including a stack with at least one electrically conductive layer structure and/or at least one electrically insulating layer structure. A component embedded in the stack, and a heat removal body configured for removing heat from the component is connected to the stack and preferably to the component. The heat removal body including a component-sided first heat removal structure thermally coupled with the component, and a second heat removal structure thermally coupled with the first heat removal structure and facing away from the component.

IPC Classes  ?

• H05K 1/02 - Printed circuits - Details

Abstract

An electronic device includes a component carrier having a stack with at least one electrically conductive layer structure and/or at least one electrically insulating layer structure, an electronic component on and/or in the stack, and a cooling member with a fluid cooling unit at least partially therein. The component carrier and the cooling member are connected by a connection structure.

IPC Classes  ?

• H05K 1/02 - Printed circuits - Details
• H05K 3/36 - Assembling printed circuits with other printed circuits
• H01R 12/52 - Fixed connections for rigid printed circuits or like structures connecting to other rigid printed circuits or like structures
• H05K 1/18 - Printed circuits structurally associated with non-printed electric components

Abstract

An electronic device includes a first component carrier having a first stack with at least one first electrically conductive layer structure and/or at least one first electrically insulating layer structure, a second component carrier having a second stack with at least one second electrically conductive layer structure and/or at least one second electrically insulating layer structure, and an intermediate structure including at least three staggered electrically conductive and coupled vertical interconnect elements in an at least partially dielectric sheet and being directly connected between the first component carrier and the second component carrier for electrically coupling the first component carrier with the second component carrier.

IPC Classes  ?

• H05K 1/14 - Structural association of two or more printed circuits
• H05K 1/11 - Printed elements for providing electric connections to or between printed circuits
• H05K 1/03 - Use of materials for the substrate
• H05K 3/46 - Manufacturing multi-layer circuits

Abstract

A drive device includes a component carrier with a stack having at least one electrically conductive layer structure and/or at least one electrically insulating layer structure and a cavity formed in the stack. A driven body is arranged at least partially in the cavity and configured for being drivable to move relative to the component carrier. At least one drive coil for creating a magnetic drive field and at least one drive magnet interacts with the magnetic drive field created by the at least one drive coil to generate a force for moving the driven body relative to the component carrier. One of the at least one drive magnet and the at least one drive coil forms part of the component carrier and the other one of the at least one drive magnet and the at least one drive coil forms part of the driven body.

IPC Classes  ?

• H01F 7/02 - Permanent magnets
• H01F 41/02 - Apparatus or processes specially adapted for manufacturing or assembling magnets, inductances or transformers; Apparatus or processes specially adapted for manufacturing materials characterised by their magnetic properties for manufacturing cores, coils or magnets

Abstract

A component carrier includes a first stack having at least one first electrically insulating layer structure and at least one first electrically conductive layer structure, and a second stack with at least one second electrically insulating layer structure and at least one second electrically conductive layer structure. The first stack and the second stack are connected with each other so that a vertical two-dimensional electrically conductive connection is established. The first stack has a first cavity and the second stack has a second cavity, the first cavity and the second cavity being separated by at least one further electrically insulating layer structure. At least one of the first cavity and the second cavity is delimited by a wall being at least partially lined with an electrically conductive coating.

IPC Classes  ?

• H05K 1/11 - Printed elements for providing electric connections to or between printed circuits
• H05K 3/46 - Manufacturing multi-layer circuits
• H05K 3/32 - Assembling printed circuits with electric components, e.g. with resistor electrically connecting electric components or wires to printed circuits
• H05K 1/18 - Printed circuits structurally associated with non-printed electric components

Abstract

A component carrier includes a stack having at least one electrically conductive layer structure and/or at least one electrically insulating layer structure. A cavity is formed in the stack. A component in the cavity has a stepped profile at at least one of its main surfaces. A resin clamping structure laterally engages the component and extends up to a step of the stepped profile. A method of manufacturing such a component carrier is also provided.

IPC Classes  ?

• H05K 1/03 - Use of materials for the substrate
• H05K 1/18 - Printed circuits structurally associated with non-printed electric components
• H05K 3/46 - Manufacturing multi-layer circuits

Abstract

A component carrier includes a stack having at least one electrically conductive layer structure and/or at least one electrically insulating layer structure. A cavity is formed in the stack and has a non-polygonal outline. A component is in the cavity. A method of manufacturing such a component carrier is also provided.

IPC Classes  ?

• H05K 1/03 - Use of materials for the substrate
• H05K 1/18 - Printed circuits structurally associated with non-printed electric components
• H05K 3/46 - Manufacturing multi-layer circuits

Abstract

A component carrier and a method for manufacturing a component carrier are disclosed. The component carrier comprises a carrier body having a plurality of electrically conductive layer structures and/or electrically isolating layer structures and a three-dimensionally printed structure forming at least a part of an antenna on the carrier body.

IPC Classes  ?

• H01Q 1/22 - Supports; Mounting means by structural association with other equipment or articles
• H05K 1/02 - Printed circuits - Details
• B33Y 80/00 - Products made by additive manufacturing
• B33Y 10/00 - Processes of additive manufacturing
• H01Q 9/04 - Resonant antennas

Abstract

A method for manufacturing a component carrier is disclosed. The method includes the steps of providing a layer stack having at least one component carrier material, forming a photoimageable dielectric layer structure on the layer stack, forming a spatial pattern of an electrically conductive layer structure on the photoimageable dielectric layer structure, wherein the spatial pattern defines openings formed within the electrically conductive layer structure, and exposing the photoimageable dielectric layer structure to electromagnetic radiation, where the spatial pattern of the electrically conductive layer structure represents a mask for selectively exposing predefined regions of the photoimageable dielectric layer structure. Furthermore, the method includes selectively removing material from the photoimageable dielectric layer depending on the spatial pattern.

IPC Classes  ?

• H01L 23/498 - Leads on insulating substrates
• G03F 7/095 - Photosensitive materials - characterised by structural details, e.g. supports, auxiliary layers having more than one photosensitive layer
• G03F 7/11 - Photosensitive materials - characterised by structural details, e.g. supports, auxiliary layers having cover layers or intermediate layers, e.g. subbing layers
• H01L 21/48 - Manufacture or treatment of parts, e.g. containers, prior to assembly of the devices, using processes not provided for in a single one of the groups
• H05K 3/06 - Apparatus or processes for manufacturing printed circuits in which the conductive material is applied to the surface of the insulating support and is thereafter removed from such areas of the surface which are not intended for current conducting or shielding the conductive material being removed chemically or electrolytically, e.g. by photo-etch process
• H05K 3/40 - Forming printed elements for providing electric connections to or between printed circuits

Abstract

A method of recovering metal from a chemical bath (100) for chemically treating a structure with metal, wherein the method comprises supplying a chemical composition comprising metal from the chemical bath (100) to a membrane distillation device (106), separating at least part of the metal in the membrane distillation device (106), and reintroducing the separated metal into the chemical bath (100).

IPC Classes  ?

• C25D 21/18 - Regeneration of process solutions of electrolytes
• C25D 21/20 - Regeneration of process solutions of rinse-solutions
• C02F 1/44 - Treatment of water, waste water, or sewage by dialysis, osmosis or reverse osmosis
• B01D 61/36 - Pervaporation; Membrane distillation; Liquid permeation
• C25D 17/00 - Constructional parts, or assemblies thereof, of cells for electrolytic coating
• C23C 18/16 - Chemical coating by decomposition of either liquid compounds or solutions of the coating forming compounds, without leaving reaction products of surface material in the coating; Contact plating by reduction or substitution, i.e. electroless plating

Abstract

Component carrier (100) which comprises a stack (102) comprising at least one electrically conductive layer structure (41) and at least one electrically insulating layer structure (40), and a recess (43), in particular a cavity, being at least partially formed in the stack (102), optionally having an electrically conductive coating (44), and being configured as waveguide, wherein a plurality of edges (67) delimiting the recess (43) are formed by electrically conductive material of the at least one electrically conductive layer structure (41) and/or of the optional electrically conductive coating (44).

IPC Classes  ?

• H05K 1/02 - Printed circuits - Details
• H05K 3/00 - Apparatus or processes for manufacturing printed circuits
• H05K 3/46 - Manufacturing multi-layer circuits

Abstract

A semi-flex component carrier includes a stack having at least one electrically insulating layer structure, at least one electrically conductive layer structure and a stress propagation inhibiting barrier. The stack defines at least one rigid portion and at least one semi-flexible portion. The stress propagation inhibiting barrier includes a plurality of stacked vias filled at least partially with electrically conductive material in an interface region between the at least one rigid portion and the at least one semi-flexible portion and configured to inhibit stress propagation between the at least one rigid portion and the at least one semi-flexible portion during bending.

IPC Classes  ?

• H05K 1/02 - Printed circuits - Details
• H05K 1/18 - Printed circuits structurally associated with non-printed electric components
• H05K 3/46 - Manufacturing multi-layer circuits