A semiconductor component and a method for manufacturing the semiconductor component that are suitable for use with low temperature processing. A semiconductor substrate is provided and an optional layer of silicon nitride is formed on the semiconductor substrate using Atomic Layer Deposition (ALD). A layer of dielectric material is formed on the silicon nitride layer using Sub-Atmospheric Chemical Vapor Deposition (SACVD) at a temperature below about 450° C. When the optional layer of silicon nitride is not present, the SACVD dielectric material is formed on the semiconductor substrate. A contact hole having sidewalls is formed through the SACVD dielectric layer, through the silicon nitride layer, and exposes a portion of the semiconductor substrate. A layer of tungsten nitride is formed on the exposed portion of the semiconductor substrate and along the sidewalls of the contact hole. Tungsten is formed on the layer of tungsten nitride.
Providing for a non-volatile semiconductor memory architecture that achieves high read performance is described herein. In one aspect, an array of memory transistors arranged electrically in serial is configured to control a gate voltage of a pass transistor. The pass transistor, in turn, enables current flow between two metal bitlines of the semiconductor memory architecture. Accordingly, a relative voltage or relative current of the two metal bitlines can be measured and utilized to determine a program or erase state of a transistor of the serial array of transistors. In a particular aspect, a transistor with small capacitance is chosen for the pass transistor, resulting in a fast correspondence of the pass transistor gate voltage/current relative to transistor array current. This can equate to fast read times for the transistor array, based on differential sensing of the two metal bitlines.
Semiconductor devices and methods of producing the devices are disclosed. The devices are formed by forming a gate structure on a substrate. The gate structure includes a charge trapping dielectric formed between the substrate and a first poly layer. A top dielectric is formed over the poly layer and a sidewall dielectric is formed on a side of the poly layer. A second poly layer is formed over the gate structure such that a portion of the second poly layer includes a vertical portion that is in contact with the sidewall dielectric and a top portion that is in contact with the top dielectric. The top portion of the second poly layer can then be removed through, for instance, planarization.
A three-dimensional charge trap semiconductor device is constructed with alternating insulating and gate layers stacked over a substrate. During the manufacturing process, a channel hole is formed in the stack and the gate layers are recessed from the channel hole. Using the recessed topography of the gate layers, a charge trap layer can be deposited on the sidewalls of the channel hole and etched, leaving individual discrete charge trap layer sections in each recess. Filling the channel hole with channel material effectively provides a three-dimensional semiconductor device having individual charge trap layer sections for each memory cell.
An apparatus and method for testing is provided. An integrated circuit includes a comparison circuit that is arranged to trip based on a power supply signal reaching a trip point. The integrated circuit also includes an analog-to-digital converter that is arranged to convert the power supply signal into a digital signal. The integrated circuit also includes a storage component that stores a digital value associated with the digital signal, and provides the power supply value at an output pin of the integrated circuit. The integrated circuit includes a latch that is coupled between the analog-to-digital converter and the storage component. The latch is arranged to open when the comparison circuit trips, such that, when the comparison circuit trips, the storage component continues to store a digital value such that the digital value corresponds to the voltage associated with the power supply signal when the comparison circuit tripped.
H03L 7/00 - Automatic control of frequency or phase; Synchronisation
H03K 3/012 - Modifications of generator to improve response time or to decrease power consumption
H03K 5/24 - Circuits having more than one input and one output for comparing pulses or pulse trains with each other according to input signal characteristics, e.g. slope, integral the characteristic being amplitude
[Problem] To provide a semiconductor storage device and a method of erasing the semiconductor storage device whereby it is possible to prevent the application of a high current when returning to a standby state after an erasing operation. [Solution] When erasing a P-type memory transistor including an N-type well, P-type first and second impurity regions formed within the well, a charge-storing layer formed upon the well between the first impurity region and the second impurity region, and a gate electrode formed upon the charge-storing layer, a negative voltage is applied to the gate electrode, a positive voltage is applied to the first impurity region and the well, and after the charge accumulated in the charge-storing layer is depleted, the first impurity region is set to a floating state, and the voltage applied to the well is reduced.
G11C 11/34 - Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices
7.
PROGRAMMABLE LATENCY COUNT TO ACHIEVE HIGHER MEMORY BANDWIDTH
Disclosed herein are system, method and/or computer program product embodiments for increasing memory bandwidth when accessing a plurality of memory devices. An embodiment operates by executing, by at least one processor, a first read operation to read data from a first memory device following an access time for the first memory device. The embodiment further includes executing, by the at least one processor, a second read operation to read data from a second memory device following an access time for the second memory device. The access time for the second memory device is substantially the same or longer than the access time for the first memory device plus a time it takes to read data from the first memory device.
09 - Scientific and electric apparatus and instruments
Goods & Services
Semiconductors; integrated circuits; microcontrollers; applications software, utility software, and drivers for functions associated with semiconductors, integrated circuits, and microcontrollers.
9.
CHARGE-TRAP NOR WITH SILICON-RICH NITRIDE AS A CHARGE TRAP LAYER
A charge-trapping NOR (CT-NOR) memory device and methods of fabricating a CT- NOR memory device utilizing silicon-rich nitride (SiRN) in a charge-trapping (CT) layer of the CT-NOR memory device.
H01L 29/792 - Field-effect transistors with field effect produced by an insulated gate with charge trapping gate insulator, e.g. MNOS-memory transistor
A semiconductor may include several vias located in an active region and a die seal region. In the active region, a photoresist can be patterned with openings corresponding to the vias. In the die seal area, however, the photoresist can be patterned to overlap the vias. With this configuration, an underlayer etch will not affect an underlayer resist in the die seal area, allowing the die seal area to be disregarded for purposes of calculating a process window.
A method of restoring an ECC syndrome in a non-volatile memory device having memory cells arranged in a plurality of sectors within a memory cell array, the method includess identifying a first sector having a page with a disabled ECC (error correction code) flag; reading the value of all data bits in the page; calculating values for ECC bits in the page; and writing the data bit values and the calculated ECC bit values to a second sector in the memory cell array.
Embodiments described herein generally relate to verifying that a FLASH memory has been erased. In an embodiment, a method of erase verifying a memory column of a FLASH memory includes applying a pass gate voltage to even numbered memory transistors while applying an erase verify voltage to the odd numbered memory transistors. Applying a string current to the memory column allows a probe to determine if the string current is successfully traversing the memory column, and thus verifying that the odd numbered memory transistors were erased. The even numbered memory transistors are verified in the following cycle.
Embodiments include a method, apparatus, and computer program product for authentication for speech recognition. The method can include sensing an authentication device with a target device. One or more decoded voice commands can be processed after verification of the authentication device by the target device. Further, one or more decoded voice commands can be executed by the target device.
Embodiments include a method, apparatus, and a computer program product for combining results from multiple decoders. For example, the method can include generating a network of paths based on one or more outputs associated with each of the multiple decoders. The network of paths can be scored to find an initial path with the highest path score based on scores associated with the one or more outputs, A weighting factor can be calculated for each of the multiple decoders based on a number of outputs from each of the multiple decoders included in the initial path with the highest path score. Further, the network of paths can be re-scored to find a new path with, the highest path score based on the scores associated with the one or more outputs and the weighting factor for each of the multiple decoders.
G10L 19/00 - Speech or audio signal analysis-synthesis techniques for redundancy reduction, e.g. in vocoders; Coding or decoding of speech or audio signals, using source filter models or psychoacoustic analysis
15.
MODIFIED LOCAL SEGMENTED SELF-BOOSTING OF MEMORY CELL CHANNELS
A method of programming a memory system by selectively applying a program voltage to a selected wordline connected to a memory transistor to be programmed. A first bias voltage is applied to a first wordline adjacent to the source side of the selected wordline. The first bias voltage is also applied to a second wordline adjacent to the drain side of the selected wordline. A second bias voltage is applied to a third wordline adjacent to the drain side of the second wordline. A third bias voltage is applied to a fourth wordline adjacent to the source side of the first wordline. A pass voltage is also applied to the remaining wordlines that do not have one of a bias voltage and a program voltage applied, the pass voltage a selected voltage level.
A system including a memory cell array including a plurality of memory cells, and a writing device to generate multiple back-to-back write pulses to write to target memory cells from among the plurality of memory cells, the multiple back-to-back write pulses overlapping during an overlap duration, the overlap duration being adjustable based on a performance parameter of the memory cell array.
A memory module includes an input/output (I/O) interface adapted to fit into a system random access memory (RAM) socket. The module also includes at least one controller coupled to the I/O interface, the controller comprising a plurality of registers, and a plurality of non-volatile memory devices coupled to the controller. In the module, when data is received at the I/O interface, the received data is stored using at least one of the plurality of registers and the controller performs one of a plurality of non-volatile memory operations on at least a portion of the plurality of non-volatile memory devices based on the received data.
A non-volatile memory device comprising a memory cell array including a plurality of non-volatile memory cells arranged in rows and columns, wherein memory cells arranged in a same row share a word line and memory cells arranged in a same column share a bit line; and at least an address decoder to provide a negative voltage to at least one non-accessed word line in said array when a programming or erasure voltage is provided along a shared bit line.
An electronic structure (for example a reliability board or a cycling control module) has a body including a body portion insertable into a connector. A plurality of contact structures are provided on a side of the body portion, each contact structure comprising a first contact and a second contact spaced from the first contact, with the first and second contacts of each contact structure being aligned in the direction of insertion of the body portion into the connector. A corresponding second plurality of contact structures is provided on a side of the body portion opposite the first—mentioned side. These contacts connect with respective corresponding contacts of the connector.
H01R 12/00 - Structural associations of a plurality of mutually-insulated electrical connecting elements, specially adapted for printed circuits, e.g. printed circuit boards [PCB], flat or ribbon cables, or like generally planar structures, e.g. terminal strips, ; Coupling devices specially adapted for printed circuits, flat or ribbon cables, or like generally planar structures; Terminals specially adapted for contact with, or insertion into, printed circuits, flat or ribbon cables, or like generally planar structures
H01R 13/04 - Pins or blades for co-operation with sockets
G01R 31/28 - Testing of electronic circuits, e.g. by signal tracer
A source-sensing configuration for non-volatile memory devices to simultaneously read 2 bits in two different memory cells sharing a same word line is disclosed. In a first cell arrangement, a drain of a first read cell is biased and its source and that of two adjacent cells in a direction towards the second read cell are connected through source bit lines to a source sense amplifier. In a second cell arrangement, the drain of the second read cell is biased and its source and that of its two adjacent cells in a direction towards the first read cell are connected through source bit lines to a source sense amplifier. A memory cell acts as a cell pipe and joins together the first and second cell arrangements. Driving all six source bit lines simultaneously allows the 2 bits to be simultaneously read while maintaining currents due to pipe effect substantially minimized.
A non-volatile memory device includes a memory cell array having memory cells distributed among a plurality of sectors and a controller operable to program, read, and erase memory cells in said memory array, the controller further operable to generate and store EPLI values for programming a number of EPLI bits in one of the plurality of sectors with the stored EPLI values. The memory device additionally include a comparator to compare the stored EPLI values with EPLI values programmed in the EPLI bits.
An approach to use silicided bit line contacts that do not short to the underlying substrate in memory devices. The approach provides for silicide formation in the bit line contact area, using a process that benefits from being self-aligned to the oxide-nitride-oxide (ONO) nitride edges, A further benefit of the approach is that the bit line contact implant and rapid temperature anneal process can be eliminated. This approach is applicable to embedded flash, integrating high density devices and advanced logic processes.
Embodiments described herein generally relate to methods of manufacturing n-type lightly doped drains and p-type lightly doped drains. In one method, a photoresist mask is used to etch a transistor, and the mask is left in place (i.e., reused) to protect other devices and poly while a high energy implantation is performed in alignment with the photoresist mask, such that the implantation is adjacent to the etched transistor. One example of a high energy implantation is forming lightly doped source and drain regions. This technique of reusing a photoresist mask can be employed for creating lightly doped source and drain regions of one conductivity followed by using the technique a second time to create lightly doped source and drain regions of the complementary conductivity type. This may prevent use of at least one hard mask during manufacturing.
09 - Scientific and electric apparatus and instruments
Goods & Services
Non-volatile memory devices, namely, flash memory semiconductor chips and mass storage semiconductor chips; applications and utility software for functions associated with memory devices, namely, code and data management software, file system management software, flash memory semiconductor chip drivers, mass storage semiconductor chip drivers, flash media drivers, and block drivers.
09 - Scientific and electric apparatus and instruments
Goods & Services
Interfaces for high-speed throughput of data between a processor or microcontroller and other semiconductor devices; interfaces for high speed throughput or data between a processor or microcontroller and peripheral components.
27.
PROGRAMMABLE AND FLEXIBLE REFERENCE CELL SELECTION METHOD FOR MEMORY DEVICES
Systems, methods, and computer program products for programmable reference cell selection for flash memory are disclosed. An exemplary system includes an array of interconnected cells and a flexible decoder. The array is configured to receive a selection signal as input, select a cell based upon the selection signal, and provide an output based on the selected cell. The flexible decoder is configured to receive an input, generate a selection signal based on the input and one or more characteristics of the array of interconnected cells, and provide the selection signal to the array of interconnected cells.
Embodiments of the present invention include an apparatus, method, and system for speech recognition of a voice command. The method can include receiving data representing a voice command, generating a list of targets based on the state information of each target within the system, and selecting a target from the list of targets, based on the voice command.
A multi-chip package is disclosed that has a construction capable of preventing and/or reducing electrical shorts caused by shifts in bond wires. The multi-chip package includes a die attach formed between connection points of a bond wire. The die attach is made of a non- conductive material and can be constructed so as to support or encompass a portion of the bond wire. By contacting the bond wire, the die attach restricts the motion of the bond wire by acting as a physical barrier to the bond wire's movement and/or as a source of friction. In this manner, undesired position shifts of the bond wires can be prevented, reducing device failures and allowing for improved manufacturing allowances.
Methods and apparatus for manufacturing semiconductor devices, and such semiconductor devices, are described. According to various aspects of the disclosure, a semiconductor device can be manufactured by forming a core region of the semiconductor device and forming a periphery region of the semiconductor device. A first polysilicon region can then be formed over the core and periphery regions of the semiconductor device. A first mask is formed on the first poly silicon layer and a second polysilicon layer is disposed such that the second polysilicon layer covers the first mask. A second mask can then be formed on the second polysilicon layer. After forming the second mask, portions of the first and second polysilicon layers that are uncovered by either the first or second masks are removed.
A memory is disclosed that can operate in a normal mode of operation or a testing mode of operation. In the testing mode of operation, the memory can measure various benchmarks of performance, such as read speed. The memory can perform an asynchronous read operation to read a word of electronic data that corresponds to an address or a page read operation in which multiple asynchronous read operations are performed to read multiple words of electronic data, also referred to as a page of electronic data, that correspond to multiple addresses. The memory can measure a time required, referred to as read speed, to read the word of electronic data or the multiple words of electronic data from the memory. In the normal mode of operation, the memory can perform the asynchronous read operation, the page read operation, an asynchronous write operation in which a word of electronic data is stored into the memory that correspond to the address, or a page write operation in which a page electronic data is stored into the memory that correspond to the multiple addresses.
Embodiments of the present invention include an acoustic processing device, a method for acoustic signal processing, and a speech recognition system. The speech processing device can include a processing unit, a histogram pruning unit, and a pre-pruning unit. The processing unit is configured to calculate one or more Hidden Markov Model (HMM) pruning thresholds. The histogram pruning unit is configured to prune one or more HMM states to generate one or more active HMM states. The pruning is based on the one or more pruning thresholds. The pre-pruning unit is configured to prune the one or more active HMM states based on an adjustable pre-pruning threshold. Further, the adjustable pre-pruning threshold is based on the one or more pruning thresholds.
Embodiments of the present invention include a data storage device and a method for storing data in a hash table. The data storage device can include a first memory device, a second memory device, and a processing device. The first memory device is configured to store one or more data elements. The second memory device is configured to store one or more status bits at one or more respective table indices. In addition, each of the table indices is mapped to a corresponding table index in the first memory device. The processing device is configured to calculate one or more hash values based on the one or more data elements.
Embodiments of the present invention include an acoustic processing device and a method for traversing a Hidden Markov Model (HMM). The acoustic processing device can include a senone scoring unit (SSU), a memory device, a HMM module, and an interface module. The SSU is configured to receive feature vectors from an external computing device and to calculate senones. The memory device is configured to store the senone scores and HMM information, where the HMM information includes HMM IDs and HMM state scores. The HMM module is configured to traverse the HMM based on the senone scores and the HMM information. Further, the interface module is configured to transfer one or more HMM scoring requests from the external computing device to the HMM module and to transfer the HMM state scores to the external computing device.
Embodiments of the present invention include a substrate package, a method for multi-chip packaging, and a multi-chip package. For example, the substrate package includes a first set of reference markers and a second set of reference markers. The first set of reference markers is disposed on the substrate package, where the first set of reference markers is configured to provide a first alignment for positioning a first integrated circuit (IC) and a second alignment for positioning a second IC on the substrate package. Further, the second set of reference markers is disposed at a different location on the substrate package than the first set of reference markers, where the second set of reference markers is configured to provide confirmation of the first alignment and the second alignment.
H01L 21/77 - Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
H01L 23/544 - Marks applied to semiconductor devices, e.g. registration marks, test patterns
Embodiments of the present invention include an apparatus, method, and system for integrating data processing logic with memory. An embodiment of a memory integrated circuit is designed to execute a task on the data in a memory array within a memory integrated circuit. The memory integrated circuit can include a memory array, a data access component, a data holding component, and a logic component. The data access component can be coupled to the memory array and configured to provide an address to the memory array. The data holding component can be coupled to the memory array and configured to temporarily store the data in the memory array located at the address. The logic component can be coupled to both the data access component and the data holding component, and be configured to execute a task using data received from the data holding component. The logic component can include combinational or sequential logic.
Embodiments of the present invention include a substrate package, a method for multi-chip packaging, and a multi-chip package. For example, the substrate package includes a first set of reference markers and a second set of reference markers. The first set of reference markers is disposed on the substrate package, where the first set of reference markers is configured to provide a first alignment for positioning a first integrated circuit (IC) and a second alignment for positioning a second IC on the substrate package. Further, the second set of reference markers is disposed at a different location on the substrate package than the first set of reference markers, where the second set of reference markers is configured to provide confirmation of the first alignment and the second alignment.
Semiconductor devices and the manufacture of such semiconductor devices are described. According to various aspects of the disclosure, a semiconductor device can include a memory region, a first logic region, and a second logic region. A select gate can be formed in the memory region of the device and a first logic gate formed in the logic region. A charge trapping dielectric can then be disposed and removed from a second logic region. A gate conductor layer can then be disposed on the device and etched to define a memory gate on the sidewall of the select gate and a second logic gate in the second logic region.
Semiconductor devices and methods of manufacturing such devices are described herein. According to embodiments, a semiconductor device includes a memory gate disposed in a first region of the semiconductor device. The memory gate may include a first gate conductor layer disposed over a charge trapping dielectric. A select gate may be disposed in the first region of the semiconductor device adjacent to a side wall of the memory gate. A side wall dielectric may be disposed between the sidewall of the memory gate and the select gate. Additionally, the device may include a logic gate disposed in a second region of the semiconductor device that comprises the first gate conductor layer.
Embodiments described herein generally relate to methods of manufacturing charge- trapping memory by patterning the high voltage gates before other gates are formed. One advantage of such an approach is that a thin poly layer may be used to form memory and low voltage gates while protecting high voltage gates from implant penetration. One approach to accomplishing this is to dispose the layer of poly, and then dispose a mask and a thick resist to pattern the high voltage gates. In this manner, the high voltage gates are formed before either the low voltage gates or the memory cells.
Embodiments described herein generally relate to charge-trapping memory with improved isolation between a select gate and a memory gate. The isolation is improved because the charge trapping layer is not present in the junction between the select gate and the memory gate. The methods described herein additionally allow insulation to be disposed between the select gate and the memory gate.
Embodiments described herein generally relate to landing gate pads for contacts and manufacturing methods therefor. A bridge is formed between two features to allow a contact to be disposed, at least partially, on the bridge. Landing the contact on the bridge avoids additional manufacturing steps to create a target for a contact.
A semiconductor device and method of making such device is presented herein. The method includes disposing a gate layer over a dielectric layer on a substrate and further disposing a cap layer over the gate layer. A first transistor gate is defined having an initial thickness substantially equal to a combined thickness of the cap layer and the gate layer. A first doped region is formed in the substrate adjacent to the first transistor gate. The cap layer is subsequently removed and a second transistor gate is defined having a thickness substantially equal to the thickness of the gate layer. Afterwards, a second doped region is formed in the substrate adjacent to the second transistor gate. The first doped region extends deeper in the substrate than the second doped region, and a final thickness of the first transistor gate is substantially equal to the thickness of the second transistor gate.
Embodiments provide a split gate device, methods for fabricating a split gate device, and integrated methods for fabricating a split gate device and a periphery device. In an embodiment, the split gate device is a charge trapping split gate device, which includes a charge trapping layer. In another embodiment, the split gate device is a non-volatile memory cell, which can be formed according to embodiments as standalone or embedded with a periphery device.
Semiconductor devices and methods of manufacturing such devices are described herein. According to embodiments, the semiconductor device can be made by forming an dielectric layer at a first region and at a second region of a semiconductor substrate. A gate conductor layer is disposed over the dielectric formed in the first and the second regions of the semiconductor substrate, and the second region is masked. A split gate memory cell is formed in the first region of the semiconductor substrate with a first gate length. The first region is then masked, and the second region is etched to define a logic gate that has a second gate length. The first and second gate lengths can be different.
Integrated capacitor structures and methods for fabricating same are provided. In an embodiment, the integrated capacitor structures exploit the capacitance that can be formed in a plane that is perpendicular to that of the substrate, resulting in three-dimensional capacitor structures. This allows for integrated capacitor structures with higher capacitance to be formed over relatively small substrate areas. Embodiments are suitable for use by charge pumps and can be fabricated to have more or less capacitance as desired by the application.
A semiconductor device and method of making such device is presented herein. The semiconductor device includes a plurality of memory cells, a plurality of p-n junctions, and a metal trace of a first metal layer. Each of the plurality of memory cells includes a first gate disposed over a first dielectric, a second gate disposed over a second dielectric and adjacent to a sidewall of the first gate, a first doped region in the substrate adjacent to the first gate, and a second doped region in the substrate adjacent to the second gate. The plurality of p-n junctions are electrically isolated from the doped regions of each memory cell. The metal trace extends along a single plane between a via to the second gate of at least one memory cell in the plurality of memory cells, and a via to a p-n junction within the plurality of p-n junctions.
A semiconducting device utilizing air-gaps for inter-layer insulation and methods of producing the device are described. The device may be produced by forming a sacrificial layer between two structures. A porous membrane layer is then formed over the sacrificial layer. The membrane layer is porous to an etch product, which allows for the subsequent etching of the sacrificial layer leaving an air gap between the device structures and the membrane intact. The device may also include a cap layer formed above the device structures and the membrane.
H01L 21/31 - Treatment of semiconductor bodies using processes or apparatus not provided for in groups to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After-treatment of these layers; Selection of materials for these layers
49.
FORMING A SUBSTANTIALLY UNIFORM WING HEIGHT AMONG ELEMENTS IN A CHARGE TRAP SEMICONDUCTOR DEVICE
During formation of a charge trap separation in a semiconductor device, an organic material is formed over a plurality of cells. This organic material is selectively removed in order to create a flat upper surface. An etching process is performed to remove the organic material as well as a charge trap layer formed over the plurality of cells, thereby exposing underlying first oxide layers in each of the cells and forming charge trap separation. Further, because of the selective removal step, the etch results in substantially uniform wing heights among the separated cells.
During formation of a charge trap separation in a semiconductor device, a polymer deposition is formed in a reactor using a first chemistry. In a following step, a second chemistry can be used to etch the polymer deposition in the reactor. The same or similar second chemistry can be used in a second etching step to expose a first oxide layer in each of the cells of the semiconductor device and to form a flat upper surface. This additional etch step can also be performed by the reactor, thereby reducing the number of machines required in the formation process.
During formation of a charge trap separation in a semiconductor device, a polymer deposition is formed in a reactor using a first chemistry. In a following step, a second chemistry can be used to etch the polymer deposition in the reactor. The same or similar second chemistry can be used in a second etching step to expose a first oxide layer in each of the cells of the semiconductor device and to form a flat upper surface. This additional etch step can also be performed by the reactor, thereby reducing the number of machines required in the formation process.
A method and apparatus to evenly distribute gas over a wafer in batch processing. Several techniques are disclosed, such as, but not limited to, angling an injector to distribute gas towards a proximate edge of the wafer, and/or reducing the amount of overlap in the center of the wafer of gas from subsequent gas injections.
H01L 21/205 - Deposition of semiconductor materials on a substrate, e.g. epitaxial growth using reduction or decomposition of a gaseous compound yielding a solid condensate, i.e. chemical deposition
H01L 21/02 - Manufacture or treatment of semiconductor devices or of parts thereof
A. method of reducing read errors in a non-volatile memory device that result from bit- line or word-line disturb conditions generated by erase operations includes selecting a subset of a memory array for refresh after each erase operation. A pointer to the refresh target section is updated as part of the method to direct the refresh operation to the appropriate subset of the memory array. Refresh may be performed subsequent to an erase operation or concurrently therewith. By distributing the time consumed by refresh operations over many erase operations so the relative refresh time for any one erase becomes small.
A semiconductor processing method to provide a high quality bottom oxide layer and top oxide layer in a charged-trapping NAND and NOR flash memory. Both the bottom oxide layer and the top oxide layer of NAND and NOR flash memory determines array device performance and reliability. The method describes overcomes the corner thinning issue and the poor top oxide quality that results from the traditional oxidation approach of using pre-deposited silicon-rich nitride.
A method of processing a wafer in a production tool includes receiving a wafer at a process tool, the wafer associated with a wafer process history, acquiring data associate with wafers processed by the process tool and having the wafer process history, when the amount of acquired data is insufficient, acquiring additional data associated with wafers processed by the process tool and having a process history differing from the wafer process history by a single factor, when the amount of acquired data is sufficient, determining a process parameter using the acquired data, and processing the wafer with the production tool using the process parameter.
09 - Scientific and electric apparatus and instruments
Goods & Services
Semiconductors; integrated circuits; microcontrollers; applications software, utility software, and drivers in the nature of software, all of such software for functions associated with semiconductors, integrated circuits, and microcontrollers, namely, applications programs, software for use in industrial and manufactured goods' electronic systems, middleware that provides command and response translation between a microcontroller and network components, software tools for generation and configuration of run time software, programming, debugging and diagnostics, and drivers that function as interfaces between higher level software components and hardware resources
57.
WEAR LEVELING IN FLASH MEMORY DEVICES WITH TRIM COMMANDS
Systems and methods are provided to implement a memory device that includes a memory array having a plurality of sectors, a non-volatile memory that stores sector state information, and a memory controller that performs wear leveling according to the sector state information. The sector state information can specify respective states for respective sectors of the plurality of sectors of the memory array. The memory controller, based on the states of respective sectors, determines whether or not to swap contents of the sectors during wear leveling, thereby reducing write amplification effects.
Computer-based speech recognition can be improved by recognizing words with an accurate accent model. In order to provide a large number of possible accents, while providing real-time speech recognition, a language tree data structure of possible accents is provided in one embodiment such that a computerized speech recognition system can benefit from choosing among accent categories when searching for an appropriate accent model for speech recognition.
Embodiments of the present invention include an apparatus, method, and system for calculating senone scores for multiple concurrent input speech streams. The method can include the following: receiving one or more feature vectors from one or more input streams; accessing the acoustic model one senone at a time; and calculating separate senone scores corresponding to each incoming feature vector. The calculation uses a single read access to the acoustic model for a single senone and calculates a set of separate senone scores for the one or more feature vectors, before proceeding to the next senone in the acoustic model.
Embodiments of the present invention include an apparatus, method, and system for calculating senone scores for multiple concurrent input speech streams. The method can include the following: receiving one or more feature vectors from one or more input streams; accessing the acoustic model one senone at a time; and calculating separate senone scores corresponding to each incoming feature vector. The calculation uses a single read access to the acoustic model for a single senone and calculates a set of separate senone scores for the one or more feature vectors, before proceeding to the next senone in the acoustic model.
Charge-trapping field effect transistors may be formed into an array on a wafer suitable to be a NAND memory device. A thick oxide layer is applied over the gates to ensure that the gap between the gates is filled. The filled gap substantially prevents nitride from being trapped, which could otherwise decrease the yield of the devices. This technique, and its variations, are useful for a range of semiconductor devices.
Charge-trapping field effect transistors may be formed into an array on a wafer suitable to be a NAND memory device. A thick oxide layer is applied over the gates to ensure that the gap between the gates is filled. The filled gap substantially prevents nitride from being trapped, which could otherwise decrease the yield of the devices. This technique, and its variations, are useful for a range of semiconductor devices.
H01L 29/792 - Field-effect transistors with field effect produced by an insulated gate with charge trapping gate insulator, e.g. MNOS-memory transistor
63.
SUPPLY POWER DEPENDENT CONTROLLABLE WRITE THROUGHPUT FOR MEMORY APPLICATIONS
Devices and methods that allow dynamic management of throughput in a memory device based on a power supply voltage are provided. According to various embodiments, the power supply level can be monitored. Based on the result of the monitoring, an appropriate throughput can be determined. Once the appropriate throughput is determined, an appropriate control signal based on the determined throughput can be generated. The control signal can be configured to cause a bitline driver circuit in a memory array to activate a number of bitlines consistent with the determined throughput.
A semiconductor device includes a semiconductor chip, a connection electrode including a first land electrode electrically coupled with the semiconductor chip, and a through electrode formed on an upper surface of the first land electrode to be electrically coupled with the first land electrode using a stud bump, and a sealing resin, through which the connection electrode passes, for sealing the semiconductor chip.
H01L 23/522 - Arrangements for conducting electric current within the device in operation from one component to another including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
09 - Scientific and electric apparatus and instruments
Goods & Services
Interfaces for high speed throughput of data between a processor or microcontroller and other semiconductor devices; interfaces for high speed throughput of data between a processor or microcontroller and peripheral components
09 - Scientific and electric apparatus and instruments
Goods & Services
Non-volatile memory devices, namely, flash memory semiconductor chips and mass storage semiconductor chips; applications and utility software for functions associated with memory devices, namely, code and data management software, file system management software, flash memory semiconductor chip drivers, mass storage semiconductor chip drivers, flash media drivers, and block drivers
Systems and methods are provided to minimize write disturb conditions in an untargeted memory cell of a non-volatile memory array. Bitline driver circuits are provided to control a ramped voltage applied both to a bitline of a target memory cell and a neighboring bitline of an untargeted memory cell, Various embodiments advantageously maintain the integrity of data stored in the untargeted memory cells by applying a controlled voltage signal to a previously floating bitline of a neighbor cell to reduce a potential difference between the source and drain nodes of the untargeted. neighbor memory cell during a write operation at a target memory cell. In another embodiment, an increased source bias voltage is applied on a "source" bitline of the target cell during the ramping of the drain bias voltage and then reduced to a ground or near ground potential during the write operation.
Embodiments are directed to reduced power consumption for memory data transfer at high frequency through synchronized clock signaling. Delay locked loop (DLL) circuits are used to generate the synchronized clock signals. A DLL circuit consumes power as long as it is outputting the synchronized clock signals. A power saving apparatus and method are described wherein the DLL circuit is powered on when memory data access is active, while the DLL circuit is powered down when memory access is idle.
Methods and systems of fabricating a wordline protection structure are described. As described, the wordline protection structure includes a polysilicon structure formed adjacent to a memory core region. The polysilicon structure includes first doped region positioned on a core side of the polysilicon structure and a second doped region positioned on a spine side of the polysilicon structure. An un-doped region positioned between the first and second doped regions. A conductive layer is formed on top of the polysilicon structure and arranged so that it does not contact the un-doped region at either the transition between the first doped region and the un-doped region or the second doped region and un-doped region.
H01L 27/04 - Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body
A method and apparatus for continuously rounded charge trapping layer formation in a flash memory device. The memory device includes a semiconductor layer, including a source/drain region. An isolation region is disposed adjacent to the source/drain region. A first insulator is disposed above the source/drain region. A charge trapping layer is disposed within the first insulator, wherein the charge trapping layer comprises a bulk portion and a first tip and a second tip on either side of said bulk portion, wherein said charge trapping layer extends beyond the width of the source/drain region. A second insulator is disposed above the charge trapping layer. A polysilicon gate structure is disposed above the second insulator, wherein a width of said control gate is wider than the width of said source/drain region.
A semiconductor device with efficient heat dissipating structures is disclosed. The semiconductor device includes a first semiconductor chip that is flip-chip mounted on a first substrate, a heat absorption portion that is formed between the first semiconductor chip and the first substrate, an outer connection portion that connects the first semiconductor chip to an external device and a heat conduction portion formed between the heat absorption portion and the outer connection portion to dissipate heat generated by the first semiconductor chip.
H01L 21/48 - Manufacture or treatment of parts, e.g. containers, prior to assembly of the devices, using processes not provided for in a single one of the groups
A voice activation system is provided. The voice activation system includes a first stage configured to output a first activation signal if at least one energy characteristic of a received audio signal satisfies at least one threshold and a second stage configured to transition from a first state to a second state in response to the first activation signal and, when in the second state, to output a second activation signal if at least a portion of a profile of the audio signal substantially matches at least one predetermined profile.
A method, apparatus, and manufacture for a memory device is provided. The memory device includes a memory cell region including sectors, where each sector includes memory cells. The memory device further includes a memory controller that is configured to control program operations and erase operations to the memory cells. During erase operations to the memory cells, pre-programming occurs in which each un-programmed memory cell in the sector being erased is programmed by applying at least one programming pulse at a program voltage until a program verify passes. Then, the program voltage is adjusted based on the number of programming pulses applied until the program-verify passed. During subsequent program operations in that sector, programming pulses are applied with the adjusted program voltage.
A method for double patterning is disclosed. In one embodiment the formation a pair of select gate wordlines on either side of a plurality of core wordlines begins by placing a spacer pattern around edges of a photoresist pattern is disclosed. The photoresist pattern is stripped away leaving the spacer pattern. A trim mask is placed over a portion of the spacer pattern. Portions of the spacer pattern are etched away that are not covered by the trim mask. The trim mask is removed, wherein first remaining portions of the spacer pattern define a plurality of core wordlines. A pad mask is placed such that the pad mask and second remaining portions of the spacer pattern define a select gate wordline on either side of the plurality of core wordlines. Finally at least one pattern transfer layer is etched through using the mad mask and the first and second remaining portions of the spacer pattern to etch the select gate wordlines and the plurality of core wordlines into a poly silicon layer.
H01L 21/302 - Treatment of semiconductor bodies using processes or apparatus not provided for in groups to change the physical characteristics of their surfaces, or to change their shape, e.g. etching, polishing, cutting
H01L 21/3213 - Physical or chemical etching of the layers, e.g. to produce a patterned layer from a pre-deposited extensive layer
H01L 21/033 - Making masks on semiconductor bodies for further photolithographic processing, not provided for in group or comprising inorganic layers
An assembly includes an integrated circuit, a film layer disposed over the integrated circuit and having a thickness of at least 50 microns, and a thermal neutron absorber layer comprising at least 0,5% thermal neutron absorber, The thermal neutron absorber layer can be a glass layer or can include a molding compound.
A semiconductor device which includes a first semiconductor chip, a second semiconductor chip flip-chip bonded to the first semiconductor chip, a resin portion for sealing the first semiconductor chip and the second semiconductor chip such that a lower surface of the first semiconductor chip and an upper surface of the second semiconductor chip are exposed and a side surface of the first semiconductor chip is covered, and a post electrode which pierces the resin portion and is connected to the first semiconductor chip, and a manufacturing method thereof are provided.
The semiconductor device according to the present invention has a planar semiconductor chip having projecting connection terminals provided on one surface thereof. A shelf is provided where a peripheral edge of a surface of the semiconductor chip opposite one surface thereof onto which connection terminals are provided is removed. This makes it possible to secure a larger volume of the fillet portion of the underfill, thereby helping improve the function of preventing the rising up of the excess underfill by providing a shelf in the semiconductor chip.
Embodiments described herein generally relate to programming and erasing a FLASH memory. In an embodiment, a method of programming or erasing the contents of a block of a FLASH memory includes determining a voltage of a pulse based on an age of the block and outputting the pulse to at least a portion of the block. The pulse is used to program or erase the block.
A semiconductor device (400) for improved charge dissipation protection includes a substrate (426), a layer of semiconductive or conductive material (406), one or more thin film devices (408) and a charge passage device (414). The thin film devices (408) are connected to the semiconductive or conductive layer (406) and the charge passage device (414) is coupled to the thin film devices (408) and to the substrate (426) and provides a connection from the thin film devices (408) to the substrate (426) to dissipate charge from the semiconductive/conductive layer (406) to the substrate (426).
H01L 21/768 - Applying interconnections to be used for carrying current between separate components within a device
G11C 8/08 - Word line control circuits, e.g. drivers, boosters, pull-up circuits, pull-down circuits, precharging circuits, for word lines
G11C 8/14 - Word line organisation; Word line lay-out
H01L 27/02 - Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including integrated passive circuit elements with at least one potential-jump barrier or surface barrier
A system comprising a processor and a memory, wherein said memory comprises instructions that when executed by said processor implement a method. The method includes loading a first portion of a set of redundancy data into a register of the processor for each redundant sector of a plurality of redundant sectors. A second portion of a set of redundancy data is also loaded into the volatile memory for each redundant sector of the plurality of redundant sectors. Loading the second portions of the sets of redundancy data comprises loading a third portion of redundancy data comprising a plurality of second portions of redundancy data for the plurality of redundant sectors.
Embodiments of the present invention include an apparatus, method, and system for acoustic modeling. The apparatus can include a senone scoring unit (SSU) control module, a distance calculator, and an addition module. The SSU control module can be configured to receive a feature vector. The distance calculator can be configured to receive a plurality of Gaussian probability distributions via a data bus having a width of at least one Gaussian probability distribution and the feature vector from the SSU control module. The distance calculator can include a plurality of arithmetic logic units to calculate a plurality of dimension distance scores and an accumulator to sum the dimension distance scores to generate a Gaussian distance score. Further, the addition module is configured to sum a plurality of Gaussian distance scores to generate a senone score.
Embodiments of the present invention include an apparatus, method, and system for acoustic modeling. In an embodiment, a speech recognition system is provided. The system includes a processing unit configured to divide a received audio signal into consecutive frames having respective frame vectors, an acoustic processing unit (APU), a data bus that couples the processing unit and the APU. The APU includes a local, non-volatile memory that stores a plurality of senones, a memory buffer coupled to the memory, the acoustic processing unit being configured to load at least one Gaussian probability distribution vector stored in the memory into the memory buffer, and a scoring unit configured to simultaneously compare a plurality of dimensions of a Gaussian probability distribution vector loaded into the memory buffer with respective dimensions of a frame vector received from the processing unit and to output a corresponding score to the processing unit. The APU is configured to perform a comparison using a first frame while the processing unit performs a search operation using a score corresponding to a second frame, the second frame immediately preceding the first frame.
Embodiments of the present invention include an apparatus, method, and system for acoustic modeling. In an embodiment, an arithmetic logic unit for computing a one-dimensional score between a feature vector and a Gaussian probability distribution vector is provided. The arithmetic logic unit includes a computational logic unit configured to compute a first value based on a mean value and a variance value associated with a dimension of the Gaussian probability distribution vector and a dimension of a feature vector, a look up table module configured to output a second value based on the variance value, and a combination module configured to combine the first value and the second value to generate the one-dimensional score.
G06F 7/57 - Arithmetic logic units [ALU], i.e. arrangements or devices for performing two or more of the operations covered by groups or for performing logical operations
Embodiments of the present invention include an apparatus, method, and system for acoustic modeling. In an embodiment, an arithmetic logic unit for computing a one-dimensional score between a feature vector and a Gaussian probability distribution vector is provided. The arithmetic logic unit includes a computational logic unit configured to compute a first value based on a mean value and a variance value associated with a dimension of the Gaussian probability distribution vector and a dimension of a feature vector, a look up table module configured to output a second value based on the variance value, and a combination module configured to combine the first value and the second value to generate the one-dimensional score.
G06F 7/38 - Methods or arrangements for performing computations using exclusively denominational number representation, e.g. using binary, ternary, decimal representation
G10L 15/187 - Phonemic context, e.g. pronunciation rules, phonotactical constraints or phoneme n-grams
G10L 15/28 - Constructional details of speech recognition systems
A memory subsystem is disclosed. The memory subsystem includes a serial peripheral interface (SPI) double data rate (DDR) volatile memory component (203), a serial peripheral interface (SPI) double data rate (DDR) non-volatile memory component (201 ) coupled to the serial peripheral interface (SPI) double data rate (DDR) volatile memory component and a serial peripheral interface (SPI) double data rate (DDR) interface (205a-c). The serial peripheral interface (SPI) double data rate (DDR) interface (205a-c) accesses the serial peripheral interface (SPI) double data rate (DDR) volatile memory component (203) and the serial peripheral interface (SPI) double data rate (DDR) non-volatile memory component (201) where data is accessed on leading and falling edges of a clock signal.
A method of manufacturing a non-volatile memory device includes forming a number of memory cells. The method also includes depositing a first dielectric layer over the memory cells, where the first dielectric layer is a conformal layer having a substantially uniform thickness. The method further includes depositing a second dielectric layer over the first dielectric layer. Together, the first and second dielectric layers form an interlayer dielectric without voids.
Wire bonds are formed at an integrated circuit device so that multiple wires are bonded to a single bond pad. In a particular embodiment, the multiple wires are bonded by first applying a stud bump to the pad and successively bonding each of the wires to the stud bump. Another stud bump can be placed over the bonded wires to provide additional connection security.
Processing of masked data using table lookups is described. A mask is applied to input data to generate masked input data. The mask and the masked input data are used in combination to locate an entry in a lookup table. The entry corresponds to a transformed version of the input data.
Memory cell regions as units of erasing operation are sectors S, and units of reading operation and/or writing operation are blocks B0 to B3 in a sector, in which a block address BA for selecting one of blocks B0 to B3 is held in block address buffer (BAB) 3. Holding operation is executed prior to reading or writing operation, and hence in subsequent reading operation or writing operation, re-input is not needed. Depending on the held block address BA, any one of selection signals YDn (n=0 to 3) is selected, and any one block is selected depending on the selection signal YDn. This state is maintained until the block address BA held in the block address buffer (BAB) 3 is rewritten, and therefore it is not required to enter or decode the block address BA on every occasion of reading and/or writing operation, so that the access operation can be executed promptly and at low current consumption.
A DC-DC converter or the like capable of generating a stable output voltage is provided. A control circuit 11 of a current mode step-down DC-DC converter 1 includes a slope compensation circuit SC and an offset circuit IF1. The slope compensation circuit SC adds an increase gradient m2 due to slope compensation to an increase gradient of a coil current waveform Vsense in a range wherein an ON period Ton of a switch SW1 exceeds ½ of an operating cycle T. An offset circuit IF1 applies an offset voltage Voffset which becomes smaller depending on the ON period Ton in excess of ½ of an operating cycle T, to a coil current waveform Vsense.
G05F 1/565 - Regulating voltage or current wherein the variable actually regulated by the final control device is dc using semiconductor devices in series with the load as final control devices sensing a condition of the system or its load in addition to means responsive to deviations in the output of the system, e.g. current, voltage, power factor
G05F 1/00 - Automatic systems in which deviations of an electric quantity from one or more predetermined values are detected at the output of the system and fed back to a device within the system to restore the detected quantity to its predetermined value or val
During semiconductor fabrication homogeneous gap-filling is achieved by depositing a thin dielectric layer into the gap, post deposition curing, and then repeating deposition and post deposition curing until gap-filling is completed. Embodiments include depositing a layer of low deposition temperature gap-fill dielectric into a high aspect ratio opening, such as a shallow trench or a gap between closely spaced apart gate electrode structures, as at a thickness of about 10 Å to about 500 Å, curing after deposition, as by UV radiation or by heating at a temperature of about 400° C. to about 1000° C., depositing another layer of low deposition temperature gap-filled dielectric, and curing after deposition. Embodiments include separately depositing and separately curing multiple layers.
H01L 21/31 - Treatment of semiconductor bodies using processes or apparatus not provided for in groups to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After-treatment of these layers; Selection of materials for these layers
H01L 21/469 - Treatment of semiconductor bodies using processes or apparatus not provided for in groups to change their surface-physical characteristics or shape, e.g. etching, polishing, cutting to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After-treatment of these layers
An arithmetic operation circuit provided in a delta-sigma modulator of a delta-sigma A/D converter includes two reference capacitors which are respectively provided at a positive side input node and a negative side input node of an operational amplifier. When a signal corresponding to an output of the modulator is added or subtracted to or from an input signal, the amount of charge added to the input node of the operational amplifier is made to be always the same regardless of the reference voltage by complementarily switching the connection of the reference capacitors at the positive side input node and the negative side input node, and thereby the potential of the input node of the operational amplifier is made to converge to the common mode potential of the circuit.
A method of manufacturing a non-volatile memory device includes forming a number of memory cells. The method also includes depositing a first dielectric layer over the memory cells, where the first dielectric layer is a conformal layer having a substantially uniform thickness. The method further includes depositing a second dielectric layer over the first dielectric layer. Together, the first and second dielectric layers form an interlayer dielectric without voids.
A phase locked loop (PLL) circuit including a phase comparator for comparing a phase of a reference signal with a phase of a feedback signal, an oscillator for outputting an output signal at a frequency in accordance with an output of the phase comparator, a feedback loop for returning the output signal of the oscillator and supplying the output signal as the feedback signal, and a delay circuit for delaying the phase of the output signal output from the oscillator to a load circuit, wherein the delay circuit is provided outside the feedback loop.
The claimed subject matter can provide an architecture that interfaces a single slave device such as a UICC smartcard with multiple host controllers. For example, a secondary host can be interfaced between a primary host (e.g., a controller in a cellular phone, a PDA, an MP3 player . . . ) to manage all transactions with the slave device. The secondary host can operate transparently to the primary host and thus does not require any modifications to the primary host. This can be accomplished, e.g., by employing the CMD channel (which is relatively sparsely used by the primary host) to communicate both commands and data with the slave.
A semiconductor apparatus is presented that includes an array of memory cells. The memory cells are arranged in rows and columns. Non-intersecting shallow trench isolation regions isolate the columns of memory cells. Also included is at least one source region that is isolated between an adjoining pair of the non-intersecting shallow trench isolation regions and isolated from a drain region. The source region is coupled to source lines in the array of memory cells. A contact couples a select plurality of the columns of memory cells, the select plurality functioning as a single content addressable memory cell.
A semiconductor device includes a nonvolatile memory, and an interface configured to transfer data to and from the nonvolatile memory. The interface includes a security logic unit which controls a security level for the data written to the nonvolatile memory, in accordance with a plurality of preset security codes and a lock code that is written to a specific area in the nonvolatile memory.
An electronic device includes a substrate with a semiconducting surface having a plurality of fin-type projections coextending in a first direction through a memory cell region and select gate regions. The electronic device further includes a dielectric isolation material disposed in spaces between the projections. In the electronic device, the dielectric isolation material in the memory cell regions have a height less than a height of the projections in the memory cell regions, and the dielectric isolation material in the select gate regions have a height greater than or equal to than a height of the projections in the select gate regions. The electronic device further includes gate features disposed on the substrate within the memory cell region and the select gate regions over the projections and the dielectric isolation material, where the gate features coextend in a second direction transverse to the first direction.
H01L 27/105 - Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body including a plurality of individual components in a repetitive configuration including field-effect components
09 - Scientific and electric apparatus and instruments
42 - Scientific, technological and industrial services, research and design
Goods & Services
[ Computer programs featuring simulation and behavioral modeling functions for use in power circuit design; downloadable simulation and behavioral modeling computer programs for use in power circuit design ] Design and development of integrated circuits; providing non-downloadable simulation and behavioral modeling programs for power circuit design
