Advantest Corporation

Japan

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G01R 31/28 - Testing of electronic circuits, e.g. by signal tracer 556
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1.

SEMICONDUCTOR APPARATUS AND METHOD FOR MANUFACTURING SEMICONDUCTOR APPARATUS

      
Application Number 18450420
Status Pending
Filing Date 2023-08-15
First Publication Date 2024-04-25
Owner
  • ADVANTEST CORPORATION (Japan)
  • Tokyo Institute of Technology (Japan)
Inventor
  • Sugatani, Shinji
  • Ohba, Takayuki
  • Sakui, Koji
  • Chujo, Norio

Abstract

To provide a semiconductor apparatus including a transistor element layer having a plurality of transistors which are multi-gate transistors of a floating body structure, a first wiring layer having at least one signal line which electrically connects between a source and a gate or between a drain and a gate of at least one pair of transistors among the plurality of transistors, the first wiring layer being laminated on the side of one surface of the transistor element layer, and a second wiring layer having at least one signal line which electrically connects between a source and a gate or between a drain and a gate of at least another pair of transistors among the plurality of transistors, the second wiring layer being laminated on the side of another surface of the transistor element layer.

IPC Classes  ?

  • H01L 23/528 - Layout of the interconnection structure
  • H01L 21/8238 - Complementary field-effect transistors, e.g. CMOS
  • H01L 27/092 - Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only the components being field-effect transistors with insulated gate complementary MIS field-effect transistors
  • H01L 29/06 - Semiconductor bodies characterised by the shapes, relative sizes, or dispositions of the semiconductor regions
  • H01L 29/423 - Electrodes characterised by their shape, relative sizes or dispositions not carrying the current to be rectified, amplified or switched
  • H01L 29/775 - Field-effect transistors with one-dimensional charge carrier gas channel, e.g. quantum wire FET

2.

MAGNETICALLY RETAINED REPLACEABLE CYLINDER COMPONENT FOR PICK-AND-PLACE TEST HEAD UNIT

      
Application Number 18379063
Status Pending
Filing Date 2023-10-10
First Publication Date 2024-04-25
Owner ADVANTEST CORPORATION (Japan)
Inventor
  • Sherman, Patrick
  • Wagner, Don
  • Akiya, Moritoshi

Abstract

Embodiments of the present invention provide a magnetically retained replaceable contact plate assembly. The magnetically retained replaceable contact plate assembly includes a contact chuck interface. The contact chuck is configured to physically mate with a device under test (DUT). The magnetically retained replaceable contact plate assembly also includes a DUT layout unit interface (DLU). The DLU is configured to couple to multiple magnetically retained replaceable contact plate assemblies and to a semiconductor handler unit. The DLU is configured to move DUTs within a test environment, and the magnetically retained replaceable contact plate assembly is configured to magnetically attach to said DLU.

IPC Classes  ?

  • B25J 15/04 - Gripping heads with provision for the remote detachment or exchange of the head or parts thereof
  • B25J 15/06 - Gripping heads with vacuum or magnetic holding means
  • B65G 47/91 - Devices for picking-up and depositing articles or materials incorporating pneumatic, e.g. suction, grippers

3.

MAGNETICALLY RETAINED REPLACEABLE CHUCK ASSEMBLY FOR PICK-AND-HOLD TEST HEAD UNIT

      
Application Number US2023035166
Publication Number 2024/086080
Status In Force
Filing Date 2023-10-14
Publication Date 2024-04-25
Owner ADVANTEST CORPORATION (Japan)
Inventor Sherman, Patrick

Abstract

Embodiments of the present invention provide a contact chuck test head for a handler of an integrated circuit tester system. The contact chuck test head comprises a magnetically held DUT contact unit that can be replaced by a technician without requiring any tool or special equipment. The contact chuck test head t is mounted to an automated handler. Magnets are employed at an interface between the DUT contact unit and contact chuck base. This allows the DUT contact unit to be brought into close proximity to the contact chuck base portion and magnetic forces act to both align and mate the two parts together. Since the DUT contact unit requires change out to accommodate different sizes and types of DUTs, it is advantageous to provide an easy swap-out mechanism.

IPC Classes  ?

  • G01R 31/28 - Testing of electronic circuits, e.g. by signal tracer

4.

MAGNETICALLY RETAINED REPLACEABLE CYLINDER COMPONENT FOR PICK-AND-PLACE TEST HEAD UNIT

      
Application Number US2023035165
Publication Number 2024/086079
Status In Force
Filing Date 2023-10-14
Publication Date 2024-04-25
Owner ADVANTEST CORPORATION (Japan)
Inventor
  • Wagner, Don
  • Akiya, Moritoshi

Abstract

Embodiments of the present invention provide a magnetically retained replaceable contact plate assembly. The magnetically retained replaceable contact plate assembly includes a contact chuck interface. The contact chuck is configured to physically mate with a device under test (DUT). The magnetically retained replaceable contact plate assembly also includes a DUT layout unit interface (DLU). The DLU is configured to couple to multiple magnetically retained replaceable contact plate assemblies and to a semiconductor handler unit. The DLU is configured to move DUTs within a test environment, and the magnetically retained replaceable contact plate assembly is configured to magnetically attach to said DLU.

IPC Classes  ?

  • G01R 31/28 - Testing of electronic circuits, e.g. by signal tracer

5.

STACKED CHIP AND FABRICATION METHOD OF STACKED CHIP

      
Application Number 18450435
Status Pending
Filing Date 2023-08-15
First Publication Date 2024-04-25
Owner
  • ADVANTEST CORPORATION (Japan)
  • Tokyo Institute of Technology (Japan)
Inventor
  • Sugatani, Shinji
  • Ohba, Takayuki
  • Chujo, Norio
  • Sakui, Koji
  • Fukuda, Tadashi

Abstract

A stacked chip is provided comprising a first semiconductor chip and a second semiconductor chip, wherein the first semiconductor chip has a first supporting substrate and a first circuit layer including a first region in which a first circuit is formed and a second region in which a second circuit is formed, the second semiconductor chip has a second supporting substrate, a second circuit layer including a third region that corresponds to a position of the first region and a fourth region that corresponds to a position of the second region and in which the second circuit is formed, a first embedded portion embedded in a first hole portion penetrating through the third region and extending to an inside of the second supporting substrate, and a first through via that penetrates through the first embedded portion and the second supporting substrate, and is electrically conducted with the first circuit.

IPC Classes  ?

  • H01L 23/00 - SEMICONDUCTOR DEVICES NOT COVERED BY CLASS - Details of semiconductor or other solid state devices
  • H01L 21/768 - Applying interconnections to be used for carrying current between separate components within a device
  • H01L 23/48 - Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads or terminal arrangements
  • H01L 23/522 - Arrangements for conducting electric current within the device in operation from one component to another including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body

6.

MAGNETICALLY RETAINED REPLACEABLE CHUCK ASSEMBLY FOR PICK-AND-HOLD TEST HEAD UNIT

      
Application Number 18379073
Status Pending
Filing Date 2023-10-10
First Publication Date 2024-04-25
Owner ADVANTEST CORPORATION (Japan)
Inventor Sherman, Patrick

Abstract

Embodiments of the present invention provide a contact chuck test head for a handler of an integrated circuit tester system. The contact chuck test head comprises a magnetically held DUT contact unit that can be replaced by a technician without requiring any tool or special equipment. The contact chuck test head t is mounted to an automated handler. Magnets are employed at an interface between the DUT contact unit and contact chuck base. This allows the DUT contact unit to be brought into close proximity to the contact chuck base portion and magnetic forces act to both align and mate the two parts together. Since the DUT contact unit requires change out to accommodate different sizes and types of DUTs, it is advantageous to provide an easy swap-out mechanism.

IPC Classes  ?

  • G01R 31/28 - Testing of electronic circuits, e.g. by signal tracer
  • B65G 47/90 - Devices for picking-up and depositing articles or materials

7.

OPTICAL WAVEGUIDE AND METHOD FOR MANUFACTURING OPTICAL WAVEGUIDE

      
Application Number JP2022039263
Publication Number 2024/084681
Status In Force
Filing Date 2022-10-21
Publication Date 2024-04-25
Owner
  • ADVANTEST CORPORATION (Japan)
  • NATIONAL INSTITUTE OF INFORMATION AND COMMUNICATIONS TECHNOLOGY (Japan)
Inventor
  • Seki Atsushi
  • Otomo Akira
  • Tominari Yukihiro

Abstract

Provided is an optical waveguide comprising: an optical propagation path that includes an organic electro-optic polymer material; and a layered structure that has a first layer that covers at least a portion of the optical propagation path and prevents oxygen permeation from outside toward the optical propagation path, and a second layer that prevents moisture permeation from outside toward the first layer. The first layer may include Al2O3 and the second layer may include SiO2. The layered structure may have a three-layer structure formed by stacking, in order, the second layer, the first layer, and a third layer that prevents moisture permeation from the optical propagation path toward the first layer.

IPC Classes  ?

  • G02F 1/065 - Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour based on electro-optical organic material in an optical waveguide structure

8.

PORE DEVICE AND FINE PARTICLE MEASUREMENT SYSTEM

      
Application Number 18485415
Status Pending
Filing Date 2023-10-12
First Publication Date 2024-04-18
Owner ADVANTEST CORPORATION (Japan)
Inventor
  • Imai, Yasuharu
  • Washizu, Nobuei
  • Oinuma, Kosuke

Abstract

A pore device is used with a measurement device. The pore device includes a pore chip and a chip case which has a chamber partitioned by the pore chip. A measurement terminal group is provided to apply an electric signal from the measurement device to the chamber and output an electric signal generated in the chamber to the measurement device. Interface means is connected to a nonvolatile memory such that the nonvolatile memory is accessible from an outside of the pore device.

IPC Classes  ?

9.

PROCESSOR TEST PATTERN GENERATION AND APPLICATION FOR TESTER SYSTEMS

      
Application Number 18230003
Status Pending
Filing Date 2023-08-03
First Publication Date 2024-04-11
Owner ADVANTEST CORPORATION (Japan)
Inventor
  • De La Puente, Edmundo
  • Su, Mei-Mei
  • Malisic, Srdjan

Abstract

A tester system includes a test computer system for coordinating and controlling testing of a plurality of devices under test (DUTs) and a hardware interface module coupled to the test computer system and controlled by the test computer system, the hardware interface module operable to apply test input signals to the plurality of DUTs and operable to receive test output signals from the plurality of DUTs. The hardware interface module includes a memory for storing instructions and data, a high performance processor coupled to the memory, the high performance processor operable to perform testing functionality at high speed for application of test signals to the plurality of DUTs, the high performance processor operable to perform the testing functionality under control of instructions and data from the memory and under control from software commands from the test computer system, wherein further the high performance processor is not natively capable of low power mode operation. The test system also includes a low power module coupled to and external to the high performance processor, the low power module capable of operating in at least one low power mode, the high performance processor for directing the low power module to configure the plurality of DUTs into at least one low power mode and further for testing the plurality of DUTs using commands and data in low power. The test system further includes driver hardware for applying the commands and data in low power to the plurality of DUTs which are configured for low power operation during the testing.

IPC Classes  ?

10.

TESTING APPARATUS, TESTING SYSTEM, TESTING METHOD, AND TESTING PROGRAM

      
Application Number JP2023028383
Publication Number 2024/075381
Status In Force
Filing Date 2023-08-03
Publication Date 2024-04-11
Owner ADVANTEST CORPORATION (Japan)
Inventor
  • Sugawara Toshihiro
  • Adachi Toshiaki

Abstract

Provided is a testing apparatus that comprises: an image data acquisition unit that acquires items of image data outputted by an image sensor as a device to be tested, in accordance with light having one or a plurality of emission patterns corresponding to a plurality of test items; an image processing control unit that transmits the one or plurality of items of image data acquired by the image data acquisition unit to two or more image processing devices, and causes image processing corresponding to separate test items in the plurality of test items to be executed in parallel by each of the two or more image processing devices; a test result acquisition unit that acquires test results of the test items corresponding to the image processing, which are derived from results of the image processing; and a determination unit that determines the quality of the device to be tested on the basis of the test results for each test item acquired by the test result acquisition unit.

IPC Classes  ?

  • G01R 31/26 - Testing of individual semiconductor devices
  • H01L 21/66 - Testing or measuring during manufacture or treatment

11.

TESTING APPARATUS, TESTING METHOD, AND COMPUTER-READABLE STORAGE MEDIUM

      
Application Number 18539320
Status Pending
Filing Date 2023-12-14
First Publication Date 2024-04-04
Owner ADVANTEST CORPORATION (Japan)
Inventor
  • Hasegawa, Kotaro
  • Miyauchi, Koji

Abstract

Provided is a testing apparatus including: a light emission control unit which causes a plurality of light emitting elements to be tested to emit light; a light measurement unit which receives the light emitted from the plurality of light emitting elements and measures wavelengths of the received light; and a determination unit which determines whether there is an abnormality in at least one light emitting element on the basis of intensity distributions of the wavelengths of the light, which is emitted from the plurality of light emitting elements, measured by the light measurement unit. The testing apparatus may further include: a light source; an optical system which irradiates the plurality of light emitting elements with light emitted from the light source; and an electrical measurement unit which measures a photoelectric signal obtained by each of the plurality of light emitting elements photoelectrically converting the light radiated by the optical system.

IPC Classes  ?

  • G01R 31/26 - Testing of individual semiconductor devices
  • G01R 31/28 - Testing of electronic circuits, e.g. by signal tracer

12.

MAGNETIC FIELD MEASURING APPARATUS

      
Application Number 18553598
Status Pending
Filing Date 2022-02-01
First Publication Date 2024-04-04
Owner ADVANTEST CORPORATION (Japan)
Inventor
  • Hata, Yoshiyuki
  • Hori, Hisao
  • Kakinuma, Bunichi

Abstract

A magnetic field measuring apparatus for measuring a to-be-measured magnetic field includes a magnetic impedance element with an impedance change rate that changes depending on the to-be-measured magnetic field, a drive signal providing section and a measurement range setting section. The drive signal providing section provides a drive signal to the magnetic impedance element. A measurement range setting section sets a measurement range in which the to-be-measured magnetic field can be measured. A relationship between the to-be-measured magnetic field and the impedance change rate is arranged to change depending on a frequency of the drive signal. The measurement range setting section is arranged to set the measurement range by setting the frequency.

IPC Classes  ?

  • G01R 33/06 - Measuring direction or magnitude of magnetic fields or magnetic flux using galvano-magnetic devices

13.

AN ANTENNA DEVICE AND AN AUTOMATED TEST EQUIPMENT

      
Application Number EP2022076877
Publication Number 2024/067957
Status In Force
Filing Date 2022-09-27
Publication Date 2024-04-04
Owner
  • ADVANTEST CORPORATION (Japan)
  • RADIO GIGABIT INC. (USA)
Inventor
  • Churkin, Sergey
  • Muravyev, Maxim
  • Bulygin, Nikita
  • Mozharovskiy, Andrey
  • Artemenko, Alexey

Abstract

The invention describes an antenna device, comprising: a printed circuit board, PCB, comprising an opening, wherein at least two probes are arranged on or in the printed circuit board orthogonally to each other; a cavity between a portion of the PCB carrying the probes and a waveguide backshort, the cavity forming a dual-polarized waveguide between the portion of the PCB carrying the probes and the waveguide backshort; wherein the opening in the printed circuit board is arranged in a central area around a central axis of the cavity; wherein the cavity has a depth of a quarter wavelength, λ/4, plus an integer multiple of a half wavelength. This invention provides the antenna design to be used in a socket for OTA testing using automated test equipment, which provides a large bandwidth.

IPC Classes  ?

  • G01R 1/04 - Housings; Supporting members; Arrangements of terminals
  • G01R 31/302 - Contactless testing
  • H01P 5/107 - Hollow-waveguide/strip-line transitions

14.

SYSTEM AND METHOD FOR RESERVING CLOUD-BASED INSTRUMENT

      
Application Number 18525900
Status Pending
Filing Date 2023-12-01
First Publication Date 2024-03-28
Owner ADVANTEST CORPORATION (Japan)
Inventor
  • Chu, Fang-Min
  • Liu, Lei

Abstract

A method for reserving a cloud-based instrument and adapted to a system for reserving an instrument is provided. The system includes a group of remote instruments with a plurality of remote instruments, a system for reserving an instrument, and a bastion server. The reservation information includes a plurality of reservable time periods and a plurality of reserved time periods. The method for reserving the cloud-based instrument includes: establishing a secure connection between the bastion server and the remote instrument designated in any one of the reserved time periods, establishing a dedicated connection between the designated remote instrument and a user workstation designated in any one of the reserved time periods at start of any one of the reserved time periods according to pairing information and the reservation information, and terminating the secure connection and the dedicated connection at end of any one of the reserved time periods.

IPC Classes  ?

  • G06Q 10/02 - Reservations, e.g. for tickets, services or events

15.

TEST SYSTEM CONFIGURATION ADAPTER SYSTEMS AND METHODS

      
Application Number 18528548
Status Pending
Filing Date 2023-12-04
First Publication Date 2024-03-28
Owner Advantest Corporation (Japan)
Inventor Chow, Eddy Wayne

Abstract

Presented embodiments facilitate efficient and effective flexible implementation of different types of testing procedures in a test system. In one embodiment, a test system configuration adapter includes a tester side socket, a break out pin, and a device under test side slot. The tester side socket is configured to couple with a test equipment socket. The break out pin is configured to couple with the supplemental equipment. The device under test side slot is configured to couple with the tester side socket, the break out pin, and a device under test, wherein the tester side socket. The test system configuration adapter is configured to enable communication between test equipment coupled to the test equipment socket and supplemental equipment coupled to the breakout pin while the device under test remains coupled to the device under test side slot. In one exemplary implementation, the breakout pin and tester side socket are selectively coupled to the device under test side slot. The test system configuration adapter can include a switch configured to switch a portion of the coupling of the device under test side slot to the tester side socket and the break out pin.

IPC Classes  ?

  • G01R 1/04 - Housings; Supporting members; Arrangements of terminals
  • G01R 31/3185 - Reconfiguring for testing, e.g. LSSD, partitioning
  • G01R 31/319 - Tester hardware, i.e. output processing circuits

16.

MANAGEMENT OF HOT ADD IN A TESTING ENVIRONMENT FOR DUTs THAT ARE CXL PROTOCOL ENABLED

      
Application Number 18129381
Status Pending
Filing Date 2023-03-31
First Publication Date 2024-03-21
Owner ADVANTEST CORPORATION (Japan)
Inventor
  • Malisic, Srdjan
  • Yuan, Chi
  • Qiu, Rebecca
  • Chen, Jenny

Abstract

Efficient and effective testing systems and methods are presented. In one embodiment, a system includes: a user interface configured to enable user interaction with the system; a test board configured to communicatively couple with a plurality of devices under test (DUTs), wherein the DUTs are compute express link (CXL) protocol compliant; and a tester configured to direct testing of the plurality of DUTs, wherein the tester is configured to enable hot add of one of the plurality of DUTs without interfering with testing of the other DUTS. In one exemplary implementation, the DUTs are memory devices and the DUTs can operate as extended memory. The user interface can be utilized to indicate a pause to remove a DUT and to indicate a DUT has been added and to trigger a re-start. The added one of the plurality of DUTs can be automatically recognized by a host in a way that is transparent to users. The tester automatically directs the hot add in response to a user trigger. In one embodiment, basic input/output system (BIOS) operations direct detection of characteristics associated with the added one of the plurality of DUTs.

IPC Classes  ?

17.

CXL PROTOCOL ENABLEMENT FOR TEST ENVIRONMENT SYSTEMS AND METHODS

      
Application Number 18129394
Status Pending
Filing Date 2023-03-31
First Publication Date 2024-03-21
Owner ADVANTEST CORPORATION (Japan)
Inventor
  • Malisic, Srdjan
  • Yuan, Chi
  • Chen, Jenny

Abstract

Efficient and effective testing systems and methods are presented. In one embodiment, a testing system includes: a user interface configured to enable user interaction with the system; a test board configured to communicatively couple with a plurality of devices under test (DUTs), wherein the DUTs are compute express link (CXL) protocol compliant; and a tester configured to direct testing of the plurality of DUTs, wherein the tester manages testing of the plurality of DUTs, including managing CXL protocol aspects of the testing. In one exemplary implementation, the tester prevents testing of a first one of the plurality of DUTs from detrimentally interfering with testing of a second one of the plurality of DUTs.

IPC Classes  ?

  • G06F 11/22 - Detection or location of defective computer hardware by testing during standby operation or during idle time, e.g. start-up testing
  • G06F 11/273 - Tester hardware, i.e. output processing circuits

18.

LOW POWER ENVIRONMENT FOR HIGH PERFORMANCE PROCESSOR WITHOUT LOW POWER MODE

      
Application Number 18229965
Status Pending
Filing Date 2023-08-03
First Publication Date 2024-03-21
Owner ADVANTEST CORPORATION (Japan)
Inventor
  • De La Puente, Edmundo
  • Hsu, Linden
  • Su, Mei-Mei
  • Kushnick, Marilyn

Abstract

A tester system includes a test computer system for coordinating and controlling testing of a plurality of devices under test (DUTs) and a hardware interface module coupled to the test computer system and controlled by the test computer system, the hardware interface module operable to apply test input signals to the plurality of DUTs and operable to receive test output signals from the plurality of DUTs. The hardware interface module includes a memory for storing instructions and data, a high performance processor coupled to the memory, the high performance processor operable to perform testing functionality at high speed for application of test signals to the plurality of DUTs, the high performance processor operable to perform the testing functionality under control of instructions and data from the memory and under control from software commands from the test computer system, wherein further the high performance processor is not natively capable of low power mode operation. The test system also includes a low power module coupled to and external to the high performance processor, the low power module capable of operating in at least one low power mode, the high performance processor for directing the low power module to configure the plurality of DUTs into at least one low power mode and further for testing the plurality of DUTs using commands and data in low power. The test system further includes driver hardware for applying the commands and data in low power to the plurality of DUTs which are configured for low power operation during the testing.

IPC Classes  ?

  • G01R 31/317 - Testing of digital circuits
  • G01R 31/3183 - Generation of test inputs, e.g. test vectors, patterns or sequences

19.

MEMORY QUEUE OPERATIONS TO INCREASE THROUGHPUT IN AN ATE SYSTEM

      
Application Number 18229981
Status Pending
Filing Date 2023-08-03
First Publication Date 2024-03-21
Owner ADVANTEST CORPORATION (Japan)
Inventor
  • De La Puente, Edmundo
  • Malisic, Srdjan

Abstract

A tester system includes a test computer system for coordinating and controlling testing of a plurality of devices under test (DUTs), and a hardware interface board coupled to the test computer system and controlled by the test computer system. The hardware interface board is operable to apply test input signals to the plurality of DUTs and operable to receive test output signals from the plurality of DUTs, the hardware interface board including: a processor operable to access test pattern data for application to a DUT. The tester system also includes a memory coupled to the processor and including a plurality of buffers, the plurality of buffers organized into a first-in-first-out (FIFO) memory queue including a buffer front end and a buffer back end, the plurality of buffers operable to receive the test pattern data from the processor at the buffer front end, a direct memory access (DMA) engine coupled to the memory and operable for reading data out of the buffer back end and supplying test pattern data to the DUT, a buffer table for maintaining a buffer sequence within the plurality of buffers and for maintaining vacancy and occupancy information regarding the plurality of buffers, and driver hardware coupled to the DMA engine and operable to receive the test pattern data and for driving the test input signals to the plurality of DUTs.

IPC Classes  ?

  • G11C 29/36 - Data generation devices, e.g. data inverters
  • G11C 29/10 - Test algorithms, e.g. memory scan [MScan] algorithms; Test patterns, e.g. checkerboard patterns

20.

SIGNAL VECTOR DERIVATION APPARATUS, METHOD, PROGRAM, AND RECORDING MEDIUM

      
Application Number 18272888
Status Pending
Filing Date 2022-03-07
First Publication Date 2024-03-21
Owner ADVANTEST CORPORATION (Japan)
Inventor
  • Ogata, Yuji
  • Yanagida, Tomonori

Abstract

A signal vector derivation apparatus receives measurement results from a plurality of sensors that receive signals each represented by a vector having a predetermined direction and measure triaxial components orthogonal to each other and derives the direction of the vector. The measurement results from the sensors are each proportional to a sum of the triaxial components of the vector multiplied, respectively, by first coefficients. The signal vector derivation apparatus includes a spectrum deriving section and a direction deriving section. The spectrum deriving section derives a spectrum obtained based on the measurement results from the sensors and a sum of the first coefficients multiplied, respectively, by second coefficients, the spectrum having local maximum values within voxels in which signal sources that output the respective signals exist. The direction deriving section derives the direction of the vector based on the second coefficients used to obtain the spectrum.

IPC Classes  ?

  • G01R 33/02 - Measuring direction or magnitude of magnetic fields or magnetic flux

21.

A PUSHER FOR USE IN AN AUTOMATED TEST EQUIPMENT AND METHOD FOR MECHANICALLY PUSHING A DEVICE UNDER TEST INTO A TEST SOCKET

      
Application Number EP2022075586
Publication Number 2024/056173
Status In Force
Filing Date 2022-09-14
Publication Date 2024-03-21
Owner
  • ADVANTEST CORPORATION (Japan)
  • UNIVERSITÄT STUTTGART (Germany)
Inventor
  • Hesselbarth, Jan
  • Moreira, José

Abstract

An embodiment according to the invention comprises a pusher (140, 240, 340, 520, 720) for use in an automated test equipment (ATE) to mechanically push a device under test, DUT (110) comprising an antenna or an antenna array into a DUT socket (130). The pusher (140, 240, 340, 520, 720) comprise relatively higher permittivity dielectric regions (160a, 260a, 560a) and relatively lower permittivity dielectric regions (160b, 260b, 560b). The relatively higher permittivity dielectric regions (160a, 260a, 560a) and the relatively lower permittivity dielectric regions (160b, 260b, 560b) are forming a structure of higher permittivity dielectric predominantly parallel columns (160a, 260a, 560a), e.g., rods or pillars or poles, with lower permittivity dielectric regions (160b, 260b, 560b) between these columns. Alternatively, the relatively higher permittivity dielectric regions (160a, 260a, 560a) and the relatively lower permittivity dielectric regions (160b, 260b, 560b) are forming a structure of a higher permittivity dielectric block with lower permittivity dielectric predominantly parallel filled or unfilled holes (160b, 260b, 560b). The higher permittivity dielectric columns (160a, 260a, 560a) or the lower permittivity dielectric holes (160b, 260b, 560b) extend in a first direction(170, 270), which is within ± 45° of a pushing direction (170, 270).

IPC Classes  ?

  • G01R 1/04 - Housings; Supporting members; Arrangements of terminals
  • G01R 29/10 - Radiation diagrams of antennas
  • G01R 31/28 - Testing of electronic circuits, e.g. by signal tracer

22.

SYSTEMS AND METHODS OF TESTING DEVICES USING CXL FOR INCREASED PARALLELISM

      
Application Number 18105792
Status Pending
Filing Date 2023-02-03
First Publication Date 2024-03-21
Owner ADVANTEST CORPORATION (Japan)
Inventor De La Puente, Edmundo

Abstract

Embodiments of the present invention can selectively enable 16 lane (×16) or 8 lane (×8) device testing using multiplexor circuitry disposed between a CXL1.1 CPU and the DUTs during testing. In this way, parallelism and testing efficiency are significantly improved compared to existing approaches that can only test devices using 8 lanes of the CXL 1.1 CPU.

IPC Classes  ?

  • G01R 31/319 - Tester hardware, i.e. output processing circuits

23.

SYSTEMS AND METHODS FOR TESTING CXL ENABLED DEVICES IN PARALLEL

      
Application Number 18129414
Status Pending
Filing Date 2023-03-31
First Publication Date 2024-03-21
Owner ADVANTEST CORPORATION (Japan)
Inventor
  • Malisic, Srdjan
  • Yuan, Chi

Abstract

Efficient and effective testing systems and methods are presented. In one embodiment, a test system includes: a user interface configured to enable user interaction with the system; a test board configured to communicatively couple with a plurality of devices under test (DUTs), wherein the DUTs are compute express link (CXL) protocol compliant; and a tester configured to direct testing of the plurality of DUTs, wherein the tester manages testing of the plurality of DUTs, including managing flexible and independent parallel testing across the plurality of DUTs. In one exemplary implementation, the tester generates and manages workloads independently for DUTs included in the plurality of DUTs. The DUTs can be memory devices the tester is configured to test different memory spaces in parallel. The different memory spaces can have various implementations (e.g., included in the plurality of DUTs, different memory spaces are within one of the DUTs included in the plurality of DUTs, etc.). Workloads can be generated based upon individual characteristics of the DUTS and managed separately. The testing can include performance testing. (e.g., bandwidth testing, latency testing, error testing, etc.).

IPC Classes  ?

  • G06F 11/263 - Generation of test inputs, e.g. test vectors, patterns or sequences
  • G06F 11/22 - Detection or location of defective computer hardware by testing during standby operation or during idle time, e.g. start-up testing

24.

SYSTEMS AND METHODS UTILIZING DAX MEMORY MANAGEMENT FOR TESTING CXL PROTOCOL ENABLED DEVICES

      
Application Number 18129422
Status Pending
Filing Date 2023-03-31
First Publication Date 2024-03-21
Owner ADVANTEST CORPORATION (Japan)
Inventor
  • Malisic, Srdjan
  • Yuan, Chi

Abstract

Efficient and effective testing systems and methods are presented. In one embodiment, a test system includes: a user interface configured to enable user interaction with the system; a test board configured to communicatively couple with a plurality of devices under test (DUTs), wherein the DUTs are compute express link (CXL) protocol compliant; and a tester configured to direct testing of the plurality of DUTs, wherein the tester includes a direct access device (DAX) interface that prevents corruption of DUTs. In one exemplary implementation, the tester isolates testing of a particular CXL enabled DUT from undesirable interference and corruption. The tester can prevent inappropriate writing over the DUT's memory. The DUTs reside in the separate per-device space of a Linux operating system rather than an extension of memory space. One of the plurality of DUTs can be a CXL type 3 memory expander device. In one exemplary implementation, the direct access device (DAX) interface creates a unique DAX instance for each individual DUT included in the plurality of DUTs

IPC Classes  ?

  • G06F 11/273 - Tester hardware, i.e. output processing circuits
  • G06F 21/53 - Monitoring users, programs or devices to maintain the integrity of platforms, e.g. of processors, firmware or operating systems during program execution, e.g. stack integrity, buffer overflow or preventing unwanted data erasure by executing in a restricted environment, e.g. sandbox or secure virtual machine

25.

A PUSHER AND A METHOD FOR PUSHING A DEVICE UNDER TEST WITH A SINGLE-LINEARLY POLARIZED ANTENNA INTO A TEST SOCKET

      
Application Number EP2022075585
Publication Number 2024/056172
Status In Force
Filing Date 2022-09-14
Publication Date 2024-03-21
Owner
  • ADVANTEST CORPORATION (Japan)
  • UNIVERSITÄT STUTTGART (Germany)
Inventor
  • Hesselbarth, Jan
  • Moreira, José

Abstract

An embodiment according to the invention comprises a pusher (140, 240, 340, 520, 720, 950, 960, 1010, 1110, 1210) for use in an automated test equipment (ATE) to mechanically push a device under test (DUT) (110, 1020, 1150, 1250) comprising an antenna (120, 220, 500, 600, 710, 810, 910) or an antenna array into a DUT socket (130). The pusher (140, 240, 340, 520, 720, 950, 960, 1010, 1110, 1210) comprises a structure (150, 250, 550, 1016, 1120, 1220), in which there are alternating parallel layers (150, 250, 550, 1016, 1120, 1220) of relatively higher dielectric permittivity (160a, 260a, 560a, 1140) and relatively lower dielectric permittivity (160b, 260b, 560b). The layers (150, 250, 550, 1016, 1120, 1220) of higher dielectric permittivity (160a, 260a, 560a, 1140) and lower dielectric permittivity (160b, 260b, 560b) extend in a first direction (170, 270), which is within ± 45° of a pushing direction (170, 270).

IPC Classes  ?

  • G01R 1/04 - Housings; Supporting members; Arrangements of terminals
  • G01R 29/10 - Radiation diagrams of antennas
  • G01R 31/28 - Testing of electronic circuits, e.g. by signal tracer

26.

AMPLIFIER ARRANGEMENT AND METHOD FOR AMPLIFIER ARRANGEMENT WITH SET CURRENT AT CONTROL INPUT OF THE AMPLIFIER ARRANGEMENT IN DEPENDENCE ON AN OUTPUT CURRENT OF THE AMPLIFIER ARRANGEMENT

      
Application Number EP2022074659
Publication Number 2024/051919
Status In Force
Filing Date 2022-09-05
Publication Date 2024-03-14
Owner ADVANTEST CORPORATION (Japan)
Inventor Bauer, Rudi

Abstract

Embodiments according to the invention comprise an amplifier arrangement the amplifier arrangement comprising an amplifier, wherein the amplifier is configured to be controlled by a voltage at a control input of the amplifier arrangement and a current adjustment circuit, wherein the current adjustment circuit is configured to set, a current at the control input of the amplifier arrangement in dependence on, an output current of the amplifier arrangement.

IPC Classes  ?

  • G01R 31/319 - Tester hardware, i.e. output processing circuits
  • H03F 1/08 - Modifications of amplifiers to reduce detrimental influences of internal impedances of amplifying elements
  • H03F 1/34 - Negative-feedback-circuit arrangements with or without positive feedback

27.

AUTOMATED TEST EQUIPMENT COMPRISING A DEVICE UNDER TEST LOOPBACK AND AN AUTOMATED TEST SYSTEM WITH AN AUTOMATED TEST EQUIPMENT COMPRISING A DEVICE UNDER TEST LOOPBACK

      
Application Number 18500127
Status Pending
Filing Date 2023-11-02
First Publication Date 2024-02-22
Owner Advantest Corporation (Japan)
Inventor Hantsch, Andreas

Abstract

An embodiment is an automated test equipment (ATE) for testing a device under test (DUT) which is connected to the ATE via a load board. The ATE comprises a stimulus module, a measurement module, a loopback, a first switch, a second switch, and a load board interface. The load board interface comprises a first radio frequency port and a second radio frequency port. The first and second radio frequency ports are configured to be coupled to the respective ports of the load board. The first switch is configured to couple the first radio frequency port to the stimulus module in a first switching state of the first switch and the second switch is configured to couple the second radio frequency port to the measurement module in a first switching state of the second switch. Further, the first switch is configured to couple the first radio frequency port to a first end of the loopback in a second switching state of the first switch and the second switch is configured to couple the second radio frequency port to a second end of the loopback in a second switching state of the second switch. When the first and second switches are in their respective second switching state, a loopback signal path is formed between the first and second radio frequency ports.

IPC Classes  ?

  • G01R 31/28 - Testing of electronic circuits, e.g. by signal tracer
  • G01R 31/317 - Testing of digital circuits

28.

OVER THE AIR (OTA) TESTING OF AN ANTENNA IN PACKAGE (AIP) DEVICE IN RADIATING NEAR FIELD USING A CHARACTERIZING DEVICE AND AUTOMATED TEST EQUIPMENT

      
Application Number 18500122
Status Pending
Filing Date 2023-11-02
First Publication Date 2024-02-22
Owner Advantest Corporation (Japan)
Inventor Moreira, José

Abstract

Embodiments according to the disclosure comprise an automated test equipment component, ATE component, e.g., a handler component, e.g., a handler arm, comprising a first antenna adapted to establish a wireless, e.g., near field, coupling with a device under test (DUT), e.g., comprising an antenna, e.g., comprising an antenna array, when the DUT is arranged on a loadboard, e.g., a DUT loadboard. Furthermore, the ATE component comprises a second antenna for establishing a wireless, e.g., near field, coupling with a characterizing device, e.g., a golden device, e.g., comprising an antenna, e.g., comprising an antenna array, when the characterizing device is arranged, e.g., placed, on the loadboard, wherein the DUT and the characterizing device are, for example, placed at different positions on the DUT loadboard. Moreover, the first antenna is electrically coupled, e.g., connected with a rigid electrical connection, with the second antenna, to allow for a forwarding of a signal, e.g., of a plurality of signals, provided, e.g., transmitted, by the DUT to the characterizing device, e.g., reference device, and/or vice versa, e.g., to allow for a forwarding of a signal, e.g., of a plurality of signals, provided, e.g., transmitted, by the characterizing device to the DUT. Optionally, a relative position of the second antenna with respect to the first antenna may be fixed, or for example, a relative position of the second antenna with respect to the first antenna may be variable.

IPC Classes  ?

29.

AUTOMATED TEST EQUIPMENT, METHOD FOR TESTING A DEVICE UNDER TEST AND COMPUTER PROGRAM USING A FITTING APPROACH TO OBTAIN TEMPERATURE CONTROL INSTRUCTIONS

      
Application Number EP2022078452
Publication Number 2024/032916
Status In Force
Filing Date 2022-10-12
Publication Date 2024-02-15
Owner ADVANTEST CORPORATION (Japan)
Inventor
  • Yoshino, Takatoshi
  • Chen, Tse-Kun

Abstract

An automated test equipment, ATE (100), for testing a device under test, DUT, is configured to obtain a testing profile (110) indicating an evolution of a DUT temperature during an execution of a given test flow. The automated test equipment is configured to analyze the testing profile, in order to determine an information (122) describing a plurality of temperature peaks using a fitting approach. The automated test equipment (100) is configured to obtain a plurality of temperature control instructions (112) for an execution of a test flow on the basis of the information describing the plurality of temperature peaks.

IPC Classes  ?

  • G01R 31/28 - Testing of electronic circuits, e.g. by signal tracer

30.

AUTOMATED TEST EQUIPMENT, METHOD FOR TESTING A DEVICE UNDER TEST AND COMPUTER PROGRAM USING AN ITERATIVE APPROACH TO OBTAIN TEMPERATURE CONTROL INSTRUCTIONS

      
Application Number EP2022078454
Publication Number 2024/032917
Status In Force
Filing Date 2022-10-12
Publication Date 2024-02-15
Owner ADVANTEST CORPORATION (Japan)
Inventor Chejanovsky, Natan

Abstract

An automated test equipment, ATE (100, 200, 300), for testing a device under test, DUT, is configured to obtain a testing profile (110, 210, 310) indicating an evolution of a DUT temperature during an execution of a given test flow. The automated test equipment is configured to analyze the testing profile, in order determine an information (122, 222, 322) describing a plurality of temperature peaks. The automated test equipment is configured to obtain a plurality of temperature control instructions (112, 212, 312) for an execution of a test flow on the basis of the information describing the plurality of temperature peaks. Moreover, the automated test equipment is configured to iteratively obtain the temperature control instructions.

IPC Classes  ?

  • G01R 31/28 - Testing of electronic circuits, e.g. by signal tracer

31.

TEST ARRANGEMENT FOR OVER-THE-AIR TESTING AN ANGLED DEVICE UNDER TEST IN A DEVICE-UNDER-TEST SOCKET

      
Application Number EP2023059652
Publication Number 2024/022625
Status In Force
Filing Date 2023-04-13
Publication Date 2024-02-01
Owner ADVANTEST CORPORATION (Japan)
Inventor
  • Takasu, Hiromitsu
  • Shiota, Natsuki
  • Kikuchi, Aritomo
  • Kato, Yasuyuki
  • Mineo, Hiroyuki

Abstract

The invention relates to a test arrangement for over-the-air testing an angled device under test, wherein the test arrangement comprises a carrier structure, wherein the test arrangement comprises a device-under-test socket which is coupled to the carrier structure, wherein the device-under-test socket is configured to establish an electrical contact with an inner surface of the angled device under test or with a connector which is arranged on the inner surface of the angled device under test.

IPC Classes  ?

  • G01R 1/04 - Housings; Supporting members; Arrangements of terminals
  • G01R 29/08 - Measuring electromagnetic field characteristics
  • G01R 31/28 - Testing of electronic circuits, e.g. by signal tracer
  • G01R 31/302 - Contactless testing
  • H01Q 21/00 - Antenna arrays or systems
  • H01Q 25/00 - Antennas or antenna systems providing at least two radiating patterns
  • H04B 17/10 - Monitoring; Testing of transmitters
  • G01R 29/10 - Radiation diagrams of antennas
  • H01Q 1/52 - Means for reducing coupling between antennas; Means for reducing coupling between an antenna and another structure
  • H01Q 17/00 - Devices for absorbing waves radiated from an antenna; Combinations of such devices with active antenna elements or systems

32.

TEST ARRANGEMENT FOR OVER-THE-AIR TESTING AN ANGLED DEVICE UNDER TEST USING A CARRIER STRUCTURE WITH AN OPENING

      
Application Number EP2023059653
Publication Number 2024/022626
Status In Force
Filing Date 2023-04-13
Publication Date 2024-02-01
Owner ADVANTEST CORPORATION (Japan)
Inventor
  • Takasu, Hiromitsu
  • Shiota, Natsuki
  • Kikuchi, Aritomo
  • Kato, Yasuyuki
  • Mineo, Hiroyuki

Abstract

The invention relates to a test arrangement for over-the-air testing an angled device under test, wherein the test arrangement comprises a carrier structure and a device-under-test socket which is coupled to the carrier structure. The device-under-test socket is configured to establish an electrical contact with an inner surface of the angled device under test or with a connector which is arranged on the inner surface of the angled device under test. The carrier structure comprises an opening extending away from the device-under-test socket in a direction of an outward surface normal of a first outer surface of the angled device-under-test.

IPC Classes  ?

  • G01R 1/04 - Housings; Supporting members; Arrangements of terminals
  • G01R 29/08 - Measuring electromagnetic field characteristics
  • G01R 31/28 - Testing of electronic circuits, e.g. by signal tracer
  • G01R 31/302 - Contactless testing
  • H01Q 21/00 - Antenna arrays or systems
  • H01Q 25/00 - Antennas or antenna systems providing at least two radiating patterns
  • H04B 17/10 - Monitoring; Testing of transmitters
  • G01R 29/10 - Radiation diagrams of antennas
  • H01Q 1/52 - Means for reducing coupling between antennas; Means for reducing coupling between an antenna and another structure
  • H01Q 17/00 - Devices for absorbing waves radiated from an antenna; Combinations of such devices with active antenna elements or systems

33.

TEST ARRANGEMENT FOR OVER-THE-AIR TESTING AN ANGLED DEVICE UNDER TEST THAT IS TILTED RELATIVE TO A SURFACE OF A CARRIER STRUCTURE

      
Application Number EP2023059654
Publication Number 2024/022627
Status In Force
Filing Date 2023-04-13
Publication Date 2024-02-01
Owner ADVANTEST CORPORATION (Japan)
Inventor
  • Takasu, Hiromitsu
  • Shiota, Natsuki
  • Kikuchi, Aritomo
  • Kato, Yasuyuki
  • Mineo, Hiroyuki

Abstract

The invention relates to a test arrangement for over-the-air testing an angled device under test, wherein the test arrangement comprises a carrier structure. The test arrangement comprises a device-under-test socket which is coupled to the carrier structure, wherein the device-under-test socket is configured to establish an electrical contact with an inner surface of the angled device under test or with a connector which is arranged on the inner surface of the angled device under test. The device-under-test socket is configured to position the angled device-under-test such that a first outer surface of the angled device-under-test is tilted by at least degrees with respect to a surface of the carrier structure.

IPC Classes  ?

  • G01R 1/04 - Housings; Supporting members; Arrangements of terminals
  • G01R 29/08 - Measuring electromagnetic field characteristics
  • G01R 31/28 - Testing of electronic circuits, e.g. by signal tracer
  • G01R 31/302 - Contactless testing
  • H01Q 21/00 - Antenna arrays or systems
  • H01Q 25/00 - Antennas or antenna systems providing at least two radiating patterns
  • H04B 17/10 - Monitoring; Testing of transmitters
  • G01R 29/10 - Radiation diagrams of antennas
  • H01Q 1/52 - Means for reducing coupling between antennas; Means for reducing coupling between an antenna and another structure
  • H01Q 17/00 - Devices for absorbing waves radiated from an antenna; Combinations of such devices with active antenna elements or systems

34.

CONNECTING DEVICE, TESTING DEVICE, AND COMMUNICATION DEVICE

      
Application Number JP2022028991
Publication Number 2024/023983
Status In Force
Filing Date 2022-07-27
Publication Date 2024-02-01
Owner ADVANTEST CORPORATION (Japan)
Inventor Tsushima Takahiro

Abstract

This connecting device comprises a first connecting unit that toggles between whether or not a first terminal and a second terminal are to be connected, and a second connecting unit that toggles between whether or not the first terminal or the second terminal and a third terminal is to be connected. The first connecting unit includes: a first transmission line; a first connection toggle unit that toggles between whether or not the first terminal and the second terminal are to be connected via the first transmission line; and a first ground toggle unit that toggles between whether or not each of three or more first connection points having different positions on the first transmission line is to be connected to a reference potential.

IPC Classes  ?

  • H03K 17/00 - Electronic switching or gating, i.e. not by contact-making and -breaking
  • H03K 17/693 - Switching arrangements with several input- or output-terminals, e.g. multiplexers, distributors

35.

AUTOMATIC TEST EQUIPMENT

      
Application Number 18354198
Status Pending
Filing Date 2023-07-18
First Publication Date 2024-01-25
Owner ADVANTEST CORPORATION (Japan)
Inventor
  • Ichikawa, Hiroki
  • Sudo, Satoshi
  • Fujibe, Tasuku

Abstract

An interface apparatus is provided between a test head and a DUT. The interface apparatus includes a frontend module configured of multiple pin electronics ICs in the form of a module.

IPC Classes  ?

36.

AUTOMATIC TEST EQUIPMENT

      
Application Number 18354255
Status Pending
Filing Date 2023-07-18
First Publication Date 2024-01-25
Owner ADVANTEST CORPORATION (Japan)
Inventor
  • Ichikawa, Hiroki
  • Fujibe, Tasuku

Abstract

An interface device is provided between a test head and a DUT. In the interface device, each pin electronics IC is coupled to a DUT via an FPC cable.

IPC Classes  ?

37.

AUTOMATIC TEST EQUIPMENT

      
Application Number 18354771
Status Pending
Filing Date 2023-07-19
First Publication Date 2024-01-25
Owner ADVANTEST CORPORATION (Japan)
Inventor
  • Tanaka, Takayuki
  • Fujibe, Tasuku

Abstract

An interface device is provided between a test head and a DUT. The interface device includes pin electronics ICs, RAM, a pin controller, and nonvolatile memory. The RAM stores data based on a device signal received from the DUT by means of the multiple pin electronics ICs. The pin controller controls the multiple pin electronics ICs according to a control signal from the test head. The multiple pin electronics ICs, the RAM, and the pin controller are mounted on a pin electronics PCB.

IPC Classes  ?

38.

AUTOMATIC TEST EQUIPMENT

      
Application Number 18354789
Status Pending
Filing Date 2023-07-19
First Publication Date 2024-01-25
Owner ADVANTEST CORPORATION (Japan)
Inventor
  • Ichikawa, Hiroki
  • Fujibe, Tasuku

Abstract

An interface device is provided between a test head and a device under test (DUT). A socket board includes sockets each configured to mount a DUT, and a socket PCB having a first face that mounts the sockets and a second face provided with multiple back face electrodes. An interposer has a first face provided with multiple deformable electrodes and a second face provided with multiple non-deformable electrodes and is configured such that the multiple deformable electrodes are in contact with the multiple back face electrodes of the socket PCB. An FPC cable has multiple electrode pads to be coupled with the multiple non-deformable electrodes on the second face of the first interposer.

IPC Classes  ?

39.

ELECTRONIC COMPONENT TESTING APPARATUS, SOCKETS, AND REPLACEMENT PARTS FOR ELECTRONIC COMPONENT TESTING APPARATUS

      
Application Number 18481760
Status Pending
Filing Date 2023-10-05
First Publication Date 2024-01-25
Owner ADVANTEST Corporation (Japan)
Inventor
  • Shiota, Natsuki
  • Mineo, Hiroyuki

Abstract

An electronic component testing apparatus for testing a device under test (DUT) includes: a socket unit that is electrically connected to the DUT; a first wiring board that includes a board opening; and a tester that includes a test head in which the first wiring board is mounted. The socket unit includes a first socket that faces a first main surface of the DUT and is electrically connected to the DUT and the first wiring board. The second socket that is exposed from the first wiring board through the board opening, contacts a second main surface of the DUT on a side opposite to the first main surface, and includes: a base that contacts the second main surface; and a test antenna unit that is electrically connected to the tester and faces a device antenna unit of the DUT.

IPC Classes  ?

  • G01R 31/28 - Testing of electronic circuits, e.g. by signal tracer
  • G01R 29/10 - Radiation diagrams of antennas

40.

HEAT EXCHANGER, ELECTRONIC COMPONENT HANDLING DEVICE, AND ELECTRONIC COMPONENT TESTING DEVICE

      
Application Number JP2022028100
Publication Number 2024/018536
Status In Force
Filing Date 2022-07-19
Publication Date 2024-01-25
Owner ADVANTEST CORPORATION (Japan)
Inventor
  • Yamada, Yuya
  • Kikuchi, Aritomo
  • Jeserer, Guenther
  • Wallner, Merlin

Abstract

A thermal head 25 is a heat exchanger that exchanges heat with a DUT 100, and comprises a main body part 30 having a flow path 34 through which a fluid for temperature adjustment of the DUT 100 can flow, and a heater 40 placed in the flow path 34 so as to be located at the bottom of the flow path 34.

IPC Classes  ?

  • G01R 31/26 - Testing of individual semiconductor devices
  • G01R 31/28 - Testing of electronic circuits, e.g. by signal tracer

41.

SIGNAL GENERATOR

      
Application Number 18476660
Status Pending
Filing Date 2023-09-28
First Publication Date 2024-01-18
Owner ADVANTEST CORPORATION (Japan)
Inventor Asami, Koji

Abstract

N (N≥2) D/A converters convert respective input data at a sampling frequency FS. A digital signal processing unit generates N items of sub-band waveform data. Each of N items of sub-band waveform data is generated by frequency-shifting corresponding one of N sub-band components included in digital waveform data that represents the analog output signal, such that each sub-band waveform data has its maximum frequency below FS/2. A local signal generating circuit generates N local signals having different frequencies.

IPC Classes  ?

  • H04B 1/04 - Circuits
  • H03M 1/06 - Continuously compensating for, or preventing, undesired influence of physical parameters

42.

ULTRASONIC MEASUREMENT APPARATUS, METHOD, AND RECORDING MEDIUM

      
Application Number 18133109
Status Pending
Filing Date 2023-04-11
First Publication Date 2024-01-18
Owner ADVANTEST CORPORATION (Japan)
Inventor Ida, Taiichiro

Abstract

An ultrasonic measurement apparatus includes a lens, an ultrasonic measuring section, an ultrasonic determining section, and a lens moving section. The lens receives an ultrasonic wave output from a measuring target. The ultrasonic measuring section measures the ultrasonic wave received by the lens in relation to time. The ultrasonic determining section determines whether or not the ultrasonic wave is included in a result of measurement by the ultrasonic measuring section at an elapsed time point when the time required for the ultrasonic wave to travel a focal distance of the lens has elapsed after the ultrasonic wave is output from the measuring target. The lens moving section moves the lens such that it is determined that the ultrasonic wave is included in the result of measurement by the ultrasonic measuring section.

IPC Classes  ?

  • G01H 9/00 - Measuring mechanical vibrations or ultrasonic, sonic or infrasonic waves by using radiation-sensitive means, e.g. optical means
  • G10K 11/30 - Sound-focusing or directing, e.g. scanning using refraction, e.g. acoustic lenses

43.

OPTICAL CIRCUIT AND METHOD

      
Application Number JP2022025660
Publication Number 2024/004012
Status In Force
Filing Date 2022-06-28
Publication Date 2024-01-04
Owner ADVANTEST CORPORATION (Japan)
Inventor Uekusa Kouichiro

Abstract

Provided is an optical circuit (10) equipped with: an optical switch (110) for outputting incident light, which is polarized in a first polarization direction, to a first optical path or to a second optical path while maintaining the state of polarization; and a polarization rotation coupling element (140) which is positioned on the output side of the first and second optical paths, and outputs the incident light inputted from the first optical path from an output port thereof while maintaining the state of polarization thereof, while also converting the incident light inputted from the second optical path into a polarization oriented in a second polarization direction which is perpendicular to the first polarization direction, and outputting the same from the output port. The optical switch (110) may be an optical switch of the Mach-Zehnder type, which switches the output-side optical path from one path among the first and second optical paths to the other of said paths, according to the size of the voltage to be applied.

IPC Classes  ?

  • G02B 6/126 - Light guides; Structural details of arrangements comprising light guides and other optical elements, e.g. couplings of the optical waveguide type of the integrated circuit kind using polarisation effects
  • G01M 11/00 - Testing of optical apparatus; Testing structures by optical methods not otherwise provided for
  • G02F 1/01 - Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour
  • H04B 10/073 - Arrangements for monitoring or testing transmission systems; Arrangements for fault measurement of transmission systems using an out-of-service signal

44.

SIGNAL/NOISE DETERMINATION APPARATUS, METHOD, AND RECORDING MEDIUM

      
Application Number 18122885
Status Pending
Filing Date 2023-03-17
First Publication Date 2023-12-28
Owner ADVANTEST CORPORATION (Japan)
Inventor
  • Ogata, Yuji
  • Yanagida, Tomonori

Abstract

A signal/noise determination apparatus includes a plurality of sensors, a determination model recording section, and a signal/noise determining section. The plurality of sensors measure a signal and a noise. The determination model recording section records a determination model used to determine whether components of results of measurement by the sensors expected with hypothetical signal information and hypothetical noise information are from a signal source or a noise source. The determination model is generated by machine learning with the measurement results, the hypothetical signal information, and the hypothetical noise information as training data. The signal/noise determining section determines whether components of the measurement results are from the signal source or the noise source based on the measurement results and the determination model. The signal information includes the position of the signal source and the signal, and the noise information includes the position of the noise source and the noise.

IPC Classes  ?

  • G01R 29/26 - Measuring noise figure; Measuring signal-to-noise ratio
  • G06N 3/0464 - Convolutional networks [CNN, ConvNet]
  • G06N 3/048 - Activation functions

45.

ELECTRONIC COMPONENT HANDLING APPARATUS, ELECTRONIC COMPONENT TESTING APPARATUS, ELECTRONIC COMPONENT TESTING

      
Application Number 18036821
Status Pending
Filing Date 2020-11-30
First Publication Date 2023-12-28
Owner ADVANTEST Corporation (Japan)
Inventor
  • Werner, Matthias
  • Hashimoto, Takashi

Abstract

An electronic component handling apparatus pressing the DUT against a socket electrically connected to a tester, includes: a first receiver that receives, from the tester, a first signal indicating a detection value of a temperature detection circuit; a calculator that calculates a temperature of the DUT based on the first signal; a calibrator that calibrates the calculated temperature; a second receiver that receives, from the tester, a second signal that causes the calibrator to start a first calibration; and a temperature adjuster that adjusts the temperature of the DUT. The second receiver receives the second signal before the tester turns on the DUT, once the second signal is received, the calibrator calculates a first calibrated temperature by executing the first calibration with respect to the calculated temperature, and the temperature adjuster adjusts the temperature of the DUT based on the first calibrated temperature.

IPC Classes  ?

  • G01R 31/28 - Testing of electronic circuits, e.g. by signal tracer
  • G01R 35/00 - Testing or calibrating of apparatus covered by the other groups of this subclass

46.

PHOTOACOUSTIC WAVE MEASUREMENT DEVICE, METHOD, PROGRAM, AND RECORDING MEDIUM

      
Application Number JP2022024291
Publication Number 2023/243075
Status In Force
Filing Date 2022-06-17
Publication Date 2023-12-21
Owner ADVANTEST CORPORATION (Japan)
Inventor Iwazaki, Hideaki

Abstract

In the present invention, an object under measurement is measured on the basis of a photoacoustic signal obtained by irradiating, with pulse light, a body to be irradiated having the object under measurement and intermingled matter. The photoacoustic wave measurement device 1 measures a body 2 to be irradiated having an object 2a under measurement and intermingled matter 2b. The photoacoustic wave measurement device 1 comprises: pulse light output units 12a, 12b for outputting pulse lights P1, P2 having a first wavelength and a second wavelength; a photoacoustic wave measurement unit 13 for measuring, in association with time for each of the first wavelength and the second wavelength, photoacoustic waves AW generated in the body 2 to be irradiated due to the pulse lights P1, P2; a time-frequency domain conversion unit 14 for converting the results of measurement by the photoacoustic wave measurement unit 12 into a time-frequency domain; a difference acquisition unit 16 for acquiring the difference between a result TF1 of conversion by the time-frequency domain conversion unit 14 with regards to the first wavelength and a result TF2 of conversion by the time-frequency domain conversion unit 14 with regards to the second wavelength; and a time domain conversion unit 18 for converting the difference acquired by the difference acquisition unit 16 into a time domain.

IPC Classes  ?

47.

APPARATUS FOR TESTING A DEVICE UNDER TEST SEPARATING ERRORS WITHIN A RECEIVED PATTERN ASSOCIATED WITH DIFFERENT FUNCTIONAL BLOCKS OF A DEVICE UNDER TEST OR ASSOCIATED WITH DIFFERENT BLOCKS OF ONE OR MORE BITS, METHOD AND COMPUTER PROGRAM

      
Application Number EP2023065148
Publication Number 2023/237565
Status In Force
Filing Date 2023-06-06
Publication Date 2023-12-14
Owner ADVANTEST CORPORATION (Japan)
Inventor
  • Braun, Michael
  • Welch, Klaus
  • Hensel, Frank
  • Müller, Nico
  • Gerlach, Arndt
  • Knoch, Ulrich

Abstract

A test apparatus (100;200;300;500) for testing a device under test, is configured to receive a pattern from the device under test (102;202;302), which comprises information from a plurality of functional blocks of the device under test. The test apparatus is configured to separate errors within the received pattern associated with different functional blocks of the device under test during an execution of a test program, or the test apparatus is configured to separate errors within the received pattern associated with different blocks of one or more bits during an execution of a test program. A method and a computer program are also described.

IPC Classes  ?

  • G01R 31/317 - Testing of digital circuits
  • G01R 31/3193 - Tester hardware, i.e. output processing circuits with comparison between actual response and known fault-free response
  • G01R 31/3185 - Reconfiguring for testing, e.g. LSSD, partitioning

48.

HEATER DRIVE CONTROLLING APPARATUS, ELECTRONIC COMPONENT HANDLING APPARATUS, ELECTRONIC COMPONENT TESTING APPARATUS, AND HEATER DRIVE CONTROLLING METHOD

      
Application Number 18325358
Status Pending
Filing Date 2023-05-30
First Publication Date 2023-12-07
Owner ADVANTEST CORPORATION (Japan)
Inventor
  • Ashizawa, Takuro
  • Sasaki, Hirotaka
  • Nitta, Keisuke

Abstract

A heater drive controlling apparatus for an electronic component testing apparatus includes a breaker disposed between a power source and heaters, and a controller that controls electric currents supplied from the power source to the heaters in order according to a first priority set for the heaters such that a sum of the supplied electric currents is within a rated current of the breaker. The electronic component testing apparatus includes a test chamber, a thermal-stress applying chamber, and a thermal-stress removing chamber each of which includes the heaters.

IPC Classes  ?

  • G01R 31/28 - Testing of electronic circuits, e.g. by signal tracer
  • H05B 1/02 - Automatic switching arrangements specially adapted to heating apparatus
  • G05D 23/19 - Control of temperature characterised by the use of electric means

49.

BIAS CIRCUIT

      
Application Number JP2022022155
Publication Number 2023/233530
Status In Force
Filing Date 2022-05-31
Publication Date 2023-12-07
Owner ADVANTEST CORPORATION (Japan)
Inventor Takayanagi Fumikazu

Abstract

In the present invention, a frequency band on the low-frequency side of an output of a bias circuit is broadened. A bias circuit 1 comprises: a signal input terminal 2; a signal output terminal 4; a first inductor 12 having one end connected to a node 6 between the signal input terminal 2 and the signal output terminal 4; and a second inductor 14 having one end connected to the other end of the first inductor 12. A core of the first inductor 12 is a ferrite bulk or formed by molding powder of a high magnetic permeability material (relative magnetic permeability exceeding 500) by means of a carbon binder. A core of the second inductor 14 is a bulk of a high magnetic permeability material (relative magnetic permeability exceeding 500).

IPC Classes  ?

  • H03H 7/03 - Frequency selective two-port networks comprising means for compensation of loss

50.

OPTICAL ELEMENT

      
Application Number JP2022021121
Publication Number 2023/228248
Status In Force
Filing Date 2022-05-23
Publication Date 2023-11-30
Owner ADVANTEST CORPORATION (Japan)
Inventor
  • Abe Shunsuke
  • Hara Hideo

Abstract

The present invention decreases resistance between an electrode and a slot (recessed section). An optical element 1 comprises a substrate 2, an intermediate layer 4 disposed on the substrate 2, a ground electrode 5G and a signal electrode 5S disposed on the intermediate layer 4, and a gate electrode 12 disposed separated from the intermediate layer 4. The intermediate layer 4 has: a ground electrode support part 4G disposed between the ground electrode 5G and the substrate 2; a signal electrode support part 4S disposed between the signal electrode 5S and the substrate 2; two first protrusions 4a, 4b separated by a recessed section 4c; a plurality of second protrusions 4A separated from each other and connecting one of the first protrusions 4a to the ground electrode support part 4G; and a plurality of third protrusions 4B separated from each other and connecting the other of the first protrusions 4b to the signal electrode support part 4S. A gate voltage Vgate is applied across the ground electrode 5G and the gate electrode 12. The application of the gate voltage Vgate induces electrons on the surface of the second protrusions 4A and the surface of the third protrusions 4B. An electrical signal is provided to light traveling through the recessed section 4c.

IPC Classes  ?

  • G02F 1/061 - Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour based on electro-optical organic material

51.

CONTROL OF AN AUTOMATED TEST EQUIPMENT BASED ON TEMPERATURE

      
Application Number 18330781
Status Pending
Filing Date 2023-06-07
First Publication Date 2023-11-30
Owner Advantest Corporation (Japan)
Inventor
  • Edelmann, Jens
  • Thoma, Anton

Abstract

Embodiments according to the disclosure comprise a control device for controlling an ATE for testing a DUT which is electrically coupled to the ATE using, or for example via, a device under test (DUT) contacting structure, e.g. using or via a probe needle, or for example using or via a DUT socket. The control device is configured to figure out a temperature of the DUT contacting structure using a thermal model, e.g. using a thermal model of the DUT contacting structure or using, for example, a thermal model comprising a thermal model of the DUT contacting structure. In addition, the control device is configured to influence, e.g. to control, to regulate, to deactivate and/or to limit, a signal applied to the DUT contacting structure based on the figured out, or for example modeled, temperature. The figured out temperature comprises at least one of a determined temperature or an estimated temperature.

IPC Classes  ?

  • G01R 31/28 - Testing of electronic circuits, e.g. by signal tracer

52.

LIGHT BEAM DIAMETER MEASUREMENT DEVICE, METHOD, PROGRAM, RECORDING MEDIUM

      
Application Number JP2023004527
Publication Number 2023/223613
Status In Force
Filing Date 2023-02-10
Publication Date 2023-11-23
Owner ADVANTEST CORPORATION (Japan)
Inventor Matsuyama Kaoru

Abstract

A light beam diameter measurement device according to the present invention comprises a light reception unit, a mobile unit, a power measurement unit, and a light beam diameter derivation unit. The light reception unit receives a light beam. The mobile unit moves the light reception unit along a plurality of straight lines that are parallel to each other in a plane to which the advancement direction of the light beam is normal. The power measurement unit measures the power of the light beam received by the light reception unit. The light beam diameter derivation unit derives the diameter of the light beam on the basis of a first range in which the ratio of the measurement results from the power measurement unit relative to the maximum value of the measurement results is at or above a first prescribed ratio for the straight line of the plurality of straight lines that has the highest maximum value.

IPC Classes  ?

  • G01B 11/08 - Measuring arrangements characterised by the use of optical techniques for measuring diameters

53.

POWER SUPPLY APPARATUS

      
Application Number 18312000
Status Pending
Filing Date 2023-05-04
First Publication Date 2023-11-02
Owner ADVANTEST CORPORATION (Japan)
Inventor
  • Shimizu, Takahiko
  • Imai, Shoichiro

Abstract

Power supply units of multiple channels each include an output stage that generates an output voltage across positive/negative outputs OUTP and OUTN, and a voltage detector that generates a voltage detection signal that indicates the output voltage. A feedback signal generating unit of the power supply unit of a master channel that is one of the multiple channels receives voltage detection signals from the power supply units of the remaining multiple channels, i.e., the slave channels, and generates a feedback signal based on the voltage detection signals of all the channels. A feedback controller generates a control signal such that the feedback signal approaches a target value. An output stage of each slave channel operates based on the control signal generated by the master channel.

IPC Classes  ?

  • H02M 3/158 - Conversion of dc power input into dc power output without intermediate conversion into ac by static converters using discharge tubes with control electrode or semiconductor devices with control electrode using devices of a triode or transistor type requiring continuous application of a control signal using semiconductor devices only with automatic control of output voltage or current, e.g. switching regulators including plural semiconductor devices as final control devices for a single load
  • H02M 1/00 - APPARATUS FOR CONVERSION BETWEEN AC AND AC, BETWEEN AC AND DC, OR BETWEEN DC AND DC, AND FOR USE WITH MAINS OR SIMILAR POWER SUPPLY SYSTEMS; CONVERSION OF DC OR AC INPUT POWER INTO SURGE OUTPUT POWER; CONTROL OR REGULATION THEREOF - Details of apparatus for conversion
  • H02M 3/157 - Conversion of dc power input into dc power output without intermediate conversion into ac by static converters using discharge tubes with control electrode or semiconductor devices with control electrode using devices of a triode or transistor type requiring continuous application of a control signal using semiconductor devices only with automatic control of output voltage or current, e.g. switching regulators with digital control

54.

MEASUREMENT ARRANGEMENT FOR CHARACTERIZING A RADIO FREQUENCY ARRANGEMENT HAVING A PLURALITY OF ANTENNAS

      
Application Number 18344202
Status Pending
Filing Date 2023-06-29
First Publication Date 2023-11-02
Owner Advantest Corporation (Japan)
Inventor
  • Hesselbarth, Jan
  • Moreira, José
  • Fischer, Serafin

Abstract

An embodiment provides a measurement arrangement for characterizing a radio frequency arrangement comprising a plurality of antennas. Measurement arrangement comprises a dielectric waveguide slab with a plurality of frequency converting structures, arranged in or on the dielectric waveguide slab. Measurement arrangement further comprises a plurality of waveguide transitions arranged at different positions of the dielectric waveguide slab and are coupled to respective radio frequency components. Radio frequency components are configured to transmit and/or receive radio signals. Frequency converting structures are associated with respective antennas of the plurality of antennas, and are configured to perform a frequency conversion on signals received, resulting in frequency-converted signals. Frequency converting structures are further configured to couple respective antennas with the dielectric slab in a frequency converting manner to establish a frequency-converting coupling between the antennas and the plurality of waveguide transitions to cause a frequency-converting coupling between the antennas and the radio frequency components.

IPC Classes  ?

55.

TEST METHOD AND MANUFACTURING METHOD

      
Application Number 18190947
Status Pending
Filing Date 2023-03-27
First Publication Date 2023-10-26
Owner ADVANTEST CORPORATION (Japan)
Inventor
  • Miura, Takeo
  • Homma, Yasuaki

Abstract

Provided is a test method including: placing, on a placement unit, a panel level package formed with a plurality of unsingulated devices; bringing at least one contact electrically connected to at least one terminal of a test circuit into contact with at least one terminal of at least one device of the plurality of devices, respectively, the terminal being exposed on a second surface on a side opposite to a first surface on the placement unit side in the panel level package; and testing, by the test circuit, the at least one device electrically connected via the at least one contact.

IPC Classes  ?

  • H01L 21/66 - Testing or measuring during manufacture or treatment
  • G01R 31/28 - Testing of electronic circuits, e.g. by signal tracer
  • H01L 21/78 - Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices

56.

IMAGE OUTPUT DEVICE, METHOD, PROGRAM, AND RECORDING MEDIUM

      
Application Number JP2023001949
Publication Number 2023/203820
Status In Force
Filing Date 2023-01-23
Publication Date 2023-10-26
Owner ADVANTEST CORPORATION (Japan)
Inventor
  • Ogata Yuji
  • Yanagida Tomonori

Abstract

This image output device comprises a signal source specifying unit and a signal source image adding unit. This signal source specifying unit receives signals represented by vectors having a predetermined direction from a plurality of signal sources, receives measurement results of a plurality of sensors for measuring components in three mutually orthogonal axes, and specifies positions of the signal sources and the orientations of the vectors. The signal source image adding unit adds an image showing the signal source to a portion corresponding to the position of the signal source specified by the signal source specifying unit in the imaging result of an imaging unit that images the signal source.

IPC Classes  ?

  • G01R 33/02 - Measuring direction or magnitude of magnetic fields or magnetic flux
  • G01N 27/72 - Investigating or analysing materials by the use of electric, electrochemical, or magnetic means by investigating magnetic variables

57.

TEST METHOD, MANUFACTURING METHOD, PANEL LEVEL PACKAGE, AND TEST APPARATUS

      
Application Number 18190949
Status Pending
Filing Date 2023-03-27
First Publication Date 2023-10-26
Owner ADVANTEST CORPORATION (Japan)
Inventor
  • Miura, Takeo
  • Homma, Yasuaki

Abstract

Provided is a test method including: placing, on a placement unit, a panel level package in which a plurality of unsingulated devices are formed in a matrix; bringing a plurality of contacts electrically connected to a plurality of terminals of a test circuit into contact with a plurality of contact terminals provided on one side in the panel level package in a row direction of the matrix and connected via a plurality of lead-out wirings to an internal circuit of each device in each row of the plurality of devices, respectively; and testing, by the test circuit, each device in the each row electrically connected via the plurality of contacts.

IPC Classes  ?

  • H01L 21/683 - Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components for supporting or gripping
  • H01L 23/498 - Leads on insulating substrates

58.

ELECTRONIC COMPONENT HANDLING APPARATUS, AND ELECTRONIC COMPONENT TEST APPARATUS

      
Application Number 18194138
Status Pending
Filing Date 2023-03-31
First Publication Date 2023-10-26
Owner ADVANTEST Corporation (Japan)
Inventor
  • Suda, Akihisa
  • Takeuchi, Yoshitaka
  • Kajihara, Takuro

Abstract

An electronic component handling apparatus includes: a pressing device that presses a device under test (DUT) or a carrier containing the DUT against a socket while a test tray having an insert containing the DUT or the carrier is in a vertical state. The pressing device includes: a pusher that contacts the DUT or the carrier; and an abutting part that abuts the insert.

IPC Classes  ?

  • G01R 31/28 - Testing of electronic circuits, e.g. by signal tracer

59.

AUTOMATED TEST EQUIPMENT COMPONENT, AUTOMATED TEST EQUIPMENT AND METHOD FOR ESTABLISHING A COUPLING WITH A DEVICE UNDER TEST AND WITH A CHARACTERIZING DEVICE USING A FIRST AND SECOND ANTENNA

      
Application Number EP2022060128
Publication Number 2023/198296
Status In Force
Filing Date 2022-04-14
Publication Date 2023-10-19
Owner ADVANTEST CORPORATION (Japan)
Inventor Moreira, José

Abstract

Embodiments according to the invention comprise an automated test equipment component, ATE component, e.g. a handler component, e.g. a handler arm, comprising a first antenna adapted to establish a wireless, e.g. nearfield, coupling with a device under test, DUT, e.g. comprising an antenna, e.g. comprising an antenna array, when the DUT is arranged on a loadboard, e.g. a DUT loadboard. Furthermore, the ATE component comprises a second antenna for establishing a wireless, e.g. nearfield, coupling with a characterizing device, e.g. a golden device, e.g. comprising an antenna, e.g. comprising an antenna array, when the characterizing device is arranged, e.g. placed, on the loadboard, wherein the DUT and the characterizing device are, for example, placed at different positions of the DUT loadboard. Moreover, the first antenna is electrically coupled, e.g. connected with a rigid electrical connection, with the second antenna, to allow for a forwarding of a signal, e.g. of a plurality of signals, provided, e.g. transmitted, by the DUT to the characterizing device, and/or vice versa, e.g. to allow for a forwarding of a signal, e.g. of a plurality of signals, provided, e.g. transmitted, by the characterizing device to the DUT. Optionally, a relative position of the second antenna with respect to the first antenna may be fixed, or for example, a relative position of the second antenna with respect to the first antenna may be variable.

IPC Classes  ?

  • G01R 1/04 - Housings; Supporting members; Arrangements of terminals
  • G01R 31/28 - Testing of electronic circuits, e.g. by signal tracer
  • G01R 31/319 - Tester hardware, i.e. output processing circuits
  • G01R 31/317 - Testing of digital circuits

60.

MITIGATING AN INFLUENCE OF A MISMATCH LOSS IN A MEASUREMENT SETUP

      
Application Number 18335703
Status Pending
Filing Date 2023-06-15
First Publication Date 2023-10-12
Owner Advantest Corporation (Japan)
Inventor
  • Burczyk, Matthias
  • Richter, Andy

Abstract

Embodiments provide an apparatus including at least one of at least one transmission line or a phase shifting device. Further, the apparatus includes a measurement device operable to couple to a signal source via the at least transmission line to receive from the signal source a first signal comprising at least a first frequency. The measurement device is operable to output a measurement result based on the received first signal. The at least one transmission line and the phase shifting device are operable to induce a respective phase shift to the first signal. Also, the apparatus includes a measurement processing component operable to average a first measurement result and a second measurement result to generate a processed measurement result related to the first signal to mitigate an influence of a mismatch loss in a measurement setup environment.

IPC Classes  ?

  • G01R 31/28 - Testing of electronic circuits, e.g. by signal tracer
  • G01R 35/00 - Testing or calibrating of apparatus covered by the other groups of this subclass

61.

TEMPERATURE CONTROL DEVICE, ELECTRONIC COMPONENT HANDLING APPARATUS, ELECTRONIC COMPONENT TEST APPARATUS, AND DUT TEMPERATURE CONTROL METHOD

      
Application Number 18091814
Status Pending
Filing Date 2022-12-30
First Publication Date 2023-10-05
Owner ADVANTEST Corporation (Japan)
Inventor Kikuchi, Aritomo

Abstract

A temperature control device controls a temperature of a device under test (DUT) including a device flow path in testing the DUT, and includes: a first flow path that has a first connection port to be connected to an inlet of the device flow path; and a fluid supply system that is connected to the first flow path and supplies a first fluid for temperature control to the device flow path.

IPC Classes  ?

  • G01R 31/28 - Testing of electronic circuits, e.g. by signal tracer

62.

SOCKET ASSEMBLY AND ELECTRONIC COMPONENT TEST DEVICE

      
Application Number JP2022014094
Publication Number 2023/181290
Status In Force
Filing Date 2022-03-24
Publication Date 2023-09-28
Owner ADVANTEST CORPORATION (Japan)
Inventor
  • Shiota, Natsuki
  • Kato, Yasuyuki
  • Moreira, Jose

Abstract

Provided is a socket assembly 50 for use in an electronic component test device 1 for testing a DUT 10 having a device antenna 12, the socket assembly comprising: a socket 51 to which the DUT 10 is mounted; a pusher 53 that is provided between the socket 51 and an antenna unit 52 having a test antenna 52b opposed to the socket 51, and pushes the DUT 10 toward the socket 51; and a frame 54 that is overlayed on the pusher 53 and reinforces the pusher 53. The dielectric constant of the material composing the pusher 53 is lower than the dielectric constant of the material composing the frame 54.

IPC Classes  ?

  • G01R 31/26 - Testing of individual semiconductor devices

63.

ELECTRONIC COMPONENT HANDLING APPARATUS AND ELECTRONIC COMPONENT TESTING APPARATUS

      
Application Number 18085794
Status Pending
Filing Date 2022-12-21
First Publication Date 2023-09-28
Owner ADVANTEST Corporation (Japan)
Inventor Yamada, Yuya

Abstract

An electronic component handling apparatus that handles a DUT or a carrier accommodating the DUT, including: a pressing device that: electrically connects the DUT to a socket by pressing the DUT or the carrier toward the socket, and includes: a temperature control device that: controls a temperature of the DUT, and includes: a heater unit that is a heat source, the heater unit including: a flat heater; a first heat transfer material disposed on a first main surface of the flat heater; and a second heat transfer material disposed on a second main surface of the flat heater.

IPC Classes  ?

  • G01R 31/28 - Testing of electronic circuits, e.g. by signal tracer
  • G01R 1/04 - Housings; Supporting members; Arrangements of terminals

64.

TEMPERATURE ADJUSTING DEVICE, ELECTRONIC COMPONENT HANDLING APPARATUS, AND ELECTRONIC COMPONENT TEST APPARATUS

      
Application Number 18163056
Status Pending
Filing Date 2023-02-01
First Publication Date 2023-09-21
Owner ADVANTEST Corporation (Japan)
Inventor
  • Yamada, Yuya
  • Kikuchi, Aritomo
  • Kato, Yasuyuki

Abstract

A temperature adjusting device adjusts a temperature of a device under test (DUT) electrically connected to a socket, and includes: a fluid connector connected to a fluid supply source that supplies a fluid; a heat exchanger thermally connected to at least one of the DUT and a carrier holding the DUT in a state that the at least one of the DUT and the carrier is pressed against the socket; a first flow path passing through an inside of the heat exchanger; and a first swirl flow forming part that swirls a flow of the fluid to form a first swirl flow and supplies the first swirl flow to the first flow path, the first swirl swirling along an inner surface of the first flow path around a first central axis of the first flow path.

IPC Classes  ?

  • G01R 31/28 - Testing of electronic circuits, e.g. by signal tracer
  • F28F 13/12 - Arrangements for modifying heat transfer, e.g. increasing, decreasing by affecting the pattern of flow of the heat-exchange media by creating turbulence, e.g. by stirring, by increasing the force of circulation

65.

TEMPERATURE CONTROL APPARATUS, TESTING APPARATUS, TEMPERATURE CONTROL METHOD, AND TEMPERATURE CONTROL PROGRAM

      
Application Number JP2022009709
Publication Number 2023/170737
Status In Force
Filing Date 2022-03-07
Publication Date 2023-09-14
Owner ADVANTEST CORPORATION (Japan)
Inventor
  • Kikuchi Aritomo
  • Ranganathan, Karthik

Abstract

Provided is a temperature control device comprising: a placement part that has a placement surface on which is placed a plate-like object to be tested having a plurality of devices formed thereon; a plurality of heaters that are respectively provided to a plurality of zones into which the placement surface is divided, and that each heat a corresponding zone; a device temperature acquisition unit that acquires device temperature data corresponding to a measured temperature value of a testing target device, among the plurality of devices of the object to be tested, which has a probe for operation testing connected thereto; and a temperature control unit that controls at least one heater corresponding to at least one zone in which at least part of the testing target device is placed, and that causes the temperature indicated by the device temperature data to approach a first target temperature.

IPC Classes  ?

  • H01L 21/66 - Testing or measuring during manufacture or treatment

66.

METHODS AND DEVICES FOR TESTING A DEVICE UNDER TEST USING MULTIPLE SIGNALS TRANSMITTED VIA A BIDIRECTIONAL REAL-TIME INTERFACE

      
Application Number 18104183
Status Pending
Filing Date 2023-01-31
First Publication Date 2023-09-07
Owner Advantest Corporation (Japan)
Inventor
  • Werner, Matthias
  • Fischer, Martin

Abstract

Embodiments of the present invention provide an automated test equipment (a “tester”) for testing a device under test, including a bidirectional dedicated real-time handler interface. Some embodiments include an interface having a trigger function, a fixed endpoint interface, an interface arranged on a test head, and/or a number of lines/communication channels adapted to a specific communication task, without separate signal lines, for example. The bidirectional dedicated real-time handler interface can be used to transmit a multiple signals, such as a thermal control signal, synchronization signal, and/or other information to the handler in real-time, and the transmitted signals can be test site specific. The real-time signaling advantageously improves testing accuracy and efficiency.

IPC Classes  ?

  • G01R 31/28 - Testing of electronic circuits, e.g. by signal tracer

67.

SEMICONDUCTOR TEST RESULT ANALYZING DEVICE, SEMICONDUCTOR TEST RESULT ANALYZING METHOD AND COMPUTER PROGRAM

      
Application Number JP2022008767
Publication Number 2023/166584
Status In Force
Filing Date 2022-03-02
Publication Date 2023-09-07
Owner ADVANTEST CORPORATION (Japan)
Inventor
  • Ikeda Kosuke
  • Sugimura Hajime

Abstract

A condition data acquiring unit 30 acquires first data (condition data) of a plurality of items related to a test process for a plurality of semiconductor chips. A test result acquiring unit 32 acquires second data (test result data) indicating the test results of the plurality of semiconductor chips in the test process. A decision tree generating unit 34 generates a decision tree using the items of the condition data as features and the test result data as target values. An analysis result outputting unit 40 outputs the information of features with relatively high significance in the decision tree as the items that have a large degree of influence on the test results.

IPC Classes  ?

  • H01L 21/66 - Testing or measuring during manufacture or treatment

68.

SEMICONDUCTOR TESTING RESULT ANALYZING DEVICE, SEMICONDUCTOR TESTING RESULT ANALYZING METHOD, AND COMPUTER PROGRAM

      
Application Number JP2022008768
Publication Number 2023/166585
Status In Force
Filing Date 2022-03-02
Publication Date 2023-09-07
Owner ADVANTEST CORPORATION (Japan)
Inventor
  • Ikeda Kosuke
  • Gunya Tatsuaki

Abstract

A condition data acquisition unit 30 acquires first data (condition data) of a plurality of items relating to a testing process for a plurality of semiconductor chips. A testing result acquisition unit 32 acquires second data (testing result data) indicating the testing result on the semiconductor chips in the testing process. A graph generation unit 38 generates, in a region in which the items of the condition data are arranged along one axis and a plurality of values for each of the items are arranged in a direction orthogonal to the axis, a graph image in which values corresponding to the respective items are connected by a line, for each group of a plurality of the semiconductor chips in an identical testing environment. The graph generation unit 38 changes the mode of the line for each group in the graph image in accordance with the proportion of semiconductor chips that had unsuccessful testing results in the group.

IPC Classes  ?

  • H01L 21/66 - Testing or measuring during manufacture or treatment

69.

POWER SUPPLY DEVICE

      
Application Number 18312009
Status Pending
Filing Date 2023-05-04
First Publication Date 2023-08-31
Owner ADVANTEST CORPORATION (Japan)
Inventor
  • Shimizu, Takahiko
  • Imai, Shoichiro

Abstract

A power supply apparatus includes multiple channels of power supply units coupled in a stack connection. Each power supply unit includes an output stage configured to generate an output voltage across a positive output and a negative output according to a control signal. A current detector of a master channel generates a current detection signal that indicates an output current of the output stage. A feedback controller generates the control signal such that the current detection signal approaches a target value.

IPC Classes  ?

  • H02M 3/335 - Conversion of dc power input into dc power output with intermediate conversion into ac by static converters using discharge tubes with control electrode or semiconductor devices with control electrode to produce the intermediate ac using devices of a triode or a transistor type requiring continuous application of a control signal using semiconductor devices only
  • H02M 1/00 - APPARATUS FOR CONVERSION BETWEEN AC AND AC, BETWEEN AC AND DC, OR BETWEEN DC AND DC, AND FOR USE WITH MAINS OR SIMILAR POWER SUPPLY SYSTEMS; CONVERSION OF DC OR AC INPUT POWER INTO SURGE OUTPUT POWER; CONTROL OR REGULATION THEREOF - Details of apparatus for conversion

70.

METHODS AND DEVICES FOR TESTING A DEVICE UNDER TEST USING A SYNCHRONIZATION SIGNAL

      
Application Number 18104159
Status Pending
Filing Date 2023-01-31
First Publication Date 2023-08-24
Owner Advantest Corporation (Japan)
Inventor
  • Werner, Matthias
  • Fischer, Martin

Abstract

Embodiments of the present invention provide an automated test equipment (a “tester”) for testing a device under test, including a bidirectional dedicated real-time handler interface. Some embodiments use the bidirectional dedicated real-time handler interface to transmit a synchronization signal between the handler and the automated test equipment to synchronize a function of the handler in real-time, which advantageously improves testing efficiency and accuracy.

IPC Classes  ?

  • G01R 31/28 - Testing of electronic circuits, e.g. by signal tracer

71.

BIOSENSOR

      
Application Number 18304858
Status Pending
Filing Date 2023-04-21
First Publication Date 2023-08-17
Owner ADVANTEST CORPORATION (Japan)
Inventor Nakamura, Kiyoto

Abstract

A container holds a liquid sample containing a substrate to be detected. A reactant member is provided in the inner part of the container. The reactant member contains an enzyme and a resin in a state in which they are not mixed.

IPC Classes  ?

  • C12M 1/34 - Measuring or testing with condition measuring or sensing means, e.g. colony counters
  • G01N 25/48 - Investigating or analysing materials by the use of thermal means by investigating the development of heat, i.e. calorimetry, e.g. by measuring specific heat, by measuring thermal conductivity on solution, sorption, or a chemical reaction not involving combustion or catalytic oxidation

72.

ELECTRONIC COMPONENT HANDLING APPARATUS AND ELECTRONIC COMPONENT TESTING APPARATUS

      
Application Number 18085917
Status Pending
Filing Date 2022-12-21
First Publication Date 2023-08-10
Owner ADVANTEST Corporation (Japan)
Inventor Yamada, Yuya

Abstract

An electronic component handling apparatus that handles a pressed body including a DUT or a carrier accommodating the DUT, includes: a pressing device that electrically connects the DUT to a socket by pressing the pressed body toward the socket, and includes: a contact plate that contacts the pressed body; and a retainer that holds the contact plate, the contact plate being separated from the retainer while the contact plate contacts the pressed body, and the contact plate being held by the retainer while the contact plate is separated from the pressed body.

IPC Classes  ?

  • G01R 31/28 - Testing of electronic circuits, e.g. by signal tracer

73.

MULTI-SECTION DIRECTIONAL COUPLER, A METHOD FOR MANUFACTURING A MULTI-SECTION DIRECTIONAL COUPLER AND A METHOD FOR OPERATING A MULTI-SECTION DIRECTIONAL COUPLER

      
Application Number 18193612
Status Pending
Filing Date 2023-03-30
First Publication Date 2023-07-27
Owner Advantest Corporation (Japan)
Inventor Bianchi, Giovanni

Abstract

The disclosure describes a multi-section directional coupler comprising: a plurality of conductive lines, each conductive line comprises a plurality of line sections; a plurality of coupled line sections, each coupled line section comprises a first line section of a first conductive line and a second line section of a second conductive line, the coupled line sections comprise different coupling strength values, the coupled line sections facilitate signal coupling; and at least one grounded conductive coupling reduction structure arranged adjacent to a selected coupled line section and operable to reduce a coupling value between a respective line section of the first conductive line and a respective line section of the second conductive line of the selected coupled line section. The selected coupled line section comprises a smaller coupling strength value than another one of the coupled line sections. Methods of manufacturing and operating the multi-section directional coupler are also provided.

IPC Classes  ?

  • H01P 5/18 - Conjugate devices, i.e. devices having at least one port decoupled from one other port consisting of two coupled guides, e.g. directional couplers

74.

METHODS AND DEVICES FOR TESTING A DEVICE UNDER TEST USING TEST SITE SPECIFIC THERMAL CONTROL SIGNALING

      
Application Number 18104165
Status Pending
Filing Date 2023-01-31
First Publication Date 2023-07-20
Owner Advantest Corporation (Japan)
Inventor Werner, Matthias

Abstract

Embodiments of the present invention provide an automated test equipment (a “tester”) for testing a device under test, including a bidirectional dedicated real-time handler interface. Some embodiments include an interface having a trigger function, a fixed endpoint interface, an interface arranged on a test head, and/or a number of lines/communication channels adapted to a specific communication task, without separate signal lines, for example. The bidirectional dedicated real-time handler interface can be used to transmit thermal control signals, and the transmitted signals can be test site specific. The real-time signaling advantageously improves testing accuracy and efficiency.

IPC Classes  ?

  • G01R 31/28 - Testing of electronic circuits, e.g. by signal tracer
  • G01R 31/317 - Testing of digital circuits

75.

DETECTION METHOD, SYSTEM, ELECTRONIC EQUIPMENT, AND STORAGE MEDIUM OF PRODUCT TEST DATA

      
Application Number 18119844
Status Pending
Filing Date 2023-03-10
First Publication Date 2023-07-06
Owner ADVANTEST CORPORATION (Japan)
Inventor Xu, Kun

Abstract

The present invention discloses a detection method, a system, an electronic equipment, and a storage medium of product test data, where the detection method includes: obtaining historical test data of historical batches of products; screening the historical test data to obtain intermediate test data; grouping the intermediate test data based on preset test parameters to obtain first groups; obtaining distribution patterns of the first groups based on the intermediate test data of the first groups; when the distribution pattern is a preset distribution pattern, using the first group corresponding to the distribution pattern as a target group; and obtaining a target test limit value based on the intermediate test data corresponding to the target group. In the present invention, the test limit value can be adjusted dynamically and adaptively, and chip test data with abnormal data can be effectively detected in real time, which improves test quality of the chip.

IPC Classes  ?

  • G06F 30/333 - Design for testability [DFT], e.g. scan chain or built-in self-test [BIST]

76.

METHOD AND APPARATUS FOR DETERMINING AN INFORMATION ABOUT CHARACTERISTICS OF ONE OR MORE DEVICES UNDER TEST, DUTs, USING A STATISTICALLY SIGNIFICANT DISSIMILARITY VALUE

      
Application Number EP2022067632
Publication Number 2023/126079
Status In Force
Filing Date 2022-06-27
Publication Date 2023-07-06
Owner ADVANTEST CORPORATION (Japan)
Inventor Rivoir, Jochen

Abstract

Embodiments comprise methods and apparatuses for determining an information about characteristics of one or more devices under test (DUTs) using measurement data from an automated test equipment (ATE), the measurement data comprising a plurality of measurement results and information describing corresponding measurement conditions of the devices under test (DUTs).

IPC Classes  ?

  • G01R 31/28 - Testing of electronic circuits, e.g. by signal tracer
  • G06F 11/26 - Functional testing

77.

MEASUREMENT ARRANGEMENT AND METHOD FOR CHARACTERIZING A RADIO FREQUENCY ARRANGEMENT COMPRISING A PLURALITY OF ANTENNAS

      
Application Number EP2021086040
Publication Number 2023/110094
Status In Force
Filing Date 2021-12-15
Publication Date 2023-06-22
Owner
  • ADVANTEST CORPORATION (Japan)
  • UNIVERSITÄT STUTTGART (Germany)
Inventor
  • Hesselbarth, Jan
  • Moreira, José
  • Fischer, Serafin

Abstract

An embodiment according to the present invention is a measurement arrangement for characterizing a radio frequency arrangement (110) comprising a plurality of antennas (120), such as a large array of patch antennas. The measurement arrangement comprises a dielectric waveguide slab (130) with a plurality of frequency converting structures (150), arranged in or on the dielectric waveguide slab. The measurement arrangement further comprises a plurality of waveguide transitions (140) arranged at different positions of the dielectric waveguide slab and are coupled to respective radio frequency components (160). The radio frequency components are configured to transmit and/or receive radio signals (233), like transmitters, receivers or transceivers. The frequency converting structures are associated with respective antennas of the plurality of antennas, and are configured to perform a frequency conversion on signals received, resulting in frequency-converted signals. The frequency converting structures are further configured to couple respective antennas with the dielectric slab in a frequency converting manner, to thereby establish a frequency-converting coupling between the antennas and the plurality of waveguide transitions, resulting in a frequency-converting coupling between the antennas and the radio frequency components. The measurement arrangement is configured to use the frequency-converting coupling between the antennas and the radio frequency components for characterizing the radio frequency arrangement. The radio frequency arrangement can comprise antennas and/or radio frequency frontends connected to the antennas.

IPC Classes  ?

  • G01R 29/08 - Measuring electromagnetic field characteristics

78.

CAPACITOR IN SOCKET

      
Application Number 18109199
Status Pending
Filing Date 2023-02-13
First Publication Date 2023-06-22
Owner Advantest America, Inc. (USA)
Inventor Thompson, Donald Eric

Abstract

An improved method and structure for forming an electrical interconnects mechanism in a Power Distribution Network (PDN) by placing capacitors on the top of the pin array on the printed circuit board (PCB) of the structure to decouple the PDN and results in lower impedance benefitting the frequency range of the PDN effecting a significant performance improvement in the spring-pin inductance from the transmission line. This reduction in impedance reduces the power supply ripple.

IPC Classes  ?

  • H01R 13/66 - Structural association with built-in electrical component
  • G01R 1/073 - Multiple probes
  • H01R 13/17 - Pins, blades or sockets having separate spring member for producing or increasing contact pressure the spring member being on the pin

79.

TEMPERATURE ADJUSTING UNIT, ELECTRONIC COMPONENT HANDLING DEVICE, AND ELECTRONIC COMPONENT TESTING DEVICE

      
Application Number JP2021046343
Publication Number 2023/112221
Status In Force
Filing Date 2021-12-15
Publication Date 2023-06-22
Owner ADVANTEST CORPORATION (Japan)
Inventor
  • Yamada, Yuya
  • Kikuchi, Aritomo
  • Jeserer, Guenther
  • Wallner, Merlin

Abstract

This temperature adjusting unit 30 that adjusts the temperature of a DUT 200 comprises: a heat exchanger 31 that has a heat exchange unit 33 that is in contact with the DUT 200 and performs heat exchange with the DUT 200; a heater 40; and an air cylinder 50 that moves the heater 40 relative to the heat exchange unit 33. The heat exchanger 31 has flow paths 34 and 35 through which a refrigerant used for the temperature adjustment of the DUT 200 can flow, and that pass through the heat exchange unit 33. The air cylinder 50 causes the heater 40 to come into contact with or move away from the heat exchange unit 33 by moving the heater 40 relatively.

IPC Classes  ?

  • G01R 31/26 - Testing of individual semiconductor devices
  • G01R 31/28 - Testing of electronic circuits, e.g. by signal tracer

80.

METHODS AND DEVICES FOR TESTING A DEVICE UNDER TEST USING TEST SITE SPECIFIC CONTROL SIGNALING

      
Application Number 18104193
Status Pending
Filing Date 2023-01-31
First Publication Date 2023-06-15
Owner ADVANTEST CORPORATION (Japan)
Inventor Werner, Matthias

Abstract

Embodiments of the present invention provide an automated test equipment (a “tester”) for testing a device under test, including a bidirectional dedicated real-time handler interface. Some embodiments include an interface having a trigger function, a fixed endpoint interface, an interface arranged on a test head, and/or a number of lines/communication channels adapted to a specific communication task, without separate signal lines, for example. The bidirectional dedicated real-time handler interface can be used to transmit a synchronization signal or other information to the handler in real-time, and the transmitted signal can be test site specific. The real-time signaling advantageously improves testing accuracy and efficiency.

IPC Classes  ?

  • G01R 31/28 - Testing of electronic circuits, e.g. by signal tracer
  • G01R 31/319 - Tester hardware, i.e. output processing circuits

81.

SYSTEMS AND METHODS FOR DETERMINING A VALID STATE OF MEASUREMENT SYSTEMS

      
Application Number 18105169
Status Pending
Filing Date 2023-02-02
First Publication Date 2023-06-15
Owner Advantest Corporation (Japan)
Inventor
  • Beterke, Bernd
  • Skwierawski, Piotr
  • Funke, Petra
  • Friedrich, Roland

Abstract

Methods and systems for determining whether a measurement system is used in a valid state, includes: automatically reading out a plurality of information items; automatically obtaining information on current operating environmental conditions; automatically reading reference information items identifying the measurement system components and/or representing one or more characteristics of the measurement system components and information on reference operating environmental conditions; and comparing the read out information items identifying the measurement system components and/or representing one or more characteristics of the measurement system components with the reference information items identifying the measurement system components and/or representing one or more characteristics of the measurement system components, and checking whether the current operating environmental conditions comprise an allowable value or are within an allowable range defined by the information on the reference operating environmental conditions, in order to determine whether the measurement system comprising the plurality of measurement system components is used in the valid state.

IPC Classes  ?

  • G06K 7/10 - Methods or arrangements for sensing record carriers by corpuscular radiation

82.

TEST ARRANGEMENT FOR TESTING ONE OR MORE DEVICES, TEST SUPPORT MODULE FOR SUPPORTING TESTING ONE OR MORE DEVICES, AND METHOD FOR OPERATING AN AUTOMATED TEST EQUIPMENT

      
Application Number 18162699
Status Pending
Filing Date 2023-01-31
First Publication Date 2023-06-15
Owner Advantest Corporation (Japan)
Inventor Werner, Matthias

Abstract

The disclosure describes a test support module for supporting a test of at least one device under test (DUT). The test support module comprises a plurality of pogo pins configured to establish a connection to at least one of a load board or a probe card of an automated test equipment and at least one electronic support component configured to support a test of at least one DUT. The at least one electronic support component is electrically coupled to the pogo pins. The test support module is configured to be inserted into a pogo block frame of the automated test equipment to position the pogo pins in an alignment position to contact at least one of the load board or the probe card. The testing innovation is more efficient in view of customization, life duration of the components, high signal performance, tester channel resources, re-usability, and costs.

IPC Classes  ?

83.

ELECTRONIC CIRCUIT, AUTOMATED TEST EQUIPMENT, METHOD AND COMPUTER PROGRAM FOR MITIGATING AN INFLUENCE OF A MISMATCH LOSS IN A MEASUREMENT SETUP

      
Application Number EP2021085114
Publication Number 2023/104314
Status In Force
Filing Date 2021-12-09
Publication Date 2023-06-15
Owner ADVANTEST CORPORATION (Japan)
Inventor
  • Burczyk, Matthias
  • Richter, Andy

Abstract

Embodiments according to the invention comprise an Automated Test Equipment (ATE) for mitigating an influence of a mismatch loss in a measurement setup, the setup comprising a source (110), a measurement device (120), and a first transmission line (130), wherein the first transmission line (130) is configured to couple the source (110) and the measurement device (120), and wherein the source (110) is configured to provide a first signal comprising at least a first frequency, for the measurement device (120). In addition, the Automated Test Equipment (ATE) is configured to average a first measurement result and a second measurement result, in order to obtain a processed measurement result, wherein the first measurement is performed when the signal source, while providing the first signal for the measurement device (120), and the measurement device (120) are coupled with the first transmission line (130). The second measurement is performed when the signal source (110), while providing the first signal for the measurement device (120), and the measurement device (120) are coupled with a second transmission line (150), wherein the second transmission line (150) is configured to induce a phase shift to the first signal at least for the first frequency of the signal, or when the signal source, while providing the first signal for the measurement device (120), and the measurement device are coupled with the first transmission (130) line and a phase shifting device (140), wherein the phase shifting device (140) is configured to induce a phase shift to the first signal at least for the first frequency of the signal, such that a phase shift between the source (110) and the measurement device (120) differs by a phase offset between the first measurement and the second measurement at least for the first frequency.

IPC Classes  ?

  • G01R 31/42 - AC power supplies
  • G01R 35/00 - Testing or calibrating of apparatus covered by the other groups of this subclass
  • G01R 27/28 - Measuring attenuation, gain, phase shift, or derived characteristics of electric four-pole networks, i.e. two-port networks; Measuring transient response
  • H04B 17/15 - Performance testing
  • H01P 1/18 - Phase-shifters
  • G01R 27/02 - Measuring real or complex resistance, reactance, impedance, or other two-pole characteristics derived therefrom, e.g. time constant

84.

METHODS AND DEVICES FOR TESTING A DEVICE UNDER TEST USING A BIDIRECTIONAL REAL-TIME INTERFACE

      
Application Number 18104149
Status Pending
Filing Date 2023-01-31
First Publication Date 2023-06-15
Owner ADVANTEST CORPORATION (Japan)
Inventor
  • Werner, Matthias
  • Fischer, Martin

Abstract

Embodiments of the present invention provide an automated test equipment (a “tester”) for testing a device under test, including a bidirectional dedicated real-time handler interface. Some embodiments include an interface having a trigger function, a fixed endpoint interface, an interface arranged on a test head, and/or a number of lines/communication channels adapted to a specific communication task, without separate signal lines, for example. The bidirectional dedicated real-time handler interface can be used to transmit a synchronization signal or other information to the handler in real-time, and the transmitted signal can be test site specific. The real-time signaling advantageously improves testing accuracy and efficiency.

IPC Classes  ?

  • G01R 31/28 - Testing of electronic circuits, e.g. by signal tracer

85.

SIGNAL SOURCE IDENTIFYING DEVICE, METHOD, PROGRAM, AND RECORDING MEDIUM

      
Application Number JP2022035075
Publication Number 2023/105885
Status In Force
Filing Date 2022-09-21
Publication Date 2023-06-15
Owner ADVANTEST CORPORATION (Japan)
Inventor
  • Ogata Yuji
  • Yanagida Tomonori

Abstract

This signal source identifying device accepts signals represented by vectors having a prescribed direction from a plurality of signal sources, accepts measurement results of a plurality of sensors for measuring components in three mutually orthogonal axes, and identifies positions of the signal sources, and the vectors. The signal source identifying device comprises a relation matrix recording unit, and a position/vector deriving unit. The relation matrix recording unit records a relation matrix representing a relationship between the measurement results, grouped into the number of sensors, for each axis, and the vectors. The position/vector deriving unit derives the positions of the signal sources and the vectors that minimize a cost function, on the basis of the measurement results and the relation matrix. In the vectors, the components are grouped, for each axis, into a number of grid points in a space in which the signal sources are positioned, for each axis.

IPC Classes  ?

  • G01C 15/00 - Surveying instruments or accessories not provided for in groups
  • G01R 29/00 - Arrangements for measuring or indicating electric quantities not covered by groups
  • G01R 33/02 - Measuring direction or magnitude of magnetic fields or magnetic flux
  • G01S 5/02 - Position-fixing by co-ordinating two or more direction or position-line determinations; Position-fixing by co-ordinating two or more distance determinations using radio waves

86.

PROTECTING A MEASUREMENT SYSTEM FROM UNAUTHORIZED CHANGES

      
Application Number 18162702
Status Pending
Filing Date 2023-01-31
First Publication Date 2023-06-08
Owner ADVANTEST CORPORATION (Japan)
Inventor
  • Beterke, Bernd
  • Skwierawski, Piotr
  • Funke, Petra
  • Friedrich, Roland

Abstract

The disclosure describes a method of protecting a measurement system from unauthorized changes. The method comprises automatically reading out a plurality of information items from the measurement system, wherein the measurement system comprises a plurality of measurement system components and at least one local storage device, wherein the plurality of information items include at least one of identity of the measurement system components or at least one characteristic of the measurement system components; automatically combining the read out information items of each of the plurality of the measurement system components into a data collection and generating a summary data which represents the data collection; creating a signature based on the summary data; and storing the summary data and the signature in the at least one local storage device of the measurement system. This method provides more efficient and secure protection of measurement system and its components from an unauthorized change.

IPC Classes  ?

  • G06F 21/82 - Protecting input, output or interconnection devices
  • G06F 21/64 - Protecting data integrity, e.g. using checksums, certificates or signatures
  • G06F 21/60 - Protecting data

87.

OPTICAL CIRCUIT, OPTICAL INTEGRATED CIRCUIT, AND METHOD FOR PROVIDING POLARIZATION-INDEPENDENT OUTPUT LIGHT

      
Application Number JP2021043593
Publication Number 2023/095323
Status In Force
Filing Date 2021-11-29
Publication Date 2023-06-01
Owner ADVANTEST CORPORATION (Japan)
Inventor
  • Uekusa Kouichiro
  • Ishida Masahiro

Abstract

An optical circuit (100) comprises: a polarization rotation/separation element (110) that spatially separates and outputs a first component being a component in a first polarization direction out of input light, and a second component obtained by converting a component in a second polarization direction orthogonal to the first polarization direction out of the input light into the first polarization direction; a multiplexer (120) that is disposed on the output side of the polarization rotation/separation element (110) and multiplexes the first component and the second component; and at least one attenuation element (131, 133) that is disposed on the output side of the polarization rotation/separation element (110) and attenuates optical power of one of the first component and the second component, both of the first component and the second component, or multiplexed light multiplexed by the multiplexer (120).

IPC Classes  ?

  • G02B 6/126 - Light guides; Structural details of arrangements comprising light guides and other optical elements, e.g. couplings of the optical waveguide type of the integrated circuit kind using polarisation effects
  • G02B 6/12 - Light guides; Structural details of arrangements comprising light guides and other optical elements, e.g. couplings of the optical waveguide type of the integrated circuit kind

88.

TEMPERATURE ADJUSTMENT DEVICE AND ELECTRONIC COMPONENT TESTING DEVICE

      
Application Number JP2021041221
Publication Number 2023/084612
Status In Force
Filing Date 2021-11-09
Publication Date 2023-05-19
Owner ADVANTEST CORPORATION (Japan)
Inventor
  • Yamada, Yuya
  • Kikuchi, Aritomo
  • Jeserer, Guenther
  • Wallner, Merlin

Abstract

This temperature adjustment device 6 comprises: a continuous flow supply unit 7 for supplying a first fluid; a pulse flow supply unit 8 for supplying a second fluid that has a different temperature than the first fluid; and a mixing unit 9 for mixing the first fluid supplied from the continuous flow supply unit 7 and the second fluid supplied from the pulse flow supply unit 8, and supplying the resultant mixed fluid to an internal space 34 in a socket 3.

IPC Classes  ?

  • G01R 31/26 - Testing of individual semiconductor devices
  • G01R 31/28 - Testing of electronic circuits, e.g. by signal tracer

89.

TEMPERATURE ADJUSTMENT SYSTEM AND ELECTRONIC COMPONENT TEST DEVICE

      
Application Number JP2021041224
Publication Number 2023/084613
Status In Force
Filing Date 2021-11-09
Publication Date 2023-05-19
Owner ADVANTEST CORPORATION (Japan)
Inventor
  • Yamada, Yuya
  • Jeserer, Guenther

Abstract

22 supply source 200 that supplies the first fluid; and a heat exchanger 74 interposed between the connecting parts 71a, 71b and the internal space 34. The heat exchanger 74 exchanges heat between the first fluid and the atmosphere of the chamber 52.

IPC Classes  ?

  • G01R 31/26 - Testing of individual semiconductor devices
  • G01R 31/28 - Testing of electronic circuits, e.g. by signal tracer

90.

AUTOMATED TEST EQUIPMENT AND METHOD USING A TRIGGER GENERATION

      
Application Number 18099613
Status Pending
Filing Date 2023-01-20
First Publication Date 2023-05-18
Owner ADVANTEST CORPORATION (Japan)
Inventor
  • Sauer, Matthias
  • Pöppe, Olaf

Abstract

An automated test equipment comprises a main test flow control configured to operate a test flow in multiple device communication units and/or to provide the trigger configuration information to a local compute unit. The automated test equipment further comprises a device communication unit comprising a trigger generation unit configured to generate a trigger signal. The trigger generation unit further configured to extract payload data from a protocol-based data stream received from the device under test, and to generate the trigger signal in response to the extracted payload data or in response to one or more protocol events. A method and a computer program for testing one or more devices under test in an automated test equipment are also disclosed.

IPC Classes  ?

  • G01R 31/3183 - Generation of test inputs, e.g. test vectors, patterns or sequences
  • G01R 31/319 - Tester hardware, i.e. output processing circuits

91.

AUTOMATED TEST EQUIPMENT, DEVICE UNDER TEST, TEST SETUP METHODS USING A TRIGGER LINE

      
Application Number EP2021080990
Publication Number 2023/078572
Status In Force
Filing Date 2021-11-08
Publication Date 2023-05-11
Owner ADVANTEST CORPORATION (Japan)
Inventor
  • Hilliges, Klaus-Dieter
  • Bücker, Markus
  • Schulze-Westenhorst, Marcus
  • Pöppe, Olaf
  • Glos, Thomas

Abstract

An automated test equipment for testing a device under test comprises a trigger line which is controllable by the device under test (or, equivalently, by a test case which may, for example, be executed on the device under test). The automated test equipment is configured to update one or more tester resources in response to an activation of the trigger line by the device under test (or, equivalently, by a test case which may, for example, be executed on the device under test). A device under test, methods and a computer program are also described.

IPC Classes  ?

  • G01R 31/28 - Testing of electronic circuits, e.g. by signal tracer
  • G01R 31/319 - Tester hardware, i.e. output processing circuits
  • G01R 13/02 - Arrangements for displaying electric variables or waveforms for displaying measured electric variables in digital form

92.

AUTOMATED TEST EQUIPMENT, DEVICE UNDER TEST, TEST SETUP METHODS USING A MEASUREMENT REQUEST

      
Application Number EP2021080991
Publication Number 2023/078573
Status In Force
Filing Date 2021-11-08
Publication Date 2023-05-11
Owner ADVANTEST CORPORATION (Japan)
Inventor
  • Hilliges, Klaus-Dieter
  • Bücker, Markus
  • Schulze-Westenhorst, Marcus
  • Pöppe, Olaf
  • Glos, Thomas

Abstract

An automated test equipment for testing one or more devices under test is configured to receive, from a device under test, a command requesting a measurement of one or more physical quantities. The automated test equipment is configured to perform or initiate the measurement of the one or more physical quantities in response to the command provided by the device under test, and the automated test equipment is configured to provide a measurement result signaling to the device under test, to thereby signal a measurement result requested by the device under test. A device under test, methods and a computer program are also described

IPC Classes  ?

  • G01R 31/319 - Tester hardware, i.e. output processing circuits
  • G01R 13/02 - Arrangements for displaying electric variables or waveforms for displaying measured electric variables in digital form
  • G01R 31/28 - Testing of electronic circuits, e.g. by signal tracer
  • G06F 11/273 - Tester hardware, i.e. output processing circuits

93.

AUTOMATED TEST EQUIPMENT, DEVICE UNDER TEST, TEST SETUP METHODS USING AN ACKNOWLEDGE SIGNALING

      
Application Number EP2021080989
Publication Number 2023/078571
Status In Force
Filing Date 2021-11-08
Publication Date 2023-05-11
Owner ADVANTEST CORPORATION (Japan)
Inventor
  • Hilliges, Klaus-Dieter
  • Bücker, Markus
  • Schulze-Westenhorst, Marcus
  • Pöppe, Olaf
  • Glos, Thomas

Abstract

An automated test equipment for testing one or more devices under test is configured to receive, from a device under test or from a test case, a command requesting an update of one or more tester resources. The automated test equipment is configured to update one or more tester resources in response to the command provided by the device under test or by the test case. The automated test equipment is configured to provide an acknowledge signaling to the device under test or to the test case, to thereby signal a completion of a tester resource update requested by the device under test or by the test case. A device under test, methods and a computer program are also described

IPC Classes  ?

  • G01R 31/319 - Tester hardware, i.e. output processing circuits
  • G01R 31/28 - Testing of electronic circuits, e.g. by signal tracer
  • G01R 13/02 - Arrangements for displaying electric variables or waveforms for displaying measured electric variables in digital form
  • G06F 11/273 - Tester hardware, i.e. output processing circuits

94.

Test carrier

      
Application Number 17508077
Grant Number 11693026
Status In Force
Filing Date 2021-10-22
First Publication Date 2023-04-27
Grant Date 2023-07-04
Owner ADVANTEST Corporation (Japan)
Inventor Kiyokawa, Toshiyuki

Abstract

A test carrier that accommodates a device under test (DUT) and has a through-hole facing the DUT, including: a movable valve that: opens by suction through the through hole such that the DUT is sucked through the through hole.

IPC Classes  ?

  • G01R 31/28 - Testing of electronic circuits, e.g. by signal tracer
  • G01R 1/04 - Housings; Supporting members; Arrangements of terminals

95.

APPARATUS FOR TESTING A COMPONENT, METHOD OF TESTING THE COMPONENT, COMPUTER-READABLE STORAGE DEVICE FOR IMPLEMENTING THE METHOD, AND TEST ARRANGEMENT USING A MAGNETIC FIELD

      
Application Number 18069233
Status Pending
Filing Date 2022-12-21
First Publication Date 2023-04-20
Owner Advantest Corporation (Japan)
Inventor Mielke, Frank

Abstract

The disclosure describes an apparatus for testing a component, wherein the apparatus is configured to apply a magnetic field with a magnetic field orientation from a set of magnetic field orientations to the component. The apparatus is further configured to perform a test on the component in the presence of the respective magnetic fields with the respective magnetic field orientations from the set of magnetic field orientations to obtain an information characterizing an operation of the component. The apparatus is also configured to determine a test result based on the information characterizing the operation of the component in the presence of different magnetic fields with different magnetic field orientations from the set of magnetic field orientations. The disclosure also describes a method of testing and a computer-readable storage device for implementing the method and provides more efficiency in view of reliability and costs.

IPC Classes  ?

  • G01R 31/26 - Testing of individual semiconductor devices

96.

SYSTEMS AND METHODS FOR MULTIDIMENSIONAL DYNAMIC PART AVERAGE TESTING

      
Application Number 17497518
Status Pending
Filing Date 2021-10-08
First Publication Date 2023-04-13
Owner ADVANTEST CORPORATION (Japan)
Inventor
  • Butler, Kenneth
  • Leventhal, Ira
  • Xanthopoulos, Constantinos
  • Hart, Alan
  • Buras, Brian
  • Schaub, Keith

Abstract

Embodiments of the present invention provide systems and methods for multidimensional parts average testing for testing devices and analyzing testing results to detect outliers according to embodiments of the present invention. The testing can include calculating multivariate (e.g., bivariate) statistics using delta measurements of like devices, a ratio of measurements, or principal component analysis that identifies eigenvectors and eigenvalues to define meta parameters, for example. Raw test result data can be converted to residual space and robust regression can be performed to prevent outlier results from influencing regression, thereby reducing overkill advantageously.

IPC Classes  ?

  • G01R 31/26 - Testing of individual semiconductor devices

97.

SYSTEMS AND METHODS FOR MULTIDIMENSIONAL DYNAMIC PART AVERAGE TESTING

      
Application Number US2022045883
Publication Number 2023/059790
Status In Force
Filing Date 2022-10-06
Publication Date 2023-04-13
Owner ADVANTEST CORPORATION (Japan)
Inventor
  • Butler, Kenneth
  • Leventhal, Ira
  • Xanthopoulos, Constantinos
  • Hart, Alan
  • Buras, Brian
  • Schaub, Keith

Abstract

Embodiments of the present invention provide systems and methods for multidimensional parts average testing for testing devices and analyzing testing results to detect outliers according to embodiments of the present invention. The testing can include calculating multivariate (e.g., bivariate) statistics using delta measurements of like devices, a ratio of measurements, or principal component analysis that identifies eigenvectors and eigenvalues to define meta parameters, for example. Raw test result data can be converted to residual space and robust regression can be performed to prevent outlier results from influencing regression, thereby reducing overkill advantageously.

IPC Classes  ?

  • G01R 31/28 - Testing of electronic circuits, e.g. by signal tracer
  • G01R 31/30 - Marginal testing, e.g. by varying supply voltage
  • G06N 20/00 - Machine learning

98.

CONTROL DEVICES FOR CONTROLLING AN AUTOMATED TEST EQUIPMENT (ATE), ATE, METHODS FOR CONTROLLING AN ATE, METHODS FOR OPERATING AN ATE AND COMPUTER PROGRAMS FOR PERFORMING SUCH METHODS, COMPRISING A TEMPERATURE ESTIMATION OR DETERMINATION

      
Application Number EP2021077031
Publication Number 2023/051927
Status In Force
Filing Date 2021-09-30
Publication Date 2023-04-06
Owner ADVANTEST CORPORATION (Japan)
Inventor
  • Edelmann, Jens
  • Thoma, Anton

Abstract

Embodiments according to the invention comprise a control device for controlling an automated test equipment (ATE) for testing a device under test (DUT) which is electrically coupled to the automated test equipment using, or for example via, a device under test contacting structure, e.g. using or via a probe needle, or for example using or via a DUT socket. The control device is configured to determine or estimate a temperature of the DUT contacting structure using a thermal model, e.g. using a thermal model of the DUT contacting structure or using, for example, a thermal model comprising a thermal model of the DUT contacting structure. In addition, the control device is configured to influence, e.g. to control, to regulate, to deactivate and/or to limit, a signal applied to the DUT contacting structure in dependence on the determined or estimated, or for example modeled, temperature. Further embodiments comprise automated test equipments and control devices configured to determine or estimate a temperature of a DUT contact using a thermal model.

IPC Classes  ?

  • G01R 31/28 - Testing of electronic circuits, e.g. by signal tracer

99.

Calibration device, conversion device, calibration method, and non-transitory computer-readable medium having recorded thereon calibration program

      
Application Number 17832667
Grant Number 11784729
Status In Force
Filing Date 2022-06-05
First Publication Date 2023-04-06
Grant Date 2023-10-10
Owner
  • ADVANTEST CORPORATION (Japan)
  • The University of Tokyo (Japan)
Inventor
  • Asami, Koji
  • Iizuka, Tetsuya
  • Byambadorj, Zolboo

Abstract

There is provided a calibration device including: a calibration signal supply unit configured to supply, as a calibration input signal, a multitone signal having tones at a plurality of frequency bands to a converter configured to multiply an input signal by each of a plurality of signal patterns and limit a band to obtain each of a plurality of bandpass signals, and reconstruct an output signal in accordance with the input signal from the plurality of bandpass signals; a calibration bandpass signal acquisition unit configured to acquire a plurality of calibration bandpass signals obtained by the converter in response to the multitone signal; and a calibration processing unit configured to calibrate a parameter for the reconstruction in the converter based on the plurality of calibration bandpass signals.

IPC Classes  ?

  • H04B 17/21 - Monitoring; Testing of receivers for correcting measurements
  • H04B 17/40 - Monitoring; Testing of relay systems
  • H04B 17/318 - Received signal strength

100.

ELECTRONIC COMPONENT TESTING APPARATUS, SOCKET, AND CARRIER

      
Application Number 17898860
Status Pending
Filing Date 2022-08-30
First Publication Date 2023-04-06
Owner ADVANTEST Corporation (Japan)
Inventor
  • Imaizumi, Naoto
  • Kim, Sungywen
  • Nagashima, Masanori
  • Kawashima, Takashi
  • Ito, Akihiko

Abstract

An electronic component testing apparatus that tests a DUT (device under test) disposed in a carrier includes: a test head including a socket; and an electronic component handling apparatus that presses the DUT in the carrier against the socket. The socket includes: contactors disposed to correspond to terminals of the DUT that are exposed to the socket via a first opening of the carrier; and a first wall projecting toward the carrier along a pressing direction of the DUT. The electronic component handling apparatus aligns the terminals with the contactors by pressing the DUT against the socket such that a first pressing mechanism of the carrier presses the DUT against the first wall.

IPC Classes  ?

  • G01R 31/28 - Testing of electronic circuits, e.g. by signal tracer
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