The disclosed device for packet coalescing includes detecting a trigger condition for initiating packet coalescing of packet traffic and sending, to an endpoint device, a notification to start packet coalescing. The device can observe a status in response to starting the packet coalescing and report a performance of the packet coalescing. A system can include a controller that detects a trigger condition for packet coalescing and notifies an endpoint device via a notification register. The controller can read a status register to report, based on the read status, a packet coalescing performance. Various other methods, systems, and computer-readable media are also disclosed.
A method and system for distributing keys in a key distribution system includes receiving a connection for communication from a first component. A determination is made whether the first component requires a key be generated and distributed. Based upon a security mode for the communication, the key generated and distributed to the first component.
G06F 21/57 - Certifying or maintaining trusted computer platforms, e.g. secure boots or power-downs, version controls, system software checks, secure updates or assessing vulnerabilities
Systems, apparatuses, and methods for prefetching data by a display controller are proposed. From time to time, a performance-state change of a memory is performed. During such changes, a memory clock frequency is changed for a memory subsystem (220) storing frame buffer(s) (230) used to drive pixels to a display device (250). During the performance-state change, memory accesses may be temporarily blocked. To sustain a desired quality of service for the display, a display controller (150) is configured to prefetch data in advance of the performance-state change. In order to ensure the display controller has sufficient memory bandwidth to accomplish the prefetch, bandwidth reduction circuitry (112A, 112N) in clients (205) of the system are configured to temporarily reduce memory bandwidth of corresponding clients.
G09G 5/00 - Control arrangements or circuits for visual indicators common to cathode-ray tube indicators and other visual indicators
G06F 1/324 - Power saving characterised by the action undertaken by lowering clock frequency
G06F 1/3234 - Power saving characterised by the action undertaken
G06F 3/06 - Digital input from, or digital output to, record carriers
G06F 12/0862 - Addressing of a memory level in which the access to the desired data or data block requires associative addressing means, e.g. caches with prefetch
G09G 5/393 - Arrangements for updating the contents of the bit-mapped memory
G11C 7/22 - Read-write [R-W] timing or clocking circuits; Read-write [R-W] control signal generators or management
G09G 5/395 - Arrangements specially adapted for transferring the contents of the bit-mapped memory to the screen
4.
SYSTEMS AND METHODS FOR GENERATING REMEDY RECOMMENDATIONS FOR POWER AND PERFORMANCE ISSUES WITHIN SEMICONDUCTOR SOFTWARE AND HARDWARE
The disclosed computer-implemented method for generating remedy recommendations for power and performance issues within semiconductor software and hardware. For example, the disclosed systems and methods can apply a rule-based model to telemetry data to generate rule-based root-cause outputs as well as telemetry-based unknown outputs. The disclosed systems and methods can further apply a root-cause machine learning model to the telemetry-based unknown outputs to analyze deep and complex failure patterns with the telemetry-based unknown outputs to ultimately generate one or more root-cause remedy recommendations that are specific to the identified failure and the client computing device that is experiencing that failure.
A remote display synchronization technique preserves the presence of a local display device for a remotely-rendered video stream. A server and a client device cooperate to dynamically determine a target frame rate for a stream of rendered frames suitable for the current capacities of the server and the client device and networking conditions. The server generates from this target frame rate a synchronization signal that serves as timing control for the rendering process. The client device may provide feedback to instigate a change in the target frame rate, and thus a corresponding change in the synchronization signal. In this approach, the rendering frame rate and the encoding frequency may be "synchronized" in a manner consistent with the capacities of the server, the network, and the client device, resulting in generation, encoding, transmission, decoding, and presentation of a stream of frames that mitigates missed encoding of frames while providing acceptable latency.
H04N 21/242 - Synchronization processes, e.g. processing of PCR [Program Clock References]
H04N 21/2662 - Controlling the complexity of the video stream, e.g. by scaling the resolution or bitrate of the video stream based on the client capabilities
H04N 21/24 - Monitoring of processes or resources, e.g. monitoring of server load, available bandwidth or upstream requests
An apparatus and method for performing efficient video transmission. In various implementations, a computing system includes a transmitter sending a video stream to a receiver over a network. Before encoding a video frame, the transmitter identifies a first set of one or more macroblocks of the video frame that includes text. The transmitter replaces pixel color information with pixel distance information for the first set of one or more macroblocks. The transmitter inserts, in metadata information, indications that identify the first set of one or more macroblocks and specify the color values of pixels in the first set of one or more macroblocks. The transmitter encodes the video frame and sends it along with the metadata information to the receiver. The receiver uses the metadata information to reproduce the original pixel colors and maintain text clarity of an image to be depicted on a display device.
H04N 19/167 - Position within a video image, e.g. region of interest [ROI]
H04N 19/46 - Embedding additional information in the video signal during the compression process
H04N 19/117 - Filters, e.g. for pre-processing or post-processing
H04N 19/176 - Methods or arrangements for coding, decoding, compressing or decompressing digital video signals using adaptive coding characterised by the coding unit, i.e. the structural portion or semantic portion of the video signal being the object or the subject of the adaptive coding the unit being an image region, e.g. an object the region being a block, e.g. a macroblock
H04N 19/186 - Methods or arrangements for coding, decoding, compressing or decompressing digital video signals using adaptive coding characterised by the coding unit, i.e. the structural portion or semantic portion of the video signal being the object or the subject of the adaptive coding the unit being a colour or a chrominance component
7.
OFFSET DATA INTEGRITY CHECKS FOR LATENCY REDUCTION
Data integrity checks for reducing communication latency is described. A transmitting endpoint transmits data to a receiving endpoint by generating an integrity tag for a first subset of data blocks and a second integrity tag for a second subset of data blocks. In implementations, the first and second integrity tags overlap at least one data block and are offset based on computational complexities of generating the integrity tags. A receiving endpoint generates comparison tags for each of the integrity tags and uses the comparison tags to validate an authenticity of received data. In response to validating the first and second integrity tags, data blocks covered by both the first and second integrity tags are released for use. Additional integrity tags are generated and validated for subsequent subsets of data blocks during data communication, thus reducing latency by offsetting times at which comparison tags are generated and validated.
H04L 9/32 - Arrangements for secret or secure communications; Network security protocols including means for verifying the identity or authority of a user of the system
Systems, apparatuses, and methods for dynamically estimating power losses in a computing system. A system management circuit tracks a state of a computing system and dynamically estimates power losses in the computing system based in part on the state. Based on the estimated power losses, power consumption of the computing system is estimated. In response to detecting reduced power losses in at least a portion of the computing system, the system management circuit is configured to increase a power-performance state of one or more circuits of the computing system while remaining within a power allocation limit of the computing system.
Systems, apparatuses, and methods for managing power allocation in a computing system. A system management unit detects a condition indicating a change in power is indicated. Such a change may be detecting an indication that a power change is either required, possible, or requested. In response to detecting a reduction in power is indicated, the system management unit identifies currently executing tasks of the computing system and accesses sensitivity data to determine which of a number of computing units (or power domains) to select for power reduction. Based at least in part on the data, a unit is identified that is determined to have a relatively low sensitivity to power state changes under the current operating conditions. A relatively low sensitivity indicates that a change in power to the corresponding unit will not have as significant an impact on overall performance of the computing system than if another unit was selected. Power allocated for the selected unit is then decreased.
A processing system including a parallel processing unit selectively allocating pages of memory for interleaving across configurable subsets of channels based on a mode of allocation. In some embodiments, in a first mode, a page of memory is allocated to and interleaved across a plurality of channels, and in a second mode, a page of memory is allocated to and interleaved across a subset of the plurality of channels.
Methods and systems are disclosed for managing performance states of a data fabric of a system on chip (SoC). Techniques disclosed include determining a performance state of the data fabric based on data fabric bandwidth utilizations of respective components of the SoC. A metric, characteristic of a workload centric to cores of the SoC, is derived from hardware counters, and, based on the metric, it is determined whether to alter the performance state.
An apparatus and method for efficiently scheduling tasks in a dynamic manner to multiple cores that support a heterogeneous computing architecture. A computing system includes multiple cores with at least two cores being capable of executing instructions of a same instruction set architecture (ISA), and therefore, are architecturally compatible. In an implementation, each of the at least two cores is a general-purpose central processing unit (CPU) core capable of executing instructions of a same ISA. However, the throughput and the power consumption greatly differ between the at least two cores based on their hardware designs. An operating system scheduler assigns a thread to a first core, and the first core measures thread dynamic behavior of the thread over a time interval. Based on the thread dynamic behavior, the scheduler reassigns the thread to a second core different from the first core.
A data processor is for accessing a memory having a first pseudo channel and a second pseudo channel. The data processor includes at least one memory accessing agent, a memory controller, and a data fabric. The at least one memory accessing agent generates generating memory access requests including first memory access requests that access the memory. The memory controller provides memory commands to the memory in response to the first memory access requests. The data fabric routes the first memory access requests to a first downstream port in response to a corresponding first memory request accessing the first pseudo channel, and to a second downstream port in response to the corresponding first memory request accessing the second pseudo channel. The memory controller has first and second upstream ports coupled to the first and second downstream ports of the data fabric, respectively, and a downstream port coupled to the memory.
A technique for operating a cache is disclosed. The technique includes in response to a power down trigger that indicates that the cache effectiveness is considered to be low, powering down the cache.
A technique for performing ray tracing operations is provided, The technique includes, in response to detecting that a threshold number of traversal stage work-items of a wavefront have terminated, increasing intersection test parallelization for non-terminated work-items..
A first frame of a video stream is obtained. The first frame is defined by a plurality of pixels associated with a set of color data. A determination is made that a pixel of the plurality of pixels comprises high-frequency information. Responsive to the determination that the pixel comprises high-frequency information, a pixel lock is generated for the pixel such that color data associated with the pixel is maintained during a color accumulation process for at least one of the first frame or a second frame of the video stream that is subsequent to the first frame.
A first frame of a video stream rendered at a first resolution is obtained. A second frame of the video stream upscaled to a second higher resolution is also obtained. The first plurality of pixels is upscaled to the second resolution. The upsampling generates upsampled color data for the upsampled first plurality of pixels. The upsampled color data is accumulated with a second set of color data associated with a second plurality of pixels defining the second frame to generate final color data for the upsampled first plurality of pixels. Color data of the second set of color data associated with a pixel lock contributes more to the final color data than corresponding color data of the upsampled color data. The upsampled first plurality of pixels is stored with the final color data as an upscaled frame representing the first frame at the second resolution.
A memory package includes first, second, third, and fourth channels arranged consecutively in a clockwise direction on the memory package, each of the first, second, third, and fourth channels having access circuitry and memory arrays. In a first mode, the first channel controls access to the memory arrays in the second channel and the fourth channel controls access to the memory arrays in the third channel.
An apparatus includes a processor configured to determine a first distribution associated with an artificial agent based on behavior associated with the artificial agent and a second distribution based on behavior of a user. The processor is further configured to generate a human-likeness similarity measurement by comparing the first distribution to the second distribution and modify the behavior of the artificial agent in response to the similarity measurement failing to satisfy a similarity threshold.
Cascading execution of atomic operations, including: receiving a request for each thread of a plurality of threads to perform an atomic operation, wherein the plurality of threads comprises a plurality of thread subsets each corresponding to a local memory, wherein the local memory for a thread subset is accessible by the thread subset and inaccessible to a remainder of threads in the plurality of threads; generating a plurality of intermediate results by performing, by each thread subset, the atomic operation in the local memory corresponding to the thread subset; and generating a result for the request by aggregating the plurality of intermediate results in a shared memory accessible to all threads in the plurality of threads.
Restricting peripheral device protocols in confidential compute architectures, the method including: receiving a first address translation request from a peripheral device supporting a first protocol, wherein the first protocol supports cache coherency between the peripheral device and a processor cache; determining that a confidential compute architecture is enabled; and providing, in response to the first address translation request, a response including an indication to the peripheral device to not use the first protocol.
A processing system [100] divides successive dispatches [135] of work items into portions [145]. The successive dispatches are separated from each other by barriers [202], [204], each barrier indicating that the work items of the previous dispatch must complete execution before work items of a subsequent dispatch can begin execution. In some embodiments, the processing system interleaves execution of portions of a first dispatch with portions of subsequent dispatches that consume data produced by the first dispatch. The processing system thereby reduces the amount of data written to the local cache [120] by a producer dispatch while preserving data locality for a subsequent consumer (or consumer/producer) dispatch and facilitating processing efficiency.
A multi-die integrated circuit [102] uses an on-chip test distribution module to distribute test data [105] to different dies, such as processor chiplets 104, 106,108, 110]. The test distribution module receives test input data [220] from an external source [115] via one or more integrated circuit pins [112] and distributes the test input data to the different dies, such that the different dies are able to concurrently apply the test data to one or more circuits. Based on application of the test input data the different dies concurrently generate corresponding test results [325] that are used to identify and address design or operation errors at the dies.
Systems, apparatuses, and methods for implementing a discard engine in a graphics pipeline are disclosed. A system includes a graphics pipeline with a geometry engine launching shaders that generate attribute data for vertices of each primitive of a set of primitives. The attribute data is consumed by pixel shaders, with each pixel shader generating a deallocation message when the pixel shader no longer needs the attribute data. A discard engine gathers deallocations from multiple pixel shaders and determines when the attribute data is no longer needed. Once a block of attributes has been consumed by all potential pixel shader consumers, the discard engine deallocates the given block of attributes. The discard engine sends a discard command to the caches so that the attribute data can be invalidated and not written back to memory.
A virtual function (VF) [111] of a virtual machine [110] is enabled to directly reset a processing portion [106] of a processing unit [104]. The VF initiates the reset of the processing portion directly and a host driver [116] associated with the processing unit is bypassed during the reset process. By allowing for a direct reset of the processing portion, a processing system [100] reduces the overhead associated with the reset process, enhances system security, and improves overall VM and hardware isolation at the processing system.
Allocating peripheral component interface express (PCIe) streams in a configurable multiport PCIe controller, including: detecting, by a PCIe controller, a link by a first PCIe device; and allocating, for the link between the PCIe controller and the first PCIe device, a first one or more PCIe streams from a pool of PCIe streams.
An approach is provided for a gaming overlay application to provide automatic in-game subtitles and/or closed captions for video game applications. The overlay application accesses an audio stream and a video stream generated by an executing game application. The overlay application processes the audio stream through a text conversion engine to generate at least one subtitle. The overlay application determines a display position to associate with the at least one subtitle. The overlay application generates a subtitle overlay comprising the at least one subtitle located at the associated display position. The overlay application causes a portion of the video stream to be displayed with the subtitle overlay.
A apparatus includes a reference signal generator, a droop detection circuit, a digital frequency-locked loop (DFLL), and a DFLL control circuit. The reference signal generator that receives a digital value and produces a pulse-density modulated signal based on the digital value. The droop detection circuit converts the pulse-density modulated signal to an analog signal, compares the analog signal to a monitored supply voltage, and responsive to detecting a droop of the monitored supply voltage below a designated value relative to the analog signal, produces a droop detection signal. The DFLL provides a clock signal for synchronizing circuitry within a domain of the monitored supply voltage. The DFLL control circuit, responsive to receiving the droop detection signal, causes the DFLL to slow the clock signal.
H03L 7/081 - Automatic control of frequency or phase; Synchronisation using a reference signal applied to a frequency- or phase-locked loop - Details of the phase-locked loop provided with an additional controlled phase shifter
H03L 7/24 - Automatic control of frequency or phase; Synchronisation using a reference signal directly applied to the generator
G01R 19/25 - Arrangements for measuring currents or voltages or for indicating presence or sign thereof using digital measurement techniques
One or more components of a computing device are run by default in a boost mode state. The one or more components continue to run in the boost mode state until the boost mode state is no longer sustainable, e.g., due to power consumption of the one or more components or temperature of the one or more components. The one or more components are switched to a reduced power state (e.g., a non-boost mode state) in response to the boost mode state no longer being sustainable. When operating the one or more components in the boost mode state again becomes sustainable due to power consumption or temperature of the one or more components, the one or more components are returned to the default boost mode state.
A processing system [100] is configured to translate a first cache access pattern of a dispatch [135] of work items to a cache access pattern [145] that facilitates consumption of data stored at a cache [120] of a parallel processing unit [110] by a subsequent access before the data is evicted to a more remote level of a memory hierarchy. For consecutive cache accesses having read-after-read data locality, in some embodiments the processing system translates the first cache access pattern to a space-filling curve [506]. In some embodiments, for consecutive accesses having read-after-write data locality, the processing system translates a first typewriter cache access pattern that proceeds in ascending order for a first access [512] to a reverse typewriter cache access pattern that proceeds in descending order for a subsequent cache access [514]. By translating the cache access pattern based on data locality, the processing system increases the hit rate of the cache.
Techniques are described for adaptive device power management. The hardware computing unit detects a launch of an application by the operating system (OS) to be executed on the hardware computing unit. The hardware computing unit identifies the launched application and determines whether a hardware profile exists that is associated with the application. The hardware profile includes one or more hardware parameters that yield the optimal performance for power consumption by the hardware computing unit when executing the launched application. Based on determining that the hardware profile exists, the power policy of the OS is updated for the launched application and a driver updates the power state of the the hardware computing unit based on the new power policy.
A read clock circuit selectively provides a read clock signal from a memory to a memory controller over a memory bus. A pulse-amplitude modulation (PAM) driver including an input and an output capable of driving at least three levels indicating respective digital values. A digital control circuit is coupled to the PAM driver and operable to cause the PAM driver to provide a preamble signal before the read clock signal, the preamble signal including an initial toggling state in which the PAM driver toggles between two selected levels at a first rate, and a final toggling state in which the PAM driver toggles between two selected levels at a second rate higher than the first rate, with a length of the initial toggling state and a length of the final toggling state are based on values in a mode register.
A method for hardware management of DMA transfer commands includes accessing, by a first DMA engine [314], a DMA transfer command and determining a first portion of a data transfer requested by the DMA transfer command. Transfer of a first portion of the data transfer by the first DMA engine is initiated based at least in part on the DMA transfer command. Similarly, a second portion of the data transfer by a second DMA engine is initiated based at least in part on the DMA transfer command. After transferring the first portion and the second portion of the data transfer, an indication is generated that signals completion of the data transfer requested by the DMA transfer command.
G06F 13/28 - Handling requests for interconnection or transfer for access to input/output bus using burst mode transfer, e.g. direct memory access, cycle steal
Systems, apparatuses, and methods for implementing duplicated registers for access by initiators across multiple semiconductor dies are disclosed. A system includes multiple initiators on multiple semiconductor dies of a chiplet processor. One of the semiconductor dies is the master die, and this master die has copies of registers which can be accessed by the multiple initiators on the multiple semiconductor dies. When a given initiator on a given secondary die generates a register access, the register access is routed to the master die and a particular duplicate copy of the register maintained for the given secondary die. From the point of view of software, the multiple semiconductor dies appear as a single die, and the multiple initiators appear as a single initiator. Multiple types of registers can be maintained by the master die, with a flush register being one of the register types.
A system and method for efficiently capturing data by sequential circuits across multiple operating conditions are described. In various implementations, an integrated circuit includes multiple signal arrival adjusters both at its I/O boundaries and across its die. The signal arrival adjuster includes two internal timing paths, each with a respective latency. The signal arrival adjuster receives an input signal, and generates an output signal from the a selected one of the first timing path and the second timing path. The signal arrival adjuster sends the output signal to a sequential circuit. The sequential circuit uses the output signal as one of an input data signal and an input clock signal. The selection between the two timing paths within the signal arrival adjuster aids satisfying the setup and hold time requirements of the sequential circuit.
A dynamic allocator for providing platform resource candidates is disclosed. In an implementation, a platform resource allocator receives a request from a workload initiator such as, an application, for a platform resource recommendation. The platform resource allocator analyzes performance capabilities and utilization metrics of a plurality of platform resources for each of a plurality of resource. The plurality of platform resources includes one or more graphics processor units (GPUs) and one or more accelerated processing units (APUs). The platform resource allocator dynamically provides the platform resource recommendation to the workload initiator to select one or more of the plurality of platform resources to execute a workload based on the performance capabilities and utilization metrics.
An optimized service-based pipeline includes a resource manager that receives a request that includes a description of a workload from a workload initiator such as an application. The resource manager identifies runtime utilization metrics of a plurality of processing resources, where the plurality of processing resources includes at least a first graphics processing unit (GPU) and a second GPU. The resource manager determines, based on the utilization metrics and one or more policies, a workload allocation recommendation for the workload. Thus, the workload initiator can determine whether placing a workload on a particular processing resource is preferable based on runtime behavior of the system and policies established of the workload.
Systems and methods for dynamic repartitioning of physical memory address mapping involve relocating data stored at one or more physical memory locations of one or more memory devices to another memory device or mass storage device, repartitioning one or more corresponding physical memory maps to include new mappings between physical memory addresses and physical memory locations of the one or more memory devices, then loading the relocated data back onto the one or more memory devices at physical memory locations determined by the new physical address mapping. Such dynamic repartitioning of the physical memory address mapping does not require a processing system to be rebooted and has various applications in connection with interleaving reconfiguration and error correcting code (ECC) reconfiguration of the processing system.
A power supply circuit is provided for supplying power from multiple peripheral power supplies to a data processor. The power supply circuit includes a power bus, a plurality of load voltage converters each including an input coupled to the power bus and an output coupled to a respective one of multiple subsystems of the data processor, a plurality of input voltage converters each including an input for coupling to a respective one of multiple peripheral power supply voltages and an output coupled to the power bus, and a feedback control circuit having an input coupled to the power bus and a plurality of outputs coupled to respective ones of the input voltage converters for controlling a current draw of the respective input voltage converter.
H02J 1/12 - Parallel operation of dc generators with converters, e.g. with mercury-arc rectifier
H02M 1/00 - APPARATUS FOR CONVERSION BETWEEN AC AND AC, BETWEEN AC AND DC, OR BETWEEN DC AND DC, AND FOR USE WITH MAINS OR SIMILAR POWER SUPPLY SYSTEMS; CONVERSION OF DC OR AC INPUT POWER INTO SURGE OUTPUT POWER; CONTROL OR REGULATION THEREOF - Details of apparatus for conversion
40.
PLATFORM RESOURCE SELCTION FOR UPSCALER OPERATIONS
Compound processing of an upscaler operation using platform resources includes: identifying a plurality of platform resources available to perform an upscaling operation, wherein the plurality of platform resources includes one or more graphics processor units (GPUs) and one or more accelerated processing units (APUs); and dynamically assigning workloads of the upscaling operation to one or more of the platform resources based on a modality of the upscaling operation; and processing the workloads of the upscaling operation by the platform resources to which the workloads are assigned.
A processing system (100) adjusts a saturation component of a hue-saturation-value (HSV) color space pixel input (108) for an organic light emitting diode (OLED) display panel (122) as a function of the hue component. The processing system converts components of a pixel input from a non-HSV color space to HSV components of the pixel input in HSV color space and modifies the saturation component of the pixel input in HSV color space based on the hue component of the pixel input to generate modified HSV components of the pixel input. The processing system then converts the modified HSV components of the pixel input back into the original color space to produce modified components of the pixel input in the original color space and provides the modified components of the pixel input for receipt by the OLED display, allowing the pixel to be driven at a lower pixel value while maintaining perceptual quality.
G09G 3/3208 - Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED] organic, e.g. using organic light-emitting diodes [OLED]
G09G 5/02 - Control arrangements or circuits for visual indicators common to cathode-ray tube indicators and other visual indicators characterised by the way in which colour is displayed
A system and method for automatically generating placement of vias within redistribution layers of a semiconductor package are described. A user defines attributes to use for automatic via generation in redistribution layers of a semiconductor package (702). The circuitry of a processor of a computing device used by the user executes instructions of an automatic redistribution layer (RDL) via generator (704). The automatic via generator uses the attributes, data indicative of the RDL netlist of signal routes within the RDL, and RDL mask layout data representing the signal masks of the metal layers within the RDL. The processor generates placement of vias for in the RDL based on the attributes and an identification of overlapping regions between metal layers.
A system and method for automatically generating layout masks of power rails within redistribution layers of a semiconductor package are described (918). A user defines attributes to use for automatic power rail generation in the redistribution layers (904, 906, 908). The circuitry of a processor of a computing device used by the user executes instructions of a redistribution layer (RDL) automated power rail generator, which is referred to as the power rail generator (910). The power rail generator uses the attributes and a copy of the RDL netlist of the signal routes within the RDL to generate RDL mask layout data representing the signal routes of the power rails within the RDL. The processor generates the power rails for a significantly large number of signal routes in the RDL based on the received data such as the attributes that allow the user to customize the automatic generation.
A disclosed technique includes transmitting data in a first buffer associated with a first display pipe to a first display associated with the first display pipe; transmitting data in a second buffer associated with a second display pipe to the first display; requesting wake-up of a memory; and refilling one or both of the first buffer and the second buffer from the memory.
G09G 5/00 - Control arrangements or circuits for visual indicators common to cathode-ray tube indicators and other visual indicators
G09G 3/20 - Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix
G06F 3/06 - Digital input from, or digital output to, record carriers
45.
IN-BAND COMMUNICATION INTERFACE POWER MANAGEMENT FENCING
An apparatus and method for providing efficient power management for data transfer protocols between components. A source generates requests and a destination services the requests. The source and destination support a communication protocol that includes both a transfer channel and one or more transaction channels for each type of request. The source and destination rely on a valid signal and a ready signal of the transfer channels to autonomously manage power consumption. The source and destination remove any dependencies on an external power manager and make it unnecessary to add signal extensions to the communication protocol to support power management.
A translation lookaside buffer (TLB) [110] receives mapping invalidation requests [105, 106] from one or more sources, such as one or more processing units [102, 104] of a processing system. The TLB includes one or more invalidation processing pipelines [112], wherein each processing pipeline includes multiple processing states arranged in a pipeline, so that a given stage executes its processing operations concurrent with other stages of the pipeline executing their processing operations.
G06F 12/1027 - Address translation using associative or pseudo-associative address translation means, e.g. translation look-aside buffer [TLB]
G06F 12/0891 - Addressing of a memory level in which the access to the desired data or data block requires associative addressing means, e.g. caches using clearing, invalidating or resetting means
Apparatuses, systems and methods for routing requests and responses targeting a shared resource. A queue in a communication fabric is located in a path between the requesters and a shared resource. In some embodiments, the shared resource is a shared address translation cache stored in an endpoint. The physical channel between the queue and the shared resource supports multiple virtual channels. The queue assigns at least one entry to each virtual channel of a group of virtual channels where the group includes a virtual channel for each address translation request type from a single requester of the multiple requesters. When the at least one entry for a given requester is de-allocated, the queue allocates this entry only with requests from the assigned virtual channel even if the empty entry is the only available entry of the queue.
A trusted processor [120] saves and restores context [155] and data [160] stored at a frame buffer [115] of a GPU [110] concurrent with initialization of a CPU [105] of the processing system [100]. In response to detecting that the GPU is powering down, the trusted processor accesses the context of the GPU and data stored at a frame buffer of the GPU via a high-speed bus [125]. The trusted processor stores the context and data at a system memory [140], which maintains the context and data while the GPU is powered down. In response to detecting that the GPU is powering up again, the trusted processor restores the context and data to the GPU, which can be performed concurrently with initialization of the CPU.
A computing system may implement a method for creating a first subdomain by configuring one of a first plurality of slave nodes as a first subdomain master node and configuring one or more other slave nodes of the first plurality of slave nodes as first subdomain slave nodes to the first subdomain master node.
A method for reducing power variations resulting from changes in processor workload includes communicating a power dip condition to a workload scheduler of a processor device in response to identifying the power dip condition. One or more target power workloads are assigned for execution at the processor device based at least in part on the power dip condition. Further, each of the one or more target power workloads is associated with a known power load.
H02J 3/12 - Circuit arrangements for ac mains or ac distribution networks for adjusting voltage in ac networks by changing a characteristic of the network load
Power shifting based on bottleneck prediction, including: determining a first plurality of performance metrics for an accelerated processing unit (APU) and a second plurality of performance metrics for a graphics processing unit (GPU); providing the first plurality of performance metrics and the second plurality of performance metrics as an input to a model configured to identify one or more bottlenecks in the APU or the GPU; determining, based on an output of the model, a power distribution between the APU and the GPU; and applying the power distribution.
An apparatus (100) includes a processor (102), a sleep state duration prediction modulem (404), and a system management unit (316). The sleep state duration prediction module is configured to predict a sleep state duration (416) for a component of the apparatus. The system management unit is to transition the component into a sleep state selected from a plurality of sleep states based on a comparison of the predicted sleep state duration to at least one duration threshold. Each sleep state of the plurality of sleep states is a lower power state than a previous sleep state of the plurality of sleep states.
A method for removing reflections from images is disclosed. The method includes identifying one or more segments of an image, the one or more segments including a reflection; identifying one or more features of the one or more segments; removing the one or more features from the segments to generate one or more sanitized segments; and combining the one or more sanitized segments with the image to generate a sanitized image.
Methods and apparatus for providing page migration of pages among tiered memories identify frequently accessed memory pages in each memory tier and generate page hotness ranking information indicating how frequently memory pages are being accessed. Methods and apparatus provide the page hotness ranking information to an operating system or hypervisor depending on which is used in the system, the operating system or hypervisor issues a page move command to a hardware data mover, based on the page hotness ranking information and the hardware data mover moves a memory page to a different memory tier in response to the page move command from the operating system.
G06F 12/121 - Replacement control using replacement algorithms
G06F 13/28 - Handling requests for interconnection or transfer for access to input/output bus using burst mode transfer, e.g. direct memory access, cycle steal
55.
GRAPHICS PROCESSING UNIT (GPU) SELECTION BASED ON A UTILIZED POWER SOURCE
Graphics processing unit (GPU) selection based on a utilized power source, including: determining that an apparatus is using a direct current (DC) power source instead of an Alternating Current (AC) power source; and causing, in response to the apparatus using the DC power source, the apparatus to preferentially utilize an integrated graphics processing unit (iGPU) over a discrete graphics processing unit (dGPU) while using the DC power source.
An electronic device includes a memory, a processor that executes a software entity, a page migration engine (PME), and an input-output memory management unit (IOMMU). The software entity and the PME perform operations for preparing to migrate a page of memory accessible by at least one IO device in the memory, the software entity and the PME setting migration state information in a page table entry for the page of memory and information in reverse map table (RMT) entries involved with migrating the page of memory based on the operations being performed. The IOMMU controls usage of information from the page table entry and controls performance of memory accesses of the page of memory based on the migration state information in the page table entry and information in the RMT entries. The PME migrates the page of memory upon completing the operations for preparing to migrate the page of memory.
Methods, systems, and apparatuses provide support for multiple address spaces in order to facilitate data movement. One system includes a host processor; a memory; a data fabric coupled to the host processor and to the memory; a plurality of input/output memory manage units (IOMMUs), each of the plurality of IOMMUs coupled to the data fabric; a plurality of root ports, each of the root ports coupled to a corresponding IOMMU of the plurality of IOMMUs; and a plurality of peripheral component endpoints, each of the plurality of peripheral component endpoints coupled to a corresponding root port of the plurality of root ports, wherein each of the root ports comprises hardware control logic operative to: synchronize the plurality of root ports; receive, from the corresponding peripheral component endpoint, a direct memory access (DMA) request; and provide the DMA request to the corresponding IOMMU of the plurality of IOMMUs.
G06F 12/1009 - Address translation using page tables, e.g. page table structures
G06F 12/1027 - Address translation using associative or pseudo-associative address translation means, e.g. translation look-aside buffer [TLB]
G06F 12/1081 - Address translation for peripheral access to main memory, e.g. direct memory access [DMA]
G06F 12/109 - Address translation for multiple virtual address spaces, e.g. segmentation
G06F 12/14 - Protection against unauthorised use of memory
G06F 13/12 - Program control for peripheral devices using hardware independent of the central processor, e.g. channel or peripheral processor
G06F 13/16 - Handling requests for interconnection or transfer for access to memory bus
G06F 13/28 - Handling requests for interconnection or transfer for access to input/output bus using burst mode transfer, e.g. direct memory access, cycle steal
Still frame detection for single pass video data, including: determining that an average quantization parameter of a frame of video data falls below a quantization parameter threshold; determining whether an amount of skipped macroblocks in the frame meets a skipped macroblock threshold; and responsive to the amount of skipped macroblocks exceeding the skipped macroblock threshold, identifying the frame as a still frame.
H04N 19/132 - Sampling, masking or truncation of coding units, e.g. adaptive resampling, frame skipping, frame interpolation or high-frequency transform coefficient masking
H04N 19/172 - Methods or arrangements for coding, decoding, compressing or decompressing digital video signals using adaptive coding characterised by the coding unit, i.e. the structural portion or semantic portion of the video signal being the object or the subject of the adaptive coding the unit being an image region, e.g. an object the region being a picture, frame or field
H04N 19/176 - Methods or arrangements for coding, decoding, compressing or decompressing digital video signals using adaptive coding characterised by the coding unit, i.e. the structural portion or semantic portion of the video signal being the object or the subject of the adaptive coding the unit being an image region, e.g. an object the region being a block, e.g. a macroblock
H04N 19/159 - Prediction type, e.g. intra-frame, inter-frame or bidirectional frame prediction
H04N 19/147 - Data rate or code amount at the encoder output according to rate distortion criteria
An address translation buffer or ATB is provided for emulating or implementing the PCIe (Peripheral Component Interface Express) ATS (Address Translation Services) protocol within a PCIe-compliant device. The ATB operates in place of (or in addition to) an address translation cache (ATC), but is implemented in firmware or hardware without requiring the robust set of resources associated with a permanent hardware cache (e.g., circuitry for cache control and lookup). A component of the device (e.g., a DMA engine) requests translation of an untranslated address, via a host input/output memory management unit for example, and the response (including a translated address) is stored in the ATB for use for a single DMA operation (which may involve multiple transactions across the PCIe bus).
G06F 12/1081 - Address translation for peripheral access to main memory, e.g. direct memory access [DMA]
G06F 13/28 - Handling requests for interconnection or transfer for access to input/output bus using burst mode transfer, e.g. direct memory access, cycle steal
G06F 13/42 - Bus transfer protocol, e.g. handshake; Synchronisation
60.
METHOD AND APPARATUS FOR PROVIDING NON-COMPUTE UNIT POWER CONTROL IN INTEGRATED CIRCUITS
Methods and apparatus employ a plurality of heterogeneous compute units and a plurality of non-compute units operatively coupled to the plurality of compute units. Power management logic (PML) determines a memory bandwidth level associated with a respective workload running on each of a plurality of heterogeneous compute units on the IC, and adjusts a power level of at least one non-compute unit of a memory system on the IC from a first power level to a second power level, based on the determined memory bandwidth levels. Memory access latency is also taken into account in some examples to adjust a power level of non-compute units.
A processing system (100) synchronizes the display of a frame of video at an array of variable refresh rate (VRR) display modules (141) of a display wall (140) by dynamically adjusting a frequency and phase of the refresh rates of the VRR display modules via network protocols based on a selected master timing signal. The processing system selects a master timing signal and transmits the master timing signal to video processing units (VPUs) (105) that render portions of the frame for display at the VRR display modules. Each VPU adjusts the frequency and phase of the VRR display modules for which it renders portions of the frame based on the master timing signal.
An electronic device includes a memory, an input-output memory management unit (IOMMU), a processor that executes a software entity, and a page migration engine. The software entity and the page migration engine perform operations for preparing to migrate a page of memory that is accessible by the at least one IO device in the memory, the software entity and the page migration engine set migration state information in a page table entry for the page of memory based on the operations being performed. When the operations for preparing to migrate the page of memory are completed, the page migration engine migrates the page of memory in the memory. The IOMMU uses the migration state information in the page table entry to control one or more operations of the IOMMU.
A processing system (100) synchronizes the frequencies and phases of the display outputs (130) of multiple video processing units (VPUs) (105) by adjusting a local time base (230) generated at each VPU to match a virtual global time base (235) generated based on a network protocol and to synchronize video timing for the display outputs based on the virtual global time base.
Systems, apparatuses, and methods for performing adaptive audio mixing are disclosed. A trained neural network dynamically selects and mixes pre-recorded, human-composed music stems that are composed as mutually compatible sets. Stem and track selection, volume mixing, filtering, dynamic compression, acoustical/reverberant characteristics, segues, tempo, beat-matching and crossfading parameters generated by the neural network are inferred from the game scene characteristics and other dynamically changing factors. The trained neural network selects an artist's pre-recorded stems and mixes the stems in real-time in unique ways to dynamically adjust and modify background music based on factors such as game scenario, the unique storyline of the player, scene elements, the player's profile, interest, and performance, adjustments made to game controls (e.g., music volume), number of viewers, received comments, player's popularity, player's native language, player's presence, and/or other factors. The trained neural network creates unique music that dynamically varies according to real-time circumstances.
A63F 13/54 - Controlling the output signals based on the game progress involving acoustic signals, e.g. for simulating revolutions per minute [RPM] dependent engine sounds in a driving game or reverberation against a virtual wall
A63F 13/67 - Generating or modifying game content before or while executing the game program, e.g. authoring tools specially adapted for game development or game-integrated level editor adaptively or by learning from player actions, e.g. skill level adjustment or by storing successful combat sequences for re-use
A63F 13/79 - Game security or game management aspects involving player-related data, e.g. identities, accounts, preferences or play histories
Systems, apparatuses, and methods for performing asynchronous memory clock changes on multiple displays are disclosed. From time to time, a memory clock frequency change is desired for a memory subsystem storing frame buffer(s) used to drive pixels to multiple displays. For example, when the real-time memory bandwidth demand differs from the memory bandwidth available with the existing memory clock frequency, a control unit tracks the vertical blanking interval (VBI) timing of a first display. Also, the control unit causes a second display to enter into panel self-refresh (PSR) mode. Once the PSR mode of the second display overlaps with a VBI of the first display, a memory clock frequency change, including memory training, is initiated. After the memory clock frequency change, the displays are driven by the frame buffer(s) in the memory subsystem at an updated frequency.
Virtual functions are implemented using a plurality of resources [220] and physical function circuitry [210] that executes a virtual function [215] using information stored in the plurality of resources. A processing unit [105] executes a host driver [205] that selectively enables access to the plurality of resources by the virtual function based on an operational state of the processing unit. In some cases, a state machine [300] that determines a state of the virtual function and the host driver that enables access to the plurality of resources by the virtual function based on the state of the virtual function executing on the processing unit. The subsets of the plurality of resources are used to implement a frame buffer [222], one or more context registers [225, 226], a doorbell [231], and one or more mailbox registers [235, 236].
Systems, apparatuses, and methods for performing a software override of a power estimation mechanism are disclosed. A computing system includes a plurality of tuned parameters for generating an estimate of power consumption. The tuned parameters are generated based on post-silicon characterization of the system. After deployment, the system executes a plurality of different applications. When launching a particular application, the system loads a corresponding set of override parameters which are used to replace the plurality of tuned parameters. The system generates an estimate of power consumption using the set of override parameters rather than the previously determined tuned parameters. Then while executing the particular application, the system makes adjustments to power and frequency values for the various system components based on the estimate of power consumption.
Refreshing displays using on-die cache, including: determining that a static display condition has been met; storing, in cache memory of a processor, first display data; and displaying the first display data from the cache memory.
G09G 5/36 - Control arrangements or circuits for visual indicators common to cathode-ray tube indicators and other visual indicators characterised by the display of individual graphic patterns using a bit-mapped memory
A processing system that includes a shared data fabric resets a first client processor while operating a second client processor. The first client processor is instructed to stop making requests to one or more devices of the shared data fabric. Status communications are blocked between the first client processor and a memory controller, the second client processor, or both, such that the first client processor enters a temporary offline state. The first client processor is indicated as being non-coherent. Accordingly, when the processor is reset some errors and efficiency losses due messages sent during or prior to the reset are prevented.
A rendering device [105] signals a display device [170] to capture and replay a current frame to maintain a static image while switching between multiple graphics processing units (GPUs) [130, 135]at a multiplexer (MUX). Replaying the current frame while the MUX switch is in progress smooths the user experience such that no screen blanking or artifacts are observable.
G09G 5/399 - Control of the bit-mapped memory using two or more bit-mapped memories, the operations of which are switched in time, e.g. ping-pong buffers
71.
VIDEO TIMING FOR DISPLAY SYSTEMS WITH VARIABLE REFRESH RATES
A display system (100) supports variable refresh rates that include a plurality of refresh rates. A source such as a GPU (140) provides frames to the display system at a selected one of the refresh rates. The refresh rates are factored into a corresponding plurality of prime factors. A plurality of numbers of lines per frame in frames provided at the plurality of refresh rates is determined based on one or more ratios of the plurality of refresh rates, the plurality of prime factors, and a line rate for providing frames to the display system at the plurality of refresh rates. The source then selectively provides frames to the display system at one refresh rate of the plurality of refresh rates using the same line rate regardless of which refresh rate is chosen. Furthermore, the number of lines per frame can be an integer for frames provided at the refresh rates.
A system includes a timing reference and one or more processors configured to generate and provide, based on the timing reference, frames to a display system that supports variable refresh rates. The frames include a vertical blanking region having a first duration. The display system transmits information indicating an operation to be performed by the display system during the vertical blanking region of one or more subsequent frames. The one or more processors are configured to increase the first duration to a second duration in response to receiving the information indicating an operation to be performed by the display system during the vertical blanking region of at least one subsequent frame. In some cases, the first duration of the vertical blanking region is a minimum duration that corresponds to a maximum refresh rate supported by the display system.
G09G 5/18 - Timing circuits for raster scan displays
H04N 7/088 - Systems for the simultaneous or sequential transmission of more than one television signal, e.g. additional information signals, the signals occupying wholly or partially the same frequency band with signal insertion during the vertical blanking interval the inserted signal being digital
Sampling circuitry independently accesses channels of texture data that represent a set of pixels. One or more processing units separately compress the channels of the texture data and store compressed data representative of the channels of the texture data for the set of pixels. The channels can include a red channel, a blue channel, and a green channel that represent color values of the set of pixels and an alpha channel that represents degrees of transparency of the set of pixels. Storing the compressed data can include writing the compress data to portions of a cache. The processing units can identify a subset of the set of pixels that share a value of a first channel of the plurality of channels and represent the value of the first channel over the subset of the set of pixels using information representing the value, the first channel, and boundaries of the subset.
Systems, apparatuses, and methods for implementing a depth buffer pre-pass are disclosed. A rendering application uses a binning approach to render primitives of a virtual scene on a tile-by-tile basis, with each tile corresponding to a portion of the screen. The application causes a depth buffer pre-pass to be performed for the primitives of the tile before a pixel shader is invoked. During the depth buffer pre-pass, only the depth part of the virtual scene is rendered to determine which pixel samples are visible and which pixel samples are hidden. Then, the scene is redrawn, but the pixel samples that are hidden are not sent to the pixel shader. In cases where a relatively large percentage of primitives overlap, this technique increases the efficiency of the rendering application since pixel shading can be avoided for the pixel samples that are hidden.
An encoder [102] encodes an image portion [122] by recursively partitioning the portion into a partitioning hierarchy of levels. The top level has a single block representing the entire portion and each lower level has four smaller blocks representing a corresponding larger block at a higher level. A palette table [124] is generated for each bottom-level block based on the pixels of the associated block. For each successively higher level, the encoder generates a palette table for each current-level block by selecting palette colors based on the palette colors from the four palette tables for the associated four blocks at the next-lowest level. A color index map [126] is then generated based on a final palette table selected from the palette tables generated for the partitioning hierarchy. A representation of the portion is then encoded using the final palette table and the color index map to generate a corresponding segment of an encoded bitstream [108].
H04N 19/186 - Methods or arrangements for coding, decoding, compressing or decompressing digital video signals using adaptive coding characterised by the coding unit, i.e. the structural portion or semantic portion of the video signal being the object or the subject of the adaptive coding the unit being a colour or a chrominance component
H04N 19/154 - Measured or subjectively estimated visual quality after decoding, e.g. measurement of distortion
H04N 19/176 - Methods or arrangements for coding, decoding, compressing or decompressing digital video signals using adaptive coding characterised by the coding unit, i.e. the structural portion or semantic portion of the video signal being the object or the subject of the adaptive coding the unit being an image region, e.g. an object the region being a block, e.g. a macroblock
76.
SECURE COLLECTION AND COMMUNICATION OF COMPUTING DEVICE WORKING DATA
Techniques described herein provide a secure data recorder, which allows targeted collection and storage of both high- and low-level working data from any subsystem of a computing device. The data recorder gathers and stores device working data based on stored configuration data. The configuration data indicates one or more memory and/or storage locations on the device from which to gather working data, and one or more storage locations at which the data recorder stores the gathered working data. The data recorder is implemented in a secure execution environment, and is functional during all of the pre-boot stage of the device. The data recorder further allows a user to update the BIOS of the computing device based on a firmware image, e.g., provided via the network. The data recorder also facilitates gathering of working data, over time, that sheds light on the functioning of particular hardware configurations and/or particular software configurations.
A semiconductor package includes a first die, a second die, and an interconnect die coupled to a first plurality of through-die vias in the first die and a second plurality of through-die vias in the second die. The interconnect die provides communications pathways the first die and the second die.
H01L 25/065 - Assemblies consisting of a plurality of individual semiconductor or other solid state devices all the devices being of a type provided for in the same subgroup of groups , or in a single subclass of , , e.g. assemblies of rectifier diodes the devices not having separate containers the devices being of a type provided for in group
H01L 25/18 - Assemblies consisting of a plurality of individual semiconductor or other solid state devices the devices being of types provided for in two or more different subgroups of the same main group of groups , or in a single subclass of ,
H01L 25/16 - Assemblies consisting of a plurality of individual semiconductor or other solid state devices the devices being of types provided for in two or more different main groups of groups , or in a single subclass of , , e.g. forming hybrid circuits
H01L 25/00 - Assemblies consisting of a plurality of individual semiconductor or other solid state devices
H01L 23/00 - SEMICONDUCTOR DEVICES NOT COVERED BY CLASS - Details of semiconductor or other solid state devices
78.
SELECTIVELY WRITING BACK DIRTY CACHE LINES CONCURRENTLY WITH PROCESSING
A graphics pipeline (200) includes a cache (207, 305) having cache lines (310-313) that are configured to store data used to process frames in the graphics pipeline. The graphics pipeline is implemented using a processor (115) that processes frames for the graphics pipeline using data stored in the cache. The processor processes a first frame and writes back a dirty cache line from the cache to a memory (105) concurrently with processing of the first frame. The dirty cache line is retained in the cache and marked as clean subsequent to being written back to the memory. In some cases, the processor generates a hint that indicates a priority for writing back the dirty cache line based on a read command occupancy at a system memory controller (335).
G06F 12/0897 - Caches characterised by their organisation or structure with two or more cache hierarchy levels
G06F 12/0811 - Multiuser, multiprocessor or multiprocessing cache systems with multilevel cache hierarchies
G06F 12/0855 - Overlapped cache accessing, e.g. pipeline
G06F 12/0888 - Addressing of a memory level in which the access to the desired data or data block requires associative addressing means, e.g. caches using selective caching, e.g. bypass
A technique for detecting a glitch in an image is provided. The technique includes providing an image to a plurality of individual classifiers to generate a plurality of individual classifier outputs and providing the plurality of individual classifier outputs to an ensemble classifier to generate a glitch classification.
A technique for generating a trained discriminator is provided, The technique includes applying one or more of a glitched image or an unglitched image to a discriminator; receiving classification output from the discriminator; adjusting weights of the discriminator to improve classification accuracy of the discriminator; applying noise to a generator; receiving an output image from the generator; applying the output image to the discriminator to obtain a classification; and adjusting weights of one of the discriminator or the generator to improve ability of the generator to reduce classification accuracy of the discriminator, based on the classification.
A display system [100] modifies display cycles of one or more displays [100] to perform a system operation [304] while avoiding visual perturbations at the one or more displays. The display system modifies, synchronizes, or both, blanking periods [204, 206] of the one or more displays such that the blanking periods equal or exceed a blackout duration [620] and overlap for at least the blackout duration. Then the system performs the system operation during an overlapping portion of the one or more blanking periods, where the system operation reduces availability of display data at the one or more displays.
Techniques for generating a task graph for workload scheduling based on a task graph specification program are provided. The techniques include executing control flow instructions of the task graph specification program to traverse the task graph specification program; generating pass nodes of the task graph based on pass instructions of the task graph specification program; generating resource nodes and directed edges based on resource declarations of the task graph specification program; and outputting the task graph specification program to a command scheduler for scheduling.
Techniques for scheduling operations for a task graph on a processing device are provided. The techniques include receiving a task graph that specifies one or more passes, one or more resources, and one or more directed edges between passes and resources; identifying independent passes and dependent passes of the task graph; based on performance criteria of the processing device, scheduling commands to execute the passes; and transmitting scheduled commands to the processing device for execution as scheduled.
A processing device for executing a machine learning neural network operation includes memory and a processor. The processor is configured to receive input data at a layer of the machine learning neural network operation, receive a plurality of sorted filters to be applied to the input data, apply the plurality of sorted filters to the input data to produce a plurality of different feature maps, compress the plurality of different feature maps according to a sparsity of the feature maps and store the plurality of different feature maps in the memory.
A processing device for executing a machine learning neural network operation includes memory and a processor. The processor is configured to receive input data at a layer of the machine learning neural network operation, receive a plurality of sorted filters to be applied to the input data, apply the plurality of sorted filters to the input data to produce a plurality of different feature maps, compress the plurality of different feature maps according to a similarity of the feature maps relative to each other and store the plurality of different feature maps in the memory.
Systems, apparatuses, and methods for hiding latency for wireless virtual reality (VR) and augmented reality (AR) applications are disclosed. A wireless VR or AR system includes a transmitter rendering, encoding, and sending video frames to a receiver coupled to a head-mounted display (HMD). In one scenario, the receiver measures a total latency required for the system to render a frame and prepare the frame for display. The receiver predicts a future head pose of a user based on the total latency. Next, a rendering unit at the transmitter renders, based on the predicted future head pose, a new frame with a rendered field of view (FOV) larger than a FOV of the headset. The receiver rotates the new frame by an amount determined by the difference between the actual head pose and the predicted future head pose to generate a rotated version of the new frame for display.
G09G 5/38 - Control arrangements or circuits for visual indicators common to cathode-ray tube indicators and other visual indicators characterised by the display of individual graphic patterns using a bit-mapped memory with means for controlling the display position
Automatic voltage reconfiguration in a computer processor including one or more cores includes executing one or more user-specified workloads; determining, based on the user-specified workloads, a respective minimum safe voltage for each core of one or more cores; and modifying a respective voltage configuration for each core of the one or more cores based on the respective minimum safe voltage.
A processing unit [110] manages temperature by correlating readings from a plurality of external temperature sensors [106, 107] to a skin temperature of the processing unit, wherein the correlation is based on characteristics of a computer chassis [223] that is to include the processing unit. The processing unit is mounted on a printed circuit board (PCB) [102] or other substrate that is to be placed in a computer chassis. Each of a plurality of temperature sensors is placed at a different location of the PCB to provide temperature readings from a variety of locations of the PCB. A temperature controller [115] of the processing unit receives temperature readings from the plurality of sensors and correlates the temperature readings with a skin temperature of the processing unit based on a plurality of correlation values [118].
Systems, apparatuses, and methods for reducing latency for wireless virtual and augmented reality applications are disclosed. A virtual reality (VR) or augmented reality (AR) system includes a transmitter rendering, encoding, and sending video frames to a receiver coupled to a head-mounted display (HMD). In one scenario, rather than waiting until the entire frame is encoded before sending the frame to the receiver, the transmitter sends an encoded left-eye portion to the receiver while the right-eye portion is being encoded. In another scenario, the frame is partitioned into a plurality of slices, and each slice is encoded and then sent to the receiver while the next slice is being encoded. In a further scenario, each slice is being encoded while the next slice is being rendered. In a still further scenario, each slice is prepared for presentation by the receiver while the next slice is being decoded by the receiver.
H04N 19/44 - Decoders specially adapted therefor, e.g. video decoders which are asymmetric with respect to the encoder
H04N 19/174 - Methods or arrangements for coding, decoding, compressing or decompressing digital video signals using adaptive coding characterised by the coding unit, i.e. the structural portion or semantic portion of the video signal being the object or the subject of the adaptive coding the unit being an image region, e.g. an object the region being a slice, e.g. a line of blocks or a group of blocks
H04N 19/70 - Methods or arrangements for coding, decoding, compressing or decompressing digital video signals characterised by syntax aspects related to video coding, e.g. related to compression standards
90.
METHOD AND APPARATUS FOR MANAGING PROCESSOR FUNCTIONALITY
A method and apparatus for managing processor functionality includes receiving, by the processor, data relating to one or more environmental conditions. The processor compares the data to pre-existing parameters to determine whether or not the environmental conditions are within the pre-existing parameters for normal operation. If the data are within the pre-existing parameters for normal operation, the processor is operated in a normal operation mode. If the data are outside the pre-existing parameters for normal operation, the processor operates in a second operation mode which is dynamically determined and calibrated during power-on, boot and operation.
An integrated coprocessor such as an accelerated processing unit (APU) generates commands for execution on a discrete coprocessor such as a discrete graphics processing unit (dGPU). Power distribution circuitry selectively provides power to the APU and the dGPU based on characteristics of workloads executing on the APU and the dGPU and based on a platform power limit that is shared by the APU and the dGPU. In some cases, the power distribution circuitry determines a first power provided to the APU and a second power provided to the dGPU. The power distribution circuitry increases the second power provided to the dGPU in response to a sum of the first and second powers being less than the platform power limit. In some cases, the power distribution circuitry modifies the power provided to the APU, the dGPU, or both in response to changes in temperatures measured by a set of sensors.
Systems, apparatuses, and methods for bit budgeting in video encode pre-analysis based on context and features are disclosed. A pre-encoder receives a video frame and evaluates each block of the frame for the presence of several contextual indicators. The contextual indicators can include memory colors, text, depth of field, and other specific objects. For each contextual indicator detected, a coefficient is generated and added with other coefficients to generate a final importance value for the block. The coefficients can be adjusted so that only a defined fraction of the picture is deemed important. The final importance value of the block is used to determine the bit budget for the block. The block bit budgets are provided to the encoder and used to influence the quantization parameters used for encoding the blocks.
H04N 19/115 - Selection of the code volume for a coding unit prior to coding
H04N 19/176 - Methods or arrangements for coding, decoding, compressing or decompressing digital video signals using adaptive coding characterised by the coding unit, i.e. the structural portion or semantic portion of the video signal being the object or the subject of the adaptive coding the unit being an image region, e.g. an object the region being a block, e.g. a macroblock
H04N 19/23 - Methods or arrangements for coding, decoding, compressing or decompressing digital video signals using video object coding with coding of regions that are present throughout a whole video segment, e.g. sprites, background or mosaic
93.
WORKLOAD-BASED CLOCK ADJUSTMENT AT A PROCESSING UNIT
A graphics processing unit (GPU) [102] adjusts a frequency of clock based on identifying a program thread [104, 106] executing at the processing unit, wherein the program thread is detected based on a workload [116, 117] to be executed. By adjusting the clock frequency based on the identified program thread, the processing unit adapts to different processing demands of different program threads. Further, by identifying the program thread based on workload, the processing unit adapts the clock frequency based on processing demands, thereby conserving processing resources.
Systems, apparatuses, and methods for implementing light volume rendering techniques are disclosed. A processor is coupled to a memory. A processor renders the geometry of a scene into a geometry buffer. For a given light source in the scene, the processor initiates two shader pipeline passes to determine which pixels in the geometry buffer to light. On the first pass, the processor renders a front-side of a light volume corresponding to the light source. Any pixels of the geometry buffer which are in front of the front-side of the light volume are marked as pixels to be discarded. Then, during the second pass, only those pixels which were not marked to be discarded are sent to the pixel shader. This approach helps to reduce the overhead involved in applying a lighting effect to the scene by reducing the amount of work performed by the pixel shader.
A floating point unit includes a non-pickable scheduler queue (NSQ) that offers a load operation concurrently with a load store unit retrieving load data for an operand that is to be loaded by the load operation. The floating point unit also includes a renamer that renames architectural registers used by the load operation and allocates physical register numbers to the load operation in response to receiving the load operation from the NSQ. The floating point unit further includes a set of pickable scheduler queues that receive the load operation from the renamer and store the load operation prior to execution. A physical register file is implemented in the floating point unit and a free list is used to store physical register numbers of entries in the physical register file that are available for allocation.
G06F 5/01 - Methods or arrangements for data conversion without changing the order or content of the data handled for shifting, e.g. justifying, scaling, normalising
G06F 9/38 - Concurrent instruction execution, e.g. pipeline, look ahead
Systems, apparatuses, and methods for performing parallel histogram calculation with application to palette table derivation are disclosed. An encoder calculates a first histogram for a first portion of pixel component value bits of a block of pixels. Then, the encoder selects a first number of the highest pixel count bins from the first histogram. Also, the encoder calculates a second histogram for a second portion of pixel component value bits of the block. The encoder selects a second number of the highest pixel count bins from the second histogram. A third histogram is calculated from the concatenation of bits assigned to the first and second number of bins, and the highest pixel count bins are selected from the third histogram. A palette table is derived based on these highest pixel count bins selected from the third histogram, and the block of pixels is encoded using the palette table.
H04N 19/176 - Methods or arrangements for coding, decoding, compressing or decompressing digital video signals using adaptive coding characterised by the coding unit, i.e. the structural portion or semantic portion of the video signal being the object or the subject of the adaptive coding the unit being an image region, e.g. an object the region being a block, e.g. a macroblock
H04N 19/182 - Methods or arrangements for coding, decoding, compressing or decompressing digital video signals using adaptive coding characterised by the coding unit, i.e. the structural portion or semantic portion of the video signal being the object or the subject of the adaptive coding the unit being a pixel
H04N 19/186 - Methods or arrangements for coding, decoding, compressing or decompressing digital video signals using adaptive coding characterised by the coding unit, i.e. the structural portion or semantic portion of the video signal being the object or the subject of the adaptive coding the unit being a colour or a chrominance component
H04N 19/593 - Methods or arrangements for coding, decoding, compressing or decompressing digital video signals using predictive coding involving spatial prediction techniques
97.
HIERARCHICAL HISTOGRAM CALCULATION WITH APPLICATION TO PALETTE TABLE DERIVATION
Systems, apparatuses, and methods for calculating multi-pass histograms for palette table derivation are disclosed. An encoder calculates a first histogram for a first portion of most significant bits (MSBs) of pixel component values of a block of an image or video frame. Then, the encoder selects a given number of the highest pixel count bins from the first histogram. The encoder then increases the granularity of these selected highest pixel count bins by evaluating one or more additional bits from the pixel component values. A second histogram is calculated for the concatenation of the original first portion MSBs from the highest pixel count bins and the one or more additional bits, and the highest pixel count bins are selected from the second histogram. A palette table is derived based on these highest pixel count bins selected from the second histogram, and the block is encoded using the palette table.
H04N 19/176 - Methods or arrangements for coding, decoding, compressing or decompressing digital video signals using adaptive coding characterised by the coding unit, i.e. the structural portion or semantic portion of the video signal being the object or the subject of the adaptive coding the unit being an image region, e.g. an object the region being a block, e.g. a macroblock
H04N 19/182 - Methods or arrangements for coding, decoding, compressing or decompressing digital video signals using adaptive coding characterised by the coding unit, i.e. the structural portion or semantic portion of the video signal being the object or the subject of the adaptive coding the unit being a pixel
H04N 19/186 - Methods or arrangements for coding, decoding, compressing or decompressing digital video signals using adaptive coding characterised by the coding unit, i.e. the structural portion or semantic portion of the video signal being the object or the subject of the adaptive coding the unit being a colour or a chrominance component
H04N 19/593 - Methods or arrangements for coding, decoding, compressing or decompressing digital video signals using predictive coding involving spatial prediction techniques
A processing system isolates at a physically or logically separate memory region of a processing unit boot code that is received from an external boot source for programming a boot memory of the processing unit until after the boot code is validated to protect against buffer overruns that could compromise the processing system. The processing unit includes a secure buffer region of memory that is physically or logically isolated from the remainder of the processing unit for receiving boot code from an external boot source such as a personal computer (PC) such that any buffer overruns at the secure buffer simply overwrite data stored at the secure buffer, and do not affect data or instructions that are executing at the processing unit.
G06F 21/57 - Certifying or maintaining trusted computer platforms, e.g. secure boots or power-downs, version controls, system software checks, secure updates or assessing vulnerabilities
G06F 21/53 - Monitoring users, programs or devices to maintain the integrity of platforms, e.g. of processors, firmware or operating systems during program execution, e.g. stack integrity, buffer overflow or preventing unwanted data erasure by executing in a restricted environment, e.g. sandbox or secure virtual machine
G06F 21/64 - Protecting data integrity, e.g. using checksums, certificates or signatures
Systems, apparatuses, and methods for using a multi-stream foveal display transport layer are disclosed. A virtual reality (VR) system includes a transmitter sending a plurality of streams over a display transport layer to a receiver coupled to a display. Each stream corresponds to a different image to be blended together by the receiver. The images include at least a foveal region image corresponding to a gaze direction of the eye and a background image which is a lower-resolution image with a wider field of view than the foveal region image. The phase timing of the foveal region stream being sent over the transport layer is adjusted with respect to the background stream to correspond to the location of the foveal region within the overall image. This helps to reduce the amount of buffering needed at the receiver for blending the images together to create a final image to be driven to the display.
H04N 19/33 - Methods or arrangements for coding, decoding, compressing or decompressing digital video signals using hierarchical techniques, e.g. scalability in the spatial domain
H04N 19/90 - Methods or arrangements for coding, decoding, compressing or decompressing digital video signals using coding techniques not provided for in groups , e.g. fractals
A processor includes a plurality of execution pipes and a distributed scheduler coupled to the plurality of execution pipes. The distributed scheduler includes a first queue to buffer instruction operations from a front end of an instruction pipeline of the processor and a plurality of second queues, wherein each second queue is to buffer instruction operations allocated from the first queue for a corresponding separate subset of execution pipes of the plurality of execution pipes. The distributed scheduler further includes a queue controller to select an allocation mode from a plurality of allocation modes based on whether at least one indicator of an imbalance at the distributed scheduler is detected, and further to control the distributed scheduler to allocate instruction operations from the first queue among the plurality of second queues in accordance with the selected allocation mode.
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