Yangtze Memory Technologies Co., Ltd.

China

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H01L 27/11582 - Electrically programmable read-only memories; Multistep manufacturing processes therefor with charge-trapping gate insulators, e.g. MNOS or NROM characterised by three-dimensional arrangements, e.g. with cells on different height levels with source and drain on different levels, e.g. with sloping channels the channels comprising vertical portions, e.g. U-shaped channels 576
H01L 27/1157 - Electrically programmable read-only memories; Multistep manufacturing processes therefor with charge-trapping gate insulators, e.g. MNOS or NROM characterised by the memory core region with cell select transistors, e.g. NAND 417
H01L 27/11556 - Electrically programmable read-only memories; Multistep manufacturing processes therefor with floating gate characterised by three-dimensional arrangements, e.g. with cells on different height levels with source and drain on different levels, e.g. with sloping channels the channels comprising vertical portions, e.g. U-shaped channels 274
G11C 16/04 - Erasable programmable read-only memories electrically programmable using variable threshold transistors, e.g. FAMOS 233
H01L 21/768 - Applying interconnections to be used for carrying current between separate components within a device 211
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1.

OPERATING METHOD FOR A MEMORY, A MEMORY AND A MEMORY SYSTEM

      
Application Number 18090104
Status Pending
Filing Date 2022-12-28
First Publication Date 2024-04-25
Owner Yangtze Memory Technologies Co., Ltd. (China)
Inventor
  • Cheng, Boxuan
  • Guo, Lu

Abstract

A method for operating a memory is provided, including, for example, obtaining a set of read voltages, each of which can include an initial voltage value and an offset voltage value with a certain offset relative to the initial voltage value. The initial voltage value in each of the set of read voltages can be a preset read voltage for distinguishing two adjacent memory states of memory cells of the memory. The operating method can further include performing read operations respectively based on the initial voltage values and the offset voltage values, obtaining the quantity of memory cells in which a read result corresponding to each voltage value meets set conditions, determining a difference between the two quantities corresponding to every two adjacent voltage values belonging to the same set of read voltages, and determining an optimal read voltage for distinguishing the two adjacent memory states based on the difference.

IPC Classes  ?

  • G11C 16/28 - Sensing or reading circuits; Data output circuits using differential sensing or reference cells, e.g. dummy cells
  • G11C 16/04 - Erasable programmable read-only memories electrically programmable using variable threshold transistors, e.g. FAMOS

2.

MEMORY SYSTEM AND OPERATION THEREOF

      
Application Number CN2022125936
Publication Number 2024/082136
Status In Force
Filing Date 2022-10-18
Publication Date 2024-04-25
Owner YANGTZE MEMORY TECHNOLOGIES CO., LTD. (China)
Inventor Cheng, Mo

Abstract

In certain aspects, a memory system includes a memory system, coupled to a host memory, comprising a memory device, comprising first memory cells and second memory cells; a memory controller, coupled to a host and the memory device, configured to write a first data to the first memory cells and/or a second data to the second memory cells, wherein the first data comprises user data, and the second data comprises swap data from the host memory.

IPC Classes  ?

3.

MEMORY SYSTEM AND OPERATION METHOD THEREFOR, MEMORY CONTROLLER, AND MEMORY

      
Application Number CN2023071798
Publication Number 2024/082466
Status In Force
Filing Date 2023-01-11
Publication Date 2024-04-25
Owner YANGTZE MEMORY TECHNOLOGIES CO., LTD. (China)
Inventor
  • Tan, Hua
  • Feng, Yufei

Abstract

Disclosed in embodiments of the present disclosure are a memory system and an operation method therefor, a memory controller, and a memory. The memory system comprises a memory; the memory comprises a memory cell array and a peripheral circuit coupled to the memory cell array; and the memory cell array comprises memory cells capable of storing m pieces of bit information, wherein m is a positive integer greater than 1. The operation method comprises: the peripheral circuit determining an (n+1)-th group of logical page data according to a received prefix command and received n groups of logical page data, wherein n is a positive integer, and n+1 is a positive integer less than or equal to m; and writing the n groups of logical page data and the (n+1)-th group of logical page data into the memory cell array, so as to generate 2n different data states in the memory cell array.

IPC Classes  ?

  • G11C 16/04 - Erasable programmable read-only memories electrically programmable using variable threshold transistors, e.g. FAMOS

4.

THREE-DIMENSIONAL NAND MEMORY DEVICE AND FABRICATION METHOD

      
Application Number 17971777
Status Pending
Filing Date 2022-10-23
First Publication Date 2024-04-25
Owner Yangtze Memory Technologies Co., Ltd. (China)
Inventor
  • Yan, Longxiang
  • Xu, Wei
  • Xue, Lei
  • Huo, Zongliang

Abstract

A method of forming a three-dimensional (3D) NAND memory device includes: forming a gate line slit through alternating layers of an oxide layer and a conductive material layer, wherein the conductive material layer is further formed on a sidewall and a bottom of the gate line slit; performing a first etch process to remove portions of the conductive material layer from the sidewall and the bottom of the gate line slit and from between adjacent oxide layers, thereby exposing portions of the oxide layer in the gate line slit; removing the exposed portions of the oxide layer on the sidewall of the gate line slit; and performing a second etch process to remove residues of the conductive material layer in the gate line slit.

IPC Classes  ?

  • H01L 27/11582 - Electrically programmable read-only memories; Multistep manufacturing processes therefor with charge-trapping gate insulators, e.g. MNOS or NROM characterised by three-dimensional arrangements, e.g. with cells on different height levels with source and drain on different levels, e.g. with sloping channels the channels comprising vertical portions, e.g. U-shaped channels
  • H01L 27/11556 - Electrically programmable read-only memories; Multistep manufacturing processes therefor with floating gate characterised by three-dimensional arrangements, e.g. with cells on different height levels with source and drain on different levels, e.g. with sloping channels the channels comprising vertical portions, e.g. U-shaped channels

5.

THREE-DIMENSIONAL MEMORY DEVICE, MANUFACTURING METHOD THEREOF, AND MEMORY SYSTEM

      
Application Number 18090380
Status Pending
Filing Date 2022-12-28
First Publication Date 2024-04-18
Owner YANGTZE MEMORY TECHNOLOGIES CO., LTD. (China)
Inventor
  • Liu, Jiayi
  • Gao, Tingting
  • Liu, Xiaoxin
  • Du, Xiaolong
  • Sun, Changzhi
  • Xia, Zhiliang

Abstract

The present disclosure provides a three-dimensional memory comprising: a storage channel structure vertically penetrating a plurality of stacked layers and comprising a first channel layer; a select gate structure on the plurality of stacked layers; and a select channel structure vertically penetrating the select gate structure and comprising: a block layer in contact with the select gate structure, an insulating layer covering the block layer, and a second channel layer in contact with the insulating layer and the first channel layer.

IPC Classes  ?

  • H10B 41/27 - Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates characterised by three-dimensional arrangements, e.g. with cells on different height levels with source and drain on different levels, e.g. with sloping channels the channels comprising vertical portions, e.g. U-shaped channels
  • H10B 41/35 - Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates characterised by the memory core region with a cell select transistor, e.g. NAND
  • H10B 41/40 - Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates characterised by the peripheral circuit region
  • H10B 43/27 - EEPROM devices comprising charge-trapping gate insulators characterised by three-dimensional arrangements, e.g. with cells on different height levels with source and drain on different levels, e.g. with sloping channels the channels comprising vertical portions, e.g. U-shaped channels
  • H10B 43/35 - EEPROM devices comprising charge-trapping gate insulators characterised by the memory core region with cell select transistors, e.g. NAND
  • H10B 43/40 - EEPROM devices comprising charge-trapping gate insulators characterised by the peripheral circuit region

6.

THREE-DIMENSIONAL MEMORY DEVICE, MANUFACTURING METHOD THEREOF, AND MEMORY SYSTEM

      
Application Number 18090374
Status Pending
Filing Date 2022-12-28
First Publication Date 2024-04-18
Owner YANGTZE MEMORY TECHNOLOGIES CO., LTD. (China)
Inventor
  • Liu, Jiayi
  • Gao, Tingting
  • Sun, Changzhi
  • Du, Xiaolong
  • Liu, Xiaoxin
  • Xia, Zhiliang

Abstract

The present disclosure provides a three-dimensional memory device and a manufacturing method thereof. The three-dimensional memory device comprises: a plurality of stacked layers; a storage channel structure vertically penetrating the stacked layers and comprising a first channel layer; a select gate structure on the plurality of stacked layers and comprising a conductive layer sandwiched between two dielectric layers; and a select channel structure vertically penetrating the select gate structure and comprising a second channel layer.

IPC Classes  ?

  • H10B 43/35 - EEPROM devices comprising charge-trapping gate insulators characterised by the memory core region with cell select transistors, e.g. NAND
  • H10B 41/27 - Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates characterised by three-dimensional arrangements, e.g. with cells on different height levels with source and drain on different levels, e.g. with sloping channels the channels comprising vertical portions, e.g. U-shaped channels
  • H10B 41/35 - Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates characterised by the memory core region with a cell select transistor, e.g. NAND
  • H10B 43/27 - EEPROM devices comprising charge-trapping gate insulators characterised by three-dimensional arrangements, e.g. with cells on different height levels with source and drain on different levels, e.g. with sloping channels the channels comprising vertical portions, e.g. U-shaped channels

7.

THREE-DIMENSIONAL MEMORY DEIVCE, MANUFACTURING METHOD THEREOF, AND MEMORY SYSTEM

      
Application Number 18090369
Status Pending
Filing Date 2022-12-28
First Publication Date 2024-04-18
Owner YANGTZE MEMORY TECHNOLOGIES CO., LTD. (China)
Inventor
  • Liu, Jiayi
  • Gao, Tingting
  • Liu, Xiaoxin
  • Du, Xiaolong
  • Sun, Changzhi
  • Xia, Zhiliang

Abstract

The present disclosure provides a three-dimensional memory device and a manufacturing method thereof, the three-dimensional memory device including: a plurality of stacked layers; a storage channel structure vertically penetrating the stacked layers and comprising a first channel layer; a select gate structure on the plurality of stacked layers; and a select channel structure vertically penetrating the select gate structure and comprising a second channel layer; wherein an outer sidewall of the second channel layer is in contact with an inner sidewall of the first channel layer.

IPC Classes  ?

  • H10B 43/35 - EEPROM devices comprising charge-trapping gate insulators characterised by the memory core region with cell select transistors, e.g. NAND
  • H10B 41/27 - Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates characterised by three-dimensional arrangements, e.g. with cells on different height levels with source and drain on different levels, e.g. with sloping channels the channels comprising vertical portions, e.g. U-shaped channels
  • H10B 41/35 - Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates characterised by the memory core region with a cell select transistor, e.g. NAND
  • H10B 43/27 - EEPROM devices comprising charge-trapping gate insulators characterised by three-dimensional arrangements, e.g. with cells on different height levels with source and drain on different levels, e.g. with sloping channels the channels comprising vertical portions, e.g. U-shaped channels

8.

MEMORY SYSTEMS AND OPERATION METHODS THEREOF, MEMORY CONTROLLERS AND MEMORIES

      
Application Number 18323948
Status Pending
Filing Date 2023-05-25
First Publication Date 2024-04-18
Owner Yangtze Memory Technologies Co., Ltd. (China)
Inventor
  • Tan, Hua
  • Feng, Yufei

Abstract

Embodiments of the present disclosure disclose a memory system and operation method thereof, a memory controller and a memory. The memory system includes a memory. The memory includes a memory cell array and a peripheral circuit coupled to the memory cell array. The memory cell array includes memory cells capable of storing m bits of information, and m is a positive integer greater than 1. The operation method includes: determining, by the peripheral circuit, (n+1)th group of page data according to a received prefix command and received n groups of page data, wherein n is a positive integer, and n+1 is a positive integer less than or equal to m; and writing the n groups of page data and the (n+1)th group of page data into the memory cell array to generate 2n different data states in the memory cell array.

IPC Classes  ?

  • G06F 3/06 - Digital input from, or digital output to, record carriers

9.

LOADING LOGICAL TO PHYSICAL MAPPING TABLE TO CACHE OF MEMORY CONTROLLER

      
Application Number 18394971
Status Pending
Filing Date 2023-12-22
First Publication Date 2024-04-18
Owner YANGTZE MEMORY TECHNOLOGIES CO., LTD. (China)
Inventor Tan, Hua

Abstract

A method of operating a memory system is provided. A logical-to-physical (L2P) address mapping table is obtained in response to a data request instruction. Corresponding data is read from a memory device based on the L2P address mapping table. The L2P address mapping table includes a base physical address of continuous first physical addresses corresponding to first logic addresses and a base physical address offset corresponding to the continuous first physical addresses.

IPC Classes  ?

  • G06F 12/0802 - Addressing of a memory level in which the access to the desired data or data block requires associative addressing means, e.g. caches

10.

NON-DESTRUCTIVE MODE CACHE PROGRAMMING IN NAND FLASH MEMORY DEVICES

      
Application Number 18538843
Status Pending
Filing Date 2023-12-13
First Publication Date 2024-04-18
Owner YANGTZE MEMORY TECHNOLOGIES CO., LTD. (China)
Inventor Guo, Jason

Abstract

A memory device includes memory cells arranged in rows and columns, each memory cell configured to store n-bit of data, where n is a whole number larger than two, and a periphery circuit coupled to the memory cells and configured to program selected memory cells according to n logic pages of current programming data. The periphery circuit includes page buffers, and each page buffer includes latches. The periphery circuit is configured to store the n logic pages of the current programming data in the latches for programming the selected memory cells, release one or more of the latches, by discarding one or more of the n logic pages of the current programming data correspondingly, before the programming the selected memory cells according to the n logic pages of the current programming data is completed, and store one of n logic pages of next programming data in one or more of the latches before the programming the selected memory cells according to the n logic pages of the current programming data is completed.

IPC Classes  ?

  • G11C 16/34 - Determination of programming status, e.g. threshold voltage, overprogramming or underprogramming, retention
  • G11C 7/10 - Input/output [I/O] data interface arrangements, e.g. I/O data control circuits, I/O data buffers
  • G11C 16/10 - Programming or data input circuits
  • G11C 16/24 - Bit-line control circuits
  • G11C 16/26 - Sensing or reading circuits; Data output circuits

11.

MEMORY SYSTEM AND OPERATION THEREOF

      
Application Number 17992869
Status Pending
Filing Date 2022-11-22
First Publication Date 2024-04-18
Owner YANGTZE MEMORY TECHNOLOGIES CO., LTD. (China)
Inventor Cheng, Mo

Abstract

In certain aspects, a memory system coupled to a host memory includes a memory device. The memory device includes first memory cells and second memory cells. The memory system further includes a memory controller coupled to a host and the memory device. The memory controller is configured to write at least one of a first data to the first memory cells or a second data to the second memory cells. The first data includes user data, and the second data includes swap data from the host memory.

IPC Classes  ?

  • G06F 3/06 - Digital input from, or digital output to, record carriers
  • G06F 12/1009 - Address translation using page tables, e.g. page table structures

12.

THREE-DIMENSIONAL MEMORY AND MANUFACTURING METHOD THEREFOR, AND MEMORY SYSTEM

      
Application Number CN2022125335
Publication Number 2024/077592
Status In Force
Filing Date 2022-10-14
Publication Date 2024-04-18
Owner YANGTZE MEMORY TECHNOLOGIES CO., LTD. (China)
Inventor
  • Liu, Jiayi
  • Gao, Tingting
  • Liu, Xiaoxin
  • Du, Xiaolong
  • Sun, Changzhi
  • Xia, Zhiliang

Abstract

Provided in the present application is a three-dimensional memory, comprising: a stacked layer, which is located on a semiconductor layer; a storage channel structure, which penetrates through the stacked layer and comprises a first channel layer; a selective gate structure, which is located on the side of the stacked layer that faces away from the semiconductor layer; a selective channel structure, which penetrates through the selective gate structure and comprises an insulating layer and a second channel layer that are arranged from outside to inside; and a barrier layer, which comprises: a first barrier portion located on the end face of the insulating layer that is close to the semiconductor layer; and a second barrier portion located on the surface of the insulating layer that faces away from the second channel layer. The barrier layer provided in the three-dimensional memory in the embodiments of the present application can effectively prevent the diffusion of impurity particles doped in a conductive layer to a gate dielectric layer, such that the quality of the gate dielectric layer is ensured, thereby facilitating control over the stability of a TSG transistor.

IPC Classes  ?

  • H01L 21/822 - Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using silicon technology
  • H10B 41/27 - Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates characterised by three-dimensional arrangements, e.g. with cells on different height levels with source and drain on different levels, e.g. with sloping channels the channels comprising vertical portions, e.g. U-shaped channels

13.

THREE-DIMENSIONAL MEMORY, MANUFACTURING METHOD THEREFOR, AND MEMORY SYSTEM

      
Application Number CN2022125342
Publication Number 2024/077593
Status In Force
Filing Date 2022-10-14
Publication Date 2024-04-18
Owner YANGTZE MEMORY TECHNOLOGIES CO., LTD. (China)
Inventor
  • Liu, Jiayi
  • Gao, Tingting
  • Sun, Changzhi
  • Du, Xiaolong
  • Liu, Xiaoxin
  • Xia, Zhiliang

Abstract

Provided in the present application are a three-dimensional memory and a manufacturing method therefor. The three-dimensional memory comprises: a stacked layer, located on a semiconductor layer; a memory channel structure, penetrating through the stacked layer and comprising a first channel layer; a selective gate structure, located on the side of the stacked layer facing away from the semiconductor layer; and a selective channel structure, penetrating through the selective gate structure, and comprising a barrier layer and a second channel layer which are arranged from outside to inside. The barrier layer arranged in the three-dimensional memory in some embodiments of the present application can effectively prevent impurity particles doped in a conductive layer from diffusing to a gate dielectric layer, thereby ensuring the quality of the gate dielectric layer, and facilitating controlling the stability of TSG transistors.

IPC Classes  ?

  • H10B 43/27 - EEPROM devices comprising charge-trapping gate insulators characterised by three-dimensional arrangements, e.g. with cells on different height levels with source and drain on different levels, e.g. with sloping channels the channels comprising vertical portions, e.g. U-shaped channels

14.

THREE-DIMENSIONAL MEMORY AND MANUFACTURING METHOD THEREFOR, AND MEMORY SYSTEM

      
Application Number CN2022125355
Publication Number 2024/077595
Status In Force
Filing Date 2022-10-14
Publication Date 2024-04-18
Owner YANGTZE MEMORY TECHNOLOGIES CO., LTD. (China)
Inventor
  • Liu, Jiayi
  • Gao, Tingting
  • Liu, Xiaoxin
  • Du, Xiaolong
  • Sun, Changzhi
  • Xia, Zhiliang

Abstract

Provided in the present application are a three-dimensional memory and a manufacturing method therefor. The three-dimensional memory comprises: a stacked layer, located on a semiconductor layer; a memory channel structure, passing through the stacked layer and comprising a first channel layer; and a selective gate structure, located on the side of the stacked layer facing away from the semiconductor layer; and a selective channel structure, passing through the selective gate structure, and comprising a second channel layer, wherein a first end portion of the first channel layer away from the semiconductor layer is in contact with a second end portion of the second channel layer close to the semiconductor layer. The first channel layer and the second channel layer of the three-dimensional memory provided in the present application can be in direct contact connection, thereby avoiding lead-in channel plugging, and ameliorating the problem of programming interference.

IPC Classes  ?

  • H10B 41/35 - Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates characterised by the memory core region with a cell select transistor, e.g. NAND
  • H10B 41/30 - Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates characterised by the memory core region
  • H10B 41/23 - Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates characterised by three-dimensional arrangements, e.g. with cells on different height levels with source and drain on different levels, e.g. with sloping channels
  • H10B 41/20 - Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates characterised by three-dimensional arrangements, e.g. with cells on different height levels
  • H10B 41/10 - Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates characterised by the top-view layout

15.

METHOD AND SYSTEM OF ERROR INJECTION FOR LOW-DENSITY PARITY-CHECK

      
Application Number 17938557
Status Pending
Filing Date 2022-10-06
First Publication Date 2024-04-11
Owner Yangtze Memory Technologies Co., Ltd. (China)
Inventor
  • Luo, Wen
  • Feng, Yufei

Abstract

A method for verifying a low-density parity-check (LDPC) unit capable of being applied in a memory system can include receiving original data corresponding to a memory device, encoding the original data by the LDPC unit to be verified, injecting errors into the encoded original data by a data pattern for generating verifying data, and verifying a soft decode capability of the LDPC unit by utilizing the verifying data. The data pattern can include the errors generated by threshold voltage (Vth) distributions interlaced between two neighboring logic states of 2n logic states of the memory device. The method and system can provide an error injection to accurately and efficiently verify a LDPC soft decode capability of the LDPC unit, decrease errors, increase error correction accuracy and efficiency, more accurately model actual threshold voltage (Vth) distributions, increase flexibility, increase speed, increase performance, and reduce firmware overhead.

IPC Classes  ?

  • H03M 13/11 - Error detection or forward error correction by redundancy in data representation, i.e. code words containing more digits than the source words using block codes, i.e. a predetermined number of check bits joined to a predetermined number of information bits using multiple parity bits
  • H03M 13/00 - Coding, decoding or code conversion, for error detection or error correction; Coding theory basic assumptions; Coding bounds; Error probability evaluation methods; Channel models; Simulation or testing of codes

16.

PROGRAMMING FOR THREE-DIMENSIONAL NAND MEMORY

      
Application Number 18537263
Status Pending
Filing Date 2023-12-12
First Publication Date 2024-04-04
Owner YANGTZE MEMORY TECHNOLOGIES CO., LTD. (China)
Inventor
  • Li, Haibo
  • Jin, Joohyun
  • Zhang, Chao

Abstract

A memory device includes selected word lines coupled to first memory cells, a first group of unselected word lines coupled to second memory cells, a second group of unselected word lines coupled to third memory cells; and a peripheral circuit coupled to the selected word lines, the first group of unselected word lines, and the second group of unselected word lines. The peripheral circuit is configured to apply program voltages on the selected word lines, apply first pass voltages on the first group of unselected word lines; and apply second pass voltages on the second group of unselected word lines. A first maximum value of the first pass voltages is different from a second maximum value of the second pass voltages.

IPC Classes  ?

  • G11C 16/10 - Programming or data input circuits
  • G11C 16/08 - Address circuits; Decoders; Word-line control circuits
  • G11C 16/14 - Circuits for erasing electrically, e.g. erase voltage switching circuits
  • G11C 16/24 - Bit-line control circuits
  • G11C 16/26 - Sensing or reading circuits; Data output circuits
  • G11C 16/34 - Determination of programming status, e.g. threshold voltage, overprogramming or underprogramming, retention

17.

MEMORY DEVICE, OPERATING METHOD THEREOF, AND MEMORY SYSTEM

      
Application Number CN2022136531
Publication Number 2024/066033
Status In Force
Filing Date 2022-12-05
Publication Date 2024-04-04
Owner YANGTZE MEMORY TECHNOLOGIES CO., LTD. (China)
Inventor Guo, Xiaojiang

Abstract

A memory device includes at least one memory cell array block and a control logic. The memory cell array block includes multiple layers of memory cells and word line layers provided corresponding to individual layers of memory cells. The memory cell array block is divided into at least two memory cell array subblocks, each memory cell array subblock comprising a number of layers of memory cells and word line layers provided corresponding to individual layers of memory cells. The control logic is coupled to the memory cell array block, and configured to: erase, read or program the memory cell array block using a block mode or a subblock mode, and when the memory cell array block is erased, read, or programmed under the subblock mode, determine, at least based on a state of one of the two memory cell array subblocks, an operation strategy of the other memory cell array subblock.

IPC Classes  ?

  • G11C 16/34 - Determination of programming status, e.g. threshold voltage, overprogramming or underprogramming, retention

18.

INTERCONNECT STRUCTURES OF THREE-DIMENSIONAL MEMORY DEVICES

      
Application Number 18538755
Status Pending
Filing Date 2023-12-13
First Publication Date 2024-04-04
Owner YANGTZE MEMORY TECHNOLOGIES CO., LTD. (China)
Inventor
  • Zhang, Kun
  • Song, Haojie
  • Bao, Kun
  • Xia, Zhiliang

Abstract

Embodiments of 3D memory devices and methods for forming the same are disclosed. In an example, a 3D memory device includes a substrate, a memory stack, a channel structure, a channel local contact, a slit structure, and a staircase local contact. The memory stack includes interleaved conductive layers and dielectric layers above the substrate. The channel structure extends vertically through the memory stack. The channel local contact is above and in contact with the channel structure. The slit structure extends vertically through the memory stack. The staircase local contact is above and in contact with one of the conductive layers at a staircase structure on an edge of the memory stack. Upper ends of the channel local contact, the slit structure, and the staircase local contact are flush with one another.

IPC Classes  ?

  • H10B 43/27 - EEPROM devices comprising charge-trapping gate insulators characterised by three-dimensional arrangements, e.g. with cells on different height levels with source and drain on different levels, e.g. with sloping channels the channels comprising vertical portions, e.g. U-shaped channels
  • H01L 21/768 - Applying interconnections to be used for carrying current between separate components within a device
  • H01L 23/522 - Arrangements for conducting electric current within the device in operation from one component to another including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
  • H01L 23/528 - Layout of the interconnection structure
  • H01L 23/535 - Arrangements for conducting electric current within the device in operation from one component to another including internal interconnections, e.g. cross-under constructions
  • H10B 41/27 - Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates characterised by three-dimensional arrangements, e.g. with cells on different height levels with source and drain on different levels, e.g. with sloping channels the channels comprising vertical portions, e.g. U-shaped channels
  • H10B 41/35 - Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates characterised by the memory core region with a cell select transistor, e.g. NAND
  • H10B 43/35 - EEPROM devices comprising charge-trapping gate insulators characterised by the memory core region with cell select transistors, e.g. NAND

19.

MEMORY DEVICE, OPERATING METHOD THEREOF, AND MEMORY SYSTEM

      
Application Number 18153843
Status Pending
Filing Date 2023-01-12
First Publication Date 2024-04-04
Owner Yangtze Memory Technologies Co., Ltd. (China)
Inventor Guo, Xiaojiang

Abstract

A memory device includes at least one memory cell array block and a control logic. The memory cell array block includes multiple layers of memory cells and word line layers provided corresponding to individual layers of memory cells. The memory cell array block is divided into at least two memory cell array subblocks, each subblock comprising a number of layers of memory cells and word line layers provided corresponding to individual layers of memory cells. The control logic is coupled to the memory cell array block, and configured to: erase, read or program the memory cell array block using a block mode or a subblock mode, and when the memory cell array block is erased, read, or programmed under the subblock mode, determine, at least based on a state of one of the two memory cell array subblocks, an operation strategy of the other memory cell array subblock.

IPC Classes  ?

  • G11C 16/28 - Sensing or reading circuits; Data output circuits using differential sensing or reference cells, e.g. dummy cells
  • G11C 16/10 - Programming or data input circuits
  • G11C 16/14 - Circuits for erasing electrically, e.g. erase voltage switching circuits

20.

METHOD OF IMPROVING PROGRAM OPERATION SPEED IN 3D NAND SYSTEMS

      
Application Number 17937016
Status Pending
Filing Date 2022-09-30
First Publication Date 2024-04-04
Owner Yangtze Memory Technologies Co., Ltd. (China)
Inventor
  • Huang, Ying
  • Liu, Hongtao
  • Min, Yuanyuan
  • Wang, Junbao

Abstract

Disclosed herein are memory device, method for program operations. In an aspect, a memory device comprises a memory configured to store a program code and a processor. The processor is configured to perform a first programming to a first cell of the memory device by incremental step pulse programming (ISPP) with a first step voltage. The processor is further configured to perform a second programming to a second cell of the memory device by ISPP with a second step voltage. The first step voltage is larger than the second step voltage. The first cell corresponds to a first target voltage and the second cell corresponds to a second target voltage. The first cell corresponds to a first target voltage and the second cell corresponds to a second target voltage.

IPC Classes  ?

  • G11C 16/10 - Programming or data input circuits
  • G11C 16/12 - Programming voltage switching circuits

21.

ERASING AND ERASING VERIFICATION FOR THREE-DIMENSIONAL NAND MEMORY

      
Application Number 17950810
Status Pending
Filing Date 2022-09-22
First Publication Date 2024-04-04
Owner Yangtze Memory Technologies Co., Ltd. (China)
Inventor Huang, Kaijin

Abstract

The present disclosure provides a method of erase and erase verification for a memory device. The method includes applying a first erase voltage to erase memory cells of the memory device. The first erase voltage is incrementally increased by a first erase step voltage until the memory cells pass an initial erase verification. The method also includes determining whether the memory cells pass or fail sub-erase verifications by applying sub-erase verification voltages. The method further includes applying a second erase voltage to erase the memory cells after the sub-erase verifications. The second erase voltage is increased from the first erase voltage by a second erase step voltage, which is smaller than the first erase step voltage and is determined according to whether the memory cells pass or fail the sub-erase verifications.

IPC Classes  ?

  • G11C 16/34 - Determination of programming status, e.g. threshold voltage, overprogramming or underprogramming, retention
  • G11C 16/08 - Address circuits; Decoders; Word-line control circuits
  • G11C 16/16 - Circuits for erasing electrically, e.g. erase voltage switching circuits for erasing blocks, e.g. arrays, words, groups

22.

DOUBLE PROGRAM DEBUG METHOD FOR NAND MEMORY USING SELF-VERIFICATION BY INTERNAL FIRMWARE

      
Application Number 18533007
Status Pending
Filing Date 2023-12-07
First Publication Date 2024-03-28
Owner YANGTZE MEMORY TECHNOLOGIES CO., LTD. (China)
Inventor He, Youxin

Abstract

The present disclosure provides a method for programing flash memory devices. The method may include programming a selected page of the NAND flash memory device according to programming data. The selected page may include memory cells corresponding to a word line. The programming of the selected page may include programming operations with programming voltages applied on the word line and a read operation performed on the selected page.

IPC Classes  ?

  • G11C 16/34 - Determination of programming status, e.g. threshold voltage, overprogramming or underprogramming, retention
  • G11C 16/08 - Address circuits; Decoders; Word-line control circuits
  • G11C 16/10 - Programming or data input circuits
  • G11C 16/26 - Sensing or reading circuits; Data output circuits
  • G11C 16/32 - Timing circuits

23.

OPENINGS LAYOUT OF THREE-DIMENSIONAL MEMORY DEVICE

      
Application Number 18534480
Status Pending
Filing Date 2023-12-08
First Publication Date 2024-03-28
Owner YANGTZE MEMORY TECHNOLOGIES CO., LTD. (China)
Inventor
  • He, Jia
  • Huang, Haihui
  • Liu, Fandong
  • Yang, Yaohua
  • Hong, Peizhen
  • Xia, Zhiliang
  • Huo, Zongliang
  • Feng, Yaobin
  • Chen, Baoyou
  • Cao, Qingchen

Abstract

Embodiments of semiconductor devices and methods for forming the semiconductor devices are disclosed. In an example, a method for forming device openings includes forming a material layer over a first region and a second region of a substrate, the first region being adjacent to the second region, forming a mask layer over the material layer, the mask layer covering the first region and the second region, and forming a patterning layer over the mask layer. The patterning layer covers the first region and the second region and including openings corresponding to the first region. The plurality of openings includes a first opening adjacent to a boundary between the first region and the second region and a second opening further away from the boundary. Along a plane parallel to a top surface of the substrate, a size of the first opening is greater than a size of the second opening.

IPC Classes  ?

  • H10B 43/20 - EEPROM devices comprising charge-trapping gate insulators characterised by three-dimensional arrangements, e.g. with cells on different height levels
  • H01L 21/28 - Manufacture of electrodes on semiconductor bodies using processes or apparatus not provided for in groups
  • H01L 29/66 - Types of semiconductor device
  • H01L 29/792 - Field-effect transistors with field effect produced by an insulated gate with charge trapping gate insulator, e.g. MNOS-memory transistor
  • H10B 43/27 - EEPROM devices comprising charge-trapping gate insulators characterised by three-dimensional arrangements, e.g. with cells on different height levels with source and drain on different levels, e.g. with sloping channels the channels comprising vertical portions, e.g. U-shaped channels
  • H10B 43/35 - EEPROM devices comprising charge-trapping gate insulators characterised by the memory core region with cell select transistors, e.g. NAND

24.

NON-VOLATILE MEMORY DEVICES AND DATA ERASING METHODS

      
Application Number 17950931
Status Pending
Filing Date 2022-09-22
First Publication Date 2024-03-28
Owner YANGTZE MEMORY TECHNOLOGIES CO., LTD. (China)
Inventor
  • Yang, Tao
  • Zhao, Dongxue
  • Liu, Lei
  • Zhang, Kun
  • Zhou, Wenxi
  • Xia, Zhiliang
  • Huo, Zongliang

Abstract

A method for data erasing of a non-volatile memory device is disclosed. The memory includes multiple memory cell strings each including a select gate transistor and multiple memory cells that are connected in series. The method comprises applying a step erase voltage to one memory cell string for an erase operation, the step erase voltage having a step-rising shaped voltage waveform. The method further comprises, during a period when the step erase voltage rises from an intermediate level to a peak level, raising a voltage of the select gate transistor from a starting level to a peak level, and raising a voltage of a predetermined region from a starting level to a peak level, such that a gate-induced drain leakage current is generated in the one memory cell string. The predetermined region is adjacent to the at least one select gate transistor and includes at least one memory cell.

IPC Classes  ?

  • G11C 16/16 - Circuits for erasing electrically, e.g. erase voltage switching circuits for erasing blocks, e.g. arrays, words, groups
  • G11C 16/04 - Erasable programmable read-only memories electrically programmable using variable threshold transistors, e.g. FAMOS

25.

MEMORY SYSTEM, SEMICONDUCTOR DEVICE AND FABRICATION METHOD THEREFOR

      
Application Number 17951980
Status Pending
Filing Date 2022-09-23
First Publication Date 2024-03-28
Owner Yangtze Memory Technologies Co., Ltd. (China)
Inventor
  • Wu, Linchun
  • Kong, Cuicui
  • Xia, Zhiliang
  • Huo, Zongliang

Abstract

Aspects of the disclosure provide a semiconductor device. The semiconductor device includes a stack of conductive layers and insulating layers stacked alternatingly in a first direction. The stack of conductive layers and insulating layers has a first side and a second side in the first direction. The semiconductor device then includes a semiconductor layer at the first side of the stack of conductive layers and insulating layers, and a first isolation structure extending through, in the first direction, the semiconductor layer and a subset of the stack of conductive layers and insulating layers. The subset of the stack of conductive layers and insulating layers includes a first conductive layer. The first isolation structure separates a first portion of the first conductive layer from a second portion of the first conductive layer.

IPC Classes  ?

  • H01L 27/11582 - Electrically programmable read-only memories; Multistep manufacturing processes therefor with charge-trapping gate insulators, e.g. MNOS or NROM characterised by three-dimensional arrangements, e.g. with cells on different height levels with source and drain on different levels, e.g. with sloping channels the channels comprising vertical portions, e.g. U-shaped channels
  • H01L 23/00 - SEMICONDUCTOR DEVICES NOT COVERED BY CLASS - Details of semiconductor or other solid state devices
  • H01L 25/065 - Assemblies consisting of a plurality of individual semiconductor or other solid state devices all the devices being of a type provided for in the same subgroup of groups , or in a single subclass of , , e.g. assemblies of rectifier diodes the devices not having separate containers the devices being of a type provided for in group
  • H01L 25/18 - Assemblies consisting of a plurality of individual semiconductor or other solid state devices the devices being of types provided for in two or more different subgroups of the same main group of groups , or in a single subclass of ,

26.

THREE-DIMENSIONAL MEMORY DEVICES AND METHODS FOR FORMING THE SAME

      
Application Number CN2022120958
Publication Number 2024/060219
Status In Force
Filing Date 2022-09-23
Publication Date 2024-03-28
Owner YANGTZE MEMORY TECHNOLOGIES CO., LTD. (China)
Inventor
  • Wang, Di
  • Zhang, Zhong
  • Zhou, Wenxi
  • Xia, Zhiliang
  • Huo, Zongliang
  • Xie, Wei

Abstract

In certain aspects, a method for forming a three-dimensional (3D) memory device is disclosed. A stack structure including interleaved first dielectric layers and second dielectric layers is formed. Channel structures extending through the first dielectric layers and the second dielectric layers in a first region of the stack structure are formed. All the second dielectric layers in the first region and parts of the second dielectric layers in a second region of the stack structure are replaced with conductive layers. Word line pick-up structures extending through the first dielectric layers and remainders of the second dielectric layers in the second region of the stack structure are formed at different depths, such that the word line pick-up structures are electrically connected to the conductive layers, respectively, in the second region of the stack structure.

IPC Classes  ?

  • G11C 16/26 - Sensing or reading circuits; Data output circuits

27.

MULTI-MODE COMPATIBLE ZQ CALIBRATION CIRCUIT IN MEMORY DEVICE

      
Application Number 18528339
Status Pending
Filing Date 2023-12-04
First Publication Date 2024-03-28
Owner YANGTZE MEMORY TECHNOLOGIES CO., LTD. (China)
Inventor
  • Song, Hang
  • Song, Daesik
  • Yang, Lin

Abstract

In certain aspects, a circuit for multi-mode calibration can include a resistor input. The circuit can also include a first comparator connected to the resistor input and to a first plurality of voltage sources. The circuit can also include a first pull-up driver. The circuit can further include a logic pull-up code generator to calibrate the first pull-up driver. The circuit can additionally include a replica of the first pull-up driver. The circuit can also include a first pull-down driver and a second comparator connected to the replica, the first pull-down driver, and a second plurality of voltage sources. The second comparator can compare a voltage of a middle point between the first pull-down driver and the second pull-up driver to one of the second plurality of voltage sources. The circuit can further include a logic pull-down code generator.

IPC Classes  ?

  • G11C 7/10 - Input/output [I/O] data interface arrangements, e.g. I/O data control circuits, I/O data buffers
  • G11C 16/06 - Auxiliary circuits, e.g. for writing into memory

28.

MULTI-MODE COMPATIBLE ZQ CALIBRATION CIRCUIT IN MEMORY DEVICE

      
Application Number 18528395
Status Pending
Filing Date 2023-12-04
First Publication Date 2024-03-28
Owner YANGTZE MEMORY TECHNOLOGIES CO., LTD. (China)
Inventor
  • Song, Hang
  • Song, Daesik
  • Yang, Lin

Abstract

In certain aspects, a circuit for multi-mode calibration can include a resistor input. The circuit can also include a first comparator connected to the resistor input and to a first plurality of voltage sources. The circuit can also include a first pull-up driver. The circuit can further include a logic pull-up code generator to calibrate the first pull-up driver. The circuit can additionally include a replica of the first pull-up driver. The circuit can also include a first pull-down driver and a second comparator connected to the replica, the first pull-down driver, and a second plurality of voltage sources. The second comparator can compare a voltage of a middle point between the first pull-down driver and the second pull-up driver to one of the second plurality of voltage sources. The circuit can further include a logic pull-down code generator.

IPC Classes  ?

  • G11C 7/10 - Input/output [I/O] data interface arrangements, e.g. I/O data control circuits, I/O data buffers
  • G11C 16/06 - Auxiliary circuits, e.g. for writing into memory

29.

THREE-DIMENSIONAL MEMORY DEVICES AND METHODS FOR FORMING THE SAME

      
Application Number 17968577
Status Pending
Filing Date 2022-10-18
First Publication Date 2024-03-28
Owner YANGTZE MEMORY TECHNOLOGIES CO., LTD. (China)
Inventor
  • Wang, Di
  • Zhang, Zhong
  • Zhou, Wenxi
  • Xia, Zhiliang
  • Huo, Zongliang
  • Xie, Wei

Abstract

In certain aspects, a three-dimensional (3D) memory device includes channel structures in a first region, word line pick-up structures in a dielectric portion of a second region, and word lines each extending in the first region and a conductive portion of the second region. The first region and the second region are arranged in a first direction. The dielectric portion and the conductive portion of the second region are arranged in a second direction perpendicular to the first direction. The word lines are discontinuous in the dielectric portion of the second region and are electrically connected to the word line pick-up structures, respectively.

IPC Classes  ?

  • H01L 27/11582 - Electrically programmable read-only memories; Multistep manufacturing processes therefor with charge-trapping gate insulators, e.g. MNOS or NROM characterised by three-dimensional arrangements, e.g. with cells on different height levels with source and drain on different levels, e.g. with sloping channels the channels comprising vertical portions, e.g. U-shaped channels
  • H01L 23/528 - Layout of the interconnection structure
  • H01L 27/11519 - Electrically programmable read-only memories; Multistep manufacturing processes therefor with floating gate characterised by the top-view layout
  • H01L 27/11524 - Electrically programmable read-only memories; Multistep manufacturing processes therefor with floating gate characterised by the memory core region with cell select transistors, e.g. NAND
  • H01L 27/11556 - Electrically programmable read-only memories; Multistep manufacturing processes therefor with floating gate characterised by three-dimensional arrangements, e.g. with cells on different height levels with source and drain on different levels, e.g. with sloping channels the channels comprising vertical portions, e.g. U-shaped channels
  • H01L 27/11565 - Electrically programmable read-only memories; Multistep manufacturing processes therefor with charge-trapping gate insulators, e.g. MNOS or NROM characterised by the top-view layout
  • H01L 27/1157 - Electrically programmable read-only memories; Multistep manufacturing processes therefor with charge-trapping gate insulators, e.g. MNOS or NROM characterised by the memory core region with cell select transistors, e.g. NAND

30.

THREE-DIMENSIONAL MEMORY DEVICES AND METHODS FOR FORMING THE SAME

      
Application Number 17968595
Status Pending
Filing Date 2022-10-18
First Publication Date 2024-03-28
Owner YANGTZE MEMORY TECHNOLOGIES CO., LTD. (China)
Inventor
  • Wang, Di
  • Zhang, Zhong
  • Zhou, Wenxi
  • Xia, Zhiliang
  • Huo, Zongliang
  • Xie, Wei

Abstract

In certain aspects, a method for forming a three-dimensional (3D) memory device is disclosed. A stack structure including interleaved first dielectric layers and second dielectric layers is formed. Channel structures extending through the first dielectric layers and the second dielectric layers in a first region of the stack structure are formed. All the second dielectric layers in the first region and parts of the second dielectric layers in a second region of the stack structure are replaced with conductive layers. Word line pick-up structures extending through the first dielectric layers and remainders of the second dielectric layers in the second region of the stack structure are formed at different depths, such that the word line pick-up structures are electrically connected to the conductive layers, respectively, in the second region of the stack structure.

IPC Classes  ?

  • H01L 27/11582 - Electrically programmable read-only memories; Multistep manufacturing processes therefor with charge-trapping gate insulators, e.g. MNOS or NROM characterised by three-dimensional arrangements, e.g. with cells on different height levels with source and drain on different levels, e.g. with sloping channels the channels comprising vertical portions, e.g. U-shaped channels
  • H01L 23/528 - Layout of the interconnection structure
  • H01L 27/11519 - Electrically programmable read-only memories; Multistep manufacturing processes therefor with floating gate characterised by the top-view layout
  • H01L 27/11524 - Electrically programmable read-only memories; Multistep manufacturing processes therefor with floating gate characterised by the memory core region with cell select transistors, e.g. NAND
  • H01L 27/11556 - Electrically programmable read-only memories; Multistep manufacturing processes therefor with floating gate characterised by three-dimensional arrangements, e.g. with cells on different height levels with source and drain on different levels, e.g. with sloping channels the channels comprising vertical portions, e.g. U-shaped channels
  • H01L 27/11565 - Electrically programmable read-only memories; Multistep manufacturing processes therefor with charge-trapping gate insulators, e.g. MNOS or NROM characterised by the top-view layout
  • H01L 27/1157 - Electrically programmable read-only memories; Multistep manufacturing processes therefor with charge-trapping gate insulators, e.g. MNOS or NROM characterised by the memory core region with cell select transistors, e.g. NAND

31.

THREE-DIMENSIONAL MEMORY DEVICES AND METHODS FOR FORMING THE SAME

      
Application Number 18090899
Status Pending
Filing Date 2022-12-29
First Publication Date 2024-03-28
Owner YANGTZE MEMORY TECHNOLOGIES CO., LTD. (China)
Inventor
  • Wang, Di
  • Zhou, Wenxi
  • Xia, Zhiliang
  • Huo, Zongliang

Abstract

In certain aspects, a three-dimensional (3D) memory device includes channel structures in a first region and word line pick-up structures in a first portion of a second region. The first region and the second region are arranged in a first direction. The 3D memory device also includes word lines each extending in the first region and a second portion of the second region. The first portion and the second portion of the second region are arranged in a second direction perpendicular to the first direction. The 3D memory device also includes dummy channel structures in the second portion of the second region. Adjacent channel structures are spaced apart from each other by a first distance. Adjacent dummy channel structures are spaced apart from each other by a second distance that is smaller than the first distance.

IPC Classes  ?

  • H10B 43/27 - EEPROM devices comprising charge-trapping gate insulators characterised by three-dimensional arrangements, e.g. with cells on different height levels with source and drain on different levels, e.g. with sloping channels the channels comprising vertical portions, e.g. U-shaped channels
  • H01L 23/528 - Layout of the interconnection structure
  • H10B 41/10 - Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates characterised by the top-view layout
  • H10B 41/27 - Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates characterised by three-dimensional arrangements, e.g. with cells on different height levels with source and drain on different levels, e.g. with sloping channels the channels comprising vertical portions, e.g. U-shaped channels
  • H10B 41/35 - Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates characterised by the memory core region with a cell select transistor, e.g. NAND
  • H10B 43/10 - EEPROM devices comprising charge-trapping gate insulators characterised by the top-view layout
  • H10B 43/35 - EEPROM devices comprising charge-trapping gate insulators characterised by the memory core region with cell select transistors, e.g. NAND

32.

THREE-DIMENSIONAL MEMORY DEVICES AND METHODS FOR FORMING THE SAME

      
Application Number CN2022120955
Publication Number 2024/060218
Status In Force
Filing Date 2022-09-23
Publication Date 2024-03-28
Owner YANGTZE MEMORY TECHNOLOGIES CO., LTD. (China)
Inventor
  • Wang, Di
  • Zhang, Zhong
  • Zhou, Wenxi
  • Xia, Zhiliang
  • Huo, Zongliang
  • Xie, Wei

Abstract

In certain aspects, a three-dimensional (3D) memory device includes channel structures in a first region, word line pick-up structures in a dielectric portion of a second region, and word lines each extending in the first region and a conductive portion of the second region. The first region and the second region are arranged in a first direction. The dielectric portion and the conductive portion of the second region are arranged in a second direction perpendicular to the first direction. The word lines are discontinuous in the dielectric portion of the second region and are electrically connected to the word line pick-up structures, respectively.

IPC Classes  ?

  • H01L 27/11556 - Electrically programmable read-only memories; Multistep manufacturing processes therefor with floating gate characterised by three-dimensional arrangements, e.g. with cells on different height levels with source and drain on different levels, e.g. with sloping channels the channels comprising vertical portions, e.g. U-shaped channels

33.

THREE-DIMENSIONAL MEMORY DEVICE AND METHOD FOR FORMING THE SAME

      
Application Number 18231731
Status Pending
Filing Date 2023-08-08
First Publication Date 2024-03-21
Owner YANGTZE MEMORY TECHNOLOGIES CO., LTD. (China)
Inventor
  • Liu, Yaqin
  • Liu, Wei
  • Wang, Yanhong
  • Huang, Shiqi
  • Liu, Zichen

Abstract

A semiconductor device, a memory system, and a fabricating method are provided. The semiconductor device comprises a memory structure bonded with a circuit structure. The memory structure comprises: first transistors each comprising a semiconductor body extending in a vertical direction, a semiconductor layer on a lateral side of the first transistors, a first isolation structure extending through the semiconductor layer and laterally encircling a first portion of the semiconductor layer, a first contact structure extending through the first portion of the semiconductor layer, and a first contact pad above the first portion of the semiconductor layer and connected with the first contact structure. A lateral dimension of the first contact pad is less than a lateral dimension of the first portion of the semiconductor layer. The circuit structure comprises a second transistor, and the first contact pad is electrically connected to the second transistor by the first contact structure.

IPC Classes  ?

  • H10B 12/00 - Dynamic random access memory [DRAM] devices

34.

THREE-DIMENSIONAL MEMORY DEVICES AND METHODS FOR FORMING THE SAME

      
Application Number 17948549
Status Pending
Filing Date 2022-09-20
First Publication Date 2024-03-21
Owner YANGTZE MEMORY TECHNOLOGIES CO., LTD. (China)
Inventor
  • Xia, Zhengliang
  • Zhou, Wenbin
  • Huo, Zongliang
  • Tang, Zhaohui

Abstract

A semiconductor device includes a plurality of memory blocks. Each memory block includes a memory deck including interleaved first conductor layers and first dielectric layers, and a separation structure extending to separate two adjacent memory blocks. Each separation structure includes a dielectric stack including interleaved third dielectric layers and fourth dielectric layers. The third dielectric layers are in contact with the first dielectric layers, and the fourth dielectric layers are in contact with the first conductor layers.

IPC Classes  ?

  • H01L 27/11556 - Electrically programmable read-only memories; Multistep manufacturing processes therefor with floating gate characterised by three-dimensional arrangements, e.g. with cells on different height levels with source and drain on different levels, e.g. with sloping channels the channels comprising vertical portions, e.g. U-shaped channels
  • H01L 27/11519 - Electrically programmable read-only memories; Multistep manufacturing processes therefor with floating gate characterised by the top-view layout
  • H01L 27/11526 - Electrically programmable read-only memories; Multistep manufacturing processes therefor with floating gate characterised by the peripheral circuit region
  • H01L 27/11565 - Electrically programmable read-only memories; Multistep manufacturing processes therefor with charge-trapping gate insulators, e.g. MNOS or NROM characterised by the top-view layout
  • H01L 27/11573 - Electrically programmable read-only memories; Multistep manufacturing processes therefor with charge-trapping gate insulators, e.g. MNOS or NROM characterised by the peripheral circuit region
  • H01L 27/11582 - Electrically programmable read-only memories; Multistep manufacturing processes therefor with charge-trapping gate insulators, e.g. MNOS or NROM characterised by three-dimensional arrangements, e.g. with cells on different height levels with source and drain on different levels, e.g. with sloping channels the channels comprising vertical portions, e.g. U-shaped channels

35.

MEMORY INCLUDING A PLURALITY OF PORTIONS AND USED FOR REDUCING PROGRAM DISTURBANCE AND PROGRAM METHOD THEREOF

      
Application Number 18518849
Status Pending
Filing Date 2023-11-24
First Publication Date 2024-03-21
Owner YANGTZE MEMORY TECHNOLOGIES CO., LTD. (China)
Inventor
  • Song, Yali
  • Zhao, Xiangnan
  • Cui, Ying

Abstract

A memory device includes a first deck including a first set of word lines, a second deck including a second set of word lines, and a controller. The controller is configured to apply a program voltage to a first word line of the first set of word lines, apply a first pass voltage to a second word line of the second set of word lines while applying the program voltage to the first word line, and apply a second pass voltage to a third word line of the first set of word lines while applying the program voltage to the first word line. The third word line is between the first word line and the second word line. The second pass voltage is greater than the first pass voltage.

IPC Classes  ?

  • G11C 16/34 - Determination of programming status, e.g. threshold voltage, overprogramming or underprogramming, retention
  • G11C 16/08 - Address circuits; Decoders; Word-line control circuits
  • G11C 16/10 - Programming or data input circuits

36.

THREE-DIMENSIONAL MEMORY DEVICES AND METHODS FOR FORMING THE SAME

      
Application Number 17983570
Status Pending
Filing Date 2022-11-09
First Publication Date 2024-03-21
Owner YANGTZE MEMORY TECHNOLOGIES CO., LTD. (China)
Inventor
  • Wu, Linchun
  • Wu, Shuangshuang
  • Li, Lei
  • Zhang, Kun
  • Xia, Zhiliang
  • Huo, Zongliang

Abstract

A three-dimensional (3D) memory device includes a stack structure including interleaved first conductive layers and first dielectric layers, and a channel structure extending through the stack structure along a first direction in contact with a first semiconductor layer at a bottom portion of the channel structure. The channel structure includes a semiconductor channel, and a memory film over the semiconductor channel. The semiconductor channel includes an angled structure, and a first width of the semiconductor channel at the bottom portion of the channel structure below the angled structure is smaller than a second width of the semiconductor channel at an upper portion of the channel structure above the angled structure.

IPC Classes  ?

  • H01L 27/11582 - Electrically programmable read-only memories; Multistep manufacturing processes therefor with charge-trapping gate insulators, e.g. MNOS or NROM characterised by three-dimensional arrangements, e.g. with cells on different height levels with source and drain on different levels, e.g. with sloping channels the channels comprising vertical portions, e.g. U-shaped channels

37.

THREE-DIMENSIONAL MEMORY DEVICE AND METHOD OF FORMING THE SAME

      
Application Number 17945703
Status Pending
Filing Date 2022-09-15
First Publication Date 2024-03-21
Owner Yangtze Memory Technologies Co., Ltd. (China)
Inventor
  • Gao, Tingting
  • Xia, Zhiliang
  • Liu, Xiaoxin
  • Du, Xiaolong
  • Sun, Changzhi
  • Liu, Jiayi
  • Huo, Zongliang

Abstract

According to an aspect of the disclosure, a semiconductor device is provided. The semiconductor device includes a stack structure that includes alternating insulating layers and word line layers. The semiconductor device also includes a first channel structure extending through the stack structure, a first top select gate (TSG) layer over the stack structure, and a second TSG layer over the first TSG layer. The semiconductor device further includes a second channel structure extending through the first and second TSG layers, where the second channel structure is positioned over and coupled to the first channel structure.

IPC Classes  ?

  • H01L 27/1157 - Electrically programmable read-only memories; Multistep manufacturing processes therefor with charge-trapping gate insulators, e.g. MNOS or NROM characterised by the memory core region with cell select transistors, e.g. NAND
  • H01L 27/11582 - Electrically programmable read-only memories; Multistep manufacturing processes therefor with charge-trapping gate insulators, e.g. MNOS or NROM characterised by three-dimensional arrangements, e.g. with cells on different height levels with source and drain on different levels, e.g. with sloping channels the channels comprising vertical portions, e.g. U-shaped channels

38.

Novel 3D NAND Memory Device And Method of Forming The Same

      
Application Number 18507574
Status Pending
Filing Date 2023-11-13
First Publication Date 2024-03-14
Owner Yangtze Memory Technologies Co., Ltd. (China)
Inventor
  • Song, Yali
  • Xiao, Li Hong
  • Wang, Ming

Abstract

A 3D-NAND memory device is provided. The memory device includes a substrate, a bottom select gate (BSG) disposed over the substrate, a plurality of word lines positioned over the BSG with a staircase configuration and a plurality of insulating layers disposed between the substrate, the BSG, and the plurality of word lines. In the disclosed memory device, one or more first dielectric trenches are formed in the BSG and extend in a length direction of the substrate to separate the BSG into a plurality of sub-BSGs. In addition, one or more common source regions are formed over the substrate and extend in the length direction of the substrate. The one or more common source regions further extend through the BSG, the plurality of word lines and the plurality of insulating layers.

IPC Classes  ?

  • H10B 43/27 - EEPROM devices comprising charge-trapping gate insulators characterised by three-dimensional arrangements, e.g. with cells on different height levels with source and drain on different levels, e.g. with sloping channels the channels comprising vertical portions, e.g. U-shaped channels
  • G11C 16/04 - Erasable programmable read-only memories electrically programmable using variable threshold transistors, e.g. FAMOS
  • G11C 16/14 - Circuits for erasing electrically, e.g. erase voltage switching circuits
  • H01L 21/311 - Etching the insulating layers
  • H01L 23/528 - Layout of the interconnection structure
  • H01L 29/08 - Semiconductor bodies characterised by the shapes, relative sizes, or dispositions of the semiconductor regions with semiconductor regions connected to an electrode carrying current to be rectified, amplified, or switched and such electrode being part of a semiconductor device which comprises three or more electrodes
  • H01L 29/10 - Semiconductor bodies characterised by the shapes, relative sizes, or dispositions of the semiconductor regions with semiconductor regions connected to an electrode not carrying current to be rectified, amplified, or switched and such electrode being part of a semiconductor device which comprises three or more electrodes
  • H10B 43/10 - EEPROM devices comprising charge-trapping gate insulators characterised by the top-view layout
  • H10B 43/35 - EEPROM devices comprising charge-trapping gate insulators characterised by the memory core region with cell select transistors, e.g. NAND

39.

THREE-DIMENSIONAL MEMORY DEVICE HAVING SOURCE-SELECT-GATE CUT STRUCTURES AND METHODS FOR FORMING THE SAME

      
Application Number 18518798
Status Pending
Filing Date 2023-11-24
First Publication Date 2024-03-14
Owner YANGTZE MEMORY TECHNOLOGIES CO., LTD. (China)
Inventor Zhang, Zhong

Abstract

A three-dimensional (3D) memory device includes a memory stack including a memory block. The memory block includes a memory array structures and a staircase structure in a first lateral direction, and fingers in a second lateral direction perpendicular to the first lateral direction. The fingers include a first finger and a second finger. The 3D memory device also includes a source-select-gate (SSG) cut structure extending through a portion of the memory stack and between the first finger and the second finger. The staircase structure includes a first staircase connected to first memory cells in the first finger and a second staircase connected to second memory cells in the second finger.

IPC Classes  ?

  • H10B 43/35 - EEPROM devices comprising charge-trapping gate insulators characterised by the memory core region with cell select transistors, e.g. NAND
  • H01L 23/522 - Arrangements for conducting electric current within the device in operation from one component to another including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
  • H01L 23/528 - Layout of the interconnection structure
  • H10B 41/27 - Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates characterised by three-dimensional arrangements, e.g. with cells on different height levels with source and drain on different levels, e.g. with sloping channels the channels comprising vertical portions, e.g. U-shaped channels
  • H10B 41/35 - Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates characterised by the memory core region with a cell select transistor, e.g. NAND
  • H10B 43/27 - EEPROM devices comprising charge-trapping gate insulators characterised by three-dimensional arrangements, e.g. with cells on different height levels with source and drain on different levels, e.g. with sloping channels the channels comprising vertical portions, e.g. U-shaped channels

40.

3D NAND MEMORY DEVICE AND CONTROL METHOD THEREOF

      
Application Number 17931764
Status Pending
Filing Date 2022-09-13
First Publication Date 2024-03-14
Owner YANGTZE MEMORY TECHNOLOGIES., LTD. (China)
Inventor
  • Dong, Zhipeng
  • Liang, Ke
  • Qiao, Liang

Abstract

The present disclosure provides a method for controlling a 3D NAND memory using a read operation. The method can include increasing a voltage to a plurality of top select gates, with respect to a first reference voltage level, during a pre-pulse period of the read operation prior to a read period of the read operation. The method can also include increasing a voltage to a plurality of word lines, with respect to a second reference voltage level, during the pre-pulse period. The method can also include decreasing a voltage to a bit line, with respect to the first voltage, during the pre-pulse period. The method can also include applying no voltage change to a bottom select gate during the pre-pulse period.

IPC Classes  ?

  • G11C 16/26 - Sensing or reading circuits; Data output circuits
  • G11C 16/08 - Address circuits; Decoders; Word-line control circuits
  • G11C 16/24 - Bit-line control circuits
  • G11C 16/30 - Power supply circuits

41.

MEMORY DEVICE, OPERATING METHOD THEREOF, SYSTEM, AND STORAGE MEDIUM

      
Application Number CN2022117280
Publication Number 2024/050689
Status In Force
Filing Date 2022-09-06
Publication Date 2024-03-14
Owner YANGTZE MEMORY TECHNOLOGIES CO., LTD. (China)
Inventor
  • Dong, Zhipeng
  • Cui, Ying
  • Xiang, Li

Abstract

A memory device, an operating method thereof, a system, and a non-transitory tangible storage medium are disclosed. The memory device includes a source line (SL), a bit line (BL), a memory string, a word line, a select line and a peripheral circuit. The memory string includes a memory cell and a select transistor including a storage layer. The word line is coupled to the memory cell. The select line is coupled to the select transistor. The peripheral circuit is coupled to the SL, the BL, the select line, and the word line. The peripheral circuit is configured to: apply a first voltage to the select line; and apply a second voltage to the SL and/or the BL, in which a first peak level of the first voltage is greater than a second peak level of second voltage.

IPC Classes  ?

  • G11C 16/20 - Initialising; Data preset; Chip identification
  • G11C 16/12 - Programming voltage switching circuits
  • G11C 16/34 - Determination of programming status, e.g. threshold voltage, overprogramming or underprogramming, retention

42.

METHOD OF CONTROLLING MEMORY, MEMORY AND MEMORY SYSTEM

      
Application Number 18238181
Status Pending
Filing Date 2023-08-25
First Publication Date 2024-03-07
Owner YANGTZE MEMORY TECHNOLOGIES CO., LTD. (China)
Inventor Li, Jianjie

Abstract

According to one aspect of the present disclosure, a method of controlling a memory is provided. The method may include performing a read operation based on a read voltage corresponding to a target logical page to obtain a hard read value and a soft read value of the target logical page. The method may include storing the hard read value, the soft read value, and inhibition information into three latches in a page buffer respectively. The method may include obtaining hard data of the target logical page based on the hard read value of the target logical page. The method may include obtaining soft data of the target logical page based on the hard data and the soft read value of the target logical page. The memory may include a plurality of memory cells, each configured to store N-bit data, where N is an integer greater than 1.

IPC Classes  ?

  • G06F 3/06 - Digital input from, or digital output to, record carriers

43.

NON-VOLATILE MEMORY DEVICE AND CONTROL METHOD

      
Application Number 18387204
Status Pending
Filing Date 2023-11-06
First Publication Date 2024-03-07
Owner YANGTZE MEMORY TECHNOLOGIES CO., LTD. (China)
Inventor
  • Jia, Jianquan
  • Cui, Ying
  • You, Kaikai

Abstract

A non-volatile memory device includes a memory string, a select gate line coupled to the memory string, word lines coupled to the memory string and including a selected word line, and a control circuit coupled to the select gate line and the word lines, and configured to apply word line pre-pulse signals to at least two groups of the word lines disposed between the select gate line and the selected word line during a pre-charge period. The at least two groups of the word lines include a first group and a second group disposed between the first group and the select gate line. A voltage level of a second word line pre-pulse signal applied to the second group is greater than a voltage level of a first word line pre-pulse signal applied to the first group. A voltage level of at least one word line pre-pulse signal of the word line pre-pulse signals is greater than 0.

IPC Classes  ?

  • G11C 11/408 - Address circuits
  • G11C 11/4074 - Power supply or voltage generation circuits, e.g. bias voltage generators, substrate voltage generators, back-up power, power control circuits
  • G11C 11/4094 - Bit-line management or control circuits
  • G11C 11/4099 - Dummy cell treatment; Reference voltage generators
  • G11C 11/419 - Read-write [R-W] circuits

44.

INPUT/OUTPUT REFERENCE VOLTAGE TRAINING METHOD IN THREE-DIMENSIONAL MEMORY DEVICES

      
Application Number 17929450
Status Pending
Filing Date 2022-09-02
First Publication Date 2024-03-07
Owner YANGTZE MEMORY TECHNOLOGIES CO., LTD. (China)
Inventor
  • Yang, Shiyang
  • Deng, Chunfei
  • Lu, Yan
  • Ding, Ling
  • Fu, Xiang

Abstract

Methods for input/output voltage training of a three-dimensional (3D) memory device is disclosed. The method can comprise the following operations: (1) setting a reference voltage value at an on-die termination (ODT) enabled status; (2) controlling the 3D memory device to perform a write training process; (3) determining whether a further write training process is needed; (4) in response to determining that the further write training process is needed, repeating operations (1), (2) and (3); and (5) in response to determining that the further write training process is not needed, setting the reference voltage value as an optimized reference voltage value.

IPC Classes  ?

  • G11C 11/56 - Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using storage elements with more than two stable states represented by steps, e.g. of voltage, current, phase, frequency
  • G11C 5/04 - Supports for storage elements; Mounting or fixing of storage elements on such supports

45.

MEMORY DEVICE, OPERATING METHOD THEREOF, SYSTEM, AND STORAGE MEDIUM

      
Application Number 17951794
Status Pending
Filing Date 2022-09-23
First Publication Date 2024-03-07
Owner YANGTZE MEMORY TECHNOLOGIES CO., LTD. (China)
Inventor
  • Dong, Zhipeng
  • Cui, Ying
  • Xiang, Li

Abstract

A memory device, an operating method thereof, a system, and a non-transitory tangible storage medium are disclosed. The memory device includes a source line (SL), a bit line (BL), a memory string, a word line, a select line and a peripheral circuit. The memory string includes a memory cell and a select transistor including a storage layer. The word line is coupled to the memory cell. The select line is coupled to the select transistor. The peripheral circuit is coupled to the SL, the BL, the select line, and the word line. The peripheral circuit is configured to: apply a first voltage to the select line; and apply a second voltage to the SL and/or the BL, in which a first peak level of the first voltage is greater than a second peak level of second voltage.

IPC Classes  ?

  • G11C 16/04 - Erasable programmable read-only memories electrically programmable using variable threshold transistors, e.g. FAMOS
  • G11C 16/08 - Address circuits; Decoders; Word-line control circuits
  • G11C 16/14 - Circuits for erasing electrically, e.g. erase voltage switching circuits

46.

THREE-DIMENSIONAL MEMORY DEVICE AND METHOD OF FORMING THE SAME

      
Application Number 17901195
Status Pending
Filing Date 2022-09-01
First Publication Date 2024-03-07
Owner Yangtze Memory Technologies Co., Ltd. (China)
Inventor
  • Gao, Tingting
  • Xia, Zhiliang
  • Huo, Zongliang

Abstract

According to an aspect of the disclosure, a semiconductor device is provided. The semiconductor device includes a stack structure of alternating insulating layers and word line layers, a first top select gate (TSG) layer over the stack structure, and a separation structure extending through the first TSG layer, where the first TSG layer is divided by the separation structure into a first sub TSG layer and a second sub TSG layer. The semiconductor device includes a conductive layer positioned between the first sub TSG layer and the separation structure, and between the second sub TSG layer and the separation structure.

IPC Classes  ?

  • H01L 27/1157 - Electrically programmable read-only memories; Multistep manufacturing processes therefor with charge-trapping gate insulators, e.g. MNOS or NROM characterised by the memory core region with cell select transistors, e.g. NAND
  • H01L 27/11582 - Electrically programmable read-only memories; Multistep manufacturing processes therefor with charge-trapping gate insulators, e.g. MNOS or NROM characterised by three-dimensional arrangements, e.g. with cells on different height levels with source and drain on different levels, e.g. with sloping channels the channels comprising vertical portions, e.g. U-shaped channels

47.

SEMICONDUCTOR DEVICE AND FABRICATION METHOD THEREFOR

      
Application Number 17901240
Status Pending
Filing Date 2022-09-01
First Publication Date 2024-03-07
Owner Yangtze Memory Technologies Co., Ltd. (China)
Inventor
  • Guo, Zhen
  • Xu, Wei
  • Yuan, Bin
  • Ma, Chuang
  • Zhang, Jiashi
  • Huo, Zongliang

Abstract

Aspects of the disclosure provide a semiconductor device. The semiconductor device includes a memory stack of gate layers and insulating layers. The gate layers and the insulating layers are stacked alternatingly and are formed into stair steps in a staircase region. The semiconductor device includes a first landing pad on a first gate layer of a first stair step. The first gate layer is a top gate layer of the first stair step. The semiconductor device further includes a first sidewall isolation structure on a riser sidewall of a second gate layer of a second stair step. The second gate layer is a top gate layer of the second stair step and is stacked on the first gate layer in the memory stack. The first sidewall isolation structure isolates the second gate layer from the first landing pad.

IPC Classes  ?

  • H01L 27/11556 - Electrically programmable read-only memories; Multistep manufacturing processes therefor with floating gate characterised by three-dimensional arrangements, e.g. with cells on different height levels with source and drain on different levels, e.g. with sloping channels the channels comprising vertical portions, e.g. U-shaped channels
  • G11C 16/04 - Erasable programmable read-only memories electrically programmable using variable threshold transistors, e.g. FAMOS
  • H01L 25/065 - Assemblies consisting of a plurality of individual semiconductor or other solid state devices all the devices being of a type provided for in the same subgroup of groups , or in a single subclass of , , e.g. assemblies of rectifier diodes the devices not having separate containers the devices being of a type provided for in group
  • H01L 27/11524 - Electrically programmable read-only memories; Multistep manufacturing processes therefor with floating gate characterised by the memory core region with cell select transistors, e.g. NAND
  • H01L 27/1157 - Electrically programmable read-only memories; Multistep manufacturing processes therefor with charge-trapping gate insulators, e.g. MNOS or NROM characterised by the memory core region with cell select transistors, e.g. NAND
  • H01L 27/11582 - Electrically programmable read-only memories; Multistep manufacturing processes therefor with charge-trapping gate insulators, e.g. MNOS or NROM characterised by three-dimensional arrangements, e.g. with cells on different height levels with source and drain on different levels, e.g. with sloping channels the channels comprising vertical portions, e.g. U-shaped channels

48.

MEMORY DEVICES AND METHODS FOR FORMING THE SAME

      
Application Number 18237291
Status Pending
Filing Date 2023-08-23
First Publication Date 2024-02-29
Owner YANGTZE MEMORY TECHNOLOGIES CO., LTD. (China)
Inventor
  • Liu, Zichen
  • Liu, Wei

Abstract

A memory device includes an array of memory cells, bit lines coupled to the memory cells, first air gaps, and second air gaps. Each of the memory cells includes a vertical transistor. The vertical transistor includes a semiconductor body extending in a first direction. Each of the bit lines is connected to a first end of the semiconductor body. At least one of the first air gaps is between adjacent bit lines. At least one of the second air gaps is between adjacent semiconductor bodies of adjacent memory cells.

IPC Classes  ?

  • H10B 12/00 - Dynamic random access memory [DRAM] devices

49.

THREE-DIMENSIONAL NAND MEMORY DEVICE AND METHOD OF FORMING THE SAME

      
Application Number 17896687
Status Pending
Filing Date 2022-08-26
First Publication Date 2024-02-29
Owner Yangtze Memory Technologies Co., Ltd. (China)
Inventor
  • Liu, Shasha
  • Mao, Xiaoming
  • Gao, Jing
  • Huo, Zongliang

Abstract

A semiconductor device includes a first stack of alternating first word line layers and first insulating layers over a semiconductor layer. A first channel structure extends from the semiconductor layer and through a first array region of the first stack. A second stack of alternating second word line layers and second insulating layers are over the first stack. A second channel structure extends from the first channel structure and through a second array region of the second stack. A thickness of a particular first insulating layer, which is positioned closest to the second stack relative to other first insulating layers, is a sum of at least two times an average thickness of the other first insulating layers and at least one time an average thickness of the first word line layers in the first array region.

IPC Classes  ?

  • H01L 27/11578 - Electrically programmable read-only memories; Multistep manufacturing processes therefor with charge-trapping gate insulators, e.g. MNOS or NROM characterised by three-dimensional arrangements, e.g. with cells on different height levels
  • G11C 8/14 - Word line organisation; Word line lay-out
  • G11C 16/08 - Address circuits; Decoders; Word-line control circuits

50.

THREE-DIMENSIONAL NAND MEMORY DEVICE AND METHOD OF FORMING THE SAME

      
Application Number 17896731
Status Pending
Filing Date 2022-08-26
First Publication Date 2024-02-29
Owner Yangtze Memory Technologies Co., Ltd. (China)
Inventor
  • Liu, Shasha
  • Zhang, Tianhui
  • Yang, Min
  • Mao, Xiaoming
  • Huo, Zongliang

Abstract

A semiconductor device includes a first stack of alternating first word line layers and first insulating layers over a semiconductor layer. The first stack includes a first array region and a first staircase region adjacent to the first array region. The semiconductor device includes a second stack of alternating second word line layers and second insulating layers, where the second stack includes a second array region over the first array region and a second staircase region adjacent to the second array region and over the first staircase region. The first stack further includes a first transition layer over the first word line layers. The first transition layer includes a first dielectric portion in the first array region that surrounds the first channel structure and a first conductive portion. The first transition layer is disposed between two adjacent first insulating layers of the first insulating layers.

IPC Classes  ?

  • H01L 27/11582 - Electrically programmable read-only memories; Multistep manufacturing processes therefor with charge-trapping gate insulators, e.g. MNOS or NROM characterised by three-dimensional arrangements, e.g. with cells on different height levels with source and drain on different levels, e.g. with sloping channels the channels comprising vertical portions, e.g. U-shaped channels

51.

VERTICAL MEMORY DEVICES

      
Application Number 18503430
Status Pending
Filing Date 2023-11-07
First Publication Date 2024-02-29
Owner Yangtze Memory Technologies Co., Ltd. (China)
Inventor
  • Zhang, Zhong
  • Zhou, Wenxi
  • Xia, Zhiliang

Abstract

In a semiconductor device, a stack of alternating gate layers and insulating layers is formed. Channel structures are formed in an array region of the stack. A first staircase is formed at a first section of the stack. A second staircase is formed at a second section of the stack. A dummy staircase is formed at the first section and disposed between the first staircase and the second staircase. The dummy staircase includes dummy group stair steps descending in a second direction parallel to a plane defined by any one of the gate layers and the insulating layers, and dummy division stair steps descending in a third direction and a fourth direction parallel to the plane and perpendicular to the second direction. The third direction and the fourth direction are opposite to each other.

IPC Classes  ?

  • H10B 43/27 - EEPROM devices comprising charge-trapping gate insulators characterised by three-dimensional arrangements, e.g. with cells on different height levels with source and drain on different levels, e.g. with sloping channels the channels comprising vertical portions, e.g. U-shaped channels
  • H01L 21/768 - Applying interconnections to be used for carrying current between separate components within a device
  • H01L 23/522 - Arrangements for conducting electric current within the device in operation from one component to another including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
  • H01L 23/528 - Layout of the interconnection structure
  • H01L 29/66 - Types of semiconductor device
  • H10B 41/27 - Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates characterised by three-dimensional arrangements, e.g. with cells on different height levels with source and drain on different levels, e.g. with sloping channels the channels comprising vertical portions, e.g. U-shaped channels
  • H10B 41/35 - Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates characterised by the memory core region with a cell select transistor, e.g. NAND
  • H10B 43/35 - EEPROM devices comprising charge-trapping gate insulators characterised by the memory core region with cell select transistors, e.g. NAND

52.

OPEN BLOCK-BASED READ OFFSET COMPENSATION IN READ OPERATION OF MEMORY DEVICE

      
Application Number 18387780
Status Pending
Filing Date 2023-11-07
First Publication Date 2024-02-29
Owner YANGTZE MEMORY TECHNOLOGIES CO., LTD. (China)
Inventor
  • Guo, Xiaojiang
  • Kang, Jong Hoon
  • He, Youxin

Abstract

Open block-based read offset compensation in read operation of memory device is disclosed. For example, a memory device includes an array of memory cells arranged in a plurality of blocks and a peripheral circuit coupled to the array of memory cells. The peripheral circuit is configured to determine that a block of the blocks is an open block based on an open block information, and in response to the block of the blocks being an open block, perform a read operation on a memory cell of the array of memory cells in the block using a compensated read voltage. The compensated read voltage has an offset from a default read voltage of the block.

IPC Classes  ?

  • G11C 16/10 - Programming or data input circuits
  • G11C 16/08 - Address circuits; Decoders; Word-line control circuits
  • G11C 16/26 - Sensing or reading circuits; Data output circuits
  • G11C 16/30 - Power supply circuits

53.

THREE-DIMENSIONAL MEMORY DEVICES AND METHODS FOR FORMING THE SAME

      
Application Number 17896959
Status Pending
Filing Date 2022-08-26
First Publication Date 2024-02-29
Owner YANGTZE MEMORY TECHNOLOGIES CO., LTD. (China)
Inventor
  • Wu, Linchun
  • Zhang, Kun
  • Zhou, Wenxi
  • Kong, Cuicui
  • Wu, Shuangshuang
  • Xia, Zhiliang
  • Huo, Zongliang

Abstract

A memory device includes a stack structure, channel structures, and a slit structure. The stack structure includes interleaved conductive layers and dielectric layers, and the conductive layers include a plurality of word lines. Each of the channel structures extends vertically through the stack structure. The slit structure extends vertically through the stack structure. An outer region of the stack structure includes a staircase structure, and the interleaved conductive layers and dielectric layers in a bottom portion of the stack structure are wider than the interleaved conductive layers and dielectric layers in a top portion of the stack structure. A first outer width of the slit structure in the bottom portion of the stack structure is greater than a second outer width of the slit structure in the top portion of the stack structure.

IPC Classes  ?

  • H01L 27/11582 - Electrically programmable read-only memories; Multistep manufacturing processes therefor with charge-trapping gate insulators, e.g. MNOS or NROM characterised by three-dimensional arrangements, e.g. with cells on different height levels with source and drain on different levels, e.g. with sloping channels the channels comprising vertical portions, e.g. U-shaped channels
  • H01L 23/528 - Layout of the interconnection structure
  • H01L 27/11519 - Electrically programmable read-only memories; Multistep manufacturing processes therefor with floating gate characterised by the top-view layout
  • H01L 27/11556 - Electrically programmable read-only memories; Multistep manufacturing processes therefor with floating gate characterised by three-dimensional arrangements, e.g. with cells on different height levels with source and drain on different levels, e.g. with sloping channels the channels comprising vertical portions, e.g. U-shaped channels
  • H01L 27/11565 - Electrically programmable read-only memories; Multistep manufacturing processes therefor with charge-trapping gate insulators, e.g. MNOS or NROM characterised by the top-view layout

54.

METHOD AND MEMORY USED FOR REDUCING PROGRAM DISTURBANCE BY ADJUSTING VOLTAGE OF DUMMY WORD LINE

      
Application Number 18385642
Status Pending
Filing Date 2023-10-31
First Publication Date 2024-02-22
Owner YANGTZE MEMORY TECHNOLOGIES CO., LTD. (China)
Inventor
  • Song, Yali
  • Ji, Jianquan
  • You, Kaikai
  • Zhang, An
  • Zhao, Xiangnan
  • Cui, Ying
  • Li, Shan
  • Li, Kaiwei
  • Jin, Lei
  • Huang, Xueqing
  • Lou, Meng
  • Zhang, Jinlong

Abstract

A method for operating a memory device is disclosed. The memory device includes a first word line, a second word line, a first dummy word line, and a second dummy word line. The first dummy word line and the second dummy word line are between the first word line and the second word line. A first pass voltage is applied to the first dummy word line in a program operation. A second pass voltage is applied to the second dummy word line in the program operation. The first pass voltage is different from the second pass voltage.

IPC Classes  ?

  • G11C 16/34 - Determination of programming status, e.g. threshold voltage, overprogramming or underprogramming, retention
  • G11C 16/04 - Erasable programmable read-only memories electrically programmable using variable threshold transistors, e.g. FAMOS

55.

READ RETRY METHOD FOR ENHANCING READ PERFORMANCE AND STABILITY OF 3D NAND MEMORY

      
Application Number 17889212
Status Pending
Filing Date 2022-08-16
First Publication Date 2024-02-22
Owner Yangtze Memory Technologies Co., Ltd. (China)
Inventor
  • Ye, Guangchang
  • Guo, Lu
  • Huo, Zhongchen

Abstract

The present disclosure provides a memory system for selecting from among a plurality of read retry routines based on metadata. The memory system can include one or more memory devices and a memory controller. The memory controller can also detect a failure of a read operation. The memory controller can also analyze a set of values that correspond to a set of effectors of the read operation. The memory controller can select one or more read retry routines from a plurality of read retry routines based on the analyzing. Each of the plurality of read retry routines can associated with a different effector from the set of effectors and a read voltage that corresponds to the different effector. The memory controller can also perform the selected one or more read retry routines at the portion of the one or more memory devices to negate the failure of the read operation.

IPC Classes  ?

  • G06F 3/06 - Digital input from, or digital output to, record carriers

56.

METHODS FOR FABRICATING A LAYERED SEMICONDUCTOR STRUCTURE FOR NAND MEMORY DEVICES

      
Application Number 17889216
Status Pending
Filing Date 2022-08-16
First Publication Date 2024-02-22
Owner Yangtze Memory Technologies Co., Ltd. (China)
Inventor
  • Li, Qian
  • Wu, Shu
  • Xiao, Liang
  • Li, Lei
  • Pu, Hao

Abstract

The present disclosure provides a fabrication method to produce a semiconductor structure with increased reliability for use in NAND memory devices. The method can include forming a layered semiconductor structure that includes a first layer, a second layer disposed on the first layer, and a third layer disposed on the second layer. The method can also include forming a channel structure, which can include etching the first layer, the second layer, and the third layer to form an opening through a surface of the semiconductor structure. A portion of the third layer can be exposed at the opening. The forming of the channel structure also include oxidizing the exposed portion of the third layer to form silicon oxide expand the exposed portion of the third layer.

IPC Classes  ?

  • H01L 27/11582 - Electrically programmable read-only memories; Multistep manufacturing processes therefor with charge-trapping gate insulators, e.g. MNOS or NROM characterised by three-dimensional arrangements, e.g. with cells on different height levels with source and drain on different levels, e.g. with sloping channels the channels comprising vertical portions, e.g. U-shaped channels
  • G11C 16/04 - Erasable programmable read-only memories electrically programmable using variable threshold transistors, e.g. FAMOS
  • H01L 27/11556 - Electrically programmable read-only memories; Multistep manufacturing processes therefor with floating gate characterised by three-dimensional arrangements, e.g. with cells on different height levels with source and drain on different levels, e.g. with sloping channels the channels comprising vertical portions, e.g. U-shaped channels
  • H01L 27/1157 - Electrically programmable read-only memories; Multistep manufacturing processes therefor with charge-trapping gate insulators, e.g. MNOS or NROM characterised by the memory core region with cell select transistors, e.g. NAND
  • H01L 27/11524 - Electrically programmable read-only memories; Multistep manufacturing processes therefor with floating gate characterised by the memory core region with cell select transistors, e.g. NAND

57.

MEMORY DEVICE AND READ OPERATION DURING SUSPENSION OF PROGRAM OPERATION THEREOF

      
Application Number 17891068
Status Pending
Filing Date 2022-08-18
First Publication Date 2024-02-22
Owner YANGTZE MEMORY TECHNOLOGIES CO., LTD. (China)
Inventor
  • Deng, Jialiang
  • Li, Bo
  • Duan, Zhuqin
  • Shi, Lei

Abstract

In certain aspects, a memory device includes an array of memory cells, including a first memory cell and a second memory cell, and a peripheral circuit. The peripheral circuit includes a page buffer circuit and control logic. The control logic is configured to suspend a program operation on the first memory cell responsive to receiving a suspension command indicative of executing a read operation on the second memory cell, control the page buffer circuit to release a sensing storage unit and a cache storage unit of the page buffer circuit from being occupied by a suspension of the program operation through a usage of a dynamic storage unit of the page buffer circuit during the suspension of the program operation, and initiate a read operation on the second memory cell using the sensing storage unit and the cache storage unit.

IPC Classes  ?

  • G11C 16/10 - Programming or data input circuits
  • G11C 16/24 - Bit-line control circuits
  • G11C 16/26 - Sensing or reading circuits; Data output circuits

58.

THREE-DIMENSIONAL MEMORY DEVICES, SYSTEMS, AND METHODS FOR FORMING THE SAME

      
Application Number 17891055
Status Pending
Filing Date 2022-08-18
First Publication Date 2024-02-22
Owner YANGTZE MEMORY TECHNOLOGIES CO., LTD. (China)
Inventor
  • Xie, Jingtao
  • Yan, Bingjie
  • Zhang, Kun
  • Zhou, Wenxi
  • Xia, Zhiliang
  • Huo, Zongliang

Abstract

A three-dimensional (3D) memory device includes a stack, a plurality of contact structures, and a plurality of support structures. The stack in an insulating structure includes a plurality of conductive layers and a plurality of dielectric layers stacked alternatingly, and the stack includes a staircase structure. The plurality of contact structures each extends through the insulating structure and in contact with a respective conductive layer of the plurality of conductive layers in the staircase structure. The plurality of support structures extends through the stack in the staircase structure. Each support structure is in contact with one of the plurality of contact structures.

IPC Classes  ?

  • H01L 27/11582 - Electrically programmable read-only memories; Multistep manufacturing processes therefor with charge-trapping gate insulators, e.g. MNOS or NROM characterised by three-dimensional arrangements, e.g. with cells on different height levels with source and drain on different levels, e.g. with sloping channels the channels comprising vertical portions, e.g. U-shaped channels
  • H01L 27/11556 - Electrically programmable read-only memories; Multistep manufacturing processes therefor with floating gate characterised by three-dimensional arrangements, e.g. with cells on different height levels with source and drain on different levels, e.g. with sloping channels the channels comprising vertical portions, e.g. U-shaped channels

59.

THREE-DIMENSIONAL MEMORY DEVICES, SYSTEMS, AND METHODS FOR FORMING THE SAME

      
Application Number 17891064
Status Pending
Filing Date 2022-08-18
First Publication Date 2024-02-22
Owner YANGTZE MEMORY TECHNOLOGIES CO., LTD. (China)
Inventor
  • Xie, Jingtao
  • Yan, Bingjie
  • Zhang, Kun
  • Zhou, Wenxi
  • Xia, Zhiliang
  • Huo, Zongliang

Abstract

A three-dimensional (3D) memory device includes a stack, a plurality of contact structures, and a plurality of support structures. The stack in an insulating structure includes conductive layers and dielectric layers stacked alternatingly, and the stack includes a staircase structure. Each contact structure extends through the insulating structure and is in contact with a respective conductive layer in the staircase structure. The support structures extend through the stack in the staircase structure. The contact structures are arranged in a first row and a second row, the first row of contact structures is in electrical contact with the peripheral device, and the second row of contact structures is in electrical insulation with the peripheral device.

IPC Classes  ?

  • H01L 23/00 - SEMICONDUCTOR DEVICES NOT COVERED BY CLASS - Details of semiconductor or other solid state devices
  • H01L 23/535 - Arrangements for conducting electric current within the device in operation from one component to another including internal interconnections, e.g. cross-under constructions
  • H01L 27/11556 - Electrically programmable read-only memories; Multistep manufacturing processes therefor with floating gate characterised by three-dimensional arrangements, e.g. with cells on different height levels with source and drain on different levels, e.g. with sloping channels the channels comprising vertical portions, e.g. U-shaped channels
  • H01L 27/11582 - Electrically programmable read-only memories; Multistep manufacturing processes therefor with charge-trapping gate insulators, e.g. MNOS or NROM characterised by three-dimensional arrangements, e.g. with cells on different height levels with source and drain on different levels, e.g. with sloping channels the channels comprising vertical portions, e.g. U-shaped channels

60.

MEMORY DEVICE AND READ OPERATION DURING SUSPENSION OF PROGRAM OPERATION THEREOF

      
Application Number 17891065
Status Pending
Filing Date 2022-08-18
First Publication Date 2024-02-22
Owner YANGTZE MEMORY TECHNOLOGIES CO., LTD. (China)
Inventor Deng, Jialiang

Abstract

In certain aspects, a memory device includes an array of memory cells, including a first memory cell and a second memory cell, and a peripheral circuit. The peripheral circuit includes a page buffer circuit and control logic. The control logic is configured to suspend a program operation on the first memory cell responsive to receiving a suspension command, control the page buffer circuit to store suspended program information associated with a suspension of the program operation, control the page buffer circuit to release a sensing storage unit and a cache storage unit of the page buffer circuit from being occupied by the suspension of the program operation through a storage of a piece of program information from the suspended program information in a memory controller, and initiate a read operation on the second memory cell using the sensing storage unit and the cache storage unit.

IPC Classes  ?

  • G11C 16/26 - Sensing or reading circuits; Data output circuits
  • G11C 16/04 - Erasable programmable read-only memories electrically programmable using variable threshold transistors, e.g. FAMOS
  • G11C 16/10 - Programming or data input circuits
  • G11C 16/24 - Bit-line control circuits
  • G11C 11/56 - Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using storage elements with more than two stable states represented by steps, e.g. of voltage, current, phase, frequency

61.

MEMORY DEVICE AND READ OPERATION DURING SUSPENSION OF PROGRAM OPERATION THEREOF

      
Application Number 17891072
Status Pending
Filing Date 2022-08-18
First Publication Date 2024-02-22
Owner YANGTZE MEMORY TECHNOLOGIES CO., LTD. (China)
Inventor
  • Shi, Lei
  • Duan, Zhuqin
  • Deng, Jialiang

Abstract

In certain aspects, a memory device includes an array of memory cells and a peripheral circuit. The array of memory cells includes a first memory cell and a second memory cell. The peripheral circuit includes a page buffer circuit and control logic. The page buffer circuit is coupled to the first and second memory cells, respectively, and includes a sense out (SO) node and a cache storage unit. The control logic is coupled to the page buffer and configured to suspend a program operation on the first memory cell responsive to receiving a suspension command indicative of executing a read operation on the second memory cell. The control logic is further configured to control the page buffer circuit to store suspended program information associated with a suspension of the program operation, and initiate the read operation on the second memory cell through the SO node and the cache storage unit.

IPC Classes  ?

  • G11C 16/26 - Sensing or reading circuits; Data output circuits
  • G11C 16/04 - Erasable programmable read-only memories electrically programmable using variable threshold transistors, e.g. FAMOS
  • G11C 16/10 - Programming or data input circuits
  • G11C 16/24 - Bit-line control circuits
  • G11C 11/56 - Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using storage elements with more than two stable states represented by steps, e.g. of voltage, current, phase, frequency

62.

SEMICONDUCTOR DEVICE AND FABRICATION METHOD THEREFOR

      
Application Number 17887071
Status Pending
Filing Date 2022-08-12
First Publication Date 2024-02-15
Owner Yangtze Memory Technologies Co., Ltd. (China)
Inventor
  • Guo, Zhen
  • Xu, Wei
  • Yuan, Bin
  • Jiang, Li
  • Huo, Zongliang

Abstract

Aspects of the disclosure provide a semiconductor device. The semiconductor device includes a memory stack of gate layers and insulating layers. The gate layers and the insulating layers are stacked alternatingly and are formed into stair steps in a staircase region. Further, the semiconductor device includes a landing stack formed on the stair steps in the staircase region. The landing stack includes an upper layer that is etch selective to a contact isolation layer that covers the staircase region. Then, the semiconductor device includes a first contact structure on a first stair step of the stair steps. The first contact structure extends through a first contact hole in the contact isolation layer and the landing stack. The first contact structure is connected with a first gate layer (e.g., a top gate layer) of the first stair step.

IPC Classes  ?

  • H01L 27/11556 - Electrically programmable read-only memories; Multistep manufacturing processes therefor with floating gate characterised by three-dimensional arrangements, e.g. with cells on different height levels with source and drain on different levels, e.g. with sloping channels the channels comprising vertical portions, e.g. U-shaped channels
  • H01L 27/11524 - Electrically programmable read-only memories; Multistep manufacturing processes therefor with floating gate characterised by the memory core region with cell select transistors, e.g. NAND
  • H01L 27/1157 - Electrically programmable read-only memories; Multistep manufacturing processes therefor with charge-trapping gate insulators, e.g. MNOS or NROM characterised by the memory core region with cell select transistors, e.g. NAND
  • H01L 27/11582 - Electrically programmable read-only memories; Multistep manufacturing processes therefor with charge-trapping gate insulators, e.g. MNOS or NROM characterised by three-dimensional arrangements, e.g. with cells on different height levels with source and drain on different levels, e.g. with sloping channels the channels comprising vertical portions, e.g. U-shaped channels

63.

MEMORY DEVICES AND METHODS FOR FORMING THE SAME

      
Application Number 18231742
Status Pending
Filing Date 2023-08-08
First Publication Date 2024-02-15
Owner YANGTZE MEMORY TECHNOLOGIES CO., LTD. (China)
Inventor
  • Wang, Yanhong
  • Liu, Wei
  • Liu, Yaqin
  • Huang, Shiqi
  • Chen, Liang

Abstract

A memory device includes a memory array structure, a first peripheral circuit, and a second peripheral circuit. The memory array structure includes a vertical transistor having a first terminal and a second terminal, a storage unit having a first end coupled to the first terminal of the vertical transistor, and a bit line coupled to the second terminal of the vertical transistor. The first peripheral circuit is disposed at one side of the memory array structure and includes a first side in contact with the memory array structure and a second side opposite to the first side in a first direction. The second peripheral circuit is disposed in contact with the second side of the first peripheral circuit away from the memory array structure.

IPC Classes  ?

  • H10B 12/00 - Dynamic random access memory [DRAM] devices
  • G11C 11/408 - Address circuits
  • G11C 11/4091 - Sense or sense/refresh amplifiers, or associated sense circuitry, e.g. for coupled bit-line precharging, equalising or isolating
  • H10B 63/10 - Phase change RAM [PCRAM, PRAM] devices

64.

CONTACT STRUCTURE AND METHOD OF FORMING THE SAME

      
Application Number 17887997
Status Pending
Filing Date 2022-08-15
First Publication Date 2024-02-15
Owner Yangtze Memory Technologies Co., Ltd. (China)
Inventor
  • Guo, Zhen
  • Xue, Lei
  • Xu, Wei
  • Yuan, Bin
  • Huo, Zongliang

Abstract

Aspects of the disclosure provide a semiconductor device. The semiconductor device includes a memory stack of gate layers and insulating layers, a landing structure and a contact structure. The gate layers and the insulating layers are stacked alternatingly, and form stair steps in a staircase region. The landing structure is disposed on a first gate layer of a first stair step of the stair steps in the staircase region. The landing structure includes an upper structure and an isolation stack between the upper structure and the first gate layer. The upper structure is etch-selective to a contact isolation layer that covers the staircase region. The contact structure extends through the contact isolation layer and the landing structure and is connected with the first gate layer of the first stair step.

IPC Classes  ?

  • H01L 23/535 - Arrangements for conducting electric current within the device in operation from one component to another including internal interconnections, e.g. cross-under constructions
  • H01L 23/528 - Layout of the interconnection structure
  • H01L 27/11556 - Electrically programmable read-only memories; Multistep manufacturing processes therefor with floating gate characterised by three-dimensional arrangements, e.g. with cells on different height levels with source and drain on different levels, e.g. with sloping channels the channels comprising vertical portions, e.g. U-shaped channels
  • H01L 27/11529 - Electrically programmable read-only memories; Multistep manufacturing processes therefor with floating gate characterised by the peripheral circuit region of memory regions comprising cell select transistors, e.g. NAND
  • H01L 27/11582 - Electrically programmable read-only memories; Multistep manufacturing processes therefor with charge-trapping gate insulators, e.g. MNOS or NROM characterised by three-dimensional arrangements, e.g. with cells on different height levels with source and drain on different levels, e.g. with sloping channels the channels comprising vertical portions, e.g. U-shaped channels
  • H01L 27/11573 - Electrically programmable read-only memories; Multistep manufacturing processes therefor with charge-trapping gate insulators, e.g. MNOS or NROM characterised by the peripheral circuit region

65.

MEMORY DEVICES AND METHODS FOR FORMING THE SAME

      
Application Number 18225593
Status Pending
Filing Date 2023-07-24
First Publication Date 2024-02-08
Owner YANGTZE MEMORY TECHNOLOGIES CO., LTD. (China)
Inventor
  • Xu, Mingliang
  • Chen, He
  • Liu, Wei

Abstract

A semiconductor device includes an array of memory cells, bit lines coupled to the memory cells, and first air gaps. Each of the memory cells includes a vertical transistor. The vertical transistor includes a semiconductor body extends in a first direction. Each of the bit lines is electrically connected to a first end of the semiconductor body. At least one of the first air gaps is between adjacent bit lines.

IPC Classes  ?

  • H10B 12/00 - Dynamic random access memory [DRAM] devices

66.

SEMICONDUCTOR DEVICES AND FABRICATING METHODS THEREOF

      
Application Number 18226159
Status Pending
Filing Date 2023-07-25
First Publication Date 2024-02-08
Owner YANGTZE MEMORY TECHNOLOGIES CO., LTD. (China)
Inventor
  • Cai, Zhiyong
  • Zhang, Ziyu
  • Yang, Kang
  • Lo, Hsing-An
  • Zhou, Yi

Abstract

Three-dimensional (3D) semiconductor devices and fabricating methods are provided. In some implementations, a disclosed semiconductor device comprises: an array of vertical transistors each comprising a semiconductor body extending in a vertical direction; a plurality of word lines each extending along a first lateral direction and comprising a plurality of gate structures of a row of the array of vertical transistors arranged in the first lateral direction; and a plurality of bit lines each extending along a second lateral direction different from the first lateral direction and comprising silicide.

IPC Classes  ?

  • H10B 12/00 - Dynamic random access memory [DRAM] devices

67.

SYSTEMS, METHODS AND MEDIA OF OPTIMIZATION OF TEMPORARY READ ERRORS IN 3D NAND MEMORY DEVICES

      
Application Number 17879593
Status Pending
Filing Date 2022-08-02
First Publication Date 2024-02-08
Owner Yangtze Memory Technologies Co., Ltd. (China)
Inventor
  • Jia, Jianquan
  • You, Kaikai
  • Jia, Xinlei
  • Zhou, Wen
  • Yang, Kun
  • Han, Jiayin
  • Xu, Pan
  • Luo, Zhe
  • Li, Da
  • Jin, Lei

Abstract

Systems, methods and media of optimization of temporary read errors (TRE) in three-dimensional (3D) NAND memory devices are disclosed. A disclosed memory device can comprises a plurality of memory cells arranged as an array of NAND memory strings, a plurality of word lines couple to the memory cells, and a controller. The controller is configured to determine whether a next read operation is a first read operation of the memory device after recovering from an idle state, and In response to a positive result of the determination, control the memory device to perform an extended pre-phase of the first read operation before a read-phase of the first read operation.

IPC Classes  ?

  • G11C 11/4096 - Input/output [I/O] data management or control circuits, e.g. reading or writing circuits, I/O drivers or bit-line switches
  • G11C 11/408 - Address circuits
  • G11C 11/4076 - Timing circuits
  • G11C 11/4074 - Power supply or voltage generation circuits, e.g. bias voltage generators, substrate voltage generators, back-up power, power control circuits

68.

FILE SYSTEM AND HOST PERFORMANCE BOOSTER FOR FLASH MEMORY

      
Application Number 18378524
Status Pending
Filing Date 2023-10-10
First Publication Date 2024-02-01
Owner YANGTZE MEMORY TECHNOLOGIES CO., LTD. (USA)
Inventor
  • Cao, Kaiyao
  • Zhang, Yaping
  • Sun, Xiuli

Abstract

In an aspect, a method for managing a logic to physical (L2P) mapping table of a memory device is disclosed. A first configuration corresponding to a file is received from a host device with the memory device. Transmitting an L2P dirty entry notification associated with the file to the host device is refrained from. The L2P dirty entry notification indicates that an L2P entry of an L2P mapping table stored in the host device has become dirty. In response to the refraining, a first confirmation is transmitted to the host device.

IPC Classes  ?

  • G06F 3/06 - Digital input from, or digital output to, record carriers

69.

3D NAND MEMORY DEVICE AND METHOD OF FORMING THE SAME

      
Application Number 18484125
Status Pending
Filing Date 2023-10-10
First Publication Date 2024-02-01
Owner Yangtze Memory Technologies Co., Ltd. (China)
Inventor
  • Sun, Zhongwang
  • Zhang, Zhong
  • Zhou, Wenxi
  • Xia, Zhiliang

Abstract

In a method for fabricating a semiconductor device, an initial stack of sacrificial word line layers and insulating layers is formed over a substrate of the semiconductor device. The sacrificial word line layers and the insulating layers are disposed over the substrate alternately. A first staircase is formed in a first staircase region of a connection region of the initial stack. A second staircase is formed in a second staircase region of the connection region of the initial stack. The connection region of the initial stack includes a separation region between the first and second staircases, and the connection region is positioned between array regions of the initial stack at opposing sides of the initial stack.

IPC Classes  ?

  • H01L 23/528 - Layout of the interconnection structure
  • H01L 21/768 - Applying interconnections to be used for carrying current between separate components within a device
  • H01L 23/522 - Arrangements for conducting electric current within the device in operation from one component to another including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
  • H01L 23/535 - Arrangements for conducting electric current within the device in operation from one component to another including internal interconnections, e.g. cross-under constructions
  • H01L 21/311 - Etching the insulating layers
  • H10B 41/10 - Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates characterised by the top-view layout
  • H10B 41/27 - Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates characterised by three-dimensional arrangements, e.g. with cells on different height levels with source and drain on different levels, e.g. with sloping channels the channels comprising vertical portions, e.g. U-shaped channels
  • H10B 43/10 - EEPROM devices comprising charge-trapping gate insulators characterised by the top-view layout
  • H10B 43/27 - EEPROM devices comprising charge-trapping gate insulators characterised by three-dimensional arrangements, e.g. with cells on different height levels with source and drain on different levels, e.g. with sloping channels the channels comprising vertical portions, e.g. U-shaped channels
  • H10B 43/40 - EEPROM devices comprising charge-trapping gate insulators characterised by the peripheral circuit region
  • H10B 43/50 - EEPROM devices comprising charge-trapping gate insulators characterised by the boundary region between the core and peripheral circuit regions

70.

SEMICONDUCTOR FABRICATION METHOD WITH IMPROVED DEPOSITION QUALITY AND SEMICONDUCTOR STRUCTURE THEREOF

      
Application Number 17878340
Status Pending
Filing Date 2022-08-01
First Publication Date 2024-02-01
Owner Yangtze Memory Technologies Co., Ltd. (China)
Inventor
  • Song, Rui
  • Pan, Jie
  • Ding, Peng
  • Zhang, Jiewen
  • Chen, Xufang

Abstract

A structure includes a base layer and conductive element in a dielectric region. The base layer includes a first material and is perpendicular to a direction. The conductive element includes a conductive material and contacts the base layer and the dielectric region. An interface parallel to the direction is formed between the conductive element and the dielectric region. A deposition rate of the conductive material over a surface of the base layer is higher than that over a surface of the dielectric region.

IPC Classes  ?

  • H01L 23/535 - Arrangements for conducting electric current within the device in operation from one component to another including internal interconnections, e.g. cross-under constructions
  • H01L 27/11556 - Electrically programmable read-only memories; Multistep manufacturing processes therefor with floating gate characterised by three-dimensional arrangements, e.g. with cells on different height levels with source and drain on different levels, e.g. with sloping channels the channels comprising vertical portions, e.g. U-shaped channels
  • H01L 27/11582 - Electrically programmable read-only memories; Multistep manufacturing processes therefor with charge-trapping gate insulators, e.g. MNOS or NROM characterised by three-dimensional arrangements, e.g. with cells on different height levels with source and drain on different levels, e.g. with sloping channels the channels comprising vertical portions, e.g. U-shaped channels
  • H01L 25/065 - Assemblies consisting of a plurality of individual semiconductor or other solid state devices all the devices being of a type provided for in the same subgroup of groups , or in a single subclass of , , e.g. assemblies of rectifier diodes the devices not having separate containers the devices being of a type provided for in group
  • H01L 25/18 - Assemblies consisting of a plurality of individual semiconductor or other solid state devices the devices being of types provided for in two or more different subgroups of the same main group of groups , or in a single subclass of ,
  • H01L 23/00 - SEMICONDUCTOR DEVICES NOT COVERED BY CLASS - Details of semiconductor or other solid state devices
  • H01L 25/00 - Assemblies consisting of a plurality of individual semiconductor or other solid state devices

71.

SEMICONDUCTOR DEVICES AND MANUFACTURING METHODS THEREOF

      
Application Number 18225588
Status Pending
Filing Date 2023-07-24
First Publication Date 2024-02-01
Owner YANGTZE MEMORY TECHNOLOGIES CO., LTD. (China)
Inventor
  • Xu, Wenxiang
  • Liu, Fandong
  • Hua, Wenyu
  • Wang, Ya
  • Song, Dongmen

Abstract

A semiconductor device includes a first vertically-oriented semiconductor pillar having one or more sidewalls, and a top surface, the first vertically-oriented semiconductor pillar having a first width, a first dielectric material abutted to the one or more sidewalls of the first vertically-oriented semiconductor pillar, and a first conductive structure having a first surface, and having a second width that is greater than the first width, the first conductive structure disposed such that a second portion of its first surface is in electrical contact with the top surface of the first vertically-oriented semiconductor pillar, wherein a first portion of the first surface of the first conductive structure extends laterally beyond the top surface of the first vertically-oriented semiconductor pillar, and the second portion of the first surface is disposed on the first dielectric material.

IPC Classes  ?

  • H01L 29/417 - Electrodes characterised by their shape, relative sizes or dispositions carrying the current to be rectified, amplified or switched
  • H01L 29/40 - Electrodes
  • H01L 21/8234 - MIS technology
  • H01L 27/088 - Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only the components being field-effect transistors with insulated gate

72.

THREE-DIMENSIONAL MEMORY DEVICES, SYSTEMS, AND METHODS FOR FORMING THE SAME

      
Application Number 17876311
Status Pending
Filing Date 2022-07-28
First Publication Date 2024-02-01
Owner YANGTZE MEMORY TECHNOLOGIES CO., LTD. (China)
Inventor
  • Xu, Wenshan
  • Wang, Xin

Abstract

A three-dimensional 3D memory device includes a substrate, a peripheral device disposed on the substrate, a memory stack disposed above the peripheral device and including a plurality of conductor/dielectric layer pairs, and a plurality of memory strings, each of the memory strings extending through the memory stack. The peripheral device includes at least a transistor disposed on the substrate. The transistor includes a gate stack. The gate stack of the transistor includes a staircase structure, and an operational voltage of the transistor is above 5 volts.

IPC Classes  ?

  • H01L 27/11573 - Electrically programmable read-only memories; Multistep manufacturing processes therefor with charge-trapping gate insulators, e.g. MNOS or NROM characterised by the peripheral circuit region
  • H01L 27/11556 - Electrically programmable read-only memories; Multistep manufacturing processes therefor with floating gate characterised by three-dimensional arrangements, e.g. with cells on different height levels with source and drain on different levels, e.g. with sloping channels the channels comprising vertical portions, e.g. U-shaped channels
  • H01L 27/11529 - Electrically programmable read-only memories; Multistep manufacturing processes therefor with floating gate characterised by the peripheral circuit region of memory regions comprising cell select transistors, e.g. NAND
  • H01L 27/11582 - Electrically programmable read-only memories; Multistep manufacturing processes therefor with charge-trapping gate insulators, e.g. MNOS or NROM characterised by three-dimensional arrangements, e.g. with cells on different height levels with source and drain on different levels, e.g. with sloping channels the channels comprising vertical portions, e.g. U-shaped channels

73.

WORD-LINE-PICKUP STRUCTURE AND METHOD FOR FORMING THE SAME

      
Application Number 18229702
Status Pending
Filing Date 2023-08-03
First Publication Date 2024-01-25
Owner YANGTZE MEMORY TECHNOLOGIES CO., LTD. (China)
Inventor
  • Song, Dongmen
  • Liu, Fandong
  • Xu, Wenxiang
  • Du, Mingli

Abstract

A memory device, having a plurality of first-word-lines, each first-word-line having a first portion, a second portion, and a third portion; a plurality of second-word-lines, each second-word-line having a first portion, a second portion, and a third portion; and a memory array having a first side, a second side laterally opposite the first side, and a third side. The first portions of each first-word-line and each second-word-line are spaced apart from their respective third portions. The second portion of each first-word-line and the second portion of each second-word-line are non-parallel and non-co-linear with their respective first portions and third portions. Each first-word-line is disposed such that its second portion is adjacent to the first side, and each second-word-line is disposed such that its second portion is adjacent to the second side. The memory device further has a plurality of first-side-word-line-pickup-structures, and a plurality of second-side-word-line-pickup-structures.

IPC Classes  ?

  • H10B 12/00 - Dynamic random access memory [DRAM] devices

74.

THREE-DIMENSIONAL MEMORY DEVICES HAVING THROUGH ARRAY CONTACTS AND METHODS FOR FORMING THE SAME

      
Application Number 18374497
Status Pending
Filing Date 2023-09-28
First Publication Date 2024-01-25
Owner YANGTZE MEMORY TECHNOLOGIES CO., LTD. (China)
Inventor
  • Guo, Mei Lan
  • Hu, Yushi
  • Xia, Ji
  • Zhu, Hongbin

Abstract

In certain aspects, a semiconductor device includes a substrate, a stack structure over the substrate and including interleaved conductive layers and dielectric layers, and a connection structure extending through the stack structure into the substrate. The connection structure includes a conductor layer and a spacer over a sidewall of the conductor layer. The conductor layer of the connection structure is in direct contact with the substrate.

IPC Classes  ?

  • H10B 41/42 - Simultaneous manufacture of periphery and memory cells
  • H01L 21/768 - Applying interconnections to be used for carrying current between separate components within a device
  • H01L 23/522 - Arrangements for conducting electric current within the device in operation from one component to another including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
  • H01L 23/528 - Layout of the interconnection structure
  • H10B 41/27 - Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates characterised by three-dimensional arrangements, e.g. with cells on different height levels with source and drain on different levels, e.g. with sloping channels the channels comprising vertical portions, e.g. U-shaped channels
  • H10B 41/35 - Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates characterised by the memory core region with a cell select transistor, e.g. NAND
  • H10B 41/41 - Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates characterised by the peripheral circuit region of a memory region comprising a cell select transistor, e.g. NAND
  • H10B 43/27 - EEPROM devices comprising charge-trapping gate insulators characterised by three-dimensional arrangements, e.g. with cells on different height levels with source and drain on different levels, e.g. with sloping channels the channels comprising vertical portions, e.g. U-shaped channels
  • H10B 43/35 - EEPROM devices comprising charge-trapping gate insulators characterised by the memory core region with cell select transistors, e.g. NAND
  • H10B 43/40 - EEPROM devices comprising charge-trapping gate insulators characterised by the peripheral circuit region

75.

MEMORY DEVICE, THE OPERATION METHOD THEREOF AND MEMORY SYSTEM

      
Application Number 17974271
Status Pending
Filing Date 2022-10-26
First Publication Date 2024-01-25
Owner YANGTZE MEMORY TECHNOLOGIES CO., LTD. (China)
Inventor
  • Li, Zhihong
  • Wei, Jing
  • Kuriyama, Masao

Abstract

The present disclosure provides a memory device comprising a memory cell array and a peripheral circuit coupled to the memory cell array. The memory cell array includes a plurality of memory planes; the peripheral circuit includes a plurality of selected voltage selection circuits corresponding to the plurality of memory planes; a plurality of global word line voltage selection circuits respectively corresponding to each memory plane, and a plurality of local word line voltage selection circuits respectively corresponding to each memory plane. The plurality of selected voltage selection circuits are configured to select a voltage from a plurality of selected voltages to output to the global word line voltage selection circuits; the global word line voltage selection circuits are configured to select a voltage from unselected voltages and the voltage output from the plurality of selected voltage selection circuits to output to the local word line voltage selection circuits.

IPC Classes  ?

  • G11C 16/04 - Erasable programmable read-only memories electrically programmable using variable threshold transistors, e.g. FAMOS
  • G11C 16/08 - Address circuits; Decoders; Word-line control circuits
  • G11C 16/10 - Programming or data input circuits
  • G11C 16/26 - Sensing or reading circuits; Data output circuits

76.

WORD-LINE-PICKUP STRUCTURE AND METHOD FOR FORMING THE SAME

      
Application Number CN2023106319
Publication Number 2024/017077
Status In Force
Filing Date 2023-07-07
Publication Date 2024-01-25
Owner YANGTZE MEMORY TECHNOLOGIES CO., LTD. (China)
Inventor
  • Song, Dongmen
  • Liu, Fandong
  • Xu, Wenxiang
  • Du, Mingli

Abstract

A memory device, having a plurality of first-word-lines, each first-word-line having a first portion, a second portion, and a third portion; a plurality of second-word-lines, each second-word-line having a first portion, a second portion, and a third portion; and a memory array having a first side, a second side laterally opposite the first side, and a third side. The first portions of each first-word-line and each second-word-line are spaced apart from their respective third portions. The second portion of each first-word-line and the second portion of each second-word-line are non-parallel and non-co-linear with their respective first portions and third portions. Each first-word-line is disposed such that its second portion is adjacent to the first side, and each second-word-line is disposed such that its second portion is adjacent to the second side. The memory device further has a plurality of first-side-word-line-pickup-structures, and a plurality of second-side-word-line-pickup-structures.

IPC Classes  ?

  • G11C 5/02 - Disposition of storage elements, e.g. in the form of a matrix array

77.

THREE-DIMENSIONAL MEMORY DEVICE, MEMORY SYSTEM, AND METHODS FOR FORMING THE SAME

      
Application Number 17868680
Status Pending
Filing Date 2022-07-19
First Publication Date 2024-01-25
Owner YANGTZE MEMORY TECHNOLOGIES CO., LTD. (China)
Inventor
  • Xie, Jingtao
  • Yan, Bingjie
  • Zhou, Wenxi
  • Xia, Zhiliang
  • Huo, Zongliang

Abstract

A 3D includes a memory array structure. The memory array structure includes a first memory array structure and a second memory array structure each having a plurality of conductive/dielectric layer pairs. The memory array structure also includes a staircase structure between the first memory array structure and the second memory array structure. The staircase structure includes a first staircase zone and a second staircase zone. The first staircase zone includes at least one staircase, each including a plurality of stairs. The second staircase zone includes a bridge structure, and at least one other staircase over the bridge structure. The bridge structure connects the first memory array structure and the second memory array structure, the at least one other staircase each including a plurality of stairs. At least one stair in one or more of the at least one staircase is electrically connected to the bridge structure.

IPC Classes  ?

  • H01L 27/11556 - Electrically programmable read-only memories; Multistep manufacturing processes therefor with floating gate characterised by three-dimensional arrangements, e.g. with cells on different height levels with source and drain on different levels, e.g. with sloping channels the channels comprising vertical portions, e.g. U-shaped channels
  • G11C 16/04 - Erasable programmable read-only memories electrically programmable using variable threshold transistors, e.g. FAMOS
  • H01L 27/11582 - Electrically programmable read-only memories; Multistep manufacturing processes therefor with charge-trapping gate insulators, e.g. MNOS or NROM characterised by three-dimensional arrangements, e.g. with cells on different height levels with source and drain on different levels, e.g. with sloping channels the channels comprising vertical portions, e.g. U-shaped channels
  • H01L 27/1157 - Electrically programmable read-only memories; Multistep manufacturing processes therefor with charge-trapping gate insulators, e.g. MNOS or NROM characterised by the memory core region with cell select transistors, e.g. NAND
  • H01L 27/11524 - Electrically programmable read-only memories; Multistep manufacturing processes therefor with floating gate characterised by the memory core region with cell select transistors, e.g. NAND

78.

THREE-DIMENSIONAL MEMORY DEVICES HAVING THROUGH STAIR CONTACTS AND METHODS FOR FORMING THE SAME

      
Application Number 18374507
Status Pending
Filing Date 2023-09-28
First Publication Date 2024-01-18
Owner YANGTZE MEMORY TECHNOLOGIES CO., LTD. (China)
Inventor
  • Wei, Qinxiang
  • Sun, Jianhua
  • Xia, Ji

Abstract

In an example, a three-dimensional (3D) memory device includes a memory stack and a through stair contact (TSC). The memory stack includes interleaved conductive layers and dielectric layers. The memory stack includes stairs in a staircase region. The TSC extends through the memory stack in the staircase region. The TSC includes a first conductor layer and a first spacer circumscribing the first conductor layer. The first conductor layer of the TSC is insulated from the conductive layers of the memory stack by the first spacer.

IPC Classes  ?

  • H10B 43/27 - EEPROM devices comprising charge-trapping gate insulators characterised by three-dimensional arrangements, e.g. with cells on different height levels with source and drain on different levels, e.g. with sloping channels the channels comprising vertical portions, e.g. U-shaped channels
  • H01L 21/768 - Applying interconnections to be used for carrying current between separate components within a device
  • H01L 23/522 - Arrangements for conducting electric current within the device in operation from one component to another including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
  • H01L 21/28 - Manufacture of electrodes on semiconductor bodies using processes or apparatus not provided for in groups
  • H10B 43/35 - EEPROM devices comprising charge-trapping gate insulators characterised by the memory core region with cell select transistors, e.g. NAND
  • H10B 43/40 - EEPROM devices comprising charge-trapping gate insulators characterised by the peripheral circuit region

79.

THREE-DIMENSIONAL MEMORY DEVICES AND METHODS FOR FORMING THE SAME

      
Application Number 17864032
Status Pending
Filing Date 2022-07-13
First Publication Date 2024-01-18
Owner YANGTZE MEMORY TECHNOLOGIES CO., LTD. (China)
Inventor
  • Huang, Yujun
  • Yang, Chuan
  • Gao, Qian
  • Zhang, Xin

Abstract

In certain aspects, a three-dimensional (3D) memory device includes a stack structure including interleaved conductive layers and dielectric layers and having a core array region and a staircase region in a plan view, one or more channel structures each extending through the core array region of the stack structure, and one or more contact structures each extending through the stack structure, wherein each of the one or more contact structures includes a head portion and a body portion, and a width of the head portion of the respective contact structure is larger than that of the body portion of the respective contact structure.

IPC Classes  ?

  • G11C 16/04 - Erasable programmable read-only memories electrically programmable using variable threshold transistors, e.g. FAMOS
  • H01L 27/11582 - Electrically programmable read-only memories; Multistep manufacturing processes therefor with charge-trapping gate insulators, e.g. MNOS or NROM characterised by three-dimensional arrangements, e.g. with cells on different height levels with source and drain on different levels, e.g. with sloping channels the channels comprising vertical portions, e.g. U-shaped channels
  • H01L 23/522 - Arrangements for conducting electric current within the device in operation from one component to another including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
  • H01L 23/528 - Layout of the interconnection structure
  • H01L 27/11573 - Electrically programmable read-only memories; Multistep manufacturing processes therefor with charge-trapping gate insulators, e.g. MNOS or NROM characterised by the peripheral circuit region
  • H01L 27/1157 - Electrically programmable read-only memories; Multistep manufacturing processes therefor with charge-trapping gate insulators, e.g. MNOS or NROM characterised by the memory core region with cell select transistors, e.g. NAND
  • H01L 27/11556 - Electrically programmable read-only memories; Multistep manufacturing processes therefor with floating gate characterised by three-dimensional arrangements, e.g. with cells on different height levels with source and drain on different levels, e.g. with sloping channels the channels comprising vertical portions, e.g. U-shaped channels
  • H01L 27/11526 - Electrically programmable read-only memories; Multistep manufacturing processes therefor with floating gate characterised by the peripheral circuit region
  • H01L 27/11524 - Electrically programmable read-only memories; Multistep manufacturing processes therefor with floating gate characterised by the memory core region with cell select transistors, e.g. NAND

80.

MEMORY DEVICES AND METHODS FOR FORMING THE SAME

      
Application Number 18219570
Status Pending
Filing Date 2023-07-07
First Publication Date 2024-01-18
Owner YANGTZE MEMORY TECHNOLOGIES CO., LTD. (China)
Inventor
  • Liu, Yaqin
  • Wang, Yanhong
  • Liu, Wei

Abstract

A memory device includes a memory array structure including a vertical transistor having a first terminal and a second terminal, a storage unit having a first end coupled to the first terminal of the vertical transistor, and a bit line coupled to the second terminal of the vertical transistor, a first peripheral circuit coupled to a first surface of the memory array structure, and a second peripheral circuit coupled to a second surface of the memory array structure opposite to the first surface. The vertical transistor includes a semiconductor body extending in a first direction, and a gate structure coupled to at least one side of the semiconductor body.

IPC Classes  ?

  • H10B 12/00 - Dynamic random access memory [DRAM] devices
  • H10B 63/10 - Phase change RAM [PCRAM, PRAM] devices
  • H10B 63/00 - Resistance change memory devices, e.g. resistive RAM [ReRAM] devices

81.

Control Gate Structures in Three-Dimensional Memory Devices and Methods for Forming the Same

      
Application Number 17861571
Status Pending
Filing Date 2022-07-11
First Publication Date 2024-01-11
Owner Yangtze Memory Technologies Co., Ltd. (China)
Inventor
  • Zhang, Kun
  • Zhou, Wenxi
  • Xia, Zhiliang
  • Huo, Zongliang

Abstract

A method for forming a three-dimensional memory device can include forming a staircase structure. An alternating layer stack is disposed and etched to form steps. A continuous layer disposed on the staircase structure continuously extends over the steps. An insulating layer is disposed on the continuous layer and a slit is formed extending through the staircase structure. The slit exposes sidewalls of the continuous layer and the steps. The sacrificial layer is removed and a cavity is formed in place of the continuous layer. An etch stop layer is disposed in the cavity and continuously extends over the steps. Openings are formed through the insulating layer and expose a portion of a lateral surface of the etch stop layer. The openings are extended through the etch stop layer to expose a lateral surface of each step of the steps. Contacts are formed in the openings.

IPC Classes  ?

  • H01L 27/11556 - Electrically programmable read-only memories; Multistep manufacturing processes therefor with floating gate characterised by three-dimensional arrangements, e.g. with cells on different height levels with source and drain on different levels, e.g. with sloping channels the channels comprising vertical portions, e.g. U-shaped channels
  • H01L 27/11519 - Electrically programmable read-only memories; Multistep manufacturing processes therefor with floating gate characterised by the top-view layout
  • H01L 27/11524 - Electrically programmable read-only memories; Multistep manufacturing processes therefor with floating gate characterised by the memory core region with cell select transistors, e.g. NAND
  • H01L 27/11565 - Electrically programmable read-only memories; Multistep manufacturing processes therefor with charge-trapping gate insulators, e.g. MNOS or NROM characterised by the top-view layout
  • H01L 27/1157 - Electrically programmable read-only memories; Multistep manufacturing processes therefor with charge-trapping gate insulators, e.g. MNOS or NROM characterised by the memory core region with cell select transistors, e.g. NAND
  • H01L 27/11582 - Electrically programmable read-only memories; Multistep manufacturing processes therefor with charge-trapping gate insulators, e.g. MNOS or NROM characterised by three-dimensional arrangements, e.g. with cells on different height levels with source and drain on different levels, e.g. with sloping channels the channels comprising vertical portions, e.g. U-shaped channels

82.

THREE-DIMENSIONAL NAND MEMORY DEVICE AND FABRICATION METHOD

      
Application Number 17862191
Status Pending
Filing Date 2022-07-11
First Publication Date 2024-01-11
Owner Yangtze Memory Technologies Co., Ltd. (China)
Inventor
  • Yan, Longxiang
  • Xu, Wei
  • Xu, Bo
  • Wang, Fazhan
  • Xue, Lei
  • Huo, Zongliang

Abstract

A method of forming a three-dimensional (3D) NAND memory device includes: forming a gate line slit through a plurality of alternating layers of an oxide layer and a conductive material layer, where the conductive material layer is further formed on a sidewall and a bottom of the gate line slit; performing an ion implantation process to dope at least a portion of the conductive material layer that is on the bottom and/or a portion of the sidewall of the gate line slit; and performing an etch process in the gate line slit to remove the conductive material layer that is weakened by the ion implantation process.

IPC Classes  ?

  • H01L 27/1157 - Electrically programmable read-only memories; Multistep manufacturing processes therefor with charge-trapping gate insulators, e.g. MNOS or NROM characterised by the memory core region with cell select transistors, e.g. NAND
  • H01L 21/8239 - Memory structures
  • H01L 21/425 - Bombardment with radiation with high-energy radiation producing ion implantation

83.

MEMORY AND ITS ERASE VERIFICATION METHOD, OPERATION METHOD, AND A MEMORY SYSTEM

      
Application Number 18092082
Status Pending
Filing Date 2022-12-30
First Publication Date 2024-01-11
Owner YANGTZE MEMORY TECHNOLOGIES CO., LTD. (China)
Inventor
  • Jing, Chong
  • Cao, Hong

Abstract

A method of erase verification of a memory includes performing a first erase verification operation on a memory block of the memory after performing an erase operation on the memory block. The method also includes determining a first verification result of the first erase verification operation. The method further includes determining whether to perform a second erase verification operation on the memory block based on the first verification result. The second erase verification operation is configured to determine whether there is inter-word line leakage in the memory block.

IPC Classes  ?

  • G11C 16/34 - Determination of programming status, e.g. threshold voltage, overprogramming or underprogramming, retention
  • G11C 16/08 - Address circuits; Decoders; Word-line control circuits
  • G11C 16/04 - Erasable programmable read-only memories electrically programmable using variable threshold transistors, e.g. FAMOS
  • G11C 29/50 - Marginal testing, e.g. race, voltage or current testing

84.

THREE-DIMENSIONAL NAND MEMORY DEVICE AND METHOD OF FORMING THE SAME

      
Application Number 17857264
Status Pending
Filing Date 2022-07-05
First Publication Date 2024-01-11
Owner Yangtze Memory Technologies Co., Ltd (China)
Inventor
  • Wu, Linchun
  • Zhang, Kun
  • Zhou, Wenxi
  • Xia, Zhiliang
  • Huo, Zongliang

Abstract

A semiconductor device semiconductor device includes a stack having a first surface and a second surface opposing the first surface. The stack can include word line layers and insulating layers alternating with the word line layers between the first surface and the second surface. The stack can further include a process stop layer between the lower most insulating layer and the second surface. The stack can extend along an X-Y plane having an X direction and a Y direction perpendicular. The semiconductor device can further include a slit structure crossing the stack between the first surface and the second surface in Z direction. In a cross-section perpendicular to the Y direction, distances between the slit structure and the process stop layer at two sides of the slit structure are each larger than distances at either side of the slit structure between the word line layers and the slit structure.

IPC Classes  ?

  • H01L 27/11575 - Electrically programmable read-only memories; Multistep manufacturing processes therefor with charge-trapping gate insulators, e.g. MNOS or NROM characterised by the boundary region between the core and peripheral circuit regions
  • H01L 23/535 - Arrangements for conducting electric current within the device in operation from one component to another including internal interconnections, e.g. cross-under constructions
  • H01L 27/11582 - Electrically programmable read-only memories; Multistep manufacturing processes therefor with charge-trapping gate insulators, e.g. MNOS or NROM characterised by three-dimensional arrangements, e.g. with cells on different height levels with source and drain on different levels, e.g. with sloping channels the channels comprising vertical portions, e.g. U-shaped channels

85.

A MEMORY DEVICE, PROGRAMMING METHOD AND MEMORY SYSTEM

      
Application Number 18147537
Status Pending
Filing Date 2022-12-28
First Publication Date 2024-01-04
Owner Yangtze Memory Technologies Co., Ltd. (China)
Inventor
  • Qiao, Liang
  • Wang, Bowen

Abstract

The present application discloses a memory device, a programming method and a memory system. The memory device comprises: a memory cell array comprising a plurality of word lines and a plurality of bit lines; each of the word lines comprising at least two word line segments; each of the word line segment in the word line having different signal transmission distances from a word line driver; different word line segments in the word line corresponding to different bit lines respectively; the word line driver configured to apply a word line voltage to the word line; a bit line driver configured to apply different bias voltages to different bit lines corresponding to the different word line segments respectively during application of a programming pulse.

IPC Classes  ?

  • G11C 16/10 - Programming or data input circuits
  • G11C 16/08 - Address circuits; Decoders; Word-line control circuits
  • G11C 16/24 - Bit-line control circuits

86.

SEMICONDUCTOR DEVICE, PROGRAMMING METHOD, MEMORY, MEMORY SYSTEM AND ELECTRONIC DEVICE

      
Application Number 18090961
Status Pending
Filing Date 2022-12-29
First Publication Date 2024-01-04
Owner Yangtze Memory Technologies Co., Ltd. (China)
Inventor
  • Wang, Yan
  • Hou, Chunyuan
  • Kuriyama, Masao
  • Du, Zhichao
  • Zhao, Lichuan

Abstract

A semiconductor device includes a bit line unit, a word line unit, a bit line drive unit, and a word line drive unit. The bit line unit is configured to divide the word line unit into a first word line unit and a second word line unit. The distance between the second word line unit and the word line drive unit is greater than that the distance between the first word line unit and the word line drive unit. The word line drive unit is configured to provide the driving voltage for programming to the word line unit. The bit line drive unit is configured to apply the first bias voltage to the bit line unit that performs the dividing to obtain the first word line unit in the charging phase of programming, and to apply the second bias voltage to the bit line unit that performs the dividing to obtain the second word line unit in the discharging phase of programming.

IPC Classes  ?

  • G11C 16/10 - Programming or data input circuits
  • G11C 16/08 - Address circuits; Decoders; Word-line control circuits
  • G11C 16/24 - Bit-line control circuits

87.

METHOD FOR PROGRAMMING A MEMORY SYSTEM

      
Application Number 18225575
Status Pending
Filing Date 2023-07-24
First Publication Date 2024-01-04
Owner YANGTZE MEMORY TECHNOLOGIES CO., LTD. (China)
Inventor
  • Li, Haibo
  • Mui, Man Lung
  • Wang, Yu

Abstract

In certain aspects, a memory device includes a plurality of memory cells and a control circuit coupled to the plurality of memory cells. The plurality of memory cells includes a first set of memory cells configured to be programmed into a first set of programming states each of which is not lower than a first predetermined programming state. The control circuit is configured to perform a first program pass on the first set of memory cells. The control circuit is configured to continue to program at least a first memory cell from the first set of memory cells with one or more first programming voltages. A threshold voltage of the first memory cell is greater than a first verification voltage that corresponds to a first programming state of the first memory cell. The control circuit is configured to perform a second program pass on the first set of memory cells.

IPC Classes  ?

  • G11C 16/34 - Determination of programming status, e.g. threshold voltage, overprogramming or underprogramming, retention
  • G11C 16/08 - Address circuits; Decoders; Word-line control circuits

88.

THREE-DIMENSIONAL MEMORY DEVICES AND FABRICATING METHODS THEREOF

      
Application Number 18141274
Status Pending
Filing Date 2023-04-28
First Publication Date 2023-12-28
Owner YANGTZE MEMORY TECHNOLOGIES CO., LTD. (China)
Inventor
  • Fan, Dongyu
  • Zhao, Dongxue
  • Zhou, Wenxi
  • Xia, Zhiliang
  • Huo, Zongliang
  • Liu, Wei

Abstract

Three-dimensional (3D) memory devices and fabricating methods are disclosed. A disclosed 3D memory device includes a first semiconductor structure. The first semiconductor structure includes an array of first-type through stack structures in a first region and an array of second-type through stack structures in a second region, and a slit structure separating the array of first-type through stack structures from the array of second-type through stack structures. The 3D memory device further includes a second semiconductor structure. The second semiconductor structure includes a first periphery circuit and a second periphery circuit at different levels. The second semiconductor structure and the first semiconductor structure are bonded together, such that the first periphery circuit is located between the second periphery circuit and the first semiconductor structure.

IPC Classes  ?

  • H10B 80/00 - Assemblies of multiple devices comprising at least one memory device covered by this subclass
  • H01L 25/065 - Assemblies consisting of a plurality of individual semiconductor or other solid state devices all the devices being of a type provided for in the same subgroup of groups , or in a single subclass of , , e.g. assemblies of rectifier diodes the devices not having separate containers the devices being of a type provided for in group
  • H01L 25/18 - Assemblies consisting of a plurality of individual semiconductor or other solid state devices the devices being of types provided for in two or more different subgroups of the same main group of groups , or in a single subclass of ,
  • H01L 23/00 - SEMICONDUCTOR DEVICES NOT COVERED BY CLASS - Details of semiconductor or other solid state devices
  • H01L 25/00 - Assemblies consisting of a plurality of individual semiconductor or other solid state devices
  • H10B 41/27 - Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates characterised by three-dimensional arrangements, e.g. with cells on different height levels with source and drain on different levels, e.g. with sloping channels the channels comprising vertical portions, e.g. U-shaped channels
  • H10B 43/27 - EEPROM devices comprising charge-trapping gate insulators characterised by three-dimensional arrangements, e.g. with cells on different height levels with source and drain on different levels, e.g. with sloping channels the channels comprising vertical portions, e.g. U-shaped channels
  • H10B 51/20 - Ferroelectric RAM [FeRAM] devices comprising ferroelectric memory transistors characterised by the three-dimensional arrangements, e.g. with cells on different height levels

89.

THREE-DIMENSIONAL MEMORY DEVICES AND FABRICATING METHODS THEREOF

      
Application Number 18196247
Status Pending
Filing Date 2023-05-11
First Publication Date 2023-12-28
Owner YANGTZE MEMORY TECHNOLOGIES CO., LTD. (China)
Inventor
  • Zhao, Dongxue
  • Yang, Tao
  • Zhou, Wenxi
  • Yang, Yuancheng
  • Xia, Zhiliang
  • Huo, Zongliang

Abstract

Three-dimensional (3D) memory devices and fabricating methods are disclosed. A disclosed 3D memory device includes a first semiconductor structure. The first semiconductor structure includes an array of first type through stack structures in a first region of a memory stack, an array of second type through stack structures in a second region of the memory stack, a semiconductor layer including a first portion on the array of first type through stack structures and a second portion on the array of second type through stack structures, multiple vias each penetrating the semiconductor layer and in contact with a corresponding one of the first type through stack structures or the array of second type through stack structures, and a slit structure separating the array of first type through stack structures from the array of second type through stack structures, and separating the first portion of the semiconductor layer from the second portion of the semiconductor layer.

IPC Classes  ?

  • H10B 80/00 - Assemblies of multiple devices comprising at least one memory device covered by this subclass
  • H01L 25/065 - Assemblies consisting of a plurality of individual semiconductor or other solid state devices all the devices being of a type provided for in the same subgroup of groups , or in a single subclass of , , e.g. assemblies of rectifier diodes the devices not having separate containers the devices being of a type provided for in group
  • H01L 25/18 - Assemblies consisting of a plurality of individual semiconductor or other solid state devices the devices being of types provided for in two or more different subgroups of the same main group of groups , or in a single subclass of ,
  • H01L 23/00 - SEMICONDUCTOR DEVICES NOT COVERED BY CLASS - Details of semiconductor or other solid state devices
  • H01L 25/00 - Assemblies consisting of a plurality of individual semiconductor or other solid state devices

90.

THREE-DIMENSIONAL MEMORY DEVICES AND METHODS FOR FORMING THE SAME

      
Application Number 18244688
Status Pending
Filing Date 2023-09-11
First Publication Date 2023-12-28
Owner YANGTZE MEMORY TECHNOLOGIES CO., LTD. (China)
Inventor
  • Lu, Zhenyu
  • Chen, Jun
  • Zhu, Jifeng
  • Hu, Yushi
  • Tao, Qian
  • Yang, Simon Shi-Ning
  • Yang, Steve Weiyi

Abstract

A semiconductor device includes a peripheral circuit, a stacked structure including a first side and a second side along a vertical direction, and alternating conductive layers and first insulating layers, a memory string extending through the stacked structure, a bonding structure located between the first side of the stacked structure and the peripheral circuit in the vertical direction and connected with the memory string and the peripheral circuit, a second insulating layer located at the second side of the stacked structure; and a conductor structure located in the second insulating layer.

IPC Classes  ?

  • H10B 43/27 - EEPROM devices comprising charge-trapping gate insulators characterised by three-dimensional arrangements, e.g. with cells on different height levels with source and drain on different levels, e.g. with sloping channels the channels comprising vertical portions, e.g. U-shaped channels
  • H01L 23/528 - Layout of the interconnection structure
  • H10B 43/10 - EEPROM devices comprising charge-trapping gate insulators characterised by the top-view layout
  • H10B 43/35 - EEPROM devices comprising charge-trapping gate insulators characterised by the memory core region with cell select transistors, e.g. NAND
  • H10B 43/40 - EEPROM devices comprising charge-trapping gate insulators characterised by the peripheral circuit region
  • H10B 43/50 - EEPROM devices comprising charge-trapping gate insulators characterised by the boundary region between the core and peripheral circuit regions

91.

MEMORY DEVICE, MEMORY SYSTEM, AND OPERATING METHOD THEREOF

      
Application Number 18357883
Status Pending
Filing Date 2023-07-24
First Publication Date 2023-12-28
Owner Yangtze Memory Technologies Co., Ltd. (China)
Inventor Guo, Xiaojiang

Abstract

A memory device, a memory system, and a method thereof are provided. In the method, an N-th programming pulse is applied to a word line coupled to memory cells of the memory device each with a target programming state being an i-th programming state. A first sub-verification and an M-th second sub-verification are performed on the memory cells to obtain a first sub-result and an M-th second sub-result, respectively. Based on the M-th second sub-result, a subset of the memory cells is determined to be programmed with an (N+1)-th programming pulse. Then, the (N+1)-th programming pulse is applied to the word line. After applying the (N+1)-th programming pulse to the word line, the memory cells are determined to be successfully programmed to the i-th programming state based on the first sub-result indicating that a number of failed bits in the first sub-verification is less than a first preset value.

IPC Classes  ?

  • G11C 16/34 - Determination of programming status, e.g. threshold voltage, overprogramming or underprogramming, retention
  • G11C 16/10 - Programming or data input circuits
  • G11C 16/26 - Sensing or reading circuits; Data output circuits
  • G11C 16/24 - Bit-line control circuits

92.

DYNAMIC PEAK POWER MANAGEMENT FOR MULTI-DIE OPERATIONS

      
Application Number 18367120
Status Pending
Filing Date 2023-09-12
First Publication Date 2023-12-28
Owner YANGTZE MEMORY TECHNOLOGIES CO., LTD. (China)
Inventor
  • Guo, Jason
  • Tang, Qiang

Abstract

A system includes multiple memory dies. Each of the memory dies includes a PPM circuit including a first pull driver, a second pull driver, and a PPM contact pad connected between the first pull driver and the second pull driver. The PPM contact pads of the multiple memory dies are electrically connected with each other. The PPM circuits of the multiple memory dies are configured to manage peak power operations according to a first pull current flowing through a certain first pull driver of a certain PPM circuit. The first pull current is a sum of second pull currents flowing through second pull drivers of the PPM circuit. Each of the second pull currents is proportional to a current level of a corresponding memory die.

IPC Classes  ?

  • G06F 3/06 - Digital input from, or digital output to, record carriers
  • G11C 5/14 - Power supply arrangements
  • G11C 16/30 - Power supply circuits
  • H01L 27/06 - Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body including a plurality of individual components in a non-repetitive configuration

93.

THREE-DIMENSIONAL MEMORY DEVICES AND MANUFACTURING METHODS THEREOF AND THREE-DIMENSIONAL MEMORIES

      
Application Number 18463900
Status Pending
Filing Date 2023-09-08
First Publication Date 2023-12-28
Owner Yangtze Memory Technologies Co., Ltd. (China)
Inventor Hu, Siping

Abstract

The present disclosure provides a three-dimensional memory device and a manufacturing method thereof, and a three-dimensional memory. The three-dimensional memory device includes a first memory cell and at least one second memory cell sequentially stacked on the first memory cell. Each memory cell includes a first set of contacts, and a memory array device and a CMOS device that are stacked and electrically connected with each other, and the first set of contacts is disposed on a side of the memory array device facing away from the CMOS device and electrically connected with the CMOS device. The second memory cell further comprises a second set of contacts that is disposed on a side of the CMOS device facing away from the memory array device and electrically connected with the CMOS device. The memory array device of the first memory cell is bonded with the CMOS device of the adjacent second memory cell, and the first set of contacts of the first memory cell is correspondingly electrically connected with the second set of contacts of the adjacent second memory cell.

IPC Classes  ?

  • H10B 80/00 - Assemblies of multiple devices comprising at least one memory device covered by this subclass
  • H01L 25/065 - Assemblies consisting of a plurality of individual semiconductor or other solid state devices all the devices being of a type provided for in the same subgroup of groups , or in a single subclass of , , e.g. assemblies of rectifier diodes the devices not having separate containers the devices being of a type provided for in group
  • H01L 25/18 - Assemblies consisting of a plurality of individual semiconductor or other solid state devices the devices being of types provided for in two or more different subgroups of the same main group of groups , or in a single subclass of ,
  • H01L 23/00 - SEMICONDUCTOR DEVICES NOT COVERED BY CLASS - Details of semiconductor or other solid state devices
  • H01L 25/00 - Assemblies consisting of a plurality of individual semiconductor or other solid state devices

94.

VERTICAL MEMORY DEVICES AND METHOD OF FABRICATION THEREOF

      
Application Number 17848008
Status Pending
Filing Date 2022-06-23
First Publication Date 2023-12-28
Owner Yangtze Memory Technologies Co., Ltd. (China)
Inventor
  • Xie, Jingtao
  • Yan, Bingjie
  • Zhou, Wenxi
  • Wang, Di
  • Xia, Zhiliang
  • Huo, Zongliang

Abstract

Aspects of the disclosure provide a semiconductor device. The semiconductor device includes a stack structure and a contact structure. The stack structure comprises interleaved gate layers and insulating layers. The contact structure comprises a conductive structure and one or more insulating structures. The conductive structure can extend through the stack structure and form a conductive connection with one of the gate layers. The one or more insulating structures surround the conductive structure and electrically isolate the conductive structure from remaining ones of the gate layers. The one or more insulating structures further include one or more first insulating structures. Each of the one or more first insulating structures is disposed between an adjacent pair of the insulating layers, and the one or more first insulating structures are disposed on a first side of the one of the gate layers.

IPC Classes  ?

  • H01L 23/535 - Arrangements for conducting electric current within the device in operation from one component to another including internal interconnections, e.g. cross-under constructions
  • H01L 27/11582 - Electrically programmable read-only memories; Multistep manufacturing processes therefor with charge-trapping gate insulators, e.g. MNOS or NROM characterised by three-dimensional arrangements, e.g. with cells on different height levels with source and drain on different levels, e.g. with sloping channels the channels comprising vertical portions, e.g. U-shaped channels

95.

THREE-DIMENSIONAL MEMORY DEVICES AND FABRICATING METHODS THEREOF

      
Application Number CN2023083667
Publication Number 2023/246209
Status In Force
Filing Date 2023-03-24
Publication Date 2023-12-28
Owner YANGTZE MEMORY TECHNOLOGIES CO., LTD. (China)
Inventor
  • Fan, Dongyu
  • Zhao, Dongxue
  • Zhou, Wenxi
  • Xia, Zhiliang
  • Huo, Zongliang
  • Liu, Wei

Abstract

Three-dimensional (3D) memory devices and fabricating methods are disclosed. A disclosed 3D memory device comprises a first semiconductor structure comprising: an array of first-type through stack structures in a first region and an array of second-type through stack structures in a second region, and a slit structure separating the array of first-type through stack structures from the array of second-type through stack structures. The 3D memory device further comprises a second semiconductor structure comprising, a first periphery circuit and a second periphery circuit at different levels. The second semiconductor structure and the first semiconductor structure are bonded together, such that the first periphery circuit is located between the second periphery circuit and the first semiconductor structure.

IPC Classes  ?

  • H10B 43/40 - EEPROM devices comprising charge-trapping gate insulators characterised by the peripheral circuit region
  • H10B 51/40 - Ferroelectric RAM [FeRAM] devices comprising ferroelectric memory transistors characterised by the peripheral circuit region
  • H10B 53/40 - Ferroelectric RAM [FeRAM] devices comprising ferroelectric memory capacitors characterised by the peripheral circuit region
  • H10B 80/00 - Assemblies of multiple devices comprising at least one memory device covered by this subclass

96.

THREE-DIMENSIONAL MEMORY DEVICES AND FABRICATING METHODS THEREOF

      
Application Number CN2023083734
Publication Number 2023/246210
Status In Force
Filing Date 2023-03-24
Publication Date 2023-12-28
Owner YANGTZE MEMORY TECHNOLOGIES CO., LTD. (China)
Inventor
  • Zhao, Dongxue
  • Yang, Tao
  • Zhou, Wenxi
  • Yang, Yuancheng
  • Xia, Zhiliang
  • Huo, Zongliang

Abstract

Three-dimensional (3D) memory devices and fabricating methods are disclosed. A disclosed 3D memory device comprises: a first semiconductor structure, comprising: an array of first type through stack structures in a first region of a memory stack; an array of second type through stack structures in a second region of the memory stack; a semiconductor layer including a first portion on the array of first type through stack structures and a second portion on the array of second type through stack structures; multiple vias each penetrating the semiconductor layer and in contact with a corresponding one of the first type through stack structures or the array of second type through stack structures; and a slit structure separating the array of first type through stack structures from the array of second type through stack structures, and separating the first portion of the semiconductor layer from the second portion of the semiconductor layer.

IPC Classes  ?

  • H10B 43/40 - EEPROM devices comprising charge-trapping gate insulators characterised by the peripheral circuit region
  • H10B 51/40 - Ferroelectric RAM [FeRAM] devices comprising ferroelectric memory transistors characterised by the peripheral circuit region
  • H10B 53/40 - Ferroelectric RAM [FeRAM] devices comprising ferroelectric memory capacitors characterised by the peripheral circuit region
  • H10B 80/00 - Assemblies of multiple devices comprising at least one memory device covered by this subclass
  • H10B 43/27 - EEPROM devices comprising charge-trapping gate insulators characterised by three-dimensional arrangements, e.g. with cells on different height levels with source and drain on different levels, e.g. with sloping channels the channels comprising vertical portions, e.g. U-shaped channels

97.

MEMORY DEVICE, MEMORY SYSTEM, AND OPERATING METHOD THEREOF

      
Application Number CN2023101998
Publication Number 2023/246931
Status In Force
Filing Date 2023-06-22
Publication Date 2023-12-28
Owner YANGTZE MEMORY TECHNOLOGIES CO., LTD. (China)
Inventor Guo, Xiaojiang

Abstract

A memory device, a memory system, and a method thereof are provided. In the method, an N-th programming pulse is applied to a word line coupled to memory cells of the memory device each with a target programming state being an i-th programming state. A first sub-verification and an M-th second sub-verification are performed on the memory cells to obtain a first sub-result and an M-th second sub-result, respectively. Based on the M-th second sub-result, a subset of the memory cells is determined to be programmed with an (N+1) -th programming pulse. Then, the (N+1) -th programming pulse is applied to the word line. After applying the (N+1) -th programming pulse to the word line, the memory cells are determined to be successfully programmed to the i-th programming state based on the first sub-result indicating that a number of failed bits in the first sub-verification is less than a first preset value.

IPC Classes  ?

98.

POWER LEAKAGE BLOCKING IN LOW-DROPOUT REGULATOR

      
Application Number 18242397
Status Pending
Filing Date 2023-09-05
First Publication Date 2023-12-21
Owner YANGTZE MEMORY TECHNOLOGIES CO., LTD. (China)
Inventor Wei, Ruxin

Abstract

In certain aspects, a circuit includes an amplifier, a first transistor, a second transistor, a third transistor, a signal pair generation circuit, and a leakage track bias generator circuit connected to the signal pair generation circuit. A gate terminal of the first transistor is connected to an output of the amplifier, and a first terminal of the first transistor is connected to an input of the amplifier. A first terminal of the second transistor is connected to a second terminal of the first transistor. A first terminal of the third transistor is connected to the first terminal of the first transistor, and a second terminal of the third transistor is connected to a second terminal of the second transistor. The signal pair generation circuit is connected to a gate terminal of the second transistor and a gate terminal of the third transistor. The leakage track bias generator circuit includes a resistor, and a first terminal of the resistor is connected to the ground.

IPC Classes  ?

  • G11C 16/30 - Power supply circuits
  • G05F 1/46 - Regulating voltage or current wherein the variable actually regulated by the final control device is dc
  • G05F 1/575 - Regulating voltage or current wherein the variable actually regulated by the final control device is dc using semiconductor devices in series with the load as final control devices characterised by the feedback circuit
  • H10B 41/41 - Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates characterised by the peripheral circuit region of a memory region comprising a cell select transistor, e.g. NAND
  • H10B 43/40 - EEPROM devices comprising charge-trapping gate insulators characterised by the peripheral circuit region

99.

THREE-DIMENSIONAL MEMORY DEVICE HAVING STAIRCASE STRUCTURE AND METHOD FOR FORMING THE SAME

      
Application Number 17843674
Status Pending
Filing Date 2022-06-17
First Publication Date 2023-12-21
Owner YANGTZE MEMORY TECHNOLOGIES CO., LTD. (China)
Inventor
  • Xu, Ling
  • Zhang, Zhong
  • Zhou, Wenxi
  • Wang, Di
  • Xia, Zhiliang
  • Huo, Zongliang

Abstract

A three-dimensional (3D) memory device includes interleaved conductive layers and dielectric layers. Edges of the conductive layers and dielectric layers define a plurality of stairs. The 3D memory device also includes a plurality of landing structures each over a respective conductive layer at a respective stair. Each of the landing structures includes a first layer having a first material and a second layer having a second material, the first layer being over the second layer.

IPC Classes  ?

  • H01L 27/11556 - Electrically programmable read-only memories; Multistep manufacturing processes therefor with floating gate characterised by three-dimensional arrangements, e.g. with cells on different height levels with source and drain on different levels, e.g. with sloping channels the channels comprising vertical portions, e.g. U-shaped channels
  • H01L 27/11521 - Electrically programmable read-only memories; Multistep manufacturing processes therefor with floating gate characterised by the memory core region

100.

THREE-DIMENSIONAL MEMORY DEVICE AND METHOD FOR FORMING THE SAME

      
Application Number 17845443
Status Pending
Filing Date 2022-06-21
First Publication Date 2023-12-21
Owner YANGTZE MEMORY TECHNOLOGIES CO., LTD. (China)
Inventor
  • Zhang, Kun
  • Zhou, Wenxi
  • Xia, Zhiliang
  • Wang, Di
  • Liu, Wei
  • Huo, Zongliang

Abstract

A three-dimensional (3D) memory device includes a plurality of memory planes and a separation block. Each memory plane includes a plurality of memory blocks. Each memory block includes a memory stack including interleaved conductive layers and first dielectric layers, and a plurality of channel structures each extending through the memory stack. The separation block extending laterally to separate each two adjacent memory planes. Each separation block includes a dielectric stack including interleaved second dielectric layers and the first dielectric layers. The first dielectric layers extend across the memory blocks and the separation block, and the second dielectric layers separate the conductive layers of two adjacent memory blocks.

IPC Classes  ?

  • H01L 27/11575 - Electrically programmable read-only memories; Multistep manufacturing processes therefor with charge-trapping gate insulators, e.g. MNOS or NROM characterised by the boundary region between the core and peripheral circuit regions
  • H01L 27/11582 - Electrically programmable read-only memories; Multistep manufacturing processes therefor with charge-trapping gate insulators, e.g. MNOS or NROM characterised by three-dimensional arrangements, e.g. with cells on different height levels with source and drain on different levels, e.g. with sloping channels the channels comprising vertical portions, e.g. U-shaped channels
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