Apparatuses, systems, and methods for data timing alignment with fast alignment mode. A stacked memory device includes an interface die and a number of core die. The interface and the core die each have an adjustable delay circuit adjusted by an interface delay code or a respective core delay code. The delay codes are adjusted based on a measured phase difference along a replica path. In a default maintenance state, the delay codes may be adjusted based on an average of the phase differences over time. Each time the phase difference matches a previous phase difference, the interface die changes a count value associated with that core die. If one or more of the count values cross a threshold, a state machine of the interface die enters a different delay adjustment state where averaging is not used. This may allow for correction of systemic errors such as voltage drift.
A method used in forming a memory array comprising strings of memory cells comprises forming a stack comprising vertically-alternating first tiers and second tiers. A channel-material string is in individual channel openings in the vertically-alternating first tiers and second tiers. A conductor-material contact is in the individual channel openings directly against the channel material of individual of the channel-material strings. The conductor-material contacts are vertically recessed in the individual channel openings. A conductive via is formed in the individual channel openings directly against the vertically-recessed conductor-material contact in that individual channel opening. Other aspects, including structure independent of method, are disclosed.
H10B 41/27 - Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates characterised by three-dimensional arrangements, e.g. with cells on different height levels with source and drain on different levels, e.g. with sloping channels the channels comprising vertical portions, e.g. U-shaped channels
H01L 23/522 - Arrangements for conducting electric current within the device in operation from one component to another including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
H10B 41/10 - Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates characterised by the top-view layout
H10B 43/10 - EEPROM devices comprising charge-trapping gate insulators characterised by the top-view layout
H10B 43/27 - EEPROM devices comprising charge-trapping gate insulators characterised by three-dimensional arrangements, e.g. with cells on different height levels with source and drain on different levels, e.g. with sloping channels the channels comprising vertical portions, e.g. U-shaped channels
H10B 43/35 - EEPROM devices comprising charge-trapping gate insulators characterised by the memory core region with cell select transistors, e.g. NAND
3.
VOLTAGE REGULATOR SUPPLY FOR INDEPENDENT WORDLINE READS
A system includes a memory device having one or more planes and a first set of voltage regulators coupled to each plane of the one or more planes, where the first set of voltage regulators is shared by the one or more planes. The system includes a second set of voltage regulators coupled to a plane of the one or more planes configured to supply a respective voltage to one or more conductive lines responsive to a memory access operation request. The system includes a switch, at the plane of the one or more planes, coupled with a first voltage regulator of the first set of voltage regulators, a second voltage regulator of the second set of voltage regulators, and a first conductive line, the switch configured to selectively couple the second voltage regulator of the second set of voltage regulators to the first conductive line.
Apparatuses and methods for determining performing write operations on a number of planes are provided. One example apparatus can include a controller configured to associate a first number of blocks together, wherein each of the first number of blocks are each located on different planes, receive commands to write data to a first page on the number of first blocks, and write data to the first page of each of the first number of blocks during a first time period.
A system can include a memory device and a processing device, operatively coupled with the memory device, to perform operations including reading a first copy of data stored in a first set of memory cells comprising a first memory cell, determining whether a threshold voltage of the first memory cell is within a first range of threshold voltages, responsive to determining that the threshold voltage of the first memory cell is within the first range of threshold voltages, reading a second copy of the data stored in a second set of memory cells comprising a second memory cell, determining whether a threshold voltage of the second memory cell is within a second range of threshold voltages, and responsive to determining that the threshold voltage of the second memory cell is outside the second range, using the second copy of the data.
Disclosed in some examples are systems, devices, machine-readable mediums, and methods for customizing an in-memory versioning mode for each memory location according to a predicted access behavior to optimize memory device performance. Usage data in a previous time period may be utilized along with policy rules to determine whether to configure a particular memory address as a zero copy or direct copy mode. For example, memory addresses that are read frequently may be configured as direct copy mode to reduce the read latency penalty. This improves the functioning of the memory system by reducing read latency for memory addresses that are frequently read but written to less frequently, and reduces write latency for memory locations that are frequently written to, but not read as frequently.
Self-identifying solid-state transducer (SST) modules and associated systems and methods are disclosed herein. In several embodiments, for example, an SST system can include a driver and at least one SST module electrically coupled to the driver. Each SST module can include an SST and a sense resistor. The sense resistors of each SST module can have at least substantially similar resistance values. The SSTs of the SST modules can be coupled in parallel across an SST channel to the driver, and the sense resistors of the SST modules can be coupled in parallel across a sense channel to the driver. The driver can be configured to measure a sense resistance across the sense resistors and deliver a current across the SSTs based on the sense resistance.
H05B 45/345 - Current stabilisation; Maintaining constant current
H01L 25/16 - Assemblies consisting of a plurality of individual semiconductor or other solid state devices the devices being of types provided for in two or more different main groups of groups , or in a single subclass of , , e.g. forming hybrid circuits
H01L 33/00 - SEMICONDUCTOR DEVICES NOT COVERED BY CLASS - Details thereof
H01L 33/62 - Arrangements for conducting electric current to or from the semiconductor body, e.g. leadframe, wire-bond or solder balls
H05B 45/00 - Circuit arrangements for operating light-emitting diodes [LED]
H05B 45/46 - Circuit arrangements for operating light-emitting diodes [LED] - Details of LED load circuits with an active control inside an LED matrix having LEDs disposed in parallel lines
Associative processing memory (APM) may be used to align reads to a reference sequence. The APM may store shifted permutations and/or other permutations of the reference sequence. A read may be compared to some or all of the permutations of the reference sequence and the APM may provide an output for each comparison. In some examples, the APM may compare the read to many permutations of the reference sequence to the read in parallel. Inferences may be made based on the comparisons between the read and the portions and/or permutations of a reference sequence. Based on the inferences, a candidate alignment location in the reference sequence for a read to be determined.
Aspects of the present disclosure configure a system component, such as a memory sub-system controller, to identify a center of valley (CoV) of a set of read levels. The controller detects a read error associated with reading data from the set of memory components in accordance with an individual read level of a plurality of read levels and, in response to detecting the read error, generates a plurality of bins as a function of a plurality of check failure bit count values and one or more error count values corresponding to a set of read levels adjacent to the individual read level. The controller computes the CoV for the individual read level based on a pair of read levels defined by a set of the plurality of bins and updates a read level used to read the data based on the computed CoV.
Sacrificial pillars for a semiconductor device assembly, and associated methods and systems are disclosed. In one embodiment, a region of a semiconductor die may be identified to include sacrificial pillars that are not connected to bond pads of the semiconductor die, in addition to live conductive pillars connected to the bond pads. The region with the sacrificial pillars, when disposed in proximity to the live conductive pillars, may prevent an areal density of the live conductive pillars from experiencing an abrupt change that may result in intolerable variations in heights of the live conductive pillars. As such, the sacrificial pillars may improve a coplanarity of the live conductive pillars by reducing variations in the heights of the live conductive pillars. Thereafter, the sacrificial pillars may be removed from the semiconductor die.
Methods, systems, and devices for command timer interrupt are described. In some cases, a memory system having a host-driven logical block interface may maintain a timer to measure processing of commands. For example, upon receiving a command and storing the command in a command queue, a protocol controller of the memory system may issue the command to a command controller of the memory system and initiate the timer. Upon receiving a response for the command from the command controller, the protocol controller may reset or stop the timer, depending on whether the command queue is empty. If the timer expires prior to receiving a response for the command, the protocol controller may issue an interrupt signal to the command controller.
Implementations described herein relate to command address fault detection using a parity bit. A memory device may receive, from a host device via a command address (CA) bus and during a unit interval, a set of CA bits associated with a CA word. The memory device may receive, from the host device via a parity bus and during the unit interval, a first parity bit that is based on the set of CA bits and a parity generation process. The memory device may generate a second parity bit based on the set of CA bits and the parity generation process. The memory device may compare the first parity bit and the second parity bit. The memory device may selectively transmit an alert signal to the host device based on a result of comparing the first parity bit and the second parity bit.
A method including storing user data in memory cells of a memory array, storing, in a counter associated to the memory cells, count data corresponding to a number of bits in the user data having a predetermined first logic value, applying a read voltage to the memory cells to read the user data, applying the read voltage to the cells of the counter to read the count data and to provide a target value corresponding to the number of bits in the user data having the first logic value. During the application of the read voltage, the count data and the user data are read simultaneously such that the target value is provided during the reading of the user data. The application of the read voltage is stopped when the number of bits in the user data having the first logic value corresponds to the target value.
Systems and methods for a semiconductor device having a front-end-of-line interconnect structure are provided. The semiconductor device may include a dielectric material having a backside formed on a front side of a semiconductor or silicon substrate material and a front side, and a conducting material on the front side of the dielectric material. The conducting material may have a line portion and an interconnect structure electrically coupled to the line portion and separated from the front side of the substrate material by the dielectric material. The interconnect structure has a backside defining a contact surface. The semiconductor device may further include a semiconductor die proximate the front side of the dielectric material, an insulating material encasing at least a portion of the semiconductor die, and an opening through which the active contact surface at the backside of the interconnect structure is exposed for electrical connection.
H01L 23/538 - Arrangements for conducting electric current within the device in operation from one component to another the interconnection structure between a plurality of semiconductor chips being formed on, or in, insulating substrates
H01L 21/50 - Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the groups
H01L 21/768 - Applying interconnections to be used for carrying current between separate components within a device
H01L 27/06 - Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body including a plurality of individual components in a non-repetitive configuration
H01L 27/092 - Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only the components being field-effect transistors with insulated gate complementary MIS field-effect transistors
15.
SOLID STATE TRANSDUCER DIES HAVING REFLECTIVE FEATURES OVER CONTACTS AND ASSOCIATED SYSTEMS AND METHODS
Systems and methods for improved light emitting efficiency of a solid state transducer (SST), for example light emitting diodes (LED), are disclosed. One embodiment of an SST die in accordance with the technology includes a reflective material disposed over electrical connectors on a front side of the die. The reflective material has a higher reflectivity than a base material of the connectors such that light traveling toward the connectors reflects back out of the device.
H01L 33/06 - SEMICONDUCTOR DEVICES NOT COVERED BY CLASS - Details thereof characterised by the semiconductor bodies with a quantum effect structure or superlattice, e.g. tunnel junction within the light emitting region, e.g. quantum confinement structure or tunnel barrier
H01L 33/32 - Materials of the light emitting region containing only elements of group III and group V of the periodic system containing nitrogen
Semiconductor devices including one or more interfacing segments patterned within an outer protective layer and associated systems and methods are disclosed herein. The one or more interfacing segments may provide attachment interfaces/surfaces for connection pads. The one or more interfacing segments or a portion thereof may remain uncovered or exposed and provide warpage control for the corresponding semiconductor device.
Methods, apparatuses and systems related to reading data from memory cells configured to store more than one bit are described. The apparatus may be configured to determine a polarity data associated with reading data stored at a target location. In reading the data stored at the target location, the apparatus may apply one or more voltage levels across different polarities according to the determined polarity data.
A request is received to perform a multi-plane operation for first data of a first plane and second data of a second plane of a memory device. Responsive to the request, first trim values are retrieved from first trim registers and second trim values are retrieved from second trim registers, the first trim values loaded to the first registers based on a first voltage distribution observed at the first plane during a first time period and the second trim values loaded to the second registers based on a second voltage distribution observed at the second plane during a second time period. The multi-plane operation is performed using at least the first trim values for the first data at the first plane and at least the second trim values for the second data at the second plane.
Associative processing memory (APM) may be used to align reads to a reference sequence. The APM may store shifted permutations and/or other permutations of the reference sequence. A read may be compared to some or all of the permutations of the reference sequence and the APM may provide an output for each comparison. In some examples, the APM may compare the read to many permutations of the reference sequence to the read in parallel. Inferences may be made based on the comparisons between the read and the portions and/or permutations of a reference sequence. Based on the inferences, a candidate alignment location in the reference sequence for a read to be determined.
Implementations described herein relate to a cluster namespace for a memory device. In some implementations, a memory device may receive a cluster namespace instruction, from a host device, that instructs the memory device to create a cluster namespace using memory resources of the memory device that are spread across a plurality of namespaces of the memory device. The memory device may identify namespace storage information that indicates memory resources associated with a plurality of namespaces of the memory device. The memory device may create the cluster namespace based on creating a plurality of extents that respectively map sets of logical block address ranges from the plurality of namespaces to the cluster namespace.
A digital thermometer includes a first oscillator to generate a first clock signal, wherein a period of the first clock signal remains constant in view of changes in a temperature of the apparatus and a first counter coupled to the first oscillator, the first counter to count a fixed number of cycles of the first clock signal associated with a measurement period. The digital thermometer further includes a second oscillator to generate a second clock signal, wherein a period of the second clock signal varies with changes in the temperature and a second counter coupled to the second oscillator, the second counter to generate an output representing a count of a number of cycles of the second clock signal that occur during the measurement period. In addition, the digital thermometer includes calibration circuitry coupled to the second counter, the calibration circuitry to calibrate the output of the second counter to generate a value representing the temperature of the apparatus.
Apparatuses and methods for read source determination are provided. One example apparatus can include a controller configured to determine a source for read requests and to direct read requests for a first portion of data to a first block of single level memory cells in response to an amount of a second portion of data written to a second block of single level memory cells being less than a threshold amount, and direct read requests for the first portion of data to a first block of quad level memory cells in response to the amount of the second portion of data written to the second block of single level memory cells being at least the threshold amount.
A structure for coupling an optical signal between an integrated circuit photonic structure and an external optical fiber is disclosed as in a method of formation. The coupling structure is sloped relative to a horizontal surface of the photonic structure such that light entering or leaving the photonic structure is substantially normal to its upper surface.
A microelectronic device comprises an access device comprising a source region and a drain region spaced from the source region, an insulative material vertically adjacent to the access device, and a capacitor within the insulative material and in electrical communication with the access device. The capacitor comprises a material comprising silicon oxynitride or titanium silicon nitride over surfaces of the insulative material, a first electrode comprising titanium nitride on the material, a dielectric material over the first electrode, and a second electrode on the dielectric material. Related methods of forming the microelectronic device and an electronic system including the microelectronic devices are also described.
Devices and techniques for continuous in-memory versioning are described herein. A memory subsystem includes a memory device configured to store a first data unit, a second data unit, and a third data unit, wherein the first, second, and third data units have a set of physical memory locations on the memory device, and metadata associated with the first, second, and third data units, the metadata including state information and a dirty commit timestamp; and a processing device, operatively coupled to the memory device, the processing device configured to: receive, from a host system, a first memory command associated with a logical memory address, the logical memory address mapped to the set of physical memory locations of the memory device; and in response to receiving the first memory command, perform a data operation on the first, second, or third data unit based on the state information and the dirty commit timestamp.
A processing device identifies a first set of bits associated with a translation unit of a memory device, wherein the first set of bits correspond to a page field; identifies a second set of bits associated with the translation unit, wherein the second set of bits corresponds to a block field; updates a first portion of an address mapping table corresponding to the second set of bits with a value representing a difference between a value stored in the page field and a threshold value; updates a second portion of the address mapping table corresponding to the first set of bits with a value representing a block number; determines, based on the updated first portion and the updated second portion, that a swapping condition is satisfied; and performs a data access operation on a set of memory cells residing at a location corresponding to the translation unit.
Methods, systems, and devices for error protection for managed memory devices are described. In some examples, a memory system may receive data units from a host device. The data units may include respective sets of parity bits, and the memory system may perform an error detection operation on the data units. A first controller of the memory system may generate a protocol unit using data (e.g., a subset of data) from the data units. The protocol unit may include a set of parity bits (e.g., a different set of parity bits), and a second controller of the memory system may perform an error detection operation on the protocol unit. The second controller of the memory system may generate a data storage unit using data (e.g., a subset of data) from the protocol unit, and may store the data unit and another set of parity bits to a memory device.
H03M 13/09 - Error detection only, e.g. using cyclic redundancy check [CRC] codes or single parity bit
H03M 13/00 - Coding, decoding or code conversion, for error detection or error correction; Coding theory basic assumptions; Coding bounds; Error probability evaluation methods; Channel models; Simulation or testing of codes
Methods, systems, and devices for command and data path error protection are described. In some examples, a memory system may receive data units from a host device. The data units may include respective sets of parity bits, and the memory system may perform an error detection operation on the data units. A first controller of the memory system may generate a protocol unit using data (e.g., a subset of data) from the data units. The protocol unit may include a set of parity bits (e.g., a different set of parity bits), and a second controller of the memory system may perform an error detection operation on the protocol unit. The second controller of the memory system may generate a data storage unit using data (e.g., a subset of data) from the protocol unit, and may store the data unit and another set of parity bits to a memory device.
In some implementations, a server device may generate a machine readable code that conveys first information associated with a first entity. The server device may provide an indication of the machine readable code that indicates the first information. The server device may obtain a request to update information conveyed by the machine readable code, the request including an indication of at least one of the machine readable code or the first information. The server device may modify the first information conveyed by the machine readable code to second information, based on the request and based on authenticating the request, wherein the second information includes a first secure information layer indicating the first information and a second secure information layer indicating information indicated by the request. The server device may provide, to the communication device, an indication of at least one of the machine readable code or the second information.
G06K 19/06 - Record carriers for use with machines and with at least a part designed to carry digital markings characterised by the kind of the digital marking, e.g. shape, nature, code
Some embodiments include apparatuses and methods using a substrate, a pillar having a length perpendicular to the substrate, a first conductive plate, a second conductive plate, a memory cell located between the first and second conductive plates and electrically separated from the first and second conductive plates, and a conductive connection. The first conductive plate is located in a first level of the apparatus and being separated from the pillar by a first dielectric located in the first level. The second conductive plate is located in a second level of the apparatus and being separated from the pillar by a second dielectric located in the second level. The memory cell includes a first semiconductor material located in a third level of the apparatus between the first and second levels and contacting the pillar and the conductive connection, and a second semiconductor material located in a fourth level of the apparatus between the first and second levels and contacting the pillar.
H10B 99/00 - Subject matter not provided for in other groups of this subclass
H01L 27/12 - Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being other than a semiconductor body, e.g. an insulating body
H01L 29/24 - Semiconductor bodies characterised by the materials of which they are formed including, apart from doping materials or other impurities, only inorganic semiconductor materials not provided for in groups , , or
Systems, methods, and apparatus for a memory device that stores a scrub list in a cache used to reduce data traffic to and from a memory array. In one approach, the cache merges the scrub list with cache data. Data in the scrub list can be identified and distinguished from the cache data by adding a one-bit scrub flag to each data entry in the merged cache. In this merged approach, the cache data shares the same memory as the scrub list. Read data that has an error is saved temporarily in this merged cache until the correct value for the data is written back into the memory array.
G06F 12/0891 - Addressing of a memory level in which the access to the desired data or data block requires associative addressing means, e.g. caches using clearing, invalidating or resetting means
A method includes selectively configuring a first subset of non-volatile memory blocks to operate in a single-level mode, configuring the first subset of non-volatile memory blocks to collectively operate as a pseudo single-level cache, writing data associated with performance of a memory operation to the first subset of non-volatile memory blocks, and migrating the data from the first subset of non-volatile memory blocks to a second subset of non-volatile memory blocks.
Substrates for semiconductor packages, including hybrid substrates for decoupling capacitors, and associated devices, systems, and methods are disclosed herein. In one embodiment, a substrate includes a first pair and a second pair of electrical contacts on a first surface of the substrate. The first pair of electrical contacts can be configured to receive a first surface-mount capacitor, and the second pair of electrical contacts can be configured to receive a second surface-mount capacitor. The first pair of electrical contacts can be spaced apart by a first space, and the second pair of electrical contacts can be spaced apart by a second space. The first and second spaces can correspond to corresponding to first and second distances between electrical contacts of the first and second surface-mount capacitors.
H01L 27/08 - Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body including only semiconductor components of a single kind
34.
VERTICAL SOLID-STATE TRANSDUCERS AND HIGH VOLTAGE SOLID-STATE TRANSDUCERS HAVING BURIED CONTACTS AND ASSOCIATED SYSTEMS AND METHODS
Solid-state transducers (“SSTs”) and vertical high voltage SSTs having buried contacts are disclosed herein. An SST die in accordance with a particular embodiment can include a transducer structure having a first semiconductor material at a first side of the transducer structure, and a second semiconductor material at a second side of the transducer structure. The SST can further include a plurality of first contacts at the first side and electrically coupled to the first semiconductor material, and a plurality of second contacts extending from the first side to the second semiconductor material and electrically coupled to the second semiconductor material. An interconnect can be formed between at least one first contact and one second contact. The interconnects can be covered with a plurality of package materials.
H01L 33/62 - Arrangements for conducting electric current to or from the semiconductor body, e.g. leadframe, wire-bond or solder balls
H01L 21/78 - Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
H01L 25/075 - Assemblies consisting of a plurality of individual semiconductor or other solid state devices all the devices being of a type provided for in the same subgroup of groups , or in a single subclass of , , e.g. assemblies of rectifier diodes the devices not having separate containers the devices being of a type provided for in group
H01L 27/04 - Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body
H01L 27/15 - Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components with at least one potential-jump barrier or surface barrier, specially adapted for light emission
H01L 33/00 - SEMICONDUCTOR DEVICES NOT COVERED BY CLASS - Details thereof
H01L 33/06 - SEMICONDUCTOR DEVICES NOT COVERED BY CLASS - Details thereof characterised by the semiconductor bodies with a quantum effect structure or superlattice, e.g. tunnel junction within the light emitting region, e.g. quantum confinement structure or tunnel barrier
H01L 33/32 - Materials of the light emitting region containing only elements of group III and group V of the periodic system containing nitrogen
H01L 33/38 - SEMICONDUCTOR DEVICES NOT COVERED BY CLASS - Details thereof characterised by the electrodes with a particular shape
Methods, systems, and devices for address verification at a memory device are described. The memory device may receive a read command for a read address. Based on the read command, the memory device may read data from the read address and a first set of error detection bits that is based on a write address associated with the data. The memory device may generate, based on the first set of error detection bits and a second set of error detection bits that is based on the read address, an address match signal that indicates whether the read address matches the write address. And the memory device may provide the data and an indication of the address match signal to a host device.
A memory controller and a physical interface layer may accommodate multiple memory types. In some examples, the memory controller and/or PHY may include a register that includes operating parameters for multiple operating modes. Different operating modes may be compatible with different memory types. In some examples, the memory controller and physical interface may be included in a system for testing multiple memory types. The system may provide multiple interfaces for communicating with the memory. The different communication types may be used for performing different tests and/or simulating different types of devices that may utilize the memory.
Methods, systems, and devices for single crystal silicon cores for stacked memory cells are described. A memory device may be formed using silicon cores that are each associated with a set of multiple memory cells. Multiple silicon cores may extend along a first direction, and multiple sleeves of memory materials and conductive materials may be formed around each silicon core. Each sleeve of memory materials may be associated with a respective memory cell and each conductive material may be associated with a word line, such that each silicon core may be associated with multiple memory cells. The respective sleeves of memory materials and conductive materials may be formed from larger sleeves of material that may be etched into sections of the memory materials and the conductive materials along the silicon cores.
H01L 27/1157 - Electrically programmable read-only memories; Multistep manufacturing processes therefor with charge-trapping gate insulators, e.g. MNOS or NROM characterised by the memory core region with cell select transistors, e.g. NAND
G11C 5/06 - Arrangements for interconnecting storage elements electrically, e.g. by wiring
H01L 27/11524 - Electrically programmable read-only memories; Multistep manufacturing processes therefor with floating gate characterised by the memory core region with cell select transistors, e.g. NAND
H01L 27/11578 - Electrically programmable read-only memories; Multistep manufacturing processes therefor with charge-trapping gate insulators, e.g. MNOS or NROM characterised by three-dimensional arrangements, e.g. with cells on different height levels
Methods, systems, and devices for differential storage in memory arrays are described. A memory device may include pairs of memory cells configured to store a single logic state (e.g., a single bit of information). Additionally, the memory device may include sense amplifiers configured to sense the logic state based on a difference between a voltage of a first ferroelectric memory cell of the pair of memory cells and a voltage of a second ferroelectric memory cell of the pair of memory cells. In one example, the memory device may include pairs of memory cells within a single memory array on a single level. Here, each memory cell pair may include a memory cells that are each coupled with a same word line and plate line. Additionally, each memory cell pair may include memory cells each coupled with different digit lines.
G11C 11/22 - Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using ferroelectric elements
An electronic device comprising a lower deck and an upper deck adjacent to a source. Each of the lower deck and the upper deck comprise tiers of alternating conductive materials and dielectric materials. Each of the lower deck and the upper deck also comprise an array region and one or more non-array regions. Memory pillars are in the lower deck and the upper deck of the array region and the memory pillars are configured to be operably coupled to the source. Dummy pillars are in the upper deck of the one or more non-array regions and the dummy pillars are configured to be electrically isolated from the source. Another conductive material is in the upper deck and the lower deck of the one or more non-array regions. Additional electronic devices and related systems and methods of forming an electronic device are also disclosed.
H10B 43/35 - EEPROM devices comprising charge-trapping gate insulators characterised by the memory core region with cell select transistors, e.g. NAND
H10B 41/27 - Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates characterised by three-dimensional arrangements, e.g. with cells on different height levels with source and drain on different levels, e.g. with sloping channels the channels comprising vertical portions, e.g. U-shaped channels
H10B 41/35 - Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates characterised by the memory core region with a cell select transistor, e.g. NAND
H10B 43/20 - EEPROM devices comprising charge-trapping gate insulators characterised by three-dimensional arrangements, e.g. with cells on different height levels
A single memory chip including both memory and storage capabilities on the single chip and accompanying process for forming a memory array including both capabilities is disclosed. In particular, the single chip may incorporate the use of two different chalcogenide materials deposited thereon to implement the memory and storage capabilities. Chalcogenide materials provide flexibility on cell performance, such as by changing the chalcogenide material composition. For the single memory chip, one type of chalcogenide material may be utilized to create memory cells and another type of chalcogenide material may be utilized to create storage cells. The process for forming the memory array includes forming first and second openings in a starting structure and performing a series of etching and deposition steps on the structure to form the memory and storage cells using the two different chalcogenide compositions. The memory and storage cells are independently addressable via wordline and bitline selection.
H01L 27/24 - Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including solid state components for rectifying, amplifying, or switching without a potential-jump barrier or surface barrier
H01L 45/00 - Solid state devices specially adapted for rectifying, amplifying, oscillating, or switching without a potential-jump barrier or surface barrier, e.g. dielectric triodes; Ovshinsky-effect devices; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof
A memory system includes a memory array having a plurality of memory cells; and a controller coupled to the memory array, the controller configured to: designate a storage mode for a target set of memory cells based on valid data in a source block, wherein the target set of memory cells are configured with a capacity to store up to a maximum number of bits per cell, and the storage mode is for dynamically configuring the target set of memory cells in as cache memory that stores a number of bits less per cell than the corresponding maximum capacity.
G06F 3/06 - Digital input from, or digital output to, record carriers
G06F 12/00 - Accessing, addressing or allocating within memory systems or architectures
G06F 12/06 - Addressing a physical block of locations, e.g. base addressing, module addressing, address space extension, memory dedication
G06F 12/0891 - Addressing of a memory level in which the access to the desired data or data block requires associative addressing means, e.g. caches using clearing, invalidating or resetting means
Apparatuses, systems, and methods for adapting a read disturb scan. One example method can include determining a delay between a first read command and a second read command, incrementing a read count based on the determined delay between the first read command and the second read command, and adapting a read disturb scan rate based on the incremented read count.
A processing device is configured to process an initial set of command types. A command extension module and a digital signature are received. The digital signature is generated based on the command extension module using a private key of a key pair. The command extension module, once installed by the processing device, enables the processing device to process a new command type that is not included in the initial set of command types. The digital signature is verified using a public key of the key pair. Based on a successful verification of the digital signature, the command extension module is temporarily installed by loading the command extension module in a volatile memory device.
G06F 12/14 - Protection against unauthorised use of memory
G06F 21/78 - Protecting specific internal or peripheral components, in which the protection of a component leads to protection of the entire computer to assure secure storage of data
H04L 9/32 - Arrangements for secret or secure communications; Network security protocols including means for verifying the identity or authority of a user of the system
44.
INDICATING A STATUS OF A MEMORY BUILT-IN SELF-TEST
Implementations described herein relate to performing a memory built-in self-test and indicating a status of the memory built-in self-test. A memory device may read one or more bits, associated with a memory built-in self-test, that are stored in a mode register of the memory device. The memory device may identify, based on the one or more bits, that the memory built-in self-test is enabled. The memory device may set a DMI bit of the memory device to a first value and perform the memory built-in self-test based on identifying that the memory built-in self-test is enabled. The memory device may set the DMI bit of the memory device to a second value based on a completion of the memory built-in self-test.
A system can include a memory device and a processing device coupled with the memory device. The processing device can receive, from a host system, a command of a type; determine a weighted count of the command according to the type of the command; track, based on the weighted count, a first count of commands of the type; determine whether the first count of commands of the type satisfies a threshold criterion for commands of the type; and responsive to determining that the first count of commands of the type satisfies the threshold criterion, transmit a notification to the host system to refrain from transmitting commands of the type.
A microelectronic device comprising tiers of alternating dielectric materials and conductive materials, pillars extending through the tiers, and a doped dielectric material adjacent to the tiers. The doped dielectric material comprises a heterogeneous chemical composition comprising one or more dopants. Conductive contact structures are in the doped dielectric material. Additional microelectronic devices, microelectronic systems, and methods of forming microelectronic devices are disclosed.
H01L 27/11582 - Electrically programmable read-only memories; Multistep manufacturing processes therefor with charge-trapping gate insulators, e.g. MNOS or NROM characterised by three-dimensional arrangements, e.g. with cells on different height levels with source and drain on different levels, e.g. with sloping channels the channels comprising vertical portions, e.g. U-shaped channels
47.
DIELECTRIC INTERPOSER WITH ELECTRICAL-CONNECTION CUT-IN
Implementations described herein relate to various semiconductor device assemblies. In some implementations, a semiconductor device assembly may include a base layer, a dielectric interposer coupled to the base layer and including a first outer surface facing the base layer and an opposing second outer surface facing away from the base layer and spaced apart from the first outer surface in a direction, a first electrical-connection cut-in in the second outer surface that extends, in the direction, toward the first outer surface, and one or more first electrical connections disposed within the first electrical-connection cut-in such that at least a portion of the one or more first electrical connections does not extend, in the direction, beyond the second outer surface.
H01L 21/48 - Manufacture or treatment of parts, e.g. containers, prior to assembly of the devices, using processes not provided for in a single one of the groups
H01L 23/00 - SEMICONDUCTOR DEVICES NOT COVERED BY CLASS - Details of semiconductor or other solid state devices
H01L 25/00 - Assemblies consisting of a plurality of individual semiconductor or other solid state devices
H01L 25/065 - Assemblies consisting of a plurality of individual semiconductor or other solid state devices all the devices being of a type provided for in the same subgroup of groups , or in a single subclass of , , e.g. assemblies of rectifier diodes the devices not having separate containers the devices being of a type provided for in group
48.
MANAGING A MEMORY SUB-SYSTEM USING A CROSS-HATCH CURSOR
One or more data items is received by a processing device managing one or more memory devices partitioned into a plurality of die partitions. The one or more data items is determined to be written sequentially to one or more blocks within a die partition of the plurality of die partitions. Metadata associated with the one or more data items is written sequentially to one or more blocks across the plurality of die partitions.
Disclosed is a three-dimensional memory device. In one embodiment, a device is disclosed comprising a source plate; plugs fabricated on or partially formed in the source plate; a stack formed on the substrate and plugs comprising alternating insulating layers and conductive layers and channel-material strings of memory cells extending through the insulating layers and conductive layers; a first set of pillars extending through the stack formed by a process including etching the alternating insulating layers and conductive layers and depositing a pillar material therein, wherein each pillar in the first set of pillars terminates atop a respective plug in the plurality of plugs; and a second set of pillars extending through the stack formed by a process including etching the alternating insulating layers and conductive layers and depositing a pillar material therein, wherein each pillar in the second set of pillars terminates in the source plate.
H01L 23/00 - SEMICONDUCTOR DEVICES NOT COVERED BY CLASS - Details of semiconductor or other solid state devices
H01L 21/768 - Applying interconnections to be used for carrying current between separate components within a device
H01L 23/535 - Arrangements for conducting electric current within the device in operation from one component to another including internal interconnections, e.g. cross-under constructions
H10B 41/10 - Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates characterised by the top-view layout
H10B 41/27 - Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates characterised by three-dimensional arrangements, e.g. with cells on different height levels with source and drain on different levels, e.g. with sloping channels the channels comprising vertical portions, e.g. U-shaped channels
H10B 41/50 - Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates characterised by the boundary region between the core region and the peripheral circuit region
H10B 43/10 - EEPROM devices comprising charge-trapping gate insulators characterised by the top-view layout
H10B 43/27 - EEPROM devices comprising charge-trapping gate insulators characterised by three-dimensional arrangements, e.g. with cells on different height levels with source and drain on different levels, e.g. with sloping channels the channels comprising vertical portions, e.g. U-shaped channels
H10B 43/50 - EEPROM devices comprising charge-trapping gate insulators characterised by the boundary region between the core and peripheral circuit regions
50.
EXTENDED ADDRESS INTERFACE ACTIVATE SEQUENCE USING MODE REGISTER WRITE
A method and a device is provided for implementing a mode register to transmit additional activate information to a memory device. Additional activate information may be transmitted to the memory device without increasing the tRCD time, or increasing the command/address (CA) bus pins, or adding additional circuit area, thereby reducing the impact on the performance of the memory device.
An electronic device comprising a cell region comprising stacks of alternating dielectric materials and conductive materials. A pillar region is adjacent to the cell region and comprises storage node segments adjacent to adjoining oxide materials and adjacent to a tunnel region. The storage node segments are separated by a vertical portion of the tunnel region. A high-k dielectric material is adjacent to the conductive materials of the cell region and to the adjoining oxide materials of the pillar region. Additional electronic devices are disclosed, as are methods of forming an electronic device and related systems.
H10B 43/27 - EEPROM devices comprising charge-trapping gate insulators characterised by three-dimensional arrangements, e.g. with cells on different height levels with source and drain on different levels, e.g. with sloping channels the channels comprising vertical portions, e.g. U-shaped channels
Apparatuses, systems, and methods for buffer threshold monitoring to reduce data loss are provided herein. In a number of embodiments of the present disclosure, a method can include buffering data in a first memory device, writing the buffered data from the first memory device to a second memory device, determining that the first memory device is storing at least a threshold amount of data, and sending a first signal to the second memory device in response to determining that the first memory device is storing at least the threshold amount of data, wherein the first signal causes the second memory device to enter an increased write performance mode.
Methods, systems, and devices for dynamic voltage supply for memory circuit are described. An apparatus may adjust a supply voltage based on a process corner and a temperature of the memory system. An apparatus may include a memory array and a controller. The controller may determine a first temperature of the apparatus is less than a first temperature threshold at a first time. The controller may transition a voltage supplied to the controller from a first voltage level to a second voltage level based on determining the first temperature is less than the first temperature threshold. The controller may determine a second temperature is greater than a second temperature threshold at a second time. The controller may transition the voltage supplied to the controller from the second voltage level to the first voltage level based on determining the second temperature is greater than the second temperature threshold.
Methods, systems, and devices for depositing carbon conducting films by atomic layer deposition are described. For instance, a device may react a first precursor with a base material to form a carbon compound on a material, where the first precursor is an acetylene, a diacetylene, a tri-acetylene, a polyacetylene, an alkene, or an arene and includes at least one germanium, silicon, or tin. Additionally, the device may react a second, carbon-containing precursor with the carbon compound to form a layer on the base material.
C23C 16/455 - Chemical coating by decomposition of gaseous compounds, without leaving reaction products of surface material in the coating, i.e. chemical vapour deposition (CVD) processes characterised by the method of coating characterised by the method used for introducing gases into the reaction chamber or for modifying gas flows in the reaction chamber
C01B 32/05 - Preparation or purification of carbon not covered by groups , , ,
Systems, apparatuses, and methods related to a controller architecture for read data alignment are described. An example method can include sending a first notification from a physical layer to each of a number of memory controllers, wherein the first notification indicates that the physical layer and/or a memory device coupled to the physical layer is busy, and blocking commands on each of the number of memory controllers in response to receiving the first notification to cause read data alignment. The method can also include sending a second notification from the physical layer to each of the number of memory controllers, wherein the second notification indicates that the physical layer and/or the memory device coupled to the physical layer is no longer busy, and resuming processing commands on each of the number of memory controllers in response to receiving the second notification.
Methods, systems, and devices for speed bins to support memory compatibility are described. A host device may read a value of a register including serial presence detect data of a memory module. The serial presence detect data may be indicative of a timing constraint for operating the memory module at a first clock rate, where the timing constraint and the first clock rate may be associated with a first speed bin. The host device may select, for communication with the memory module, a second speed bin associated with a second clock rate at the host device and the timing constraint, where the host device may support operations according to a set of timing constraints that includes a set of values. The timing constraint may be selected from a subset of the set of timing constraints, where the subset may be exclusive of at least one of the set of values.
Stacked semiconductor die assemblies with support members and associated systems and methods are disclosed herein. In one embodiment, a semiconductor die assembly can include a package substrate, a first semiconductor die attached to the package substrate, and a plurality of support members also attached to the package substrate. The plurality of support members can include a first support member and a second support member disposed at opposite sides of the first semiconductor die, and a second semiconductor die can be coupled to the support members such that at least a portion of the second semiconductor die is over the first semiconductor die.
H01L 25/00 - Assemblies consisting of a plurality of individual semiconductor or other solid state devices
H01L 23/00 - SEMICONDUCTOR DEVICES NOT COVERED BY CLASS - Details of semiconductor or other solid state devices
H01L 23/31 - Encapsulation, e.g. encapsulating layers, coatings characterised by the arrangement
H01L 25/065 - Assemblies consisting of a plurality of individual semiconductor or other solid state devices all the devices being of a type provided for in the same subgroup of groups , or in a single subclass of , , e.g. assemblies of rectifier diodes the devices not having separate containers the devices being of a type provided for in group
H01L 25/18 - Assemblies consisting of a plurality of individual semiconductor or other solid state devices the devices being of types provided for in two or more different subgroups of the same main group of groups , or in a single subclass of ,
58.
CONTROLLER ARCHITECTURE FOR RELIABILITY, AVAILABILITY, SERVICEABILITY ACCESS
An apparatus can include a plurality of memory devices and a memory controller coupled to the plurality of memory devices via a plurality of memory channels. The plurality of memory channels can be each organized as a plurality of channel groups that can be operated as independent RAS channels (e.g., channels for independent RAS accesses). Data received at the memory controller via different memory channels of one RAS channel can be aligned at various circuits and/or components of the memory controller.
An antifuse device, including a gate having a gate dielectric layer; a first doping region connected to a first end of the gate; a second doping region connected to a second end of the gate, the second end being opposite to the first end of the gate; a channel that is disposed under the gate and that connects the first doping region and the second doping region; and an interconnection jumper that electrically connects the first doping region and the second doping region.
H01L 29/86 - Types of semiconductor device controllable only by variation of the electric current supplied, or only the electric potential applied, to one or more of the electrodes carrying the current to be rectified, amplified, oscillated, or switched
60.
TEMPERATURE-BASED ERROR MASKING DURING MBIST OPERATION
Methods, apparatuses, and systems related to masking of self-test results are described. A memory device may include a self-test circuit that is configured to selectively suspend collection of test results from one or more portions of a self-test when a temperature of the memory device exceeds a temperature threshold.
According to one or more embodiments of the disclosure, a through-silicon via (TSV)-Bump structure is provide. The TSV-Bump structure comprises a TSV in a semiconductor substrate and a bump on the TSV. The bump includes a conductive plug portion and a step structure portion under the conductive plug portion. The step structure is configured to electrically couple the TSV and the conductive plug portion with each other.
H01L 23/48 - Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads or terminal arrangements
H01L 21/306 - Chemical or electrical treatment, e.g. electrolytic etching
H01L 21/324 - Thermal treatment for modifying the properties of semiconductor bodies, e.g. annealing, sintering
H01L 21/48 - Manufacture or treatment of parts, e.g. containers, prior to assembly of the devices, using processes not provided for in a single one of the groups
H01L 23/00 - SEMICONDUCTOR DEVICES NOT COVERED BY CLASS - Details of semiconductor or other solid state devices
Systems and methods are disclosed including a memory device and a processing device operatively coupled to the memory device. The processing device can perform operations comprising determining a data validity metric value with respect to a set of memory cells of the memory device; responsive to determining that the data validity metric value satisfies a first threshold criterion, performing a data integrity check on the set of memory cells to obtain a data integrity metric value; and responsive to determining that the data integrity metric value satisfies a second threshold criterion, performing an error handling operation on the data stored on the set of memory cells to generate corrected data.
Memory devices and systems with post-packaging master die selection, and associated methods, are disclosed herein. In one embodiment, a memory device includes a plurality of memory dies. Each memory die of the plurality includes a command/address decoder. The command/address decoders are configured to receive command and address signals from external contacts of the memory device. The command/address decoders are also configured, when enabled, to decode the command and address signals and transmit the decoded command and address signals to every other memory die of the plurality. Each memory die further includes circuitry configured to enable, or disable, or both individual command/address decoders of the plurality of memory dies. In some embodiments, the circuitry can enable a command/address decoder of a memory die of the plurality after the plurality of memory dies are packaged into a memory device.
G06F 12/06 - Addressing a physical block of locations, e.g. base addressing, module addressing, address space extension, memory dedication
G06F 11/07 - Responding to the occurrence of a fault, e.g. fault tolerance
G11C 11/407 - Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing or timing for memory cells of the field-effect type
G11C 29/04 - Detection or location of defective memory elements
H01L 25/065 - Assemblies consisting of a plurality of individual semiconductor or other solid state devices all the devices being of a type provided for in the same subgroup of groups , or in a single subclass of , , e.g. assemblies of rectifier diodes the devices not having separate containers the devices being of a type provided for in group
64.
LIGHT EMITTING DIODES WITH N-POLARITY AND ASSOCIATED METHODS OF MANUFACTURING
Light emitting diodes (“LEDs”) with N-polarity and associated methods of manufacturing are disclosed herein. In one embodiment, a method for forming a light emitting diode on a substrate having a substrate material includes forming a nitrogen-rich environment at least proximate a surface of the substrate without forming a nitrodizing product of the substrate material on the surface of the substrate. The method also includes forming an LED structure with a nitrogen polarity on the surface of the substrate with a nitrogen-rich environment.
H01L 33/00 - SEMICONDUCTOR DEVICES NOT COVERED BY CLASS - Details thereof
H01L 33/16 - SEMICONDUCTOR DEVICES NOT COVERED BY CLASS - Details thereof characterised by the semiconductor bodies with a particular crystal structure or orientation, e.g. polycrystalline, amorphous or porous
H01L 33/32 - Materials of the light emitting region containing only elements of group III and group V of the periodic system containing nitrogen
A method and a device is provided for utilizing unused valid (V) bits residing on a previous command to transmit additional activate information to a memory device. Additional activate information may be transmitted to the memory device without increasing the tRCD time, or increasing the command/address (CA) bus pins, or adding additional circuit area, thereby reducing the impact on the performance of the memory device.
Solid state lighting (“SSL”) devices with improved contacts and associated methods of manufacturing are disclosed herein. In one embodiment, an SSL device includes an SSL structure having a first semiconductor material, a second semiconductor material spaced apart from the first semiconductor material, and an active region between the first and second semiconductor materials. The SSL device also includes a first contact on the first semiconductor material and a second contact on the second semiconductor material, where the first and second contacts define the current flow path through the SSL structure. The first or second contact is configured to provide a current density profile in the SSL structure based on a target current density profile.
H01L 33/62 - Arrangements for conducting electric current to or from the semiconductor body, e.g. leadframe, wire-bond or solder balls
H01L 33/06 - SEMICONDUCTOR DEVICES NOT COVERED BY CLASS - Details thereof characterised by the semiconductor bodies with a quantum effect structure or superlattice, e.g. tunnel junction within the light emitting region, e.g. quantum confinement structure or tunnel barrier
H01L 33/10 - SEMICONDUCTOR DEVICES NOT COVERED BY CLASS - Details thereof characterised by the semiconductor bodies with a light reflecting structure, e.g. semiconductor Bragg reflector
H01L 33/14 - SEMICONDUCTOR DEVICES NOT COVERED BY CLASS - Details thereof characterised by the semiconductor bodies with a carrier transport control structure, e.g. highly-doped semiconductor layer or current-blocking structure
H01L 33/32 - Materials of the light emitting region containing only elements of group III and group V of the periodic system containing nitrogen
H01L 33/36 - SEMICONDUCTOR DEVICES NOT COVERED BY CLASS - Details thereof characterised by the electrodes
H01L 33/38 - SEMICONDUCTOR DEVICES NOT COVERED BY CLASS - Details thereof characterised by the electrodes with a particular shape
H01L 33/44 - SEMICONDUCTOR DEVICES NOT COVERED BY CLASS - Details thereof characterised by the coatings, e.g. passivation layer or anti-reflective coating
H01L 33/46 - Reflective coating, e.g. dielectric Bragg reflector
Some embodiments include a reticle which includes first pattern features and second pattern features. A first optimal dose of actinic radiation is associated with the first pattern features and a second optimal dose of the actinic radiation is associated with the second pattern features. The second pattern features are larger than the first pattern features. Each of the second pattern features has a configuration which includes a central region laterally surrounded by an outer region, with the central region being of different opacity than the outer region. The configurations of the second pattern features balance the second optimal dose of the actinic radiation to be within about 5% of the first optimal dose of the actinic radiation. Some embodiments include photo-processing methods.
G03F 1/38 - Masks having auxiliary features, e.g. special coatings or marks for alignment or testing; Preparation thereof
G03F 1/36 - Masks having proximity correction features; Preparation thereof, e.g. optical proximity correction [OPC] design processes
G03F 7/00 - Photomechanical, e.g. photolithographic, production of textured or patterned surfaces, e.g. printed surfaces; Materials therefor, e.g. comprising photoresists; Apparatus specially adapted therefor
Methods, systems, and devices for determining offsets for memory read operations are described. In response to a threshold quantity of pages failing initial reads but being successfully read using a same reference adjustment during re-reads, the offset responsible for the adjustment may be used as a first-applied offset for subsequent re-reads or a baseline offset for subsequent initial reads. After the initial reads begin using the reference adjustment, if a threshold quantity of pages fail initial reads, the offset used for the initial read may be adjusted to be the offset used to perform the successful re-reads. If an updated offset to use a baseline is not identified, the baseline offset may be cleared so the original reference may again be used without adjustment for initial reads.
Methods, systems, and devices for error detection and classification are described. A memory device may read a codeword from a memory and generate a first set of syndrome bits for the codeword. The memory device may use the first set of syndrome bits to generate a first error detection bit. The memory device may generate a second set of syndrome bits for the codeword and use the second set of syndrome bits to generate a second error detection bit. The memory device may provide the first error detection bit and the second error detection bit to a host device.
Apparatuses, systems, and methods for a damper for a printed circuit board assembly (PCBA). One example apparatus can include a PCBA of a solid state drive (SSD) and a damper configured to contact the PCBA, contact an enclosure of the SSD, and damp shock impulses applied to the SSD.
F16F 15/04 - Suppression of vibrations of non-rotating, e.g. reciprocating, systems; Suppression of vibrations of rotating systems by use of members not moving with the rotating system using elastic means
H05K 5/02 - Casings, cabinets or drawers for electric apparatus - Details
Systems, methods, and apparatus related to data storage devices. In one approach, a string of storage devices are chained together and coupled to a host device for storing data. Each storage device may, for example, execute read, write, or erase commands received from the host device. Each storage device in the chain is a master to the next storage device in the chain, and each storage device is a slave to the previous storage device in the chain. In one example, the host device is a system-on-chip. The chain can manage itself and is seen as a single large storage space to the host device. The host device does not require knowledge about each individual storage device, and each storage device does not require knowledge about the other storage devices in the chain (other than whether the storage device is attached to another storage device on its master port).
Some embodiments include an integrated assembly having first conductive structures extending along a first direction. Spaced-apart upwardly-opening container-shapes are over the first conductive structures. Each of the container-shapes has a first sidewall region, a second sidewall region, and a bottom region extending from the first sidewall region to the second sidewall region. Each of the first and second sidewall regions includes a lower source/drain region, an upper source/drain region, and a channel region between the upper and lower source/drain regions. The lower source/drain regions are electrically coupled with the first conductive structures. Second conductive structures extend along a second direction which crosses the first direction. The second conductive structures have gate regions operatively adjacent the channel regions. Storage elements are electrically coupled with the upper source/drain regions. Some embodiments include methods of forming integrated assemblies.
The present disclosure includes apparatuses, methods, and systems for three-state programming of memory cells. An embodiment includes a memory having a plurality of memory cells, and circuitry configured to program a memory cell of the plurality of memory cells to one of three possible data states by applying a voltage pulse to the memory cell, determining whether the memory cell snaps back in response to the applied voltage pulse, and applying an additional voltage pulse to the memory cell based on the determination of whether the memory cell snaps back.
Methods, systems, and devices for error detection and classification at a host device are described. A host device may communicate a read command for a codeword stored at a memory device. In response to communicating the read command, the host device may receive the codeword and an error indication bit that indicates whether the memory device detected an error in the codeword. The host device may use the codeword to generate a set of syndrome bits. The host device may determine an error status of the codeword based on the error indication bit for the codeword and the set of syndrome bits for the codeword.
H03M 13/15 - Cyclic codes, i.e. cyclic shifts of codewords produce other codewords, e.g. codes defined by a generator polynomial, Bose-Chaudhuri-Hocquenghem [BCH] codes
H03M 13/00 - Coding, decoding or code conversion, for error detection or error correction; Coding theory basic assumptions; Coding bounds; Error probability evaluation methods; Channel models; Simulation or testing of codes
H03M 13/11 - Error detection or forward error correction by redundancy in data representation, i.e. code words containing more digits than the source words using block codes, i.e. a predetermined number of check bits joined to a predetermined number of information bits using multiple parity bits
Described are semiconductor interposer, and microelectronic device assemblies incorporating such semiconductor interposers. The described interposers include multiple redistribution structures on each side of the core; each of which may include multiple individual redistribution layers. The interposers may optionally include circuit elements, such as passive and/or active circuit. The circuit elements may be formed at least partially within the semiconductor core.
H01L 23/538 - Arrangements for conducting electric current within the device in operation from one component to another the interconnection structure between a plurality of semiconductor chips being formed on, or in, insulating substrates
H01L 21/48 - Manufacture or treatment of parts, e.g. containers, prior to assembly of the devices, using processes not provided for in a single one of the groups
H01L 23/00 - SEMICONDUCTOR DEVICES NOT COVERED BY CLASS - Details of semiconductor or other solid state devices
H01L 23/14 - Mountings, e.g. non-detachable insulating substrates characterised by the material or its electrical properties
H01L 25/18 - Assemblies consisting of a plurality of individual semiconductor or other solid state devices the devices being of types provided for in two or more different subgroups of the same main group of groups , or in a single subclass of ,
76.
TEMPORARY PARITY BUFFER ALLOCATION FOR ZONES IN A PARITY GROUP
Methods, systems, and apparatuses include allocating a temporary parity buffer to a parity group. A write command is received that includes user data and is directed to a portion of memory included in a zone which is included in the parity group. A memory identifier is determined for the portion of memory. Parity group data is received from the temporary parity buffer using the memory identifier. Updated parity group data is determined using the parity group data and the user data. The updated parity group data is sent to the temporary parity buffer.
Systems, methods, and apparatus related to dynamically adjusting sensing and/or processing resources of a vehicle. In one approach, sensor data is collected by sensing devices of the vehicle. A controller of the vehicle uses the sensor data to control one or more functions of the vehicle. The controller evaluates the sensor data to determine a context of operation (e.g., weather, lighting, and/or traffic) for the vehicle. Based on the context of operation, the controller adjusts the operation of one or more of the sensing or processing devices in real-time during operation of the vehicle. In one example, the adjustment reduces power consumption by the vehicle.
B60W 60/00 - Drive control systems specially adapted for autonomous road vehicles
B60L 58/10 - Methods or circuit arrangements for monitoring or controlling batteries or fuel cells, specially adapted for electric vehicles for monitoring or controlling batteries
H04W 4/48 - Services specially adapted for particular environments, situations or purposes for vehicles, e.g. vehicle-to-pedestrians [V2P] for in-vehicle communication
78.
WAFER-LEVEL SOLID STATE TRANSDUCER PACKAGING TRANSDUCERS INCLUDING SEPARATORS AND ASSOCIATED SYSTEMS AND METHODS
Wafer-level packaging of solid-state transducers (“SSTs”) is disclosed herein. A method in accordance with a particular embodiment includes forming a transducer structure having a first surface and a second surface opposite the first surface, and forming a plurality of separators that extend from at least the first surface of the transducer structure to beyond the second surface. The separators can demarcate lateral dimensions of individual SSTs. The method can further include forming a support substrate on the first surface of the transducer structure, and forming a plurality of discrete optical elements on the second surface of the transducer structure. The separators can form barriers between the discrete optical elements. The method can still further include dicing the SSTs along the separators. Associated SST devices and systems are also disclosed herein.
H01L 27/15 - Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components with at least one potential-jump barrier or surface barrier, specially adapted for light emission
H01L 33/46 - Reflective coating, e.g. dielectric Bragg reflector
H01L 33/48 - SEMICONDUCTOR DEVICES NOT COVERED BY CLASS - Details thereof characterised by the semiconductor body packages
A memory device includes an array of memory cells, a diode having a threshold voltage that changes with temperature, an analog-to-digital converter (ADC), and a pulse generator. The ADC includes a voltage comparator having a positive terminal coupled with the diode. The ADC further includes a first capacitor coupled between a negative terminal of the voltage comparator and ground, and a second capacitor selectively coupled between the first capacitor and a voltage reference node. The second capacitor has a smaller capacitance than that of the first capacitor. The pulse generator is coupled with the ADC and generates pulses. The pulses cause the first capacitor to connect to the second capacitor and equalize charge between the first capacitor and the second capacitor. An inverted signal of the pulses causes the second capacitor to be coupled with the voltage reference node to pre-charge the first capacitor.
G11C 7/04 - Arrangements for writing information into, or reading information out from, a digital store with means for avoiding disturbances due to temperature effects
G11C 16/04 - Erasable programmable read-only memories electrically programmable using variable threshold transistors, e.g. FAMOS
The disclosed embodiments relate to securely booting firmware images. In one embodiment, a method is disclosed comprising receiving, by a memory device, a firmware update; validating, by the memory device, a signature associated with the firmware update; copying, by the memory device, an existing firmware image to an archive location, the archive location storing a plurality of firmware images sorted by version identifiers; booting, by the memory device, and executing the firmware update; and replacing, by the memory device, the firmware update with the existing firmware image stored in the archive location upon detecting an error while booting the firmware update.
G06F 21/57 - Certifying or maintaining trusted computer platforms, e.g. secure boots or power-downs, version controls, system software checks, secure updates or assessing vulnerabilities
G06F 11/14 - Error detection or correction of the data by redundancy in operation, e.g. by using different operation sequences leading to the same result
H04L 9/32 - Arrangements for secret or secure communications; Network security protocols including means for verifying the identity or authority of a user of the system
81.
DIE FAMILY MANAGEMENT ON A MEMORY DEVICE USING BLOCK FAMILY ERROR AVOIDANCE
A target block family of a plurality of block families is identified periodically every predetermined number of program erase cycles (PECs) of a memory device. Each block family includes a plurality of blocks. A respective temporal voltage shift of each block of a subset of blocks of the target block family from each die of a plurality of dies associated with the target block family is obtained. A respective die measurement for each respective die is obtained based on an average of the respective temporal voltage shifts of the subset of blocks from each die. Each respective die to a respective die family of a plurality of consecutive die families is assigned based on the respective die measurement for each respective die.
A storage product having a network interface and a bus switch connecting a random-access memory, a processing device, and a storage device, and connected via an external computer bus to an external processor. The storage product can receive via the network interface first messages and second messages for network storage services. The bus switch is operable to provide a first bus between the processing device and the random-access memory to buffer the first messages into the random-access memory, a second bus between the processing device and the storage device to buffer the second messages into a local memory of the storage device, and a third bus between the processor and the random-access memory to retrieve the first messages from the random-access memory and generate third messages. The storage device is configured to process the second and third messages to provide network storage services.
Control logic in a memory device initiates a program operation on a memory array, the program operation comprising a seeding phase. During the seeding phase, the control logic causes a seeding voltage to be applied to a string of memory cells in a data block of the memory array during the seeding phase of the program operation and causes a first positive voltage to be applied to a first plurality of word lines of the data block during the seeding phase, wherein each of the first plurality of word lines is coupled to a corresponding memory cell of a first plurality of memory cells in the string of memory cells, the first plurality of word lines comprising a selected word line associated with the program operation. The control logic further causes a second positive voltage to be applied to one or more second word lines coupled to one or more second memory cells on a source-side of the first plurality of memory cells in the string of memory cells during the seeding phase, wherein the second positive voltage is less than the first positive voltage.
Fin field effect transistor (FinFET) sense amplifier circuitry and related apparatuses and computing systems are disclosed. An apparatus includes a pull-up sense amplifier, a pull-down sense amplifier, column select gates, global input-output (GIO) lines, and GIO pre-charge circuitry. The pull-up sense amplifier includes P-type FinFETs having a first threshold voltage potential associated therewith. The pull-down sense amplifier includes N-type FinFETs having a second threshold voltage potential associated therewith. The second threshold voltage potential is substantially equal to the first threshold voltage potential. The GIO lines are electrically connected to the pull-up sense amplifier and the pull-down sense amplifier through the column select gates. The GIO pre-charge circuitry is configured to pre-charge the GIO lines to a low power supply voltage potential.
G11C 11/4091 - Sense or sense/refresh amplifiers, or associated sense circuitry, e.g. for coupled bit-line precharging, equalising or isolating
H01L 25/065 - Assemblies consisting of a plurality of individual semiconductor or other solid state devices all the devices being of a type provided for in the same subgroup of groups , or in a single subclass of , , e.g. assemblies of rectifier diodes the devices not having separate containers the devices being of a type provided for in group
H01L 25/18 - Assemblies consisting of a plurality of individual semiconductor or other solid state devices the devices being of types provided for in two or more different subgroups of the same main group of groups , or in a single subclass of ,
85.
SEMICONDUCTOR DEVICE HAVING READ DATA BUSES AND WRITE DATA BUSES
An apparatus that includes: a plurality of first data amplifiers arranged in line in a first direction; a plurality of first read data buses each coupled to a corresponding one of the plurality of first data amplifiers, the plurality of first read data buses having different lengths one another; and a plurality of first write data buses each coupled to the corresponding one of the plurality of first data amplifiers, the plurality of first write data buses having different lengths one another. The plurality of first read data buses and the plurality of first write data buses are alternately arranged in parallel in a second direction vertical to the first direction. The plurality of first read data buses are arranged in longest order and the plurality of first write data buses are arranged in shortest order.
Global column repair with local column decoder circuitry and related apparatuses, methods, and computing systems are disclosed. An apparatus includes global column repair circuitry including column address drivers corresponding to respective ones of column planes of a memory array. The column address drivers are configured to, if enabled, drive a received column address signal to local column decoder circuitry local to respective ones of the column planes. The global column repair circuitry also includes match circuitry and data storage elements configured to store defective column addresses corresponding to defective column planes. The match circuitry is configured to compare a received column address indicated by the received column address signal to the defective column addresses and disable a column address driver corresponding to a defective column plane responsive to a determination that the received column address matches a defective column address associated with the defective column plane.
A system can include a memory device a memory device comprising multiple dies, and a processing device, operatively coupled with the memory device, to perform various operations including identifying multiple management units to be programmed, where one management unit contains memory cells from a die having one endurance metric and another management unit contains memory cells from a die having another endurance metric, and determining a value of a media endurance metric for each management unit. The operations further include determining, for each management unit, a respective endurance exhaustion parameter defined by a relationship media endurance metrics, and distributing operations to each management unit based on the endurance exhaustion parameter.
Methods, systems, and devices for error status determination at a memory device are described. A memory device may generate, based on syndrome bits for a codeword read from a memory, an error detection signal for the codeword that indicates whether an error has been detected in the codeword. The memory device may generate, based on the syndrome bits, an error correction signal for the codeword that indicates whether an error has been corrected in the codeword. And the memory device may provide an indication of the error detection signal and an indication of the error correction signal to a host device.
Memory with deterministic worst-case row address servicing is disclosed herein. A method of the present technology comprises (1) updating a counter value corresponding to a memory row of a memory device in response to detecting activation of the memory row; (2) comparing the updated counter value to a worst-case count value; and (3) in response to determining that the updated counter value is greater than the worst-case count value, setting the worst-case count value equal to the updated counter value and storing a memory row address of the memory row as a worst-case memory row address. The counter value can be one of a plurality of counter values, each counter value (a) corresponding to a respective memory row and (b) configured to track a number of activations of the respective memory row. The method can further comprise performing a row disturb refresh operation using the worst-case memory row address.
Example embodiments are directed to a solid-state drive (SSD) enclosure design that is adaptable for different printed circuit board assemblies (PCBA). The SSD enclosure design comprises a three-piece construction that includes a top enclosure, a bottom enclosure, and an intermediate structure. The bottom enclosure is coupled to the top enclosure to form a housing for a PCBA having NOT AND (NAND) devices and a controller. The intermediate structure is coupled to the PCBA and positioned between the top enclosure and the bottom enclosure within the housing. The intermediate structure comprises a plurality of heatsinks to transfer heat from the NAND devices and a controller heatsink to transfer heat from the controller, whereby the type and location of the heatsinks can be changed for a different PCBA without having to change the top enclosure or bottom enclosure. The top enclosure can include vents that allow air to flow through.
Disclosed in some examples, are methods, systems, devices, and machine-readable mediums which provide for more efficient CGRA execution by assigning different initiation intervals to different PEs executing a same code base. The initiation intervals may be a multiple of each other and the PE with the lowest initiation interval may be used to execute instructions of the code that is to be executed at a greater frequency than other instructions than other instructions that may be assigned to PEs with higher initiation intervals.
Disclosed in some examples are improvements to data placement architectures in NAND that provide additional data protection through an improved NAND data placement schema that allows for recovery from certain failure scenarios. The present disclosure stripes data diagonally across page lines and planes to enhance the data protection. Parity bits are stored in SLC blocks for extra protection until the block is finished writing and then the parity bits may be deleted.
G11C 16/26 - Sensing or reading circuits; Data output circuits
G11C 29/42 - Response verification devices using error correcting codes [ECC] or parity check
H03K 19/21 - EXCLUSIVE-OR circuits, i.e. giving output if input signal exists at only one input; COINCIDENCE circuits, i.e. giving output only if all input signals are identical
A variety of applications can include memory devices designed to provide enhanced gate-induced-drain-leakage (GIDL) current during memory erase operations. The enhanced operation can be provided by enhancing the electric field in the channel structures of select gate transistors to strings of memory cells. The channel structures can be implemented as a segmented portion for drains and a portion opposite a gate. The segmented portion includes one or more fins and one or more non-conductive regions with both fins and non-conductive regions extending vertically from the portion opposite the gate. Variations of a border region for the portion opposite the gate with the segmented portion can include fanged regions extending from the fins into the portion opposite the gate or rounded border regions below the non-conductive regions. Such select gate transistors can be formed using a single photo mask process. Additional devices, systems, and methods are discussed.
H01L 29/78 - Field-effect transistors with field effect produced by an insulated gate
H10B 41/10 - Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates characterised by the top-view layout
H10B 41/27 - Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates characterised by three-dimensional arrangements, e.g. with cells on different height levels with source and drain on different levels, e.g. with sloping channels the channels comprising vertical portions, e.g. U-shaped channels
H10B 41/35 - Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates characterised by the memory core region with a cell select transistor, e.g. NAND
H10B 43/10 - EEPROM devices comprising charge-trapping gate insulators characterised by the top-view layout
H10B 43/27 - EEPROM devices comprising charge-trapping gate insulators characterised by three-dimensional arrangements, e.g. with cells on different height levels with source and drain on different levels, e.g. with sloping channels the channels comprising vertical portions, e.g. U-shaped channels
H10B 43/35 - EEPROM devices comprising charge-trapping gate insulators characterised by the memory core region with cell select transistors, e.g. NAND
94.
SEMICONDUCTOR DEVICES COMPRISING TRANSISTORS HAVING INCREASED THRESHOLD VOLTAGE AND RELATED METHODS AND SYSTEMS
A transistor comprising threshold voltage control gates. The transistor also comprises active control gates adjacent opposing first sides of a channel region, the threshold voltage control gates adjacent opposing second sides of the channel region, and a dielectric region between the threshold voltage control gates and the channel region and between the active control gates and the channel region. A semiconductor device comprising memory cells comprising the transistor is also disclosed, as are systems comprising the memory cells, methods of forming the semiconductor device, and methods of operating a semiconductor device.
Systems, methods, and apparatus related to cruise control for a vehicle. In one approach, speed for a first vehicle is controlled in a first mode using data from sensors. The speed is controlled while keeping at least a minimum distance from a second vehicle being followed by the first vehicle. In response to determining that data from the sensors is not usable to control the first vehicle (e.g., the data cannot be used to measure the minimum distance), the first vehicle changes from the first mode to a second mode. In the second mode, the first vehicle maintains a constant speed and/or obtains additional data from sensors and/or computing devices located externally to the first vehicle. In another approach, the additional data can additionally or alternatively be obtained from a mobile device of a passenger of the first vehicle. The additional data is used to maintain a safe minimum distance from the second vehicle.
Some embodiments include an integrated assembly having a CMOS region. Fins extend across the CMOS region and are on a first pitch. A circuit arrangement is associated with the CMOS region and includes segments of one or more of the fins. The circuit arrangement has a first dimension along a first direction. A second region is proximate the CMOS region. Conductive structures are associated with the second region. The conductive structures extend along a second direction different than the first direction. Some of the conductive structures are electrically coupled with the circuit arrangement. The conductive structures are on a second pitch different from the first pitch. A second dimension is a distance across said some of the conductive structures along the first direction, and the second dimension is substantially the same as the first dimension.
G11C 11/4091 - Sense or sense/refresh amplifiers, or associated sense circuitry, e.g. for coupled bit-line precharging, equalising or isolating
H01L 27/092 - Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only the components being field-effect transistors with insulated gate complementary MIS field-effect transistors
H01L 29/78 - Field-effect transistors with field effect produced by an insulated gate
Exemplary methods, apparatuses, and systems include an intelligent boot manager for controlling initialization of components of vehicle computing systems. The intelligent boot manager receives an access request for a vehicle. The intelligent boot manager initializes a set of components of vehicle systems of the vehicle in response to the access request. The intelligent boot manager executes a first portion of code from a read-only memory (ROM) location, the first portion of code configuring a processor to initialize a random-access memory (RAM) location. The intelligent boot manager downloads a set of applications to the RAM location. The intelligent boot manager receives an engine start request for the vehicle, wherein the engine start request is distinct from the access request. The intelligent boot manager initiates an engine start sequence of the vehicle in response to the engine start request.
Systems, methods, and apparatuses for data prioritization and selective data processing are described herein. A computing device may receive sensor data and prioritize a first portion of the sensor data over a second portion of the sensor data. The first portion of sensor data may be stored in a first memory that has a higher access rate than a second memory where the second portion of sensor data is stored. The first portion of sensor data may be processed with priority and the second portion of sensor data may be transmitted to a cloud computing device.
A microelectronic device comprises a stack structure, a staircase structure, a first liner material, a liner structure, conductive contact structures, and barrier structures. The stack structure comprises vertically alternating conductive structures and insulative structures arranged in tiers. Each of the tiers individually comprises one of the conductive structures and one of the insulative structures. The staircase structure has steps comprising edges of at least some of the tiers of the stack structure. The first liner material is on the steps of the staircase structure, and the liner structure on the first liner material. The conductive contact structures extend through the first liner material and the liner structure and to the conductive structures of the stack structure. The barrier structures are between the conductive contact structures and the liner structure vertically span substantially the same tiers of the stack structure as the liner structure. Memory devices, electronic systems, and methods of forming microelectronic devices are also described.
H01L 23/522 - Arrangements for conducting electric current within the device in operation from one component to another including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
H01L 21/768 - Applying interconnections to be used for carrying current between separate components within a device
H01L 23/532 - Arrangements for conducting electric current within the device in operation from one component to another including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body characterised by the materials
H01L 27/11556 - Electrically programmable read-only memories; Multistep manufacturing processes therefor with floating gate characterised by three-dimensional arrangements, e.g. with cells on different height levels with source and drain on different levels, e.g. with sloping channels the channels comprising vertical portions, e.g. U-shaped channels
H01L 27/11582 - Electrically programmable read-only memories; Multistep manufacturing processes therefor with charge-trapping gate insulators, e.g. MNOS or NROM characterised by three-dimensional arrangements, e.g. with cells on different height levels with source and drain on different levels, e.g. with sloping channels the channels comprising vertical portions, e.g. U-shaped channels
A redundant array of independent disks (RAID) protection can be provided along with other types of error correction code (ECC) schemes that correct either errors in data prior to the data being input to the RAID process or residual errors from the RAID process. The ECC schemes can utilize parity bits generated using a parity matrix whose bit patterns have an amount of bits that can be used to identify a location of the memory system from which data corresponding to the respective bit pattern is read.
patents
