Abstract

A method of growing a single crystal ingot includes growing a single crystal silicon ingot from a silicon melt in a crucible within an inner chamber, adding a volatile dopant into a feed tube, positioning the feed tube within an inner chamber at a first height relative to a surface of the melt, adjusting the feed tube within the inner chamber to a second height at a speed rate, and heating the volatile dopant to form a gaseous dopant as the feed tube is moved from the first height to the second height at the speed rate. Each of the second height and the speed rate are selected to control a vaporization rate of the volatile dopant. The method also includes introducing dopant species into the melt while growing the ingot by contacting the surface of the melt with the gaseous dopant.

IPC Classes  ?

• C30B 15/04 - Single-crystal growth by pulling from a melt, e.g. Czochralski method adding crystallising materials or reactants forming it in situ to the melt adding doping materials, e.g. for n–p-junction
• C30B 15/14 - Heating of the melt or the crystallised materials
• C30B 15/20 - Controlling or regulating
• C30B 29/06 - Silicon

Abstract

A method of growing a single crystal ingot includes growing a single crystal silicon ingot from a silicon melt in a crucible within an inner chamber, adding a volatile dopant into a feed tube, positioning the feed tube within an inner chamber at a first height relative to a surface of the melt, adjusting the feed tube within the inner chamber to a second height at a speed rate, and heating the volatile dopant to form a gaseous dopant as the feed tube is moved from the first height to the second height at the speed rate. Each of the second height and the speed rate are selected to control a vaporization rate of the volatile dopant. The method also includes introducing dopant species into the melt while growing the ingot by contacting the surface of the melt with the gaseous dopant.

IPC Classes  ?

• C30B 15/04 - Single-crystal growth by pulling from a melt, e.g. Czochralski method adding crystallising materials or reactants forming it in situ to the melt adding doping materials, e.g. for n–p-junction
• C30B 15/14 - Heating of the melt or the crystallised materials
• C30B 29/06 - Silicon

Abstract

A semiconductor substrate includes a high-resistivity silicon carbide layer and a gallium nitride epitaxial layer. The gallium nitride epitaxial layer is formed on a surface, a thickness of the gallium nitride epitaxial layer is less than 2 μm, and a full width at half maximum (FWHM) of an X-ray diffraction analysis (002) plane is less than 100 arcsec. The thickness of the high-resistivity silicon carbide layer ranges from 20 μm to 50 μm. The surface of the high-resistivity silicon carbide layer has an angle ranging from 0° to +/−8° with respect to a (0001) plane. The micropipe density (MPD) of the high-resistivity silicon carbide layer is less than 0.5 ea/cm2, the basal plane dislocation (BPD) of the high-resistivity silicon carbide layer is less than 10 ea/cm2, and the threading screw dislocation (TSD) of the high-resistivity silicon carbide layer is less than 500 ea/cm2.

IPC Classes  ?

• H01L 21/78 - Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
• H01L 21/02 - Manufacture or treatment of semiconductor devices or of parts thereof
• H01L 21/762 - Dielectric regions
• H01L 29/04 - Semiconductor bodies characterised by their crystalline structure, e.g. polycrystalline, cubic or particular orientation of crystalline planes
• H01L 29/16 - Semiconductor bodies characterised by the materials of which they are formed including, apart from doping materials or other impurities, only elements of Group IV of the Periodic System in uncombined form
• H01L 29/20 - Semiconductor bodies characterised by the materials of which they are formed including, apart from doping materials or other impurities, only AIIIBV compounds
• H01L 29/267 - Semiconductor bodies characterised by the materials of which they are formed including, apart from doping materials or other impurities, elements provided for in two or more of the groups , , , , in different semiconductor regions

Abstract

A processing method of a single crystal material includes the following steps. A single crystal material is provided as an object to be modified. The amorphous phase modification apparatus is used for emitting a femtosecond laser beam to process an internal portion of the object to be modified. The processing includes using a femtosecond laser beam to form a plurality of processing lines in the internal portion of the object to be modified, wherein each of the processing lines include a zigzag pattern processing, and a processing line spacing between the plurality of processing lines is in a range of 200 μm to 600 μm, wherein after the object to be modified is processed, a modified layer is formed in the object to be modified. Slicing or separating out a portion in the object to be modified that includes the modified layer.

IPC Classes  ?

• B23K 26/364 - Laser etching for making a groove or trench, e.g. for scribing a break initiation groove
• B23K 26/06 - Shaping the laser beam, e.g. by masks or multi-focusing
• B23K 26/082 - Scanning systems, i.e. devices involving movement of the laser beam relative to the laser head

Abstract

A susceptor assembly for supporting a crucible during a crystal growth process includes a susceptor base, a tubular sidewall connected to the susceptor base, and a removable sacrifice ring interposed between the susceptor base and the sidewall. Each of the susceptor base and the sidewall is formed of a carbon-containing material. The susceptor base has an annular wall and a shoulder extending radially outward from an outer surface of the annular wall. The sidewall has a first end that receives the annular wall to connect the sidewall to the susceptor base. The sacrifice ring has a first surface that faces the outer surface of the annular wall, a second surface that faces an interior surface of the sidewall, and a ledge extending outward from the second surface that engages the first end of the sidewall.

IPC Classes  ?

• C30B 15/10 - Crucibles or containers for supporting the melt
• C30B 15/20 - Controlling or regulating
• C30B 29/06 - Silicon

Abstract

Synesthetic quartz crucibles for holding a silicon melt during growth of single crystal silicon ingots are disclosed. The crucibles may include a coating disposed on the inner and outer surface of the crucible body along the rim. The coating extends only partially down the sidewall of the crucible and may extend to or beyond the melt line of the crucible.

IPC Classes  ?

• C30B 15/10 - Crucibles or containers for supporting the melt
• C30B 15/22 - Stabilisation or shape controlling of the molten zone near the pulled crystal; Controlling the section of the crystal
• C30B 29/06 - Silicon

Abstract

Methods for producing a silicon ingot in which a horizontal magnetic field is generated are disclosed. The magnet position is controlled in at least two stages of ingot growth. The magnetic poles may be at a first position during the first stage of ingot growth and lowered to a second position in a second stage of ingot growth. By controlling the magnet position, the crystal-melt interface shape may be relatively more consistent.

IPC Classes  ?

• C30B 15/22 - Stabilisation or shape controlling of the molten zone near the pulled crystal; Controlling the section of the crystal

Abstract

Methods for producing a silicon ingot in which a horizontal magnetic field is generated are disclosed. The magnet position is controlled in at least two stages of ingot growth. The magnetic poles may be at a first position during the first stage of ingot growth and lowered to a second position in a second stage of ingot growth. By controlling the magnet position, the crystal-melt interface shape may be relatively more consistent.

IPC Classes  ?

• C30B 15/30 - Mechanisms for rotating or moving either the melt or the crystal
• C30B 15/20 - Controlling or regulating
• C30B 29/06 - Silicon

Abstract

A light-emitting element structure includes a substrate, a nucleation layer located above the substrate, a buffer layer located above the nucleation layer, a first nitride layer located above the buffer layer and being in contact with the buffer layer, a second nitride layer located above the first nitride layer and being in contact with the first nitride layer, a first semiconductor layer located above the second nitride layer, a light-emitting layer, and a second semiconductor layer located above the light-emitting layer. A film thickness of the first nitride layer is smaller than a film thickness of the second nitride layer. A dislocation defect density of the second nitride layer is smaller than or equal to 3×109 cm−2. The light-emitting layer is located above the first semiconductor layer and is adapted to emit light when electrons and holes recombine.

IPC Classes  ?

• H01L 33/12 - SEMICONDUCTOR DEVICES NOT COVERED BY CLASS - Details thereof characterised by the semiconductor bodies with a stress relaxation structure, e.g. buffer layer
• H01L 33/00 - SEMICONDUCTOR DEVICES NOT COVERED BY CLASS - Details thereof
• H01L 33/32 - Materials of the light emitting region containing only elements of group III and group V of the periodic system containing nitrogen

Abstract

A method for epitaxy of a high electron mobility transistor includes: provide a substrate; form a nucleation layer on the substrate; form a buffer layer on the nucleation layer; form a first nitride layer being in contact with the buffer layer on the buffer layer; form a second nitride layer being in contact with the first nitride layer on the first nitride layer, and perform carbon doping on the second nitride layer; form a channel layer on the second nitride layer; and form a barrier layer on the channel layer; a two-dimensional electron gas is formed in the channel layer along an interface between the channel layer and the barrier layer; a growth temperature of the second nitride layer is less than a growth temperature of the first nitride layer; a film thickness of the first nitride layer is less than a film thickness of the second nitride layer.

IPC Classes  ?

• H01L 29/66 - Types of semiconductor device
• H01L 29/20 - Semiconductor bodies characterised by the materials of which they are formed including, apart from doping materials or other impurities, only AIIIBV compounds
• H01L 29/778 - Field-effect transistors with two-dimensional charge carrier gas channel, e.g. HEMT

Abstract

A high electron mobility transistor epitaxial structure includes a substrate, a nucleation layer, a buffer layer, a first nitride layer, a second nitride layer, a channel layer, and a barrier layer. The nucleation layer is located above the substrate. The buffer layer is located above the nucleation layer. The first nitride layer is located above the buffer layer and is in contact with the buffer layer. The second nitride layer is located above the first nitride layer and is in contact with the first nitride layer. A film thickness of the first nitride layer is less than a film thickness of the second nitride layer. The second nitride layer is carbon doped. A carbon concentration of the first nitride layer is less than a carbon concentration of the second nitride layer. The channel layer is located above the second nitride layer.

IPC Classes  ?

• H01L 29/20 - Semiconductor bodies characterised by the materials of which they are formed including, apart from doping materials or other impurities, only AIIIBV compounds
• H01L 29/778 - Field-effect transistors with two-dimensional charge carrier gas channel, e.g. HEMT
• H01L 29/06 - Semiconductor bodies characterised by the shapes, relative sizes, or dispositions of the semiconductor regions

Abstract

A method of manufacturing a light-emitting element, including: provide a substrate; form a nucleation layer above the substrate; form a buffer layer above the nucleation layer; form a first nitride layer being in contact with the buffer layer above the buffer layer; form a second nitride layer being in contact with the first nitride layer above the first nitride layer; form a first semiconductor layer above the second nitride layer; form a light-emitting layer above the first semiconductor layer; form a second semiconductor layer above the light-emitting layer. The light-emitting layer is adapted to emit light when electrons and holes recombine. A film thickness of the first nitride layer is smaller than a film thickness of the second nitride layer, and a growth pressure of the first nitride layer is smaller than a growth pressure of the second nitride layer.

IPC Classes  ?

• H01L 33/00 - SEMICONDUCTOR DEVICES NOT COVERED BY CLASS - Details thereof

Abstract

An ingot puller for producing a doped single crystal silicon ingot includes a housing defining a chamber, a crucible disposed within the chamber, and a dopant injector attached to and extending into the housing. The chamber is maintained at a first pressure. The dopant injector includes a reservoir for containing a liquid dopant, a feed tube positioned within the chamber and connected to the reservoir, and a vaporization cup positioned within the feed tube and the chamber.

IPC Classes  ?

• C30B 15/04 - Single-crystal growth by pulling from a melt, e.g. Czochralski method adding crystallising materials or reactants forming it in situ to the melt adding doping materials, e.g. for n–p-junction
• C30B 15/14 - Heating of the melt or the crystallised materials
• C30B 29/06 - Silicon

Abstract

Cooling jacket devices of ingot puller apparatus used to prepare silicon ingots by the Czochralski method are disclosed. The cooling jacket device may include an inner shell that forms an inner chamber through which the ingot is pulled. The cooling jacket includes an outer shell. A plurality of tubes are disposed between the inner shell and outer shell. Each tube forms a cooling fluid passageway through which cooling fluid passes.

IPC Classes  ?

• C30B 15/10 - Crucibles or containers for supporting the melt

Abstract

A method for producing a single crystal silicon ingot from a silicon melt includes providing a crucible within an inner chamber of an ingot puller, the crucible including an inner surface and a synthetic liner on the inner surface. The method further includes adding an initial charge of polysilicon to the crucible, melting the initial charge of polysilicon to cause the silicon melt to form in the crucible, and dissolving a melt modifier into the silicon melt to devitrify the synthetic liner and form a crystallized layer on the crucible. The crystallized layer has a thickness less than 700 microns. The method further includes pulling a single crystal silicon ingot from the silicon melt.

IPC Classes  ?

• C30B 29/06 - Silicon
• C30B 15/10 - Crucibles or containers for supporting the melt
• C30B 15/04 - Single-crystal growth by pulling from a melt, e.g. Czochralski method adding crystallising materials or reactants forming it in situ to the melt adding doping materials, e.g. for n–p-junction

Abstract

A method of growing the silicon carbide crystal includes the following steps. A raw material containing a carbon element and a silicon element, and a seed crystal located above the raw material are provided in a reactor. A growth process of the silicon carbide crystal is performed, wherein the growth process includes heating the reactor and the raw material to form silicon carbide crystal on the seed crystal. In the growth process, a ratio difference (ΔTz/ΔTx) between an axial temperature gradient (ΔTz) and a radial temperature gradient (ΔTx) of the silicon carbide crystal is adjusted so that the ratio difference is controlled in the range of 0.5 to 3 to form the silicon carbide crystal. The silicon carbide crystal formed by the above growth method can have a uniform resistivity distribution and excellent geometric performance.

IPC Classes  ?

• C30B 25/10 - Heating of the reaction chamber or the substrate
• C30B 25/16 - Controlling or regulating
• C30B 29/36 - Carbides

Abstract

A crystal growing method for crystals include the following steps. A first crystal seed is provided, the first crystal seed has a first monocrystalline proportion and a first size. N times of crystal growth processes are performed on the first crystal seed, wherein each of the crystal growth process will increase the monocrystalline proportion, and the N times of crystal growth processes are performed until a second crystal having a monocrystalline proportion of 100% is reached, and wherein the N times includes more than 3 times of crystal growth processes. Each crystal growth process includes adjusting a ratio difference (ΔTz/ΔTx) between an axial temperature gradient (ΔTz) and a radial temperature gradient (ΔTx) of the crystal, so as to control the ratio difference within a range of 0.5 to 3 for forming the second crystal.

IPC Classes  ?

• C30B 23/00 - Single-crystal growth by condensing evaporated or sublimed materials

Abstract

A crystal growth furnace system, including an external heating module, a furnace, a first driven device, a second driven device, and a control device, is provided. The furnace is movably disposed in the external heating module. The first driven device drives the furnace to move along an axis. The second driven device drives the furnace to rotate around the axis. The control device is electrically connected to the first driven device, the second driven device, and the external heating module.

IPC Classes  ?

• C30B 23/06 - Heating of the deposition chamber, the substrate, or the materials to be evaporated

Abstract

A crystal growth method, including providing a seed crystal in a crystal growth furnace, and forming a crystal on the seed crystal along a first direction after multiple time points, is provided. The crystal includes multiple sub-crystals stacked along the first direction, a corresponding one of the sub-crystals is formed at each of the time points, and the sub-crystals include multiple end surfaces away from the seed crystal, so that a difference value of maximum temperatures of any two of the end surfaces is less than or equal to 20 degrees. A wafer is also provided.

IPC Classes  ?

• C30B 23/00 - Single-crystal growth by condensing evaporated or sublimed materials

Abstract

A silicon carbide crystal and a silicon carbide wafer, wherein a monocrystalline proportion of the silicon carbide crystal and the silicon carbide wafer is 100%, the resistivity thereof is in a range of 15 mΩ·cm to 20 mΩ·cm, and a deviation of an uniformity of the resistivity thereof is less than 0.4%.

IPC Classes  ?

• C30B 29/36 - Carbides

Abstract

A susceptor for supporting a semiconductor wafer in a heated chamber includes a body that has a front surface, a rear surface, and a central plane between the front and rear surfaces. The susceptor also includes a recess that extends into the body from the front surface to a recess floor and a ledge that circumscribes the recess floor in the recess. The ledge includes a first surface oriented at a first angle relative to a horizontal plane parallel to the central plane, a second surface that extends radially inward from the first surface, the second surface optionally oriented at a second acute angle relative to the horizontal plane, and a third surface that extends between the second surface and the recess floor, the third surface oriented at a third acute angle relative to the horizontal plane. Each of the first, second, and third surfaces extends circumferentially along the ledge.

IPC Classes  ?

• H01L 21/687 - Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components for supporting or gripping using mechanical means, e.g. chucks, clamps or pinches
• C30B 25/12 - Substrate holders or susceptors

Abstract

A measurement system includes a target object at least partially visible through an opening in a crystal puller. The crystal puller has a silicon melt in a crucible and a reflector defining a central passage through which a crystal is pulled. A detector array captures light through the opening. The detector array is directed to a surface of the silicon melt in the crystal puller and to the target object, and a laser selectively transmits a coherent light beam through the opening to the target object to produce a reflection of the target object on the surface of the silicon melt. An optical modulator pulses the coherent light beams of the laser into discrete coherent light beams having a period, and a lock-in amplifier is connected to the detector array to filter discrete coherent light having the period from captured light.

IPC Classes  ?

• C30B 15/24 - Stabilisation or shape controlling of the molten zone near the pulled crystal; Controlling the section of the crystal using mechanical means, e.g. shaping guides
• C30B 15/26 - Stabilisation or shape controlling of the molten zone near the pulled crystal; Controlling the section of the crystal using photo or X-ray detectors
• C30B 29/06 - Silicon

Abstract

A graphite susceptor for supporting a quartz crucible during a crystal growth process includes a body having an interior surface and a coating deposited onto the interior surface. The interior surface of the body defines a cavity, and the cavity has a size and shape complementary to an outer size and shape of the crucible. The coating includes boron nitride and a sintering additive. The sintering additive is configured to promote densification of the boron nitride.

IPC Classes  ?

• C30B 15/10 - Crucibles or containers for supporting the melt
• C30B 29/06 - Silicon

Abstract

Systems and methods for controlling the surface profiles of wafers sliced in a wire saw machine. The systems and methods are generally operable to alter the nanotopology of wafers sliced from an ingot by controlling the shape of the wafers. The shape of the wafers is altered for example by changing the temperature of a temperature-controlling fluid circulated in fluid communication with side walls attached to a fixed bearing sidewall of the wire saw.

IPC Classes  ?

• B28D 5/00 - Fine working of gems, jewels, crystals, e.g. of semiconductor material; Apparatus therefor
• B28D 5/04 - Fine working of gems, jewels, crystals, e.g. of semiconductor material; Apparatus therefor by tools other than of rotary type, e.g. reciprocating tools
• B28D 7/00 - Accessories specially adapted for use with machines or devices of the other groups of this subclass

Abstract

A heterostructure, includes: a substrate; and a buffer layer that includes a plurality of layers having a composition AlxInyGa1-x-yN, where x≤1 and 0≤y≤1; wherein the buffer layer has a first region that includes at least two layers, a second region that includes at least two layers, and a third region that includes at least two layers. The aluminum content varies continuously throughout a thickness of at least one of the layers.

IPC Classes  ?

• H01L 29/205 - Semiconductor bodies characterised by the materials of which they are formed including, apart from doping materials or other impurities, only AIIIBV compounds including two or more compounds in different semiconductor regions
• H01L 29/20 - Semiconductor bodies characterised by the materials of which they are formed including, apart from doping materials or other impurities, only AIIIBV compounds
• H01L 21/02 - Manufacture or treatment of semiconductor devices or of parts thereof

Abstract

A method of manufacturing a high electron mobility transistor (HEMT) structure is disclosed. By controlling a passivation layer and a barrier layer to uninterruptedly grow in the same growth chamber, defects of the passivation layer generated in the growth process due to a drastic change in temperature, pressure, or atmosphere or degrading a quality of an interface between the passivation layer and the barrier layer could be avoided, thereby providing the passivation layer with a good quality and the interface between the passivation layer and the barrier layer with a good quality, so that the objective of improving the performance of the HEMT structure could be achieved.

IPC Classes  ?

• H01L 29/66 - Types of semiconductor device
• H01L 23/29 - Encapsulation, e.g. encapsulating layers, coatings characterised by the material
• H01L 23/31 - Encapsulation, e.g. encapsulating layers, coatings characterised by the arrangement
• H01L 29/20 - Semiconductor bodies characterised by the materials of which they are formed including, apart from doping materials or other impurities, only AIIIBV compounds
• H01L 29/778 - Field-effect transistors with two-dimensional charge carrier gas channel, e.g. HEMT
• H01L 21/02 - Manufacture or treatment of semiconductor devices or of parts thereof
• H01L 21/66 - Testing or measuring during manufacture or treatment

Abstract

A method of manufacturing an epitaxial structure includes steps of: A: provide a silicon carbide (SiC) substrate, wherein a silicon face (Si-face) of the SiC substrate is taken as a growth face, and the growth face has an off-angle relative to the Si-face of the SiC substrate; B: deposit a nitride angle adjustment layer on the growth face of the SiC substrate through physical vapor deposition (PVD); C: deposit a first group III nitride layer on the nitride angle adjustment layer; and D: deposit a second group III nitride layer on the first group III nitride layer. Through the method of manufacturing the epitaxial structure, when the silicon face of the silicon carbide substrate has the off-angle, the problem of a poor epitaxial quality of the first group III nitride layer and a poor epitaxial quality of the second group III nitride layer could be effectively relieved.

IPC Classes  ?

• H01L 21/02 - Manufacture or treatment of semiconductor devices or of parts thereof
• H01L 29/20 - Semiconductor bodies characterised by the materials of which they are formed including, apart from doping materials or other impurities, only AIIIBV compounds
• H01L 29/205 - Semiconductor bodies characterised by the materials of which they are formed including, apart from doping materials or other impurities, only AIIIBV compounds including two or more compounds in different semiconductor regions
• C30B 25/18 - Epitaxial-layer growth characterised by the substrate
• C30B 29/40 - AIIIBV compounds
• C30B 29/36 - Carbides

Abstract

A method of manufacturing an epitaxial structure includes steps of: A: provide a silicon carbide (SiC) substrate, wherein a silicon face (Si-face) of the SiC substrate is taken as a growth face having an off-angle relative to the Si-face of the SiC substrate; B: deposit a nitride angle adjustment layer having a thickness less than 50 nm on the growth face of the SiC substrate through physical vapor deposition (PVD); C: deposit a first group III nitride layer on the nitride angle adjustment layer; and D: deposit a second group III nitride layer on the first group III nitride layer. Through the method of manufacturing the epitaxial structure, when the silicon face of the silicon carbide substrate has the off-angle, the problem of a poor epitaxial quality of the first group III nitride layer and a poor epitaxial quality of the second group III nitride layer could be effectively relieved.

IPC Classes  ?

• H01L 21/02 - Manufacture or treatment of semiconductor devices or of parts thereof
• C30B 25/18 - Epitaxial-layer growth characterised by the substrate
• C30B 29/40 - AIIIBV compounds
• C30B 29/68 - Crystals with laminate structure, e.g. "superlattices"
• C23C 16/30 - Deposition of compounds, mixtures or solid solutions, e.g. borides, carbides, nitrides
• C23C 16/02 - Pretreatment of the material to be coated

Abstract

A method of manufacturing an epitaxial structure includes steps of: A: provide a silicon nitride (SiC) substrate having a carbon face (C-face) without an off-angle; B: form an amorphous structure layer on the C-face of the SiC substrate; C: deposit a first group III nitride layer on the amorphous structure layer; and D: deposit a second group III nitride layer on the first group III nitride layer. By forming the amorphous structure layer, a top surface of the second group III nitride layer could be made to be in a flat and smooth state.

IPC Classes  ?

• C23C 14/06 - Coating by vacuum evaporation, by sputtering or by ion implantation of the coating forming material characterised by the coating material
• C23C 16/02 - Pretreatment of the material to be coated
• C23C 16/18 - Chemical coating by decomposition of gaseous compounds, without leaving reaction products of surface material in the coating, i.e. chemical vapour deposition (CVD) processes characterised by the deposition of metallic material from metallo-organic compounds
• C23C 14/54 - Controlling or regulating the coating process

Abstract

A method for collecting dust from a single crystal growth system includes providing dry air and oxygen into an exit pipe connecting to the single crystal growth system, blowing a first inert gas into the exit pipe to compel the dust oxide toward a dust collecting device, collecting the dust oxide by the dust collecting device; and providing a rotary pump to transport residues of the dust oxide backward. The oxygen reacts with the unstable dust for forming dust oxide. The exit pipe is used to exhaust unstable dust from the single crystal growth system.

IPC Classes  ?

• B01D 45/16 - Separating dispersed particles from gases or vapours by gravity, inertia, or centrifugal forces by centrifugal forces generated by the winding course of the gas stream
• C30B 35/00 - Apparatus not otherwise provided for, specially adapted for the growth, production or after-treatment of single crystals or of a homogeneous polycrystalline material with defined structure
• B01D 53/14 - Separation of gases or vapours; Recovering vapours of volatile solvents from gases; Chemical or biological purification of waste gases, e.g. engine exhaust gases, smoke, fumes, flue gases or aerosols by absorption
• B01D 53/76 - Gas phase processes, e.g. by using aerosols
• B04C 5/185 - Dust collectors
• B04C 9/00 - Combinations with other devices, e.g. fans
• B01D 53/46 - Removing components of defined structure

Abstract

Cleaning tools for cleaning the pull cable of an ingot puller apparatus and methods for cleaning the pull cable are disclosed. The cleaning tool includes a chamber for receiving the pull cable. Pressurized fluid is discharged through one or more nozzles to detach debris from the pull cable. The fluid and debris are collected in an exhaust plenum of the cleaning tool and are expelled through an exhaust tube. The cleaning tool includes one or more guides that guide the cleaning tool in an upper segment of the ingot puller apparatus.

IPC Classes  ?

• B08B 5/02 - Cleaning by the force of jets, e.g. blowing-out cavities
• C30B 15/30 - Mechanisms for rotating or moving either the melt or the crystal
• C30B 29/06 - Silicon

Abstract

A polishing assembly for polishing of silicon wafers includes a polishing pad, a polishing head assembly, a temperature sensor, and a controller. The polishing head assembly holds a silicon wafer to position the silicon wafer in contact with the polishing pad. The polishing head assembly selectively varies a removal profile of the silicon wafer. The temperature sensor collects thermal data from a portion of the polishing pad. The controller is communicatively coupled to the polishing head assembly and the temperature sensor. The controller receives the thermal data from the temperature sensor and operates the polishing head assembly to selectively vary the removal profile of the silicon wafer based at least in part on the thermal data.

IPC Classes  ?

• H01L 21/02 - Manufacture or treatment of semiconductor devices or of parts thereof
• B24B 37/015 - Temperature control
• B24B 49/14 - Measuring or gauging equipment for controlling the feed movement of the grinding tool or work; Arrangements of indicating or measuring equipment, e.g. for indicating the start of the grinding operation taking regard of the temperature during grinding

Abstract

A method of manufacturing a semiconductor wafer in a reaction apparatus includes channeling a process gas into a reaction chamber of the reaction apparatus, heating the semiconductor wafer with a high intensity lamp positioned below the reaction chamber, blocking radiant heat from the high intensity lamp from heating a center region of the semiconductor wafer with a cap positioned on a shaft within the reaction chamber, the cap including a tube and a disc attached to the tube, where the disc generates a uniform temperature distribution on the semiconductor wafer, and depositing a layer on the semiconductor wafer with the process gas, where the uniform temperature distribution forms a uniform thickness of the layer on the semiconductor wafer.

IPC Classes  ?

• H05B 3/00 - Ohmic-resistance heating
• H01L 21/263 - Bombardment with wave or particle radiation with high-energy radiation

Abstract

A semiconductor structure includes a silicon carbide (SiC) substrate, a nucleation layer and a gallium nitride (GaN) layer. The silicon carbide layer has a first thickness T1. The nucleation layer is located on the silicon carbide layer and has a second thickness T2. The nucleation layer is made of AlGaN (AlGaN), and the second thickness T2 fulfills a thickness range of T1*0.002% to T1*0.006%. The gallium nitride layer is located on the nucleation layer and is separated from the silicon carbide substrate.

IPC Classes  ?

• H01L 21/02 - Manufacture or treatment of semiconductor devices or of parts thereof

Abstract

Methods for forming single crystal silicon ingots with improved resistivity control are disclosed. The methods involve growth of a sample rod. The sample rod may have a diameter less than the diameter of the product ingot. The sample rod is cropped to form a center slab. The resistivity of the center slab may be measured directly such as by a four-point probe. The sample rod or optionally the center slab may be annealed in a thermal donor kill cycle prior to measuring the resistivity, and the annealed rod or slab is irradiated with light in order to enhance the relaxation rate and enable more rapid resistivity measurement.

IPC Classes  ?

• C30B 15/10 - Crucibles or containers for supporting the melt
• C30B 33/02 - Heat treatment
• C30B 15/02 - Single-crystal growth by pulling from a melt, e.g. Czochralski method adding crystallising materials or reactants forming it in situ to the melt
• C30B 15/14 - Heating of the melt or the crystallised materials
• C30B 29/06 - Silicon

Abstract

Nitrogen-doped CZ silicon crystal ingots and wafers sliced therefrom are disclosed that provide for post epitaxial thermally treated wafers having oxygen precipitate density and size that are substantially uniformly distributed radially and exhibit the lack of a significant edge effect. Methods for producing such CZ silicon crystal ingots are also provided by controlling the pull rate from molten silicon, the temperature gradient and the nitrogen concentration. Methods for simulating the radial bulk micro defect size distribution, radial bulk micro defect density distribution and oxygen precipitation density distribution of post epitaxial thermally treated wafers sliced from nitrogen-doped CZ silicon crystals are also provided.

IPC Classes  ?

• C30B 33/02 - Heat treatment
• C30B 29/06 - Silicon
• H01L 21/02 - Manufacture or treatment of semiconductor devices or of parts thereof
• H01L 21/00 - Processes or apparatus specially adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
• C30B 15/20 - Controlling or regulating

Abstract

A detection system includes a loadcell connected to a gear and motor of a crystal puller apparatus to measure force applied to the gear in a time domain. The data is analyzed though a Fourier transform to obtain data in the frequency domain. The frequency domain data includes an amplitude which corresponds to mechanical wear of the gear. The time domain data is compared against a threshold amplitude to determine if the gears have mechanical wear such that preventative maintenance can be performed on the motor.

IPC Classes  ?

• G01M 13/021 - Gearings
• C30B 15/20 - Controlling or regulating
• C30B 15/30 - Mechanisms for rotating or moving either the melt or the crystal
• C30B 29/06 - Silicon

Abstract

A method for producing Si ingot single crystal by NOC growth method including a Si ingot single crystal growing step and a continuous growing step is provided. The growing step includes providing a low temperature region in the Si melt where the Si ingot single crystal is grown along the surface of the Si melt or toward the inside of the Si melt, and the Si ingot single crystal has distribution of a vacancy concentration and an interstitial concentration in which respectively a vacancy concentration and an interstitial concentration vary with a distance from the growth interface; and adjusting a temperature gradient and a growth rate in the Si melt, so that along with the increasing of the distance from the growth interface, the vacancy concentration and the interstitial concentration in the Si ingot single crystal respectively decrease come near to each other.

IPC Classes  ?

• C30B 15/00 - Single-crystal growth by pulling from a melt, e.g. Czochralski method
• C30B 29/06 - Silicon
• C30B 35/00 - Apparatus not otherwise provided for, specially adapted for the growth, production or after-treatment of single crystals or of a homogeneous polycrystalline material with defined structure
• C30B 15/36 - Single-crystal growth by pulling from a melt, e.g. Czochralski method characterised by the seed, e.g. its crystallographic orientation
• C30B 15/10 - Crucibles or containers for supporting the melt

Abstract

An improved high electron mobility transistor (HEMT) structure includes a substrate, a nitride nucleation layer, a nitride buffer layer, a nitride channel layer, and a barrier layer. The nitride buffer layer includes a metal dopant. The nitride channel layer has a metal doping concentration less than that of the nitride buffer layer. A two-dimensional electron gas is formed in the nitride channel layer along an interface between the nitride channel layer and the barrier layer. A metal doping concentration X at an interface between the nitride buffer layer and the nitride channel layer is defined as the number of metal atoms per cubic centimeter, and a thickness Y of the nitride channel later is in microns (μm) and satisfies Y≤(0.2171)ln(X)−8.34, thereby reducing an influence of the metal dopant to a sheet resistance value of the nitride channel layer and providing the improved HEMT structure having a better performance.

IPC Classes  ?

• H01L 29/778 - Field-effect transistors with two-dimensional charge carrier gas channel, e.g. HEMT
• H01L 29/66 - Types of semiconductor device
• H01L 29/20 - Semiconductor bodies characterised by the materials of which they are formed including, apart from doping materials or other impurities, only AIIIBV compounds
• H01L 29/10 - Semiconductor bodies characterised by the shapes, relative sizes, or dispositions of the semiconductor regions with semiconductor regions connected to an electrode not carrying current to be rectified, amplified, or switched and such electrode being part of a semiconductor device which comprises three or more electrodes

Abstract

An improved high electron mobility transistor (HEMT) structure includes in order a substrate, a nucleation layer, a buffer layer, a channel layer, and a barrier layer, wherein the buffer layer includes a dopant. The channel layer having a dopant doping concentration less than that of the buffer layer. A two-dimension electron gas is formed in the channel layer along an interface between the channel layer and the barrier layer. A dopant doping concentration of the channel layer at an interface between the channel layer and the barrier layer is equal to or greater than 1×1015 cm−3.

IPC Classes  ?

• H01L 29/778 - Field-effect transistors with two-dimensional charge carrier gas channel, e.g. HEMT
• H01L 29/66 - Types of semiconductor device
• H01L 29/20 - Semiconductor bodies characterised by the materials of which they are formed including, apart from doping materials or other impurities, only AIIIBV compounds
• H01L 29/10 - Semiconductor bodies characterised by the shapes, relative sizes, or dispositions of the semiconductor regions with semiconductor regions connected to an electrode not carrying current to be rectified, amplified, or switched and such electrode being part of a semiconductor device which comprises three or more electrodes

Abstract

A wafer and a wafer processing method are included. The wafer processing method includes the following steps. A wafer is provided having a first surface and a second surface opposite to the first surface. A fixture pattern is pasted on the first surface to cover a first portion of the first surface of the wafer, and a second portion of the first surface is exposed by the fixture pattern. A first etching step is performed on the second portion of the first surface to form a first etching pattern on the first surface of the wafer. The fixture pattern is removed from the first surface, and the second surface of the wafer is ground.

IPC Classes  ?

• H01L 21/02 - Manufacture or treatment of semiconductor devices or of parts thereof

Abstract

A computer device is programmed to store a model for converting shape maps to simulate a portion of an assembly line, receive scan data of a first inspection of a product being assembled, generate a shape map from the scan data of the first inspection, execute the model using the shape map as an input to generate a final shape map of the product, compare the final shape map to one or more thresholds, determine if the final shape map exceeds at least one of the one or more thresholds, and if the determination is that the final shape map exceeds at least one of the one or more thresholds, cause the first device to be adjusted.

IPC Classes  ?

• H01L 21/66 - Testing or measuring during manufacture or treatment

Abstract

Ingot puller apparatus that include a silicon feed tube for adding solid silicon to a crucible assembly are disclosed. The silicon feed tubes include a conduit portion having an inner diameter and a kick plate disposed below the conduit portion. The kick plate extends across at least 60% of the inner diameter of the conduit portion.

IPC Classes  ?

• C30B 29/06 - Silicon
• C30B 15/10 - Crucibles or containers for supporting the melt
• C30B 15/20 - Controlling or regulating

Abstract

A slurry sprayer for supplying a slurry to a wire saw during ingot slicing is disclosed. The slurry sprayer includes a main body and a cover plate that is detachable from the main body for cleaning the slurry sprayer. In some embodiments, the slurry sprayer includes an adjustable support that allows the incline angle of the sprayer to be adjusted and allows the vertical and horizontal position of the slurry sprayer to be adjusted. In some embodiments, the slurry sprayer includes two feed openings to allow the slurry pressure to be more equalized across the slurry sprayer.

IPC Classes  ?

• B28D 5/00 - Fine working of gems, jewels, crystals, e.g. of semiconductor material; Apparatus therefor
• B28D 5/04 - Fine working of gems, jewels, crystals, e.g. of semiconductor material; Apparatus therefor by tools other than of rotary type, e.g. reciprocating tools

Abstract

A method of producing an epitaxial semiconductor wafer includes measuring one or more epitaxial semiconductor wafers to determine an epitaxial deposition layer profile produced by an epitaxy apparatus. The method also includes polishing a semiconductor wafer using a polishing assembly and measuring the polished semiconductor wafer to determine a surface profile of the polished wafer. The method further includes generating a predicted post-epitaxy surface profile of the polished wafer by comparing the surface profile of the polished wafer and the determined epitaxial deposition layer profile produced by the epitaxy apparatus. The method also includes determining a predicted post-epitaxy parameter based on the predicted post-epitaxy surface profile and adjusting, based on the predicted post-epitaxy parameter, a process condition of the polishing assembly.

IPC Classes  ?

• H01L 21/304 - Mechanical treatment, e.g. grinding, polishing, cutting
• H01L 21/66 - Testing or measuring during manufacture or treatment
• B24B 37/04 - Lapping machines or devices; Accessories designed for working plane surfaces
• H01L 21/02 - Manufacture or treatment of semiconductor devices or of parts thereof

Abstract

Methods for removing an oxide film and for cleaning silicon-on-insulator structures are disclosed. The methods may involve immersing the silicon-on-insulator structure in a stripping bath to strip an oxide film from the surface of the silicon-on-insulator structure. The stripped silicon-on-insulator structure is immersed in an ozone bath comprising ozone. The ozone-treated silicon-on-insulator structure may be immersed in an SC-1 bath comprising ammonium hydroxide and hydrogen peroxide to clean the structure.

IPC Classes  ?

• H01L 21/02 - Manufacture or treatment of semiconductor devices or of parts thereof
• B08B 3/08 - Cleaning involving contact with liquid the liquid having chemical or dissolving effect
• C11D 3/04 - Water-soluble compounds
• C11D 11/00 - Special methods for preparing compositions containing mixtures of detergents
• C11D 1/72 - Ethers of polyoxyalkylene glycols
• F26B 21/14 - Arrangements for supplying or controlling air or gases for drying solid materials or objects using gases or vapours other than air or steam

Abstract

A liner assembly for a substrate processing system includes a first liner and a second liner. The first liner includes an annular body and an outer peripheral surface including a first fluid guide. The first fluid guide is curved about a circumferential line extending around the first liner. The second liner includes an annular body, an outer rim, an inner rim, a second fluid guide extending between the outer rim and the inner rim, and a plurality of partition walls extending outwardly from the second fluid guide. The second fluid guide is curved about the circumferential line when the first and second liners are positioned within the processing system.

IPC Classes  ?

• C23C 16/455 - Chemical coating by decomposition of gaseous compounds, without leaving reaction products of surface material in the coating, i.e. chemical vapour deposition (CVD) processes characterised by the method of coating characterised by the method used for introducing gases into the reaction chamber or for modifying gas flows in the reaction chamber
• H01J 37/32 - Gas-filled discharge tubes

Abstract

Methods for producing a product ingot from a silicon melt held within a crucible are disclosed. The methods involve evaluating one or more ingot puller apparatus to determine if the apparatus is capable of producing low oxygen content silicon product ingots. A sample rod is pulled from the silicon melt and the oxygen content of the sample rod is measured.

IPC Classes  ?

• C30B 15/20 - Controlling or regulating
• C30B 29/06 - Silicon
• C30B 33/08 - Etching

Abstract

A method for producing a silicon ingot includes withdrawing a seed crystal from a melt that includes melted silicon in a crucible that is enclosed in a vacuum chamber containing a cusped magnetic field. At least one process parameter is regulated in at least two stages, including a first stage corresponding to formation of the silicon ingot up to an intermediate ingot length, and a second stage corresponding to formation of the silicon ingot from the intermediate ingot length to the total ingot length. During the second stage process parameter regulation may include reducing a crystal rotation rate, reducing a crucible rotation rate, and/or increasing a magnetic field strength relative to the first stage.

IPC Classes  ?

• C30B 15/20 - Controlling or regulating
• C30B 29/06 - Silicon
• C30B 15/30 - Mechanisms for rotating or moving either the melt or the crystal
• C30B 15/10 - Crucibles or containers for supporting the melt
• C30B 30/04 - Production of single crystals or homogeneous polycrystalline material with defined structure characterised by the action of electric or magnetic fields, wave energy or other specific physical conditions using magnetic fields

Abstract

A method of manufacturing a semiconductor wafer in a reaction apparatus comprising channeling a process gas into a reaction chamber through the process gas inlet and heating the process gas with the preheat ring having an edge bar. The method also includes adjusting at least one of a velocity and a direction of the process gas with the edge bar, and depositing a layer on the semiconductor wafer with the process gas, wherein the edge bar facilitates forming a uniform thickness of the layer on the semiconductor wafer.

IPC Classes  ?

• C30B 25/10 - Heating of the reaction chamber or the substrate
• C30B 25/14 - Feed and outlet means for the gases; Modifying the flow of the reactive gases
• C23C 16/458 - Chemical coating by decomposition of gaseous compounds, without leaving reaction products of surface material in the coating, i.e. chemical vapour deposition (CVD) processes characterised by the method of coating characterised by the method used for supporting substrates in the reaction chamber
• C30B 25/12 - Substrate holders or susceptors
• H01L 21/02 - Manufacture or treatment of semiconductor devices or of parts thereof
• C23C 16/455 - Chemical coating by decomposition of gaseous compounds, without leaving reaction products of surface material in the coating, i.e. chemical vapour deposition (CVD) processes characterised by the method of coating characterised by the method used for introducing gases into the reaction chamber or for modifying gas flows in the reaction chamber
• C30B 29/06 - Silicon

Abstract

Methods for forming a unitized crucible assembly for holding a melt of silicon for forming a silicon ingot are disclosed. In some embodiments, the methods involve a porous crucible mold having a channel network with a bottom channel, an outer sidewall channel that extends from the bottom channel, and a central weir channel that extends from the bottom channel. A slip slurry may be added to the channel network and the liquid carrier of the slip slurry may be drawn into the mold. The resulting green body may be sintered to form the crucible assembly.

IPC Classes  ?

• C30B 15/10 - Crucibles or containers for supporting the melt
• B28B 7/16 - Moulds for making shaped articles with cavities or holes open to the surface
• C30B 15/00 - Single-crystal growth by pulling from a melt, e.g. Czochralski method
• B28B 1/26 - Producing shaped articles from the material by slip-casting, i.e. by casting a suspension or dispersion of the material in a liquid-absorbent or porous mould, the liquid being allowed to soak into or pass through the walls of the mould; Moulds therefor
• C30B 35/00 - Apparatus not otherwise provided for, specially adapted for the growth, production or after-treatment of single crystals or of a homogeneous polycrystalline material with defined structure
• C30B 29/06 - Silicon
• B22C 9/00 - Moulds or cores; Moulding processes
• C04B 38/00 - Porous mortars, concrete, artificial stone or ceramic ware; Preparation thereof
• C30B 15/12 - Double crucible methods

Abstract

A semiconductor structure, including a substrate, a first nitride layer, a polarity inversion layer, a second nitride layer, and a third nitride layer, is provided. The first nitride layer is located on the substrate. The polarity inversion layer is located on a surface of the first nitride layer to convert a non-metallic polarity surface of the first nitride layer into a metallic polarity surface of the polarity inversion layer. The second nitride layer is located on the polarity inversion layer. The third nitride layer is located on the second nitride layer. The substrate, the first nitride layer, the polarity inversion layer, and the second nitride layer include iron element.

IPC Classes  ?

• H01L 29/34 - Semiconductor bodies having polished or roughened surface the imperfections being on the surface
• H01L 29/20 - Semiconductor bodies characterised by the materials of which they are formed including, apart from doping materials or other impurities, only AIIIBV compounds

Abstract

Methods for growing single crystal silicon ingots that involve silicon feed tube inert gas control are disclosed. Ingot puller apparatus that include a flange that extends radially from a silicon funnel or from a silicon feed tube to reduce backflow of gases from the silicon feed tube into the growth chamber are also disclosed.

IPC Classes  ?

• C30B 15/10 - Crucibles or containers for supporting the melt
• C30B 35/00 - Apparatus not otherwise provided for, specially adapted for the growth, production or after-treatment of single crystals or of a homogeneous polycrystalline material with defined structure
• C30B 15/20 - Controlling or regulating

Abstract

A semiconductor-on-insulator (e.g., silicon-on-insulator) structure having superior radio frequency device performance, and a method of preparing such a structure, is provided by utilizing a single crystal silicon handle wafer sliced from a float zone grown single crystal silicon ingot.

IPC Classes  ?

• H01L 21/762 - Dielectric regions
• C30B 15/20 - Controlling or regulating
• C30B 29/06 - Silicon
• H01L 21/322 - Treatment of semiconductor bodies using processes or apparatus not provided for in groups to modify their internal properties, e.g. to produce internal imperfections
• H01L 23/66 - High-frequency adaptations
• H01L 27/12 - Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being other than a semiconductor body, e.g. an insulating body
• H01L 29/06 - Semiconductor bodies characterised by the shapes, relative sizes, or dispositions of the semiconductor regions

Abstract

A heterostructure, includes: a substrate; and a buffer layer that includes a plurality of layers having a composition AlxInyGa1-x-yN, where x≤1 and y≥0; wherein the buffer layer has a first region that includes at least two layers, a second region that includes at least two layers, and a third region that includes at least two layers.

IPC Classes  ?

• H01L 29/205 - Semiconductor bodies characterised by the materials of which they are formed including, apart from doping materials or other impurities, only AIIIBV compounds including two or more compounds in different semiconductor regions
• H01L 29/20 - Semiconductor bodies characterised by the materials of which they are formed including, apart from doping materials or other impurities, only AIIIBV compounds
• H01L 21/02 - Manufacture or treatment of semiconductor devices or of parts thereof

Abstract

Methods for growing single crystal silicon ingots that involve silicon feed tube inert gas control are disclosed. Ingot puller apparatus that include a flange that extends radially from a silicon funnel or from a silicon feed tube to reduce backflow of gases from the silicon feed tube into the growth chamber are also disclosed.

IPC Classes  ?

• C30B 15/10 - Crucibles or containers for supporting the melt
• C30B 29/06 - Silicon

Abstract

A polishing head assembly for polishing of semiconductor wafers includes a polishing head and a cap. The polishing head has a recess along a bottom portion. The recess has a recessed surface. The cap is positioned within the recess. The cap includes an annular wall secured to the polishing head and a floor joined to the annular wall at a joint. The floor extends across the annular wall, and the floor has an upper surface and a lower surface. The upper surface is spaced from the recessed surface to form a chamber therebetween. A deformation resistance of a portion of the floor proximate the joint is weakened to allow the portion of the floor proximate the joint to deflect relative to the polishing head by a change of pressure in the chamber.

IPC Classes  ?

• B24B 37/26 - Lapping pads for working plane surfaces characterised by the shape of the lapping pad surface, e.g. grooved

Abstract

An ingot evaluation method and a detecting apparatus are provided. Defect information of a wafer is obtained from an ingot. The defect information includes a position of at least one defect identified by optical detection. A center-of-gravity position of the defect is determined according to the defect information. Uniformity of the defect is evaluated according to the center-of-gravity position. The uniformity is related to quality of a processed wafer.

IPC Classes  ?

• G01N 21/95 - Investigating the presence of flaws, defects or contamination characterised by the material or shape of the object to be examined
• G01M 1/12 - Static balancing; Determining position of centre of gravity

Abstract

Methods for polishing semiconductor substrates are disclosed. The methods may involve alternating a first and second polishing slurry during polishing. The first and second slurries each contain silica particles with the silica particles of the first slurry containing more silica than the particles of the second slurry. By alternating between first and second polishing slurries, the polishing method may improve wafer flatness.

IPC Classes  ?

• H01L 21/306 - Chemical or electrical treatment, e.g. electrolytic etching
• B24B 37/04 - Lapping machines or devices; Accessories designed for working plane surfaces
• C09G 1/02 - Polishing compositions containing abrasives or grinding agents
• C09K 3/14 - Anti-slip materials; Abrasives

Abstract

A method for producing Si ingot single crystal including a Si ingot single crystal growing step, a temperature gradient controlling step and a continuous growing step is provided. In the growing step, the Si ingot single crystal is grown in silicon melt in crucible, and the growing step includes providing a low-temperature region in the Si melt and providing a silicon seed to contact the melt surface of the silicon melt to start crystal growth, and silicon single crystal grows along the melt surface of the silicon melt and toward the inside of the silicon melt. In the temperature gradient controlling step, the under-surface temperature gradient of the silicon single crystal is G1, the above-surface temperature gradient of the silicon single crystal is G2, G1 and G2 satisfy: G2/G1<6. The step of controlling the temperature gradient of silicon single crystal is repeated to obtain the Si ingot single crystal.

IPC Classes  ?

• C30B 15/14 - Heating of the melt or the crystallised materials
• C30B 29/06 - Silicon
• C30B 35/00 - Apparatus not otherwise provided for, specially adapted for the growth, production or after-treatment of single crystals or of a homogeneous polycrystalline material with defined structure
• C30B 15/10 - Crucibles or containers for supporting the melt
• C30B 15/20 - Controlling or regulating

Abstract

A multilayer composite structure and a method of preparing a multilayer composite structure are provided. The multilayer composite structure comprises a semiconductor handle substrate having a minimum bulk region resistivity of at least about 500 ohm-cm and an isolation region that impedes the transfer of charge carriers along the surface of the handle substrate and reduces parasitic coupling between RF devices.

IPC Classes  ?

• H01L 21/762 - Dielectric regions
• H01L 21/304 - Mechanical treatment, e.g. grinding, polishing, cutting
• H01L 21/02 - Manufacture or treatment of semiconductor devices or of parts thereof
• H01L 21/761 - PN junctions
• H01L 29/06 - Semiconductor bodies characterised by the shapes, relative sizes, or dispositions of the semiconductor regions
• H01L 21/322 - Treatment of semiconductor bodies using processes or apparatus not provided for in groups to modify their internal properties, e.g. to produce internal imperfections

Abstract

Methods for producing a single crystal silicon ingot are disclosed. The ingot is doped with boron using solid-phase boric acid as the source of boron. Boric acid may be used to counter-dope the ingot during ingot growth. Ingot puller apparatus that use a solid-phase dopant are also disclosed. The solid-phase dopant may be disposed in a receptacle that is moved closer to the surface of the melt or a vaporization unit may be used to produce a dopant gas from the solid-phase dopant.

IPC Classes  ?

• C30B 15/04 - Single-crystal growth by pulling from a melt, e.g. Czochralski method adding crystallising materials or reactants forming it in situ to the melt adding doping materials, e.g. for n–p-junction
• C30B 15/10 - Crucibles or containers for supporting the melt
• C30B 15/14 - Heating of the melt or the crystallised materials
• C30B 29/06 - Silicon
• C30B 35/00 - Apparatus not otherwise provided for, specially adapted for the growth, production or after-treatment of single crystals or of a homogeneous polycrystalline material with defined structure

Abstract

Methods for producing a single crystal silicon ingot are disclosed. The ingot is doped with boron using solid-phase boric acid as the source of boron. Boric acid may be used to counter-dope the ingot during ingot growth. Ingot puller apparatus that use a solid-phase dopant are also disclosed. The solid-phase dopant may be disposed in a receptacle that is moved closer to the surface of the melt or a vaporization unit may be used to produce a dopant gas from the solid-phase dopant.

IPC Classes  ?

• C30B 15/04 - Single-crystal growth by pulling from a melt, e.g. Czochralski method adding crystallising materials or reactants forming it in situ to the melt adding doping materials, e.g. for n–p-junction
• C30B 15/10 - Crucibles or containers for supporting the melt
• C30B 15/14 - Heating of the melt or the crystallised materials
• C30B 29/06 - Silicon
• C30B 35/00 - Apparatus not otherwise provided for, specially adapted for the growth, production or after-treatment of single crystals or of a homogeneous polycrystalline material with defined structure

Abstract

Crystal pulling system having a housing and a crucible assembly are disclosed. The system includes a heat shield that defines a central passage through which an ingot passes during ingot growth. A cover member is moveable within the heat shield along a pull axis. The cover member may include an insulation layer. The cover member covers at least a portion of the charge during meltdown.

IPC Classes  ?

• C30B 15/10 - Crucibles or containers for supporting the melt
• C30B 15/14 - Heating of the melt or the crystallised materials
• C30B 29/06 - Silicon

Abstract

Methods for producing single crystal silicon ingots in which an array of quartz particles are added to the crucible assembly before ingot growth are disclosed. The array may be disposed in the outer melt zone of the crucible assembly as in a continuous Czochralski (CCz) process. The array may be made of quartz particles that are interconnected by linking members.

IPC Classes  ?

• C30B 15/02 - Single-crystal growth by pulling from a melt, e.g. Czochralski method adding crystallising materials or reactants forming it in situ to the melt
• C30B 15/12 - Double crucible methods
• C30B 15/00 - Single-crystal growth by pulling from a melt, e.g. Czochralski method
• C30B 29/06 - Silicon

Abstract

Crystal pulling system having a housing and a crucible assembly are disclosed. The system includes a heat shield that defines a central passage through which an ingot passes during ingot growth. A cover member is moveable within the heat shield along a pull axis. The cover member may include an insulation layer. The cover member covers at least a portion of the charge during meltdown.

IPC Classes  ?

• C30B 15/10 - Crucibles or containers for supporting the melt
• C30B 15/14 - Heating of the melt or the crystallised materials
• C30B 29/06 - Silicon

Abstract

Methods for producing single crystal silicon ingots by Continuous Czochralski (CCz) are disclosed. A batch of buffer members (e.g., quartz cullets) is added to an outer melt zone of the crucible assembly before the main body of the ingot is grown. In some embodiments, the ratio of the mass M of the batch of buffer members added to the melt to the time between adding the batch of buffer members to the melt and when the ingot main body begins to grow is controlled such that the ratio of M/T is greater than a threshold M/T.

IPC Classes  ?

• C30B 15/00 - Single-crystal growth by pulling from a melt, e.g. Czochralski method
• C30B 15/12 - Double crucible methods
• C30B 15/20 - Controlling or regulating
• C30B 29/06 - Silicon

Abstract

A semiconductor epitaxy structure includes a silicon carbide substrate, a nucleation layer, a gallium nitride buffer layer, and a stacked structure. The nucleation layer is formed on the silicon carbide substrate, the gallium nitride buffer layer is disposed on the nucleation layer, and the stacked structure is formed between the nucleation layer and the gallium nitride buffer layer. The stacked structure includes: a plurality of silicon nitride (SiNx) layers and a plurality of aluminum gallium nitride (AlxGa1-xN) layers alternately stacked, wherein the first layer of the plurality of silicon nitride layers is in direct contact with the nucleation layer.

IPC Classes  ?

• H01L 29/15 - Structures with periodic or quasi periodic potential variation, e.g. multiple quantum wells, superlattices
• H01L 29/267 - Semiconductor bodies characterised by the materials of which they are formed including, apart from doping materials or other impurities, elements provided for in two or more of the groups , , , , in different semiconductor regions

Abstract

A method for calculating an object pick-and-place sequence and an electronic apparatus for automatic storage pick-and-place are provided. When a warehousing operation is to be performed, the following steps are performed. A weight of an object to be stocked that is to be put on a shelf is obtained. The weight is substituted into a plurality of coordinate positions corresponding to a plurality of unused grid positions respectively, so as to calculate a plurality of estimated center of gravity positions. Whether the estimated center of gravity positions are located within a balance standard area is determined so as to sieve out a plurality of candidate grid positions from these unused grid positions. One of the candidate grid positions is selected as a recommended position of the object to be stocked.

IPC Classes  ?

• B65G 1/137 - Storage devices mechanical with arrangements or automatic control means for selecting which articles are to be removed
• G06Q 10/04 - Forecasting or optimisation specially adapted for administrative or management purposes, e.g. linear programming or "cutting stock problem"
• G06Q 10/08 - Logistics, e.g. warehousing, loading or distribution; Inventory or stock management
• G01G 19/52 - Weighing apparatus combined with other objects, e.g. with furniture

Abstract

Provided is a wafer jig including a bottom wall and a ring-shaped side wall. The bottom wall has a supporting surface. The ring-shaped side wall is connected to a periphery of the bottom wall. The ring-shaped side wall includes at least two step portions. The two step portions include a first step portion and a second step portion. The first step portion is connected between the supporting surface and the second step portion, and the first step portion protrudes along a direction toward a center of the bottom wall. The ring-shaped side wall surrounds the center. In addition, a wafer structure and a wafer processing method are also provided.

IPC Classes  ?

• H01L 21/683 - Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components for supporting or gripping
• H01L 21/02 - Manufacture or treatment of semiconductor devices or of parts thereof
• H01L 29/16 - Semiconductor bodies characterised by the materials of which they are formed including, apart from doping materials or other impurities, only elements of Group IV of the Periodic System in uncombined form

Abstract

An epitaxial reactor system includes a reactor, a cooling circuit, and a controller. The reactor includes a reaction chamber having an upper wall and a lower wall, an upper module positioned above the upper wall, and a lower module positioned below the lower wall. The cooling circuit includes a blower to circulate fluid within the upper module and the lower module and a damper selectably positioned to control an amount of fluid flow provided to each of the upper module and the lower module. The damper is coupled to a damper actuator that adjusts a position of the damper. The system further includes a controller configured to: receive epitaxial process information associated with the reactor, generate a blower output and a damper position output based on the epitaxial process information, transmit the blower output to the blower, and transmit the damper position output to the damper actuator.

IPC Classes  ?

• H01L 21/67 - Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components
• H01L 21/02 - Manufacture or treatment of semiconductor devices or of parts thereof

Abstract

Methods for producing single crystal silicon ingots are disclosed. The methods may involve modeling formation of thermal donors and target resistivity during downstream annealing processes such as during subsequent device manufacturing such as manufacturing of interposer devices. The model may output a pre-anneal wafer resistivity target range. The single crystal silicon ingot production process may be modeled to determine a counter-doping schedule to achieve the pre-anneal wafer resistivity target range across a longer length of the main body of the ingot.

IPC Classes  ?

• C30B 15/20 - Controlling or regulating
• C30B 15/04 - Single-crystal growth by pulling from a melt, e.g. Czochralski method adding crystallising materials or reactants forming it in situ to the melt adding doping materials, e.g. for n–p-junction
• C30B 33/02 - Heat treatment
• C30B 29/06 - Silicon

Abstract

Ingot puller apparatus for preparing a single crystal silicon ingot by the Czochralski method are disclosed. The ingot puller apparatus includes a heat shield. The heat shield has a leg segment that includes a void (i.e., an open space without insulation) disposed in the leg segment. The heat shield may also include insulation partially within the heat shield.

IPC Classes  ?

• C30B 15/10 - Crucibles or containers for supporting the melt
• C30B 15/08 - Downward pulling
• C30B 29/06 - Silicon
• C30B 35/00 - Apparatus not otherwise provided for, specially adapted for the growth, production or after-treatment of single crystals or of a homogeneous polycrystalline material with defined structure

Abstract

Crystal pulling systems having composite polycrystalline silicon feed tubes, methods for forming such tubes, and methods for forming a single crystal silicon ingot with use of such tubes. The composite polycrystalline silicon feed tubes include quartz and at least one dopant. The composite polycrystalline silicon feed tube may be made by a slip cast method.

IPC Classes  ?

• C30B 15/04 - Single-crystal growth by pulling from a melt, e.g. Czochralski method adding crystallising materials or reactants forming it in situ to the melt adding doping materials, e.g. for n–p-junction
• C30B 15/00 - Single-crystal growth by pulling from a melt, e.g. Czochralski method
• B28B 1/26 - Producing shaped articles from the material by slip-casting, i.e. by casting a suspension or dispersion of the material in a liquid-absorbent or porous mould, the liquid being allowed to soak into or pass through the walls of the mould; Moulds therefor
• B28B 11/24 - Apparatus or processes for treating or working the shaped articles for curing, setting or hardening
• C30B 29/06 - Silicon

Abstract

A cost effective process flow for manufacturing semiconductor on insulator structures is parallel is provided. Each of the multiple semiconductor-on-insulator composite structures prepared in parallel comprises a charge trapping layer (CTL).

IPC Classes  ?

• H01L 21/762 - Dielectric regions
• H01L 21/20 - Deposition of semiconductor materials on a substrate, e.g. epitaxial growth
• H01L 27/12 - Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being other than a semiconductor body, e.g. an insulating body
• H01L 21/84 - Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being other than a semiconductor body, e.g. being an insulating body
• H01L 23/522 - Arrangements for conducting electric current within the device in operation from one component to another including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
• H01L 29/04 - Semiconductor bodies characterised by their crystalline structure, e.g. polycrystalline, cubic or particular orientation of crystalline planes

Abstract

A method for identifying a wafer is provided, which includes the following steps. A marked frame is obtained from a wafer inspection picture. A gray scale index corresponding to the marked frame is calculated based on a gray scale value corresponding to each of multiple pixels included in the marked frame. The gray scale index indicates a proportion of pixels whose gray scale values are greater than a specified value. Whether a trace pattern in the marked frame is a scratch or a grain boundary is determined based on the gray scale index.

IPC Classes  ?

• G06T 7/00 - Image analysis
• G06T 7/13 - Edge detection

Abstract

A semiconductor-on-insulator (e.g., silicon-on-insulator) structure having superior radio frequency device performance, and a method of preparing such a structure, is provided by utilizing a single crystal silicon handle wafer sliced from a float zone grown single crystal silicon ingot.

IPC Classes  ?

• H01L 21/762 - Dielectric regions
• C30B 29/06 - Silicon
• H01L 21/322 - Treatment of semiconductor bodies using processes or apparatus not provided for in groups to modify their internal properties, e.g. to produce internal imperfections
• H01L 23/66 - High-frequency adaptations
• H01L 27/12 - Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being other than a semiconductor body, e.g. an insulating body
• H01L 29/06 - Semiconductor bodies characterised by the shapes, relative sizes, or dispositions of the semiconductor regions
• C30B 15/20 - Controlling or regulating

Abstract

The disclosure provides a silicon carbide seed crystal and a method of manufacturing a silicon carbide ingot. The silicon carbide seed crystal has a silicon surface and a carbon surface opposite to the silicon surface. A difference D between a basal plane dislocation density BPD1 of the silicon surface and a basal plane dislocation density BPD2 of the carbon surface satisfies the following formula (1), a local thickness variation (LTV) of the silicon carbide seed crystal is 2.5 μm or less, and a stacking fault (SF) density of the silicon carbide seed crystal is 10 EA/cm2 or less: The disclosure provides a silicon carbide seed crystal and a method of manufacturing a silicon carbide ingot. The silicon carbide seed crystal has a silicon surface and a carbon surface opposite to the silicon surface. A difference D between a basal plane dislocation density BPD1 of the silicon surface and a basal plane dislocation density BPD2 of the carbon surface satisfies the following formula (1), a local thickness variation (LTV) of the silicon carbide seed crystal is 2.5 μm or less, and a stacking fault (SF) density of the silicon carbide seed crystal is 10 EA/cm2 or less: D=(BPD1−BPD2)/BPD1≤25%  (1).

IPC Classes  ?

• C30B 23/02 - Epitaxial-layer growth
• C30B 29/36 - Carbides

Abstract

Methods for etching a semiconductor structure and for conditioning a processing reactor in which a single semiconductor structure is treated are disclosed. An engineered polycrystalline silicon surface layer is deposited on a susceptor which supports the semiconductor structure. The polycrystalline silicon surface layer may be engineered by controlling the temperature at which the layer is deposited, by grooving the polycrystalline silicon surface layer or by controlling the thickness of the polycrystalline silicon surface layer.

IPC Classes  ?

• H01L 21/687 - Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components for supporting or gripping using mechanical means, e.g. chucks, clamps or pinches
• H01L 21/311 - Etching the insulating layers
• C23C 16/24 - Deposition of silicon only
• H01J 37/32 - Gas-filled discharge tubes

Abstract

A method for processing semiconductor wafers includes obtaining measurement data of an edge profile of a semiconductor wafer processed by a front-end process tool. The method includes determining an edge profile center point based on the measurement data, generating a raw height profile, and generating an ideal edge profile. The method further includes generating a Gapi edge profile of the semiconductor wafer based on the raw height profile and the ideal edge profile and calculating a Gapi edge value of the semiconductor wafer based on the Gapi edge profile. The generated Gapi edge profile and/or the calculated Gapi edge value may be used to tune the front-end process tool and/or sort the semiconductor wafer for polishing. Systems include at least a front-end process tool, a flatness measurement tool, and a computing device.

IPC Classes  ?

• B24B 9/06 - Machines or devices designed for grinding edges or bevels on work or for removing burrs; Accessories therefor characterised by a special design with respect to properties of materials specific to articles to be ground of non-metallic inorganic material, e.g. stone, ceramics, porcelain
• H01L 21/66 - Testing or measuring during manufacture or treatment
• H01L 21/67 - Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components

Abstract

A method for processing semiconductor wafers includes obtaining measurement data from a surface of a semiconductor wafer processed by a front-end process tool. The method includes determining a center plane of the wafer based on the measurement data, generating raw shape profiles, and generating ideal shape profiles. The method further includes generating Gapi profiles based on the raw shape profiles and the ideal shape profiles, and calculating a Gapi value of the semiconductor wafer based on the Gapi profiles. The generated Gapi profiles and/or the calculated Gapi value may be used to tune the front-end process tool and/or sort the semiconductor wafer for polishing. Systems include at least a front-end process tool, a flatness measurement tool, and a computing device.

IPC Classes  ?

• G01N 21/88 - Investigating the presence of flaws, defects or contamination
• H01L 21/304 - Mechanical treatment, e.g. grinding, polishing, cutting
• H01L 21/67 - Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components
• H01L 21/66 - Testing or measuring during manufacture or treatment

Abstract

Provided is a method of SiC wafer processing, and the method includes the following steps. A SiC wafer is provided, and the SiC wafer has a first surface and an opposing second surface. A fine grinding process is performed on the first surface and the second surface of the SiC wafer. A dry etching process is performed on the first surface and the second surface of the SiC wafer to make the roughness of the first surface and the second surface 2.5 nm or less. After the dry etching process, a polishing process is performed on the first surface and the second surface of the SiC wafer.

IPC Classes  ?

• H01L 21/02 - Manufacture or treatment of semiconductor devices or of parts thereof

Abstract

A semiconductor structure includes a substrate, a first nitride layer, a second nitride layer, a third nitride layer, and a polarity inversion layer. The first nitride layer is formed on the substrate, and the polarity inversion layer formed at a surface of the first nitride layer converts a non-metallic polar surface of the first nitride layer into a metallic polar surface of the polarity inversion layer. The second nitride layer is formed on the polarity inversion layer. The third nitride layer is formed on the second nitride layer.

IPC Classes  ?

• H01L 29/20 - Semiconductor bodies characterised by the materials of which they are formed including, apart from doping materials or other impurities, only AIIIBV compounds
• H01L 21/02 - Manufacture or treatment of semiconductor devices or of parts thereof

Abstract

An ingot jig assembly is provided, including an end surface clamping jig and an ingot positioning jig. The end surface clamping jig includes two opposite clamping parts. The ingot positioning jig is located below the end surface clamping jig and includes a first base, an adjusting base, and two rollers. The adjusting base is located between the first base and the end surface clamping jig and is movably disposed on the first base along a first axis to be close to or away from the end surface clamping jig. The two rollers are rotatably disposed on the adjusting base. An ingot edge-polishing machine tool is also provided.

IPC Classes  ?

• B23Q 3/06 - Work-clamping means
• B24B 31/12 - Accessories; Protective equipment or safety devices; Installations for exhaustion of dust or for sound absorption specially adapted for machines covered by group
• B24B 41/06 - Work supports, e.g. adjustable steadies

Abstract

A crystal growth doping apparatus and a crystal growth doping method are provided. The crystal growth doping apparatus includes a crystal growth furnace and a doping device that includes a feeding tube inserted to the furnace body along an oblique insertion direction, and a storage cover and a gate tube that are disposed in the feeding tube. The feeding tube extends from an outer surface thereof to form a placement opening, and the placement opening is recessed from an edge thereof to form an upper recessed portion and a lower recessed portion along the oblique insertion direction. The storage cover includes a storage tank and a handle. When the storage cover is disposed in the gate tube body, the gate tube body is configured to isolate an inner space of the feeding tube from the placement opening.

IPC Classes  ?

• C30B 35/00 - Apparatus not otherwise provided for, specially adapted for the growth, production or after-treatment of single crystals or of a homogeneous polycrystalline material with defined structure
• C30B 15/04 - Single-crystal growth by pulling from a melt, e.g. Czochralski method adding crystallising materials or reactants forming it in situ to the melt adding doping materials, e.g. for n–p-junction
• C30B 11/04 - Single-crystal-growth by normal freezing or freezing under temperature gradient, e.g. Bridgman- Stockbarger method adding crystallising materials or reactants forming it in situ to the melt

Abstract

Cleave systems for cleaving a semiconductor structure are disclosed. The cleave systems may include a cleave arm that is moveable from a starting position to a raised position in which a cleave stress is applied to the semiconductor structure. Spring members store energy as the cleave arm is raised with the stored spring energy causing the structure to cleave into two pieces upon initiation of the cleave across the structure.

IPC Classes  ?

• H01L 21/67 - Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components
• H01L 21/683 - Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components for supporting or gripping
• H01L 21/78 - Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices

Abstract

A wafer includes a semiconductor substrate. The semiconductor substrate includes a plurality of first doped regions and a plurality of second doped regions. The first doped regions and the second doped regions are located on a first surface of the semiconductor substrate. The second doped regions contact the first doped regions. The first doped regions and the second doped regions are alternately arranged. Both of the first doped regions and the second doped regions include a plurality of N-type dopants. The doping concentration of the N-type dopants in each of the first doped regions is not greater than the doping concentration of the N-type dopants in each of the second doped regions.

IPC Classes  ?

• H01L 21/266 - Bombardment with wave or particle radiation with high-energy radiation producing ion implantation using masks
• H01L 29/36 - Semiconductor bodies characterised by the concentration or distribution of impurities
• H01L 21/265 - Bombardment with wave or particle radiation with high-energy radiation producing ion implantation

Abstract

A silicon carbide crystal includes a seed layer, a bulk layer, and a stress buffering structure formed between the seed layer and the bulk layer. The seed layer, the bulk layer, and the stress buffering structure are each formed with a dopant that cycles between high and low dopant concentration. The stress buffering structure includes a plurality of stacked buffer layers and a transition layer over the buffer layers. The buffer layer closest to the seed layer has the same variation trend of the dopant concentration as the buffer layer closest to the transition layer, and the dopant concentration of the transition layer is equal to the dopant concentration of the seed layer.

IPC Classes  ?

• C30B 23/02 - Epitaxial-layer growth
• H01L 29/36 - Semiconductor bodies characterised by the concentration or distribution of impurities
• H01L 21/02 - Manufacture or treatment of semiconductor devices or of parts thereof
• C30B 23/00 - Single-crystal growth by condensing evaporated or sublimed materials
• H01L 29/32 - Semiconductor bodies having polished or roughened surface the imperfections being within the semiconductor body
• H01L 29/16 - Semiconductor bodies characterised by the materials of which they are formed including, apart from doping materials or other impurities, only elements of Group IV of the Periodic System in uncombined form
• C30B 25/02 - Epitaxial-layer growth
• C30B 29/36 - Carbides

Abstract

A polishing head assembly for polishing of semiconductor wafers includes a polishing head and a cap. The polishing head has a top portion and a recess along a bottom portion. The recess has a recessed surface. Holes extend from the top portion through the recessed surface. The cap is positioned within the recess and the cap has an annular wall and a floor extending across the annular wall. The annular wall has apertures corresponding to the holes. The floor is spaced from the recessed surface to form a chamber therebetween. The polishing head assembly also includes a band that circumscribes a portion of the annular wall. The holes and the corresponding apertures receive fasteners to removably secure the annular wall to the recessed surface.

IPC Classes  ?

• B24B 37/26 - Lapping pads for working plane surfaces characterised by the shape of the lapping pad surface, e.g. grooved

Abstract

A wafer processing apparatus includes a pressure applying element, a rotatable element, a control element, and a heat source. The pressure applying element includes a first pressure applying head having a first working surface and a second pressure applying head having a second working surface. The rotatable element and the pressure applying element are connected. The control element is electrically connected to the rotatable element. The heat source is disposed beside the pressure applying element.

IPC Classes  ?

• H01L 21/67 - Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components
• H01L 21/687 - Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components for supporting or gripping using mechanical means, e.g. chucks, clamps or pinches
• H05B 6/80 - Apparatus for specific applications
• H05B 6/64 - Heating using microwaves

Abstract

Methods for determining suitability of Czochralski growth conditions to produce silicon substrates for epitaxy. The methods involve evaluating substrates sliced from ingots grown under different growth conditions (e.g., impurity profiles) by imaging the wafer by infrared depolarization. An infrared depolarization parameter is generated for each epitaxial wafer. The parameters may be compared to determine which growth conditions are well-suited to produce substrates for epitaxial and/or post-epi heat treatments.

IPC Classes  ?

• C30B 25/16 - Controlling or regulating
• C30B 15/00 - Single-crystal growth by pulling from a melt, e.g. Czochralski method
• C30B 25/20 - Epitaxial-layer growth characterised by the substrate the substrate being of the same materials as the epitaxial layer
• C30B 29/06 - Silicon

Abstract

Methods for determining suitability of a silicon substrate for epitaxy and/or for determining slip resistance during epitaxy and post-epitaxy thermal treatment are disclosed. The methods involve evaluating different substrates of the epitaxial wafers by imaging the wafer by infrared depolarization. An infrared depolarization parameter is generated for each epitaxial wafer. The parameters may be compared to determine which substrates are well-suited for epitaxial and/or post-epi heat treatments.

IPC Classes  ?

• C30B 25/16 - Controlling or regulating
• H01L 21/66 - Testing or measuring during manufacture or treatment
• C30B 25/20 - Epitaxial-layer growth characterised by the substrate the substrate being of the same materials as the epitaxial layer
• C30B 29/06 - Silicon
• C30B 33/02 - Heat treatment

Abstract

A method of manufacturing silicon carbide seed crystal and method of manufacturing silicon carbide ingot are provided. The silicon carbide seed crystal has a silicon surface and a carbon surface opposite to the silicon surface. A difference D between a basal plane dislocation density BPD1 of the silicon surface BPD1 and a basal plane dislocation density BPD2 of the carbon surface satisfies the following formula (1): A method of manufacturing silicon carbide seed crystal and method of manufacturing silicon carbide ingot are provided. The silicon carbide seed crystal has a silicon surface and a carbon surface opposite to the silicon surface. A difference D between a basal plane dislocation density BPD1 of the silicon surface BPD1 and a basal plane dislocation density BPD2 of the carbon surface satisfies the following formula (1): D=(BPD1−BPD2)/BPD1≤25%  (1).

IPC Classes  ?

• C30B 23/02 - Epitaxial-layer growth
• C30B 29/36 - Carbides
• C30B 23/06 - Heating of the deposition chamber, the substrate, or the materials to be evaporated

Abstract

Methods for producing single crystal silicon ingots by Continuous Czochralski (CCz) are disclosed. One or more plates are added to the outer melt zone of a crucible assembly such that the plates are disposed on the initial charge of solid-state silicon. The silicon is melted and the plates float on the silicon melt. When silicon is added to the outer melt zone to replenish the melt during ingot growth, the silicon contacts the plates rather than falling directly into the melt in the outer melt zone. The silicon melts and falls through openings that extend through the thickness of the plates.

IPC Classes  ?

• C30B 15/14 - Heating of the melt or the crystallised materials
• C30B 15/10 - Crucibles or containers for supporting the melt
• C30B 29/06 - Silicon
• C30B 15/02 - Single-crystal growth by pulling from a melt, e.g. Czochralski method adding crystallising materials or reactants forming it in situ to the melt

Abstract

A method for grinding a silicon carbide wafer includes the following steps. Firstly, a single crystal is sliced into several wafers, in which each wafer has a silicon-side surface, which is the first surface. The opposite side is a carbon-side surface, which is the second surface. Subsequently, the silicon-side of the wafer is faced down and placed on a grinding stage for performing a first grinding process. It should be noted that a supporting structure exist between the wafer and the grinding stage. The supporting structure can have a concave or a convex framework. After grinding the carbon-side and removing the wafer from the stage, the wafer will appear convex or concave shape on the carbon-side surface. Thereafter, the wafer is flipped upside down and the carbon-side is placed on a flat stage without any supporting structure. Finally, the silicon-side is ground as a second grinding process.

IPC Classes  ?

• H01L 21/02 - Manufacture or treatment of semiconductor devices or of parts thereof
• H01L 29/16 - Semiconductor bodies characterised by the materials of which they are formed including, apart from doping materials or other impurities, only elements of Group IV of the Periodic System in uncombined form
• C30B 29/36 - Carbides

Abstract

A method for preparing semiconductor on insulator structures comprises transferring a thin layer of silicon from a donor substrate onto a handle substrate.

IPC Classes  ?

• H01L 21/762 - Dielectric regions

Abstract

Methods for etching a semiconductor structure and for conditioning a processing reactor in which a single semiconductor structure is treated are disclosed. An engineered polycrystalline silicon surface layer is deposited on a susceptor which supports the semiconductor structure. The polycrystalline silicon surface layer may be engineered by controlling the temperature at which the layer is deposited, by grooving the polycrystalline silicon surface layer or by controlling the thickness of the polycrystalline silicon surface layer.

IPC Classes  ?

• H01L 21/687 - Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components for supporting or gripping using mechanical means, e.g. chucks, clamps or pinches
• H01L 21/311 - Etching the insulating layers
• H01J 37/32 - Gas-filled discharge tubes
• C23C 16/24 - Deposition of silicon only

Abstract

Methods for etching a semiconductor structure and for conditioning a processing reactor in which a single semiconductor structure is treated are disclosed. An engineered polycrystalline silicon surface layer is deposited on a susceptor which supports the semiconductor structure. The polycrystalline silicon surface layer may be engineered by controlling the temperature at which the layer is deposited, by grooving the polycrystalline silicon surface layer or by controlling the thickness of the polycrystalline silicon surface layer.

IPC Classes  ?

• C23C 16/44 - Chemical coating by decomposition of gaseous compounds, without leaving reaction products of surface material in the coating, i.e. chemical vapour deposition (CVD) processes characterised by the method of coating
• B08B 3/08 - Cleaning involving contact with liquid the liquid having chemical or dissolving effect
• C23C 16/24 - Deposition of silicon only
• C23C 16/458 - Chemical coating by decomposition of gaseous compounds, without leaving reaction products of surface material in the coating, i.e. chemical vapour deposition (CVD) processes characterised by the method of coating characterised by the method used for supporting substrates in the reaction chamber
• C30B 25/12 - Substrate holders or susceptors
• H01L 21/02 - Manufacture or treatment of semiconductor devices or of parts thereof
• H01L 21/20 - Deposition of semiconductor materials on a substrate, e.g. epitaxial growth
• H01L 21/311 - Etching the insulating layers
• H01L 21/687 - Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components for supporting or gripping using mechanical means, e.g. chucks, clamps or pinches

Abstract

Methods for preparing epitaxial wafers are disclosed. The methods may involve control of the (i) a growth velocity, v, and/or (ii) an axial temperature gradient, G, during the growth of an ingot segment such that v/G is less than a critical v/G. An epitaxial layer is deposited on a substrate sliced from the silicon ingot.

IPC Classes  ?

• H01L 21/02 - Manufacture or treatment of semiconductor devices or of parts thereof
• H01L 21/203 - Deposition of semiconductor materials on a substrate, e.g. epitaxial growth using physical deposition, e.g. vacuum deposition, sputtering
• H01L 21/205 - Deposition of semiconductor materials on a substrate, e.g. epitaxial growth using reduction or decomposition of a gaseous compound yielding a solid condensate, i.e. chemical deposition
• C30B 25/20 - Epitaxial-layer growth characterised by the substrate the substrate being of the same materials as the epitaxial layer

Abstract

A material analysis method is provided. A plurality of wafers processed from a plurality of ingots are measured by a measuring instrument to obtain an average of a bow of each of the wafers processed from the ingots and a plurality of full widths at half maximum (FWHM) of each of the wafers. Key factors respectively corresponding to the ingots are calculated according to the FWHM of the wafers. A regression equation is obtained according to the key factors and the average of the bows.

IPC Classes  ?

• G01N 23/00 - Investigating or analysing materials by the use of wave or particle radiation, e.g. X-rays or neutrons, not covered by groups , or
• G01B 15/04 - Measuring arrangements characterised by the use of electromagnetic waves or particle radiation, e.g. by the use of microwaves, X-rays, gamma rays or electrons for measuring contours or curvatures
• G01N 23/20 - Investigating or analysing materials by the use of wave or particle radiation, e.g. X-rays or neutrons, not covered by groups , or by using reflection of the radiation by the materials