Providing for a non-volatile semiconductor memory architecture that achieves high read performance is described herein. In one aspect, an array of memory transistors arranged electrically in serial is configured to control a gate voltage of a pass transistor. The pass transistor, in turn, enables current flow between two metal bitlines of the semiconductor memory architecture. Accordingly, a relative voltage or relative current of the two metal bitlines can be measured and utilized to determine a program or erase state of a transistor of the serial array of transistors. In a particular aspect, a transistor with small capacitance is chosen for the pass transistor, resulting in a fast correspondence of the pass transistor gate voltage/current relative to transistor array current. This can equate to fast read times for the transistor array, based on differential sensing of the two metal bitlines.
Semiconductor devices and methods of producing the devices are disclosed. The devices are formed by forming a gate structure on a substrate. The gate structure includes a charge trapping dielectric formed between the substrate and a first poly layer. A top dielectric is formed over the poly layer and a sidewall dielectric is formed on a side of the poly layer. A second poly layer is formed over the gate structure such that a portion of the second poly layer includes a vertical portion that is in contact with the sidewall dielectric and a top portion that is in contact with the top dielectric. The top portion of the second poly layer can then be removed through, for instance, planarization.
A three-dimensional charge trap semiconductor device is constructed with alternating insulating and gate layers stacked over a substrate. During the manufacturing process, a channel hole is formed in the stack and the gate layers are recessed from the channel hole. Using the recessed topography of the gate layers, a charge trap layer can be deposited on the sidewalls of the channel hole and etched, leaving individual discrete charge trap layer sections in each recess. Filling the channel hole with channel material effectively provides a three-dimensional semiconductor device having individual charge trap layer sections for each memory cell.
[Problem] To provide a semiconductor storage device and a method of erasing the semiconductor storage device whereby it is possible to prevent the application of a high current when returning to a standby state after an erasing operation. [Solution] When erasing a P-type memory transistor including an N-type well, P-type first and second impurity regions formed within the well, a charge-storing layer formed upon the well between the first impurity region and the second impurity region, and a gate electrode formed upon the charge-storing layer, a negative voltage is applied to the gate electrode, a positive voltage is applied to the first impurity region and the well, and after the charge accumulated in the charge-storing layer is depleted, the first impurity region is set to a floating state, and the voltage applied to the well is reduced.
G11C 11/34 - Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices
5.
PROGRAMMABLE LATENCY COUNT TO ACHIEVE HIGHER MEMORY BANDWIDTH
Disclosed herein are system, method and/or computer program product embodiments for increasing memory bandwidth when accessing a plurality of memory devices. An embodiment operates by executing, by at least one processor, a first read operation to read data from a first memory device following an access time for the first memory device. The embodiment further includes executing, by the at least one processor, a second read operation to read data from a second memory device following an access time for the second memory device. The access time for the second memory device is substantially the same or longer than the access time for the first memory device plus a time it takes to read data from the first memory device.
A charge-trapping NOR (CT-NOR) memory device and methods of fabricating a CT- NOR memory device utilizing silicon-rich nitride (SiRN) in a charge-trapping (CT) layer of the CT-NOR memory device.
H01L 29/792 - Field-effect transistors with field effect produced by an insulated gate with charge trapping gate insulator, e.g. MNOS-memory transistor
A semiconductor may include several vias located in an active region and a die seal region. In the active region, a photoresist can be patterned with openings corresponding to the vias. In the die seal area, however, the photoresist can be patterned to overlap the vias. With this configuration, an underlayer etch will not affect an underlayer resist in the die seal area, allowing the die seal area to be disregarded for purposes of calculating a process window.
A method of restoring an ECC syndrome in a non-volatile memory device having memory cells arranged in a plurality of sectors within a memory cell array, the method includess identifying a first sector having a page with a disabled ECC (error correction code) flag; reading the value of all data bits in the page; calculating values for ECC bits in the page; and writing the data bit values and the calculated ECC bit values to a second sector in the memory cell array.
Embodiments described herein generally relate to verifying that a FLASH memory has been erased. In an embodiment, a method of erase verifying a memory column of a FLASH memory includes applying a pass gate voltage to even numbered memory transistors while applying an erase verify voltage to the odd numbered memory transistors. Applying a string current to the memory column allows a probe to determine if the string current is successfully traversing the memory column, and thus verifying that the odd numbered memory transistors were erased. The even numbered memory transistors are verified in the following cycle.
Embodiments include a method, apparatus, and computer program product for authentication for speech recognition. The method can include sensing an authentication device with a target device. One or more decoded voice commands can be processed after verification of the authentication device by the target device. Further, one or more decoded voice commands can be executed by the target device.
Embodiments include a method, apparatus, and a computer program product for combining results from multiple decoders. For example, the method can include generating a network of paths based on one or more outputs associated with each of the multiple decoders. The network of paths can be scored to find an initial path with the highest path score based on scores associated with the one or more outputs, A weighting factor can be calculated for each of the multiple decoders based on a number of outputs from each of the multiple decoders included in the initial path with the highest path score. Further, the network of paths can be re-scored to find a new path with, the highest path score based on the scores associated with the one or more outputs and the weighting factor for each of the multiple decoders.
G10L 19/00 - Speech or audio signal analysis-synthesis techniques for redundancy reduction, e.g. in vocoders; Coding or decoding of speech or audio signals, using source filter models or psychoacoustic analysis
12.
MODIFIED LOCAL SEGMENTED SELF-BOOSTING OF MEMORY CELL CHANNELS
A method of programming a memory system by selectively applying a program voltage to a selected wordline connected to a memory transistor to be programmed. A first bias voltage is applied to a first wordline adjacent to the source side of the selected wordline. The first bias voltage is also applied to a second wordline adjacent to the drain side of the selected wordline. A second bias voltage is applied to a third wordline adjacent to the drain side of the second wordline. A third bias voltage is applied to a fourth wordline adjacent to the source side of the first wordline. A pass voltage is also applied to the remaining wordlines that do not have one of a bias voltage and a program voltage applied, the pass voltage a selected voltage level.
A system including a memory cell array including a plurality of memory cells, and a writing device to generate multiple back-to-back write pulses to write to target memory cells from among the plurality of memory cells, the multiple back-to-back write pulses overlapping during an overlap duration, the overlap duration being adjustable based on a performance parameter of the memory cell array.
A memory module includes an input/output (I/O) interface adapted to fit into a system random access memory (RAM) socket. The module also includes at least one controller coupled to the I/O interface, the controller comprising a plurality of registers, and a plurality of non-volatile memory devices coupled to the controller. In the module, when data is received at the I/O interface, the received data is stored using at least one of the plurality of registers and the controller performs one of a plurality of non-volatile memory operations on at least a portion of the plurality of non-volatile memory devices based on the received data.
A non-volatile memory device comprising a memory cell array including a plurality of non-volatile memory cells arranged in rows and columns, wherein memory cells arranged in a same row share a word line and memory cells arranged in a same column share a bit line; and at least an address decoder to provide a negative voltage to at least one non-accessed word line in said array when a programming or erasure voltage is provided along a shared bit line.
A source-sensing configuration for non-volatile memory devices to simultaneously read 2 bits in two different memory cells sharing a same word line is disclosed. In a first cell arrangement, a drain of a first read cell is biased and its source and that of two adjacent cells in a direction towards the second read cell are connected through source bit lines to a source sense amplifier. In a second cell arrangement, the drain of the second read cell is biased and its source and that of its two adjacent cells in a direction towards the first read cell are connected through source bit lines to a source sense amplifier. A memory cell acts as a cell pipe and joins together the first and second cell arrangements. Driving all six source bit lines simultaneously allows the 2 bits to be simultaneously read while maintaining currents due to pipe effect substantially minimized.
A non-volatile memory device includes a memory cell array having memory cells distributed among a plurality of sectors and a controller operable to program, read, and erase memory cells in said memory array, the controller further operable to generate and store EPLI values for programming a number of EPLI bits in one of the plurality of sectors with the stored EPLI values. The memory device additionally include a comparator to compare the stored EPLI values with EPLI values programmed in the EPLI bits.
An approach to use silicided bit line contacts that do not short to the underlying substrate in memory devices. The approach provides for silicide formation in the bit line contact area, using a process that benefits from being self-aligned to the oxide-nitride-oxide (ONO) nitride edges, A further benefit of the approach is that the bit line contact implant and rapid temperature anneal process can be eliminated. This approach is applicable to embedded flash, integrating high density devices and advanced logic processes.
Embodiments described herein generally relate to methods of manufacturing n-type lightly doped drains and p-type lightly doped drains. In one method, a photoresist mask is used to etch a transistor, and the mask is left in place (i.e., reused) to protect other devices and poly while a high energy implantation is performed in alignment with the photoresist mask, such that the implantation is adjacent to the etched transistor. One example of a high energy implantation is forming lightly doped source and drain regions. This technique of reusing a photoresist mask can be employed for creating lightly doped source and drain regions of one conductivity followed by using the technique a second time to create lightly doped source and drain regions of the complementary conductivity type. This may prevent use of at least one hard mask during manufacturing.
Systems, methods, and computer program products for programmable reference cell selection for flash memory are disclosed. An exemplary system includes an array of interconnected cells and a flexible decoder. The array is configured to receive a selection signal as input, select a cell based upon the selection signal, and provide an output based on the selected cell. The flexible decoder is configured to receive an input, generate a selection signal based on the input and one or more characteristics of the array of interconnected cells, and provide the selection signal to the array of interconnected cells.
Embodiments of the present invention include an apparatus, method, and system for speech recognition of a voice command. The method can include receiving data representing a voice command, generating a list of targets based on the state information of each target within the system, and selecting a target from the list of targets, based on the voice command.
A multi-chip package is disclosed that has a construction capable of preventing and/or reducing electrical shorts caused by shifts in bond wires. The multi-chip package includes a die attach formed between connection points of a bond wire. The die attach is made of a non- conductive material and can be constructed so as to support or encompass a portion of the bond wire. By contacting the bond wire, the die attach restricts the motion of the bond wire by acting as a physical barrier to the bond wire's movement and/or as a source of friction. In this manner, undesired position shifts of the bond wires can be prevented, reducing device failures and allowing for improved manufacturing allowances.
Methods and apparatus for manufacturing semiconductor devices, and such semiconductor devices, are described. According to various aspects of the disclosure, a semiconductor device can be manufactured by forming a core region of the semiconductor device and forming a periphery region of the semiconductor device. A first polysilicon region can then be formed over the core and periphery regions of the semiconductor device. A first mask is formed on the first poly silicon layer and a second polysilicon layer is disposed such that the second polysilicon layer covers the first mask. A second mask can then be formed on the second polysilicon layer. After forming the second mask, portions of the first and second polysilicon layers that are uncovered by either the first or second masks are removed.
A memory is disclosed that can operate in a normal mode of operation or a testing mode of operation. In the testing mode of operation, the memory can measure various benchmarks of performance, such as read speed. The memory can perform an asynchronous read operation to read a word of electronic data that corresponds to an address or a page read operation in which multiple asynchronous read operations are performed to read multiple words of electronic data, also referred to as a page of electronic data, that correspond to multiple addresses. The memory can measure a time required, referred to as read speed, to read the word of electronic data or the multiple words of electronic data from the memory. In the normal mode of operation, the memory can perform the asynchronous read operation, the page read operation, an asynchronous write operation in which a word of electronic data is stored into the memory that correspond to the address, or a page write operation in which a page electronic data is stored into the memory that correspond to the multiple addresses.
Embodiments of the present invention include an acoustic processing device, a method for acoustic signal processing, and a speech recognition system. The speech processing device can include a processing unit, a histogram pruning unit, and a pre-pruning unit. The processing unit is configured to calculate one or more Hidden Markov Model (HMM) pruning thresholds. The histogram pruning unit is configured to prune one or more HMM states to generate one or more active HMM states. The pruning is based on the one or more pruning thresholds. The pre-pruning unit is configured to prune the one or more active HMM states based on an adjustable pre-pruning threshold. Further, the adjustable pre-pruning threshold is based on the one or more pruning thresholds.
Embodiments of the present invention include a data storage device and a method for storing data in a hash table. The data storage device can include a first memory device, a second memory device, and a processing device. The first memory device is configured to store one or more data elements. The second memory device is configured to store one or more status bits at one or more respective table indices. In addition, each of the table indices is mapped to a corresponding table index in the first memory device. The processing device is configured to calculate one or more hash values based on the one or more data elements.
Embodiments of the present invention include an acoustic processing device and a method for traversing a Hidden Markov Model (HMM). The acoustic processing device can include a senone scoring unit (SSU), a memory device, a HMM module, and an interface module. The SSU is configured to receive feature vectors from an external computing device and to calculate senones. The memory device is configured to store the senone scores and HMM information, where the HMM information includes HMM IDs and HMM state scores. The HMM module is configured to traverse the HMM based on the senone scores and the HMM information. Further, the interface module is configured to transfer one or more HMM scoring requests from the external computing device to the HMM module and to transfer the HMM state scores to the external computing device.
Embodiments of the present invention include an apparatus, method, and system for integrating data processing logic with memory. An embodiment of a memory integrated circuit is designed to execute a task on the data in a memory array within a memory integrated circuit. The memory integrated circuit can include a memory array, a data access component, a data holding component, and a logic component. The data access component can be coupled to the memory array and configured to provide an address to the memory array. The data holding component can be coupled to the memory array and configured to temporarily store the data in the memory array located at the address. The logic component can be coupled to both the data access component and the data holding component, and be configured to execute a task using data received from the data holding component. The logic component can include combinational or sequential logic.
Embodiments of the present invention include a substrate package, a method for multi-chip packaging, and a multi-chip package. For example, the substrate package includes a first set of reference markers and a second set of reference markers. The first set of reference markers is disposed on the substrate package, where the first set of reference markers is configured to provide a first alignment for positioning a first integrated circuit (IC) and a second alignment for positioning a second IC on the substrate package. Further, the second set of reference markers is disposed at a different location on the substrate package than the first set of reference markers, where the second set of reference markers is configured to provide confirmation of the first alignment and the second alignment.
Semiconductor devices and the manufacture of such semiconductor devices are described. According to various aspects of the disclosure, a semiconductor device can include a memory region, a first logic region, and a second logic region. A select gate can be formed in the memory region of the device and a first logic gate formed in the logic region. A charge trapping dielectric can then be disposed and removed from a second logic region. A gate conductor layer can then be disposed on the device and etched to define a memory gate on the sidewall of the select gate and a second logic gate in the second logic region.
Semiconductor devices and methods of manufacturing such devices are described herein. According to embodiments, a semiconductor device includes a memory gate disposed in a first region of the semiconductor device. The memory gate may include a first gate conductor layer disposed over a charge trapping dielectric. A select gate may be disposed in the first region of the semiconductor device adjacent to a side wall of the memory gate. A side wall dielectric may be disposed between the sidewall of the memory gate and the select gate. Additionally, the device may include a logic gate disposed in a second region of the semiconductor device that comprises the first gate conductor layer.
Embodiments described herein generally relate to methods of manufacturing charge- trapping memory by patterning the high voltage gates before other gates are formed. One advantage of such an approach is that a thin poly layer may be used to form memory and low voltage gates while protecting high voltage gates from implant penetration. One approach to accomplishing this is to dispose the layer of poly, and then dispose a mask and a thick resist to pattern the high voltage gates. In this manner, the high voltage gates are formed before either the low voltage gates or the memory cells.
Embodiments described herein generally relate to charge-trapping memory with improved isolation between a select gate and a memory gate. The isolation is improved because the charge trapping layer is not present in the junction between the select gate and the memory gate. The methods described herein additionally allow insulation to be disposed between the select gate and the memory gate.
Embodiments described herein generally relate to landing gate pads for contacts and manufacturing methods therefor. A bridge is formed between two features to allow a contact to be disposed, at least partially, on the bridge. Landing the contact on the bridge avoids additional manufacturing steps to create a target for a contact.
A semiconductor device and method of making such device is presented herein. The method includes disposing a gate layer over a dielectric layer on a substrate and further disposing a cap layer over the gate layer. A first transistor gate is defined having an initial thickness substantially equal to a combined thickness of the cap layer and the gate layer. A first doped region is formed in the substrate adjacent to the first transistor gate. The cap layer is subsequently removed and a second transistor gate is defined having a thickness substantially equal to the thickness of the gate layer. Afterwards, a second doped region is formed in the substrate adjacent to the second transistor gate. The first doped region extends deeper in the substrate than the second doped region, and a final thickness of the first transistor gate is substantially equal to the thickness of the second transistor gate.
Embodiments provide a split gate device, methods for fabricating a split gate device, and integrated methods for fabricating a split gate device and a periphery device. In an embodiment, the split gate device is a charge trapping split gate device, which includes a charge trapping layer. In another embodiment, the split gate device is a non-volatile memory cell, which can be formed according to embodiments as standalone or embedded with a periphery device.
Semiconductor devices and methods of manufacturing such devices are described herein. According to embodiments, the semiconductor device can be made by forming an dielectric layer at a first region and at a second region of a semiconductor substrate. A gate conductor layer is disposed over the dielectric formed in the first and the second regions of the semiconductor substrate, and the second region is masked. A split gate memory cell is formed in the first region of the semiconductor substrate with a first gate length. The first region is then masked, and the second region is etched to define a logic gate that has a second gate length. The first and second gate lengths can be different.
Integrated capacitor structures and methods for fabricating same are provided. In an embodiment, the integrated capacitor structures exploit the capacitance that can be formed in a plane that is perpendicular to that of the substrate, resulting in three-dimensional capacitor structures. This allows for integrated capacitor structures with higher capacitance to be formed over relatively small substrate areas. Embodiments are suitable for use by charge pumps and can be fabricated to have more or less capacitance as desired by the application.
A semiconductor device and method of making such device is presented herein. The semiconductor device includes a plurality of memory cells, a plurality of p-n junctions, and a metal trace of a first metal layer. Each of the plurality of memory cells includes a first gate disposed over a first dielectric, a second gate disposed over a second dielectric and adjacent to a sidewall of the first gate, a first doped region in the substrate adjacent to the first gate, and a second doped region in the substrate adjacent to the second gate. The plurality of p-n junctions are electrically isolated from the doped regions of each memory cell. The metal trace extends along a single plane between a via to the second gate of at least one memory cell in the plurality of memory cells, and a via to a p-n junction within the plurality of p-n junctions.
A semiconducting device utilizing air-gaps for inter-layer insulation and methods of producing the device are described. The device may be produced by forming a sacrificial layer between two structures. A porous membrane layer is then formed over the sacrificial layer. The membrane layer is porous to an etch product, which allows for the subsequent etching of the sacrificial layer leaving an air gap between the device structures and the membrane intact. The device may also include a cap layer formed above the device structures and the membrane.
H01L 21/31 - Treatment of semiconductor bodies using processes or apparatus not provided for in groups to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After-treatment of these layers; Selection of materials for these layers
41.
FORMING A SUBSTANTIALLY UNIFORM WING HEIGHT AMONG ELEMENTS IN A CHARGE TRAP SEMICONDUCTOR DEVICE
During formation of a charge trap separation in a semiconductor device, an organic material is formed over a plurality of cells. This organic material is selectively removed in order to create a flat upper surface. An etching process is performed to remove the organic material as well as a charge trap layer formed over the plurality of cells, thereby exposing underlying first oxide layers in each of the cells and forming charge trap separation. Further, because of the selective removal step, the etch results in substantially uniform wing heights among the separated cells.
During formation of a charge trap separation in a semiconductor device, a polymer deposition is formed in a reactor using a first chemistry. In a following step, a second chemistry can be used to etch the polymer deposition in the reactor. The same or similar second chemistry can be used in a second etching step to expose a first oxide layer in each of the cells of the semiconductor device and to form a flat upper surface. This additional etch step can also be performed by the reactor, thereby reducing the number of machines required in the formation process.
A method and apparatus to evenly distribute gas over a wafer in batch processing. Several techniques are disclosed, such as, but not limited to, angling an injector to distribute gas towards a proximate edge of the wafer, and/or reducing the amount of overlap in the center of the wafer of gas from subsequent gas injections.
H01L 21/205 - Deposition of semiconductor materials on a substrate, e.g. epitaxial growth using reduction or decomposition of a gaseous compound yielding a solid condensate, i.e. chemical deposition
H01L 21/02 - Manufacture or treatment of semiconductor devices or of parts thereof
A. method of reducing read errors in a non-volatile memory device that result from bit- line or word-line disturb conditions generated by erase operations includes selecting a subset of a memory array for refresh after each erase operation. A pointer to the refresh target section is updated as part of the method to direct the refresh operation to the appropriate subset of the memory array. Refresh may be performed subsequent to an erase operation or concurrently therewith. By distributing the time consumed by refresh operations over many erase operations so the relative refresh time for any one erase becomes small.
A semiconductor processing method to provide a high quality bottom oxide layer and top oxide layer in a charged-trapping NAND and NOR flash memory. Both the bottom oxide layer and the top oxide layer of NAND and NOR flash memory determines array device performance and reliability. The method describes overcomes the corner thinning issue and the poor top oxide quality that results from the traditional oxidation approach of using pre-deposited silicon-rich nitride.
A method of processing a wafer in a production tool includes receiving a wafer at a process tool, the wafer associated with a wafer process history, acquiring data associate with wafers processed by the process tool and having the wafer process history, when the amount of acquired data is insufficient, acquiring additional data associated with wafers processed by the process tool and having a process history differing from the wafer process history by a single factor, when the amount of acquired data is sufficient, determining a process parameter using the acquired data, and processing the wafer with the production tool using the process parameter.
Systems and methods are provided to implement a memory device that includes a memory array having a plurality of sectors, a non-volatile memory that stores sector state information, and a memory controller that performs wear leveling according to the sector state information. The sector state information can specify respective states for respective sectors of the plurality of sectors of the memory array. The memory controller, based on the states of respective sectors, determines whether or not to swap contents of the sectors during wear leveling, thereby reducing write amplification effects.
Computer-based speech recognition can be improved by recognizing words with an accurate accent model. In order to provide a large number of possible accents, while providing real-time speech recognition, a language tree data structure of possible accents is provided in one embodiment such that a computerized speech recognition system can benefit from choosing among accent categories when searching for an appropriate accent model for speech recognition.
Embodiments of the present invention include an apparatus, method, and system for calculating senone scores for multiple concurrent input speech streams. The method can include the following: receiving one or more feature vectors from one or more input streams; accessing the acoustic model one senone at a time; and calculating separate senone scores corresponding to each incoming feature vector. The calculation uses a single read access to the acoustic model for a single senone and calculates a set of separate senone scores for the one or more feature vectors, before proceeding to the next senone in the acoustic model.
Charge-trapping field effect transistors may be formed into an array on a wafer suitable to be a NAND memory device. A thick oxide layer is applied over the gates to ensure that the gap between the gates is filled. The filled gap substantially prevents nitride from being trapped, which could otherwise decrease the yield of the devices. This technique, and its variations, are useful for a range of semiconductor devices.
Devices and methods that allow dynamic management of throughput in a memory device based on a power supply voltage are provided. According to various embodiments, the power supply level can be monitored. Based on the result of the monitoring, an appropriate throughput can be determined. Once the appropriate throughput is determined, an appropriate control signal based on the determined throughput can be generated. The control signal can be configured to cause a bitline driver circuit in a memory array to activate a number of bitlines consistent with the determined throughput.
Systems and methods are provided to minimize write disturb conditions in an untargeted memory cell of a non-volatile memory array. Bitline driver circuits are provided to control a ramped voltage applied both to a bitline of a target memory cell and a neighboring bitline of an untargeted memory cell, Various embodiments advantageously maintain the integrity of data stored in the untargeted memory cells by applying a controlled voltage signal to a previously floating bitline of a neighbor cell to reduce a potential difference between the source and drain nodes of the untargeted. neighbor memory cell during a write operation at a target memory cell. In another embodiment, an increased source bias voltage is applied on a "source" bitline of the target cell during the ramping of the drain bias voltage and then reduced to a ground or near ground potential during the write operation.
Embodiments are directed to reduced power consumption for memory data transfer at high frequency through synchronized clock signaling. Delay locked loop (DLL) circuits are used to generate the synchronized clock signals. A DLL circuit consumes power as long as it is outputting the synchronized clock signals. A power saving apparatus and method are described wherein the DLL circuit is powered on when memory data access is active, while the DLL circuit is powered down when memory access is idle.
Methods and systems of fabricating a wordline protection structure are described. As described, the wordline protection structure includes a polysilicon structure formed adjacent to a memory core region. The polysilicon structure includes first doped region positioned on a core side of the polysilicon structure and a second doped region positioned on a spine side of the polysilicon structure. An un-doped region positioned between the first and second doped regions. A conductive layer is formed on top of the polysilicon structure and arranged so that it does not contact the un-doped region at either the transition between the first doped region and the un-doped region or the second doped region and un-doped region.
H01L 27/04 - Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body
A method and apparatus for continuously rounded charge trapping layer formation in a flash memory device. The memory device includes a semiconductor layer, including a source/drain region. An isolation region is disposed adjacent to the source/drain region. A first insulator is disposed above the source/drain region. A charge trapping layer is disposed within the first insulator, wherein the charge trapping layer comprises a bulk portion and a first tip and a second tip on either side of said bulk portion, wherein said charge trapping layer extends beyond the width of the source/drain region. A second insulator is disposed above the charge trapping layer. A polysilicon gate structure is disposed above the second insulator, wherein a width of said control gate is wider than the width of said source/drain region.
A voice activation system is provided. The voice activation system includes a first stage configured to output a first activation signal if at least one energy characteristic of a received audio signal satisfies at least one threshold and a second stage configured to transition from a first state to a second state in response to the first activation signal and, when in the second state, to output a second activation signal if at least a portion of a profile of the audio signal substantially matches at least one predetermined profile.
A method, apparatus, and manufacture for a memory device is provided. The memory device includes a memory cell region including sectors, where each sector includes memory cells. The memory device further includes a memory controller that is configured to control program operations and erase operations to the memory cells. During erase operations to the memory cells, pre-programming occurs in which each un-programmed memory cell in the sector being erased is programmed by applying at least one programming pulse at a program voltage until a program verify passes. Then, the program voltage is adjusted based on the number of programming pulses applied until the program-verify passed. During subsequent program operations in that sector, programming pulses are applied with the adjusted program voltage.
An assembly includes an integrated circuit, a film layer disposed over the integrated circuit and having a thickness of at least 50 microns, and a thermal neutron absorber layer comprising at least 0,5% thermal neutron absorber, The thermal neutron absorber layer can be a glass layer or can include a molding compound.
Embodiments described herein generally relate to programming and erasing a FLASH memory. In an embodiment, a method of programming or erasing the contents of a block of a FLASH memory includes determining a voltage of a pulse based on an age of the block and outputting the pulse to at least a portion of the block. The pulse is used to program or erase the block.
A system comprising a processor and a memory, wherein said memory comprises instructions that when executed by said processor implement a method. The method includes loading a first portion of a set of redundancy data into a register of the processor for each redundant sector of a plurality of redundant sectors. A second portion of a set of redundancy data is also loaded into the volatile memory for each redundant sector of the plurality of redundant sectors. Loading the second portions of the sets of redundancy data comprises loading a third portion of redundancy data comprising a plurality of second portions of redundancy data for the plurality of redundant sectors.
Embodiments of the present invention include an apparatus, method, and system for acoustic modeling. The apparatus can include a senone scoring unit (SSU) control module, a distance calculator, and an addition module. The SSU control module can be configured to receive a feature vector. The distance calculator can be configured to receive a plurality of Gaussian probability distributions via a data bus having a width of at least one Gaussian probability distribution and the feature vector from the SSU control module. The distance calculator can include a plurality of arithmetic logic units to calculate a plurality of dimension distance scores and an accumulator to sum the dimension distance scores to generate a Gaussian distance score. Further, the addition module is configured to sum a plurality of Gaussian distance scores to generate a senone score.
Embodiments of the present invention include an apparatus, method, and system for acoustic modeling. In an embodiment, a speech recognition system is provided. The system includes a processing unit configured to divide a received audio signal into consecutive frames having respective frame vectors, an acoustic processing unit (APU), a data bus that couples the processing unit and the APU. The APU includes a local, non-volatile memory that stores a plurality of senones, a memory buffer coupled to the memory, the acoustic processing unit being configured to load at least one Gaussian probability distribution vector stored in the memory into the memory buffer, and a scoring unit configured to simultaneously compare a plurality of dimensions of a Gaussian probability distribution vector loaded into the memory buffer with respective dimensions of a frame vector received from the processing unit and to output a corresponding score to the processing unit. The APU is configured to perform a comparison using a first frame while the processing unit performs a search operation using a score corresponding to a second frame, the second frame immediately preceding the first frame.
Embodiments of the present invention include an apparatus, method, and system for acoustic modeling. In an embodiment, an arithmetic logic unit for computing a one-dimensional score between a feature vector and a Gaussian probability distribution vector is provided. The arithmetic logic unit includes a computational logic unit configured to compute a first value based on a mean value and a variance value associated with a dimension of the Gaussian probability distribution vector and a dimension of a feature vector, a look up table module configured to output a second value based on the variance value, and a combination module configured to combine the first value and the second value to generate the one-dimensional score.
G06F 7/57 - Arithmetic logic units [ALU], i.e. arrangements or devices for performing two or more of the operations covered by groups or for performing logical operations
A memory subsystem is disclosed. The memory subsystem includes a serial peripheral interface (SPI) double data rate (DDR) volatile memory component (203), a serial peripheral interface (SPI) double data rate (DDR) non-volatile memory component (201 ) coupled to the serial peripheral interface (SPI) double data rate (DDR) volatile memory component and a serial peripheral interface (SPI) double data rate (DDR) interface (205a-c). The serial peripheral interface (SPI) double data rate (DDR) interface (205a-c) accesses the serial peripheral interface (SPI) double data rate (DDR) volatile memory component (203) and the serial peripheral interface (SPI) double data rate (DDR) non-volatile memory component (201) where data is accessed on leading and falling edges of a clock signal.
A memory array includes a plurality of bit lines and a plurality of word lines, a gate region, and a charge trapping layer. The charge trapping layer is wider than a word line; the charge trapping layer is extended beyond the edge of the gate region to facilitate capturing and removing charges.
Embodiments of the present technology are directed toward gate sidcwall engineering of field effect transistors. The techniques include formation of a blocking dielectric region and nitridation of a surface thereof. After nitridation of the blocking dielectric region, a gate region is formed thereon and the sidewails of the gate region are oxidized to round off gate sharp corners and reduce the electrical field at the gate comers.
Embodiments of the present technology arc directed toward charge trapping region process margin engineering for charge trapping field effect transistor. The techniques include forming a plurality of shallow trench isolation regions on a substrate, wherein the tops of the shallow trench isolation regions extend above the substrate by a given amount. A portion of the substrate is oxidized to form a tunneling dielectric region. A first set of one or more nitride layers are deposited on the tunneling dielectric region and shallow trench isolation regions, wherein a thickness of the first set of nitride layers is approximately half of the given amount that the tops of the shallow trench isolation regions extend above the substrate. A portion of the first set of nitride layers is etched back to the tops of the trench isolation regions. A second set of one or more nitride layers is deposited on the etched back first set of nitride layers. The second set of nitride layers is oxidized to form a charge trapping region on the tunneling dielectric region and a blocking dielectric region on the charge trapping region. A gate region is then deposited on the blocking dielectric region.
A method for double patterning is disclosed. In one embodiment the formation a pair of select gate wordlines on either side of a plurality of core wordlines begins by placing a spacer pattern around edges of a photoresist pattern is disclosed. The photoresist pattern is stripped away leaving the spacer pattern. A trim mask is placed over a portion of the spacer pattern. Portions of the spacer pattern are etched away that are not covered by the trim mask. The trim mask is removed, wherein first remaining portions of the spacer pattern define a plurality of core wordlines. A pad mask is placed such that the pad mask and second remaining portions of the spacer pattern define a select gate wordline on either side of the plurality of core wordlines. Finally at least one pattern transfer layer is etched through using the mad mask and the first and second remaining portions of the spacer pattern to etch the select gate wordlines and the plurality of core wordlines into a poly silicon layer.
A method for die stacking is disclosed. In one embodiment a first die is formed overlying a substrate. A first wire is bonded to the first die and to a bond finger of the substrate, wherein the first wire is bonded to the bond finger with a first bond. A first stitch bump is formed overlying the first stitch bond, wherein the first stitch bump is formed from a molten ball of conductive material. A second die is formed overlying the first die. A second wire is bonded to the second die and to the first stitch bump, wherein the second wire is bonded to the first stitch bump with a second bond.
A system and method for a thin multi chip stack package with film on wire and copper wire. The package comprises a substrate and a first die overlying the substrate. Copper wires electrically connect the first die to the substrate. A film overlies the first die and a portion of the copper wires. In addition, the film adheres a second die to the first die. The film also electrically insulates the copper wires from the second die.
H01L 23/49 - Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads or terminal arrangements consisting of soldered or bonded constructions wire-like
H01L 23/12 - Mountings, e.g. non-detachable insulating substrates
71.
ELECTRONIC DEVICE HAVING A MOLDING COMPOUND INCLUDING A COMPOSITE MATERIAL
An electronic device includes a packaged integrated circuit (100) having an integrated circuit die (102) having an active surface (112), and a molding compound (104) overlaying the active surface (112) of the integrated circuit die. In a particular embodiment, the packaged integrated circuit (100) includes at least approximately five weight percent (5 wt %) zinc relative to the molding compound (114). In another embodiment, the packaged integrated circuit (100) includes approximately 0.3 µmol/cm2 of zinc in an area parallel to the active surface of the integrated circuit die (102).
To provide a memory system, a memory controller and a refresh operation control method of the memory controller capable of preventing a degradation of the performance of the refresh operation for one memory caused by the influence of the heat released by the other memories which differ from the one memory from amongst the plurality of memories. A memory controller (10) that is connected to a1 plurality of memories (20 and 30) including the memory (20) requiring a refresh operation in a predetermined cycle is provided with an operation cycle setting section for setting a refresh operation cycle of the memory (20) to a different cycle between before accessing to the memory (30) which differs from the memory (20) requiring the refresh operation and after accessing thereto.
Systems and methods of regulating voltage at a memory cell are disclosed. An address for the memory cell is determined. Table lookups based on the address are performed. The table lookups yield voltage compensation parameters that can be used to set voltages on the terminals (e.g., source and drain) of the memory cell.
Systems and methods for effectively protecting data against differential fault analysis involved in Rivest, Shamir, and Adleman ('RSA') cryptography using the Chinese Remainder Theorem ('CRT') are described herein. A CRT RSA component (110, 310) facilitates modular exponentiation of a received message, and a verification component (120, 330) reconstructs the received message. An exponentiation component (210) performs a first modular exponentiation and a second modular exponentiation of the received message. A recombination component (220) performs a recombination step utilizing CRT computation as a function of the first and second modular exponentiations. A modular exponentiation component (320) performs first and second public exponent derivations as a function of a private exponent. The verification component (120, 330) reconstructs the received message as a function of the first and second public exponent derivations. The verification component (120, 330) calculates the received message utilizing Chinese Remainder Theorem computation.
A method for adjusting the voltage threshold values of select gates (311, 312) of NAND strings (2300) is disclosed. The select gates (311, 312) of the NAND string (2300) can be read, erased, and programmed.
An electronic device can include a silicon nitride layer. In an embodiment, the silicon nitride layer can include boron, grains, or both. The silicon nitride layer may be used as part of a charge storage layer within a nonvolatile memory cell within the electronic device. In a particular embodiment, the boron within the silicon nitride layer may be no greater than approximately 9 atomic % of the layer. The boron can be incorporated into the silicon nitride layer as it is being formed. The layer can be formed using chemical vapor deposition, physical vapor deposition, another suitable formation process, or any combination thereof.
A system and methodology that can minimize disturbance during an AC operation associated with a memory (102), such as, program, read and/or erase, is provided. The system pre-charges all or a desired subset of the bit lines in a memory array (104) to a specified voltage, during an AC operation to facilitate reducing AC disturbances between neighboring cells (402, 404). A pre-charge voltage can be applied to all bit lines in a block in the memory array (104), or to bit lines associated with a selected memory cell (402) and neighbor memory cells (404) adjacent to the selected memory cell (402) in the block. The system ensures that source and drain voltage levels can be set to desired levels at the same or substantially the same time, while selecting a memory cell (402). This can facilitate minimizing AC disturbances in the selected memory cell (402) during the AC operation.
Providing for extended data retention of flash memory devices by program state rewrite is disclosed herein. By way of example, a memory cell or group of memory cells can be evaluated to determine a program state of the cell(s). If the cell(s) is in a program state, as opposed to a natural or non-programmed state, a charge level, voltage level and/or the like can be rewritten to a default level associated with the program state, without erasing the cell(s) first. Accordingly, conventional mechanisms for refreshing cell program state that require rewriting and erasing, typically degrading storage capacity of the memory cell, can be avoided. As a result, data stored in flash memory can be refreshed in a manner that mitigates loss of memory integrity, providing substantial benefits over conventional mechanisms that can degrade memory integrity at a relatively high rate.
Neutron detectors including one or more gamma shields over memory dies and methods of making the neutron detectors are provided. The neutron detectors can contain two or more memory dies, neutron-reactant layers over the two or more memory dies, and one or more gamma shields over at least a portion of or an entire of the two or more memory dies. By containing the gamma shield over the at least a portion of or an entire of the two or more memory dies, the neutron detector can detect and discriminate neutrons in the presence of gamma rays.
Charge storage stacks containing hetero-structure variable silicon richness nitride for memory cells and methods for making the charge storage stacks are provided. The charge storage stack can contain a first insulating layer (212) on a semiconductor substrate; n charge storage layers (214, 216) comprising silicon-rich silicon nitride on the first insulating layer, wherein numbers of the charge storage layers increase from the bottom to the top and a k-value respectively the silicon richness of an n-1th charge storage layer is higher than a k-value respectively the silicon richness of an nth charge storage layer; n-1 dielectric layers (218) comprising substantially stoichiometric silicon nitride between each of the n charge storage layers; and a second insulating layer (220) on the nth charge storage layers. In this context, the k-value is a refrective index determined by an optical measurement.
H01L 21/28 - Manufacture of electrodes on semiconductor bodies using processes or apparatus not provided for in groups
H01L 29/792 - Field-effect transistors with field effect produced by an insulated gate with charge trapping gate insulator, e.g. MNOS-memory transistor
A nonvolatile storage device and control method are capable of supplying a ground potential to the source terminal of a memory cell while avoiding interference from a global bit line. The storage device has a first local bit line to which a first terminal of a memory cell is coupled; a second local bit line to which a second terminal of the memory cell is coupled; a first selector switch for coupling the first local bit line to a first global bit line; a second selector switch for coupling the second local bit line to a second global bit line; a third selector switch for coupling the first local bit line to a grounding line; and a fourth selector switch for coupling the second local bit line to the grounding line. The first and fourth selector switches or the second and third selector switches become conductive when reading a bit.
Systems and methods for extending the usable lifetime.of memory cells' by utilizing reference-free sampled sensing. A stimulus component (105) applies a plurality of different stimuli to a plurality of memory cells (110) of a memory device. A sense component (115) senses a characteristic of each memory cell of the plurality of memory cells (110) as a function of the applied plurality of different stimuli. An analysis component (120) determines a logic state of each memory cell of the plurality of memory cells (110) as a function of the sensed characteristic of each memory cell of the plurality of memory cells (110).
A semiconductor device has a plurality of memory cells storing two bits of data in a cell, and a first reference cell (RCl) and a second reference cell (RC2) being shared by the plurality of memory cells. When programming the memory cell, programming a program subjected cell and refreshing a refresh subjected cell are both verified with a threshold value of the second reference cell corresponding to a programmed state of the memory cell. The second reference cell is programmed with a first threshold value (PRGV) to verify when programming, and is refreshed with a second threshold value (REFV) lower than the first threshold value to verify when refreshing.
A method of forming an electronic device is provided that includes selectively implanting ions into a workpiece, wherein ions are implanted into a first region of the workpiece that includes a semiconductor material, while substantially none of the ions are implanted into a second region of the workpiece that also includes a semiconductor material. The method further includes depositing a metal-containing film over the first region and the second region after selectively implanting, and then reacting the metal-containing film with the semiconductor material to form a first metal-semiconductor film within the first region and a second metal-semiconductor film within the second region. The first metal-semiconductor film has a first thickness and the second metal-semiconductor film has a second thickness that is different from the first thickness.
H01L 27/105 - Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body including a plurality of individual components in a repetitive configuration including field-effect components
Efficient and convenient storage systems and methods are presented. In one embodiment a storage system (100) includes a plurality of storage nodes (120, 130, 140) and a master controller (110). The storage nodes store information. The storage node (120, 130, 140) includes an upstream communication buffer (160) which is locally controlled at the storage node (120, 130, 140) to facilitate resolution of conflicts in upstream communications. The master controller (110) controls the flow of traffic to the node (120, 130, 140) based upon constraints of the upstream communication buffer. In one embodiment, communication between the master controller (110) and the node (120,130, 140) has a determined maximum latency. The storage node (120, 130, 140) can be coupled to the master controller (110) in accordance with a chain memory configuration.
A storage system and method for setting parameters and determining latency in a chained device system. Storage nodes store information (112, 114) and the storage nodes (120, 130, 140) are organized in a daisy chained network. At least one of one of the storage nodes includes an upstream communication buffer (132, 134). Flow of information to the storage nodes is based upon constraints of the communication buffer within the storage nodes. In one embodiment, communication between the master controller (110) and the plurality storage nodes (120, 130, 140) has a determined maximum latency.
A storage system and method for storing information in memory nodes. The storage or memory nodes include a communication buffer (205). Flow of information to the storage nodes is controlled based upon constraints on the communication buffer. In one embodiment, communications between a master controller (110) and a storage node (120) have a determined maximum latency.
The method for manufacturing the semiconductor device, which includes the steps of forming a charge storage layer (22) on a semiconductor substrate (10), forming an extending first groove (12) in the charge storage layer and the semiconductor substrate using a mask layer (30) formed on the charge storage layer as a mask, forming an insulating film (14) in the first groove, forming a second groove (32) extending across the first groove in the mask layer and the insulating film, forming a gate insulating film (18) formed below the second groove, forming a first conductive layer (34) in the second groove, eliminating the mask layer, forming a second conductive layer (36) on both side surfaces of the first conductive layer to form a word line (16) which includes the first and the second conductive layers, and eliminating the charge storage layer using the word line as a mask.
H01L 29/792 - Field-effect transistors with field effect produced by an insulated gate with charge trapping gate insulator, e.g. MNOS-memory transistor
H01L 29/423 - Electrodes characterised by their shape, relative sizes or dispositions not carrying the current to be rectified, amplified or switched
H01L 21/768 - Applying interconnections to be used for carrying current between separate components within a device
Methods for controlling read data buffering are disclosed. In one of the methods core operations are performed (431) in response to a receipt of a read command from a master controller and an internal or external communication buffer of a data storage node is selected (432) to forward information to the master controller. The data storage node is selected based upon constraints and contents of one or more communication buffers. Information is forwarded (433) from the selected internal or external communication buffer to the master controller.
A memory buffering system (200) is disclosed that arbitrates bus (204) ownership through an arbitration scheme (300) for memory elements (206) in chain architecture. A unified host memory controller (203) arbitrates bus (204) ownership for transfer to a unified memory buffer (236) and other buffers (238) within the chain architecture The system (200) is used within a communication system (1000) with a bus in chain (204) architectures and parallel (706) architectures.
A memory device is disclosed, and includes an array of memory cells and a partitioning system configured to address a first portion of the array in a single level cell mode, and a second portion of the array in a multi-level cell mode.
G11C 11/56 - Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using storage elements with more than two stable states represented by steps, e.g. of voltage, current, phase, frequency
G11C 8/06 - Address interface arrangements, e.g. address buffers
92.
SELECTIVE SILICIDE FORMATION USING RESIST ETCH BACK
Methods of selectively forming metal silicides on a memory device are provided. The methods can include forming a mask layer over the memory device; forming a patterned resist over the mask layer; removing upper portions of the patterned resist; forming a patterned mask layer by removing portions of the mask layer that are not covered by the patterned resist; and forming metal silicides on the memory device by a chemical reaction of a metal layer formed on the memory device with portions of the memory device that are not covered by the patterned mask layer. By preventing silicidation of underlying silicon containing layers/components of the memory device that are covered by the patterned mask layer, the methods can selectively form the metal silicides on the desired portions of the memory device.
H01L 27/105 - Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body including a plurality of individual components in a repetitive configuration including field-effect components
Systems (500, 530, 900) and methods (800) that control the switching transition times or profile of a ramped voltage write signal (535) used for programming or erasing at least a wordline (309) of an array (300, 920) of multi-bit and/or multi-level flash memory cells (200) are provided. In one embodiment, this goal is accomplished by applying a ramped or otherwise controlled profile write voltage (535) to the flash memory cells (304) in order to avoid disturb issues to the unselected (non-targeted) neighboring memory cells (305), which preserves the existing state of the neighboring cells (305) while keeping the design as compact and manageable as possible yet maintains a high write speed. The systems and method are applicable to, and reliable for various memory technologies, since the size of the steps or other such functional transitions of the ramped voltage profile (535) can be adjusted or trimmed (590) to any level of resolution required.
Systems and methods that can facilitate securing data associated with a memory (104, 1306) from tampering are presented. A counter tamper component (106) can detect tamper attacks or tamper attempts associated with a memory (104, 1306) and/or data stored therein or associated therewith and reacts to such tamper attacks/attempts, as the counter tamper component (106) can provide evidence of, provide a response to, and/or resist tamper attacks/attempts. The counter tamper component (106) can be associated with a memory module (102) that includes a memory device(s) (104) module and is contained in an electronic device (402, 1300) and the memory module (102) can change a color state to provide evidence of tampering. A window component (408) is positioned on the casing of the electronic device (402, 1300) so that the memory module (102) is visible to the user so the user can perceive that a tamper attack associated with the module (102) has occurred.
There is provided a method for manufacturing a flash memory device comprising forming a first insulating film and a conductive layer on a semiconductor substrate; forming a first mask layer on the conductive layer; forming a second mask layer in isolation regions isolated between the first mask layer,- forming first openings by removing the conductive layer and the first insulating film by using the first and second mask layer as a mask; forming a second insulating film in the first openings and the isolation regions; removing the first mask layer, the conductive layer and the first insulating film by using the second insulating film as a mask, forming gate electrodes between the second openings; removing, through the second openings, the first insulating film, forming a gate insulating film at center portions below the gate electrodes; and forming a charge storage layer in an area where the first insulating film is removed. The finished device' has bit lines (18), gate insulating film (22), tunnel insulating film (12), separated charge storage layer (14), top insulating film (12), and gate electrode (24).
H01L 29/423 - Electrodes characterised by their shape, relative sizes or dispositions not carrying the current to be rectified, amplified or switched
H01L 29/788 - Field-effect transistors with field effect produced by an insulated gate with floating gate
H01L 29/792 - Field-effect transistors with field effect produced by an insulated gate with charge trapping gate insulator, e.g. MNOS-memory transistor
96.
SEMICONDUCTOR DEVICE AND METHOD FOR MANUFACTURING THEREOF
A semiconductor device includes a bit line 18 formed to extend inside a semiconductor substrate 10, a gate electrode 24 formed above the semiconductor substrate 10 between the bit lines 18, a gate insulating film 22 formed on the semiconductor substrate 10 below a center of the gate electrode 24, charge storage layers 14 formed on the semiconductor substrate 10 below the gate electrode 24 to interpose the gate insulating film 22 in a width direction of the bit line 18, and a first insulating film formed on the semiconductor substrate 10 between the gate electrodes 24 in an extending direction of the bit line 18. A width of a first insulating film 30 in the width direction of the bit line 18 is larger than that of the gate insulating film 22.
H01L 29/788 - Field-effect transistors with field effect produced by an insulated gate with floating gate
H01L 29/792 - Field-effect transistors with field effect produced by an insulated gate with charge trapping gate insulator, e.g. MNOS-memory transistor
H01L 21/28 - Manufacture of electrodes on semiconductor bodies using processes or apparatus not provided for in groups
Systems and/or methods that facilitate secure electronic communication of data are presented. A cryptographic component (102) facilitates securing data associated with messages in accordance with a cryptographic protocol. The cryptographic component (102) includes a randomized exponentiation component (104) that facilitates decryption of data and generation of digital signatures by exponentiating exponents (202) associated with messages. An exponent (202) is divided into more than one subexponent at an exponent bit that corresponds to a random number. Exponentiation of the first subexponent (210) can be performed based on a left-to-right-type of exponentiation algorithm, and exponentiation of the second subexponent (212) can be performed based on a right-to-left square-and-multiply-type of exponentiation algorithm. The final value is based on the exponentiations of the subexponents and can be decrypted data or a digital signature, which can be provided as an output.
G06F 7/72 - Methods or arrangements for performing computations using a digital non-denominational number representation, i.e. number representation without radix; Computing devices using combinations of denominational and non-denominational quantity representations using residue arithmetic
Methods of forming a top oxide around a charge storage material layer of a memory cell and methods of improving quality of a top oxide around a charge storage material layer of a memory cell are provided. The method can involve providing a charge storage layer on a semiconductor substrate, a nitride layer on the charge storage layer, and a first poly layer on the nitride layer, and converting at least a portion of the nitride layer to a top oxide. By converting at least a portion of a nitride layer to a top oxide layer, the quality of the resultant top oxide layer can be improved.
H01L 21/28 - Manufacture of electrodes on semiconductor bodies using processes or apparatus not provided for in groups
H01L 29/792 - Field-effect transistors with field effect produced by an insulated gate with charge trapping gate insulator, e.g. MNOS-memory transistor
H01L 29/423 - Electrodes characterised by their shape, relative sizes or dispositions not carrying the current to be rectified, amplified or switched
A semiconductor device that includes a gate electrode (16) formed above a semiconductor substrate (10), a gate insulating film (12) formed on the semiconductor substrate (10) below the center of the gate electrode (16), a first insulating film (14) which is applied from an area on the gate insulating film (12) to areas below both ends of the gate electrode (16) and which is formed of a material different from that of the gate insulating film (12), a tunnel insulating film (21) formed on the semiconductor substrate (10) at both sides of the gate insulating film (12), and a charge storage layer (26) interposed between the tunnel insulating film (21) and the first insulating film (14), and a method for manufacturing the semiconductor device are provided.
H01L 21/28 - Manufacture of electrodes on semiconductor bodies using processes or apparatus not provided for in groups
H01L 29/792 - Field-effect transistors with field effect produced by an insulated gate with charge trapping gate insulator, e.g. MNOS-memory transistor
H01L 29/423 - Electrodes characterised by their shape, relative sizes or dispositions not carrying the current to be rectified, amplified or switched
A process of forming an electronic device can include depositing a first layer over a substrate and depositing a second layer over the first layerby physical vapor deposition. In one embodiment, depositing the first layer is performed at a first alternating current ('AC') power, and depositing the second layer is performed at a second AC power that is different from the first AC power. In another embodiment, the first layer is formed by a physical vapor deposition technique at a first power sufficient to remove the insulating layer using first metal ions, wherein the first layer includes an overhanging portion extending over the bottom of the opening. In a further embodiment, the second layer is formed by the physical vapor deposition technique using second metal ions and a second power sufficient to reduce a lateral dimension of the overhanging portion.
patents
