A system and corresponding method enable payment hardware system module (HSM) communications. The system comprises a multiPayHSM module that transforms an input request, sourced by an application, into a transformed request interpretable by a target payment HSM. The application is integrated, currently, with a current payment HSM that is different from the target payment HSM. The input request is uninterpretable by the target payment HSM. The multiPayHSM module transmits the transformed request to the target payment HSM for processing. The system enables the application, integrated with the different payment HSM, to
Packet metadata for incoming packets are buffered in queue selection buffers associated with a port of a network node. Packet data for outgoing packets are buffered in a port selection buffer associated with the port. At a selection clock cycle, while a port scheduler of the network node selects a subset of the packet data for a subset of the outgoing packets from the port selection buffer, a queue scheduler of the port concurrently selects a subset of the packet metadata for a subset of the incoming packets from the queue selection buffers and adds new packet data for new outgoing packets to the port selection buffer of the port. The new packet data are derived based at least in part on the subset of the packet metadata for the subset of the incoming packets.
H04L 47/625 - Queue scheduling characterised by scheduling criteria for service slots or service orders
H04L 47/628 - Queue scheduling characterised by scheduling criteria for service slots or service orders based on packet size, e.g. shortest packet first
3.
Method and apparatus for performing machine learning operations in parallel on machine learning hardware
A method includes receiving a set of data. The set of data is divided into a plurality of data portions. The method includes transmitting the plurality of data portions to a plurality of processing tiles, wherein each data portion of the plurality of data portions is associated with a processing tile of a plurality of tiles. Each processing tile of the plurality of tiles performs at least one local operation on its respective data portion to form a local result. The method includes exchanging local results between the plurality of processing tiles. Moreover, the method includes calculating a global value based on the local results. The method further includes performing at least one local operation by each processing tile of the plurality of tiles on its respective data portion based on the global value to form a computed result.
G06N 20/10 - Machine learning using kernel methods, e.g. support vector machines [SVM]
G06F 15/80 - Architectures of general purpose stored program computers comprising an array of processing units with common control, e.g. single instruction multiple data processors
A multi-chiplet module system, method and device including a memory storing chiplet operational data and a plurality of chiplets serially operably coupled to each other forming a chiplet chain. The chiplets in the middle and at one end of the chain each include a local cache with the chiplet at the one end of the chain coupling with the memory. When one of the chiplets requires data stored on the memory it checks the local cache (if it has one), and if not in the local cache, it then queries the cache of the next chiplet in the chain until the required data is propagated from the memory up the caches of the chain to the requesting chiplet.
A method of reading data read from a NAND Flash memory device includes decoding a set of data read from the device, using an initial set of hard bit thresholds, when the decoding is unsuccessful, performing a read-retry operation that retries the decoding using, in order, each of a plurality of entries in a read-retry table of hard bit thresholds, stopping when decoding based on one of the entries is successful, and when the read-retry operation is unsuccessful, performing a deep retry operation using a set of log-likelihood ratios (LLRs) that vary in at least one of values or symmetries. NAND Flash memory apparatus includes a Flash media controller, a data bus, and an adaptive LLR engine configured to generate, for use in a deep retry operation, a set of LLRs that, and to transfer the set of LLRs that vary to the media controller via the bus.
H03M 13/11 - Error detection or forward error correction by redundancy in data representation, i.e. code words containing more digits than the source words using block codes, i.e. a predetermined number of check bits joined to a predetermined number of information bits using multiple parity bits
G06N 3/04 - Architecture, e.g. interconnection topology
G06F 11/10 - Adding special bits or symbols to the coded information, e.g. parity check, casting out nines or elevens
H03M 13/29 - Coding, decoding or code conversion, for error detection or error correction; Coding theory basic assumptions; Coding bounds; Error probability evaluation methods; Channel models; Simulation or testing of codes combining two or more codes or code structures, e.g. product codes, generalised product codes, concatenated codes, inner and outer codes
H03M 13/37 - Decoding methods or techniques, not specific to the particular type of coding provided for in groups
H03M 13/39 - Sequence estimation, i.e using statistical methods for the reconstruction of the original codes
H03M 13/45 - Soft decoding, i.e. using symbol reliability information
H04L 1/00 - Arrangements for detecting or preventing errors in the information received
6.
Transmitting Traffic Streams via Multiple WLAN Communication Links
In response to a first communication device determining that a specific wireless local area network (WLAN) communication link has been negotiated with a second communication device for traffic corresponding to a first traffic identifier (TID), the first communication device transmits packets corresponding to the first TID to the second communication device only via the specific WLAN communication link. In response to the first communication device determining that no WLAN communication link has been negotiated with the second communication device for traffic corresponding to a second TID, transmitting, by the first communication device, packets corresponding to the second TID to the second communication device via multiple WLAN communication links.
H04L 1/1607 - Arrangements for detecting or preventing errors in the information received by using return channel in which the return channel carries supervisory signals, e.g. repetition request signals - Details of the supervisory signal
H04W 28/082 - Load balancing or load distribution among bearers or channels
The present disclosure describes apparatuses and methods for implementing a pipelined processor with configurable grouping of processor elements. In aspects, an apparatus comprises a host interface configured for communication with a host system, a media interface configured to enable access to storage media, and a plurality of processor elements operably coupled to at least one of the host interface and the media interface. The plurality of processor elements is organized into multiple stages of a pipelined processor for processing data access commands associated with the host system. In various implementations, the plurality of processor elements can be selectively grouped to form the multiple stages of the pipelined processor and loaded with microcode to implement respective functions of each stage of the pipelined processor. By so doing, the pipelined processor may be configured based on various parameters to improve processing performance when processing the data access commands of the host system.
Embodiments address optimization of an electrical interface between an optical host device and an optical module device at installation time. Certain methods try each entry in a set of Finite Impulse Response (FIR) filter settings at the host transmitter, while asking the module to measure the signal integrity for each. The module will then provide an indication of which entry was the best choice for signal integrity in the current hardware configuration. Note that for the module to host electrical interface, this same technique can be used in reverse, whereby the host asks the module to configure its transmitting FIR filter, and the host records and keeps track of which filter setting is the best, and then configures the module with that filter setting. In both cases, for modules supporting CMIS (Common Management Interface Specification) for module configuration and control, methods are provided.
H04B 10/079 - Arrangements for monitoring or testing transmission systems; Arrangements for fault measurement of transmission systems using an in-service signal using measurements of the data signal
Transceiver circuitry for coupling a functional circuit to a transmission medium includes a transmit path for coupling between the functional circuit and the transmission medium, a receive path for coupling between the transmission medium and the functional circuit, and clock generation circuitry coupled to at least one of the transmit path and the receive path. The clock generation circuitry includes an oscillator having transconductance circuitry, a capacitance element coupled in parallel with the transconductance circuitry, a plurality of inductors coupled in parallel with the transconductance circuitry and the capacitance element, and with each other, and a current source coupled to the plurality of inductors. The capacitance element may be variable. An even number of inductors are arranged so that half of the inductors generate magnetic flux in a first direction, and half of the inductors generate magnetic flux in a second direction opposite to the first direction.
H03B 7/06 - Generation of oscillations using active element having a negative resistance between two of its electrodes with frequency-determining element comprising lumped inductance and capacitance active element being semiconductor device
10.
Method and apparatus for sharing clocks between separate integrated circuit chips
An integrated circuit device includes a plurality of integrated circuit chips located on a common substrate, each respective integrated circuit chip from among the plurality of integrated circuit chips including functional circuitry, a clock generator, clock circuitry including clock terminals at an edge of the respective integrated circuit chip, initial clock conductors configured to conduct a clock signal output by the clock generator from the clock generator to the clock terminals, and functional clock conductors configured to conduct the clock signal from the clock terminals to the functional circuitry. Each respective chip is located on the common substrate in an orientation that exposes the clock terminals on the respective chip to face corresponding clock terminals on at least one other chip among the plurality of integrated circuit chips, configured for interconnection of the plurality of integrated circuit chips into a multi-chip module with a common clock.
H03K 3/01 - Circuits for generating electric pulses; Monostable, bistable or multistable circuits - Details
G06F 1/06 - Clock generators producing several clock signals
H01L 25/00 - Assemblies consisting of a plurality of individual semiconductor or other solid state devices
H01L 25/065 - Assemblies consisting of a plurality of individual semiconductor or other solid state devices all the devices being of a type provided for in the same subgroup of groups , or in a single subclass of , , e.g. assemblies of rectifier diodes the devices not having separate containers the devices being of a type provided for in group
11.
Lateral escape using triangular structure of transceivers
An electronic network device includes: (i) an integrated circuit (IC) die configured to exchange signals between the electronic network device and one or more other devices that are remote from the electronic network device, (ii) a plurality of transceiver dies, separate from the IC die, the plurality of transceiver dies being disposed along at least a first axis extending at an acute angle from an edge of the IC die and intersecting the edge at a first point, the transceiver dies being configured to exchange the signals between the IC die and the other devices, and (iii) electrical connections configured to connect between the IC die and at least one of the transceiver dies for exchanging at least some of the signals between the IC die and the transceiver dies.
H04K 1/10 - Secret communication by using two signals transmitted simultaneously or successively
H01L 23/538 - Arrangements for conducting electric current within the device in operation from one component to another the interconnection structure between a plurality of semiconductor chips being formed on, or in, insulating substrates
A circuit and corresponding method enable bitcoin mining in a blockchain network. The circuit comprises a nonce generator that generates a nonce value, on a cycle-by-cycle basis, and changes only one binary digit of the nonce value per cycle. The circuit further comprises a hash engine that inserts, on the cycle-by-cycle basis, the nonce value into a block header of a block candidate and generates a digest by applying a hash function to the block header. The block header includes a representation of a target value. The circuit further comprises a validator that compares, on the cycle-by-cycle basis, the digest to the target value. In an event the digest satisfies the target value, the validator submits the block candidate to the blockchain network, causing newly minted bitcoin to be mined from the blockchain network. Changing only one binary digit of the nonce value, per cycle, reduces power consumption of the circuit.
H04L 9/32 - Arrangements for secret or secure communications; Network security protocols including means for verifying the identity or authority of a user of the system
G06F 21/76 - Protecting specific internal or peripheral components, in which the protection of a component leads to protection of the entire computer to assure secure computing or processing of information in application-specific integrated circuits [ASIC] or field-programmable devices, e.g. field-programmable gate arrays [FPGA] or programmable logic devices [PLD]
G06Q 20/06 - Private payment circuits, e.g. involving electronic currency used only among participants of a common payment scheme
H04L 9/00 - Arrangements for secret or secure communications; Network security protocols
A communication apparatus includes a receiver disposed in proximity to a transmitter, and a crosstalk cancellation circuit. The receiver includes an input buffer, a front end, and an adaptive resampling circuit. The input buffer receives from the transmitter aggressor data, the aggressor data being timed by a transmitter clock clocking the transmitter. The front end receives data over a communication link, the data being serialized according to a receiver clock clocking the receiver, the receiver clock operating independently of the transmitter clock. The front end further generates a stream of data samples corresponding to the received data. The adaptive resampling circuit resamples the aggressor data, and generates resampled data timed by the receiver clock. The crosstalk cancellation circuit estimates, based on the resampled data, a crosstalk error signal related to the aggressor data, and subtracts the estimated crosstalk error signal from the stream of data samples.
A physical layer transceiver assembly includes physical layer transceiver circuitry having an input/output terminal configured for coupling to data channel medium, and an electrostatic discharge protection circuit coupled between the terminal and a ground of the assembly. The electrostatic discharge protection circuit includes a reactive filter network coupled to the terminal and configured to selectively limit current flow through the electrostatic discharge protection circuit, and an electrostatic discharge protection device coupled between the reactive filter network and the ground of the assembly. Where the electrostatic discharge protection device is a snapback device, the reactive filter network is configured to limit current at frequencies that adversely affect the snapback device. One implementation of the reactive filter network is a band-stop filter that limits current in a frequency band including the frequencies that adversely affect the snapback device, and passes current at frequencies above and below the frequency band.
A multi-chip module (MCM includes a substrate and first and second integrated circuit chips disposed on the substrate. The second IC chip includes transceiver circuitry configured to communicate with the first IC chip. The transceiver circuitry includes transmit circuitry having an inverter circuit to generate a first signal for transmission to the first IC chip along a signaling link. The signaling link includes a line termination impedance. Receiver circuitry includes a receiver circuit to receive a second signal from the first IC chip along the signaling link concurrently with transmission of the first signal along the signaling link. Hybrid circuitry is coupled to the transmit circuitry and to the receiver circuitry. The hybrid circuitry is configured to cancel a received component of the first signal. The hybrid circuitry includes a replica termination impedance that is configured in an open state.
A new approach is proposed to support device under test (DUT) validation reuse across a plurality of platforms, e.g., hardware simulation, hardware emulation, and post-silicon validation. First, an inference profile used for an inference operation of an application, e.g., a machine learning (ML) application, is generated based on a set of profile configurations, a set of test parameters, and a set of randomized constraints. A plurality of math functions specified by, e.g., an architecture team, for the ML application are also statically and/or dynamically verified via block simulation and/or formal verification. An inference model for the DUT is then built based on the inference profile and the plurality of verified math functions. Finally, an inference database including one or more of stimulus, DUT configurations, input data and predicted output results is generated based on the inference model, wherein the inference database for the DUT is reusable across the plurality of platforms.
A method and structure for probabilistic shaping and compensation techniques in coherent optical receivers. According to an example, the present invention provides a method and structure for an implementation of distribution matcher encoders and decoders for probabilistic shaping applications. The techniques involved avoid the traditional implementations based on arithmetic coding, which requires intensive multiplication functions. Furthermore, these probabilistic shaping techniques can be used in combination with LDPC codes through reverse concatenation techniques.
H04B 10/00 - Transmission systems employing electromagnetic waves other than radio-waves, e.g. infrared, visible or ultraviolet light, or employing corpuscular radiation, e.g. quantum communication
A communication device determines that a communication channel to be used for a multi-user (MU) transmission spans a frequency bandwidth greater than 160 MHz. The communication device allocates one or more frequency resource units (RUs) for the MU transmission, including: in response to determining that the communication channel spans the frequency bandwidth greater than 160 MHz, selecting one or more frequency RUs from a second set of frequency RUs. The second set of frequency RUs omits at least some RUs of a smallest bandwidth that are included in a first set of RUs that is used for allocating frequency RUs for communication channels having bandwidths of at most 160 MHz. The communication device generates allocation information that indicates the allocation of the one or more frequency RUs for the MU transmission, and transmits the allocation information to one or more other communication devices in connection with the MU transmission.
A first component of a network device determines that the first component is to provide packet data to a second component of the network device for processing by the second component. In connection with determining that the first component is to provide packet data to the second component of the network device, the first component prompts the second component to activate a clock network of the second component. In connection with prompting the second component to activate the clock network, the first component sends the packet data to the second component to be processed by the second component. The first component determines when the second component has completed processing of the packet data, and prompts the second component to deactivate the clock network in response to determining that the second component has completed processing of the packet data.
Clock data recovery circuitry, for a deserializer of a data transceiver, includes a clock recovery loop with a first feed-forward equalizer having a smaller number of taps and operating on received signals to recover a clock signal, and a data recovery loop including a second feed-forward equalizer having a larger number of taps, operating on received signals to recover a data signal. Output of the second feed-forward equalizer is coupled to output of the first feed-forward equalizer to improve recovery of the clock signal. The clock recovery loop may include adaptation circuitry configured to operate on output of the first feed-forward equalizer to counteract effects, on the clock signal, of adaptation of the second feed-forward equalizer by signals output by a decision feedback equalizer in the data recovery loop.
In a vehicular communication network, a communication device generates a physical layer (PHY) preamble of a PHY protocol data unit (PPDU) for transmission in the vehicular communication network. The communication device generates a plurality of PHY data segments of the PPDU, and one or more PHY midambles, each PHY midamble to be transmitted between a respective pair of adjacent PHY data segments, and each PHY midamble including one or more training signal fields. Generating the one or more PHY midambles includes, when the PPDU is to be transmitted according to an extended range (ER) mode, generating each training signal field to include i) a first portion based on a very high throughput long training field (VHT-LTF) defined by the IEEE 802.11ac Standard and ii) a second portion based on the VHT-LTF defined by the IEEE 802.11ac Standard; and transmitting, by the communication device, the PPDU in the vehicular communication network.
Methods and apparatus for combining received uplink transmissions. In an embodiment, a method is provided that includes receiving a descrambled resource element associated with selected second channel state information (CSI2) and receiving a descrambling sequence used to generate the descrambled RE. The method also includes rescrambling the descrambled RE using the descrambling sequence to generate a rescrambled RE and modifying the descrambling sequence to generate a modified descrambling sequence. The method also includes descrambling the rescrambled RE with the modified descrambling sequence to generate a modified descrambled RE and accumulating the modified descrambled RE to form a combined CSI2 value.
A coordinator communication device operates in a communication network according to a communication protocol that defines repeating time cycles and specifies that each of multiple communication devices is provided a respective transmit opportunity in each time cycle. The coordinator communication device determines a number of follower communication devices in a communication network while the follower communication devices are selecting transmit opportunities using respective initial device identifiers. The coordinator communication device determines a quantity of transmit opportunities to be provided in each of multiple time cycles during which the follower communication devices are selecting transmit opportunities using respective new device identifiers. The coordinator communication device determines the quantity of transmit opportunities at least by using the number of follower communication devices. While the follower communication devices are selecting transmit opportunities using the respective new device identifiers, the coordinator communication device provides the quantity of transmit opportunity periods in each time cycle.
A coordinator communication device operates in a communication network according to a communication protocol that defines repeating time cycles and specifies that each of multiple communication devices is provided a respective transmit opportunity in each time cycle. The coordinator communication device determines a number of follower communication devices in a communication network while the follower communication devices are selecting transmit opportunities using respective initial device identifiers. The coordinator communication device determines a quantity of transmit opportunities to be provided in each of multiple time cycles during which the follower communication devices are selecting transmit opportunities using respective new device identifiers. The coordinator communication device determines the quantity of transmit opportunities at least by using the number of follower communication devices. While the follower communication devices are selecting transmit opportunities using the respective new device identifiers, the coordinator communication device provides the quantity of transmit opportunity periods in each time cycle.
A pre-scaled accumulated byte count of a port of a network node over a sampling period is scaled with a scaling factor to generate a scaled accumulated byte count. The pre-scaled accumulated byte count represents a total number of bytes in packets transferred by the port. The scaling factor represents a first port-specific attribute of the port and scales a port-specific maximum throughput of the port to a specific maximum port throughput of the network node. An iterative vector encoding method is applied to the scaled accumulated byte count to generate an encoded bit vector comprising bits respectively ordered bit positions. Each set bit of the encoded bit vector represents a respective weighted value of port utilization of the port. The encoded bit vector is stored, at a map location, in an operational statistics map.
A pre-scaled accumulated byte count of a port of a network node over a sampling period is scaled with a scaling factor to generate a scaled accumulated byte count. The pre-scaled accumulated byte count represents a total number of bytes in packets transferred by the port. The scaling factor represents a first port-specific attribute of the port and scales a port-specific maximum throughput of the port to a specific maximum port throughput of the network node. An iterative vector encoding method is applied to the scaled accumulated byte count to generate an encoded bit vector comprising bits respectively ordered bit positions. Each set bit of the encoded bit vector represents a respective weighted value of port utilization of the port. The encoded bit vector is stored, at a map location, in an operational statistics map.
An optoelectronic device includes a gain medium configured to amplify laser radiation within a given gain band. A resonant optical cavity contains the gain medium and includes first and second reflectors disposed on first and second sides of the gain medium. A comb filter between the first and second reflectors and configured to pass a set of distinct wavelength sub-bands within the gain band, the set of distinct wavelength sub-bands defining a comb. A plurality of optical ring resonators between the first and second reflectors in series with the comb filter have tunable resonant wavelengths in proximity to different, respective wavelength sub-bands of the comb. A control circuit applies respective control voltages to the optical ring resonators so as to tune the respective resonant wavelengths relative to the respective wavelength sub-bands, thereby modulating the sub-bands in the laser radiation that is output from the device.
H01S 3/107 - Controlling the intensity, frequency, phase, polarisation or direction of the emitted radiation, e.g. switching, gating, modulating or demodulating by controlling devices placed within the cavity using electro-optic devices, e.g. exhibiting Pockels or Kerr effect
H01S 3/082 - Construction or shape of optical resonators or components thereof comprising three or more reflectors defining a plurality of resonators, e.g. for mode selection or suppression
An integrated circuit device includes a main integrated circuit die having functional circuitry configured to communicate over a network through one or more high-speed communications interfaces, and at least one secondary integrated circuit die including serial interface circuitry. Each integrated circuit die among the at least one secondary integrated circuit die is mounted on a first surface of the main integrated circuit die, and first metallization connections extend along one or more first through-silicon vias between the functional circuitry and the serial interface circuitry of the at least one secondary integrated circuit die. The first metallization connections may be configured to provide data from the main die to the secondary die, and the secondary die may be configured to communicate data between the integrated circuit device and a remote integrated circuit device. Second metallization connections extend between the serial interface circuitry of and terminals of the main integrated circuit die.
H01L 25/065 - Assemblies consisting of a plurality of individual semiconductor or other solid state devices all the devices being of a type provided for in the same subgroup of groups , or in a single subclass of , , e.g. assemblies of rectifier diodes the devices not having separate containers the devices being of a type provided for in group
H01L 23/00 - SEMICONDUCTOR DEVICES NOT COVERED BY CLASS - Details of semiconductor or other solid state devices
H01L 23/48 - Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads or terminal arrangements
H01L 25/00 - Assemblies consisting of a plurality of individual semiconductor or other solid state devices
29.
MECHANICAL STIFFENER FOR INTEGRATED CIRCUIT PACKAGE WITH VARYING HEAT DISSIPATION MODES
An integrated circuit device package includes a substrate, at least two integrated circuit dies mounted to the substrate, and a thermally conductive stiffener attached to the substrate to counteract warping of the substrate. The stiffener has a first portion in a thermally conductive relationship with a surface of a first integrated circuit die to provide a first heat dissipation mode for the first integrated circuit die, and has a second portion, different from the first portion, the second portion being configured to provide a second heat dissipation mode, different from the first heat dissipation mode, for a second integrated circuit die. The stiffener may be configured to expose a surface of the second integrated circuit die through an opening in the stiffener. A heat sink may be disposed in a thermally conductive relationship with the second integrated circuit die through the opening in the stiffener.
H01L 25/065 - Assemblies consisting of a plurality of individual semiconductor or other solid state devices all the devices being of a type provided for in the same subgroup of groups , or in a single subclass of , , e.g. assemblies of rectifier diodes the devices not having separate containers the devices being of a type provided for in group
H01L 23/00 - SEMICONDUCTOR DEVICES NOT COVERED BY CLASS - Details of semiconductor or other solid state devices
H01L 23/367 - Cooling facilitated by shape of device
H01L 23/552 - Protection against radiation, e.g. light
09 - Scientific and electric apparatus and instruments
Goods & Services
Electronic circuits; semiconductors; semiconductor chips; semiconductor computer chips; integrated circuits; computer hardware; microprocessors; micro controllers, data storage devices, components, or circuits, namely, computer hardware in the nature of memory expander controllers, compute express link, active memory expanders; computer hardware and downloadable computer software and firmware for use in controlling, storing, monitoring, and managing data in processors, workload accelerators, data centers, attached storage devices and systems; integrated circuits for controlling hard disk drives; integrated circuits for processing data read from, and written to, hard disk drives; integrated circuits for controlling solid state drives; integrated circuits for processing data read from, and written to, solid state drives; integrated circuits for controlling the storage of data on a peripheral storage device connected to a host computer; integrated circuits for connecting multiple devices to a host computer over a compute express link (CXL) compliant connection; compute express link (CXL) switches and bridges; semiconductor memory subsystems, namely, memory storage subsystems, and computer hardware and downloadable software for supporting, controlling and operating semiconductor memory subsystems; memory circuit designs, namely, integrated circuit memory and memory controller layouts recorded on computer media; downloadable computer software and firmware for managing the storage of data on a peripheral storage device; downloadable computer software and firmware for managing the storage of data on a hard disk drive; downloadable computer software and firmware for managing the storage of data on a solid state drive; flash memory controllers; nonvolatile memory accelerators; computer memories; computer memory devices; computer memories, namely, memory devices and controllers for use with computers.
A method for recovering a clock from input data, in a deserializer that couples a transmission medium to receive circuitry of a data transceiver, includes operating, in a first clock recovery loop, on equalized input data from a data recovery loop to provide a first timing error signal, operating, in a second clock recovery loop, on unequalized input data to provide a second timing error signal, combining the first and second timing error signals, and deriving a recovered clock signal from the combined first and second timing error signals using an oscillator circuit. Combining the first and second timing error signals may include operating on the first and second timing error signals in a manner that filters the first timing error signal to remove low-frequency components including adaptation errors introduced by the data recovery loop, and that filters the second timing error signal to remove high frequency components including jitter.
H04L 7/033 - Speed or phase control by the received code signals, the signals containing no special synchronisation information using the transitions of the received signal to control the phase of the synchronising-signal- generating means, e.g. using a phase-locked loop
H04L 7/00 - Arrangements for synchronising receiver with transmitter
The present disclosure describes apparatuses and methods for scalable packet processing. In some aspects, match logic of a scalable packet processor extracts and compares bits from a packet header to determine if the packet matches a context. The match logic may also determine a context index value based on other bits extracted from the header. In response to the match and based on a virtual function associated with the packet, context generation logic of the packet processor obtains a base context value and a context range value from a lookup table. The context generation logic then determines a context identifier for the packet based on the context index value, base context value, and context range value through modular arithmetic. Accordingly, the packet processor can generate context identifiers for packet distribution across contexts without maintaining a table of every context, enabling efficient scaling of the packet processor with less silicon area.
An Integrated Circuit (IC) includes one or more functional circuits of a given type, a test circuit including a selected one of the functional circuits or a replica circuit of the same type as the functional circuits, and an Adaptive Voltage Scaling (AVS) circuit. The AVS circuit is configured to determine a delay of the test circuit, and to adjust a supply voltage of the functional circuits in response to the determined delay of the test circuit.
A system and corresponding method isolate work within a virtualized scheduler using tag-spaces. The system comprises a tag-space resource configured to store at least one respective assignment of at least one scheduling group to a given tag-space. The given tag-space defines a given ordering-atomicity domain that isolates, within the virtualized scheduler, (i) work belonging to the at least one scheduling group from (ii) work belonging to at least one other scheduling group, assigned, in the tag-space resource, to a respective tag-space different from the given tag-space. The system further comprises a work scheduler that schedules, for processing, work belonging to the at least one scheduling group and work belonging to the at least one other scheduling group. Such scheduling may have independent ordering and atomicity effectuated therebetween by the given ordering-atomicity domain. Such independency of ordering and atomicity improves quality-of-service of the virtualized scheduler.
09 - Scientific and electric apparatus and instruments
Goods & Services
Electronic circuits; semiconductors; semiconductor chips; semiconductor computer chips; integrated circuits; computer hardware; microprocessors; micro controllers, data storage devices, components, or circuits, namely, computer hardware in the nature of memory expander controllers, compute express link, active memory expanders; computer hardware and downloadable computer software and firmware for use in controlling, storing, monitoring, and managing data in processors, workload accelerators, data centers, attached storage devices and systems; integrated circuits for controlling hard disk drives; integrated circuits for processing data read from, and written to, hard disk drives; integrated circuits for controlling solid state drives; integrated circuits for processing data read from, and written to, solid state drives; integrated circuits for controlling the storage of data on a peripheral storage device connected to a host computer; integrated circuits for connecting multiple devices to a host computer over a compute express link (CXL) compliant connection; compute express link (CXL) switches and bridges; semiconductor memory subsystems, namely, memory storage subsystems, and computer hardware and downloadable software for supporting, controlling and operating semiconductor memory subsystems; memory circuit designs, namely, integrated circuit memory and memory controller layouts recorded on computer media; downloadable computer software and firmware for managing the storage of data on a peripheral storage device; downloadable computer software and firmware for managing the storage of data on a hard disk drive; downloadable computer software and firmware for managing the storage of data on a solid state drive; flash memory controllers; nonvolatile memory accelerators; computer memories; computer memory devices; computer memories, namely, memory devices and controllers for use with computers
36.
METHOD AND APPARATUS FOR SHARING KEYS FOR ENCRYPTION AND/OR DECRYPTION
A vehicle subsystem assembly transmits an identifier of the vehicle subsystem assembly to an electronic control unit (ECU) via an Ethernet link as part of a procedure for obtaining a first key for secure communications with the ECU via the Ethernet link from a backend system. Then, the vehicle subsystem assembly receives an encrypted message from the ECU via the Ethernet link and decrypts the encrypted message using a second key stored at the vehicle subsystem assembly to generate a first decrypted message. The vehicle subsystem assembly determines whether the first decrypted message includes a second identifier that matches the first identifier, and extracts the first key from the decrypted message. In response to determining that the decrypted message includes the second identifier that matches the first identifier, the vehicle subsystem assembly uses the first key in connection with secure communications between the vehicle subsystem assembly and the ECU.
H04L 9/32 - Arrangements for secret or secure communications; Network security protocols including means for verifying the identity or authority of a user of the system
37.
NETWORK USING ASYMMETRIC UPLINK AND DOWNLINK BAUD RATES TO REDUCE CROSSTALK
A transmitter transmits a first signal via a first cable at a first baud rate. A receiver receives a second signal via the first cable concurrently with transmitting the first signal via the first cable. The second signal is transmitted by another device at a second baud rate that is lower than both i) the first baud rate and ii) a third baud rate at which a third signal is being transmitted in a second cable that causes crosstalk in the second signal being received via the first cable. Reception of the second signal at the second baud rate that is lower than the third baud rate facilitates mitigation of the crosstalk in the second signal caused by transmission of the third signal in the second cable at the third baud rate.
H04B 3/32 - Reducing cross-talk, e.g. by compensating
H04B 3/21 - Reducing echo effects or singing; Opening or closing transmitting path; Conditioning for transmission in one direction or the other using a set of bandfilters
An optoelectronic device includes a reflective semiconductor optical amplifier (RSOA), which includes a gain medium to amplify laser radiation within a given gain band, a first reflector at a first end of the gain medium, and a waveguide coupled to convey the laser radiation into and out of a second end of the gain medium. An external laser cavity, disposed on an optical substrate, is optically coupled to the waveguide. The external laser cavity includes a second reflector, a comb filter, disposed between the second reflector and the RSOA and configured to pass a set of distinct wavelength sub-bands within the gain band, the set of distinct wavelength sub-bands defining a comb, and a bandpass filter between the second reflector and the RSOA in series with the comb filter, having a passband encompassing a subset of the wavelength sub-bands in the comb.
H01S 3/10 - Controlling the intensity, frequency, phase, polarisation or direction of the emitted radiation, e.g. switching, gating, modulating or demodulating
H01S 5/30 - Structure or shape of the active region; Materials used for the active region
H01S 5/50 - Amplifier structures not provided for in groups
39.
METHOD AND APPARATUS FOR DETERMINING TIME OF FLIGHT
A first communication device receives an analog receive signal via a communication medium. An ADC of the first communication device converts the analog receive signal to a digital receive signal. Logic circuitry of the first communication device detects a plurality of timing signals from a second communication device based on analyzing the digital receive signal. The logic circuitry adjusts a sampling phase of the ADC in connection with at least some of the timing signals so that the ADC is using different sampling phases when different ones of the timing signals are detected. The logic circuitry determines timing information based on the detection of the plurality of timing signals when the ADC is using different sampling phases when different ones of the timing signals are detected. The first communication device determines a time of flight between the first communication device and the second communication device based on the timing information.
A circuit and corresponding method provide a translation lookaside buffer (TLB) implementation. The circuit comprises a plurality of TLB banks and TLB logic. The TLB logic computes a plurality of hash values of a tag included in a memory request. The TLB logic locates, based on hash values of the plurality of hash values computed, a contiguous translation entry (TE) and a non-contiguous TE in different TLB banks of the plurality of TLB banks. The TLB logic determines a result by comparing the tag with the contiguous TE located and by comparing the tag with the non-contiguous TE located. The TLB logic outputs the result determined toward servicing the memory request. The TLB logic advantageously enables the TLB implementation to support contiguous pages using standard random-access memories for the plurality of TLB banks.
G06F 12/1027 - Address translation using associative or pseudo-associative address translation means, e.g. translation look-aside buffer [TLB]
G06F 12/0864 - Addressing of a memory level in which the access to the desired data or data block requires associative addressing means, e.g. caches using pseudo-associative means, e.g. set-associative or hashing
G06F 12/1009 - Address translation using page tables, e.g. page table structures
41.
Network identifiers for WLAN using multiple communication links
A communication device assigns a first basic service set (BSS) color identifier (ID) to a first communication link among multiple communication links corresponding to multiple frequency segments, and assigns a second BSS color ID to a second communication link among the multiple communication links. The communication device uses the first BSS color ID when communicating via the first communication link, and uses the second BSS color ID when communicating via the second communication link.
A transmitter includes a shift register, a lookup table, and a digital to analog converter. The shift register is configured to receive an input signal and to output delayed copies of the input signal. The lookup table is configured to store compensation values estimated based on the input signal and the delayed copies of the input signal. The digital to analog converter is configured to output a transmit signal based on the input signal and the compensation values. The compensation values are designed to mitigate distortion of the transmit signal from conversion of the input signal to a digital signal.
A method and system for flexibly assigning hardware resources to physical and virtual functions in a processor system supporting hardware virtualization is disclosed. The processor system includes a resource virtualization unit which is used to flexibly assign hardware resources to physical functions and also flexibly assign local functions to virtual functions associated with one or more of the physical functions. Thereby, standard PCI software is compatible with the physical functions and any associated virtualized hardware resources that have been flexibly assigned to the virtual and local functions.
G06F 9/455 - Emulation; Interpretation; Software simulation, e.g. virtualisation or emulation of application or operating system execution engines
G06F 13/24 - Handling requests for interconnection or transfer for access to input/output bus using interrupt
G06F 13/28 - Handling requests for interconnection or transfer for access to input/output bus using burst mode transfer, e.g. direct memory access, cycle steal
G06F 13/42 - Bus transfer protocol, e.g. handshake; Synchronisation
A communication device includes a plurality of communication pipelines configured to receive respective input data streams and a multiplexer coupled to the plurality of communication pipelines. The multiplexer is configured to generate an output data stream by combining the input data streams and to insert one or more special characters into the output data stream in response to a fault with one of the communication pipelines.
A system and corresponding method employ an object-oriented memory device. The object-oriented memory device includes at least one physical memory and a hardware controller. The hardware controller is coupled intra the object-oriented memory device to the at least one physical memory. The hardware controller (i) decodes an object-oriented message received from a hardware client of the object-oriented memory device and (ii) performs an action for the hardware client based on the object-oriented message received and decoded. The object-oriented message is associated with an object instantiated or to-be-instantiated in the at least one physical memory. The action is associated with the object. The object-oriented memory device alleviates the hardware client(s) from having to manage structure of respective data stored in the at least one physical memory, obviating duplication of code among the hardware clients for managing same and efforts for design and verification thereof.
G06F 9/50 - Allocation of resources, e.g. of the central processing unit [CPU]
G06F 5/06 - Methods or arrangements for data conversion without changing the order or content of the data handled for changing the speed of data flow, i.e. speed regularising
G06F 9/38 - Concurrent instruction execution, e.g. pipeline, look ahead
G06F 9/448 - Execution paradigms, e.g. implementations of programming paradigms
A method of scan-chain testing of an integrated circuit device having a plurality of respective scan-chain paths, at least some of the respective scan-chain paths being designated as having resource constraints, includes propagating a respective scan-chain data pattern through each of the respective scan-chain paths, and gating each respective scan-chain path designated as having resource constraints, to reduce a rate of scan-chain data propagation through the respective scan-chain path, without gating any scan-chain path not designated as having resource constraints. Scan-chain paths may be designated as having resource constraints because of high power consumption or data congestion.
A controller of a solid state drive (SSD) device, in response to determining that the SSD device is to transition to a power saving mode: transfers information from at least some of a volatile memory of an SSD device controller of the SSD device to a host memory of a host computer via a communication interface; and transitions the at least some of the volatile memory to an OFF state to reduce power consumption of the SSD device. In response to determining that the SSD device is to transition from the power saving mode to a normal operating mode, the controller also: transitions the at least some of the volatile memory to an ON state in which the at least some of the volatile memory is configured to retain data; and transfers the information from the host memory to the volatile memory of the SSD device controller via the communication interface.
G06F 3/06 - Digital input from, or digital output to, record carriers
G06F 11/10 - Adding special bits or symbols to the coded information, e.g. parity check, casting out nines or elevens
G06F 12/0804 - Addressing of a memory level in which the access to the desired data or data block requires associative addressing means, e.g. caches with main memory updating
G06F 13/16 - Handling requests for interconnection or transfer for access to memory bus
A hardware client and corresponding method employ an object-oriented memory device. The hardware client generates an object-oriented message associated with an object of an object class. The object class includes at least one data member and at least one method. The hardware client transmits the object-oriented message generated to the object-oriented memory device via a hardware communications interface. The hardware communications interface couples the hardware client to the object-oriented memory device. The object is instantiated or to-be instantiated in at least one physical memory of the object-oriented memory device according to the object class. The at least one method enables the object-oriented memory device to access the at least one data member for the hardware client.
G06F 9/50 - Allocation of resources, e.g. of the central processing unit [CPU]
G06F 5/06 - Methods or arrangements for data conversion without changing the order or content of the data handled for changing the speed of data flow, i.e. speed regularising
G06F 9/38 - Concurrent instruction execution, e.g. pipeline, look ahead
G06F 9/448 - Execution paradigms, e.g. implementations of programming paradigms
A communication device performs a first backoff operation with a first backoff counter to determine when to transmit a first packet in a first frequency, and performs a second backoff operation with a second backoff counter to determine when to transmit a second packet in a second frequency segment. In connection with the first backoff counter expiring, the communication device transmits the first packet in the first frequency segment. In connection with the second backoff counter expiring, the communication device transmits the second packet in the second frequency segment simultaneously with transmitting the first packet in the first frequency segment. In response to determining that transmission of the first packet in the first frequency segment failed, the communication device increases a first contention window for a retransmission of the first packet, and does not adjust the second contention window for a next transmission in the second frequency segment.
An access point (AP) device that serves a wireless local area network (WLAN) determines that a coverage area of the AP device is partitioned into a plurality of sectors, the coverage area corresponding to the WLAN. The AP device determines that a first transmission is occurring within a first sector among the plurality of sectors, and determines that a client station is located in a second sector among the plurality of sectors, the second sector different than the first sector. In response to determining that the first transmission is occurring within the first sector, the AP device selects the client station for a directional second transmission in a direction i) within the second sector and ii) outside of the first sector, and transmits the directional second transmission to the client station in the second sector while the first transmission in the first sector is occurring.
A network interface device decodes a first set of encoded bits in a fixed-length frame according to a first error correction encoding scheme to generate a first set of bits among decoded bits. The network interface device decodes a second set of encoded bits in the fixed-length frame according to a second error correction encoding scheme to generate a second set of bits among the decoded bits. The network interface device generates a first set of bit blocks and a second set of bit blocks from the decoded bits at least by de-aggregating the decoded bits. A decoder of the network interface device decodes the first set of bit blocks and the second set of bit blocks to generate a plurality of uncoded bits.
H04L 1/00 - Arrangements for detecting or preventing errors in the information received
H03M 13/00 - Coding, decoding or code conversion, for error detection or error correction; Coding theory basic assumptions; Coding bounds; Error probability evaluation methods; Channel models; Simulation or testing of codes
Methods and apparatus for combining received uplink transmissions. In an embodiment, a method is provided that includes receiving a descrambled resource element associated with selected second channel state information (CSI2) and receiving a descrambling sequence used to generate the descrambled RE. The method also includes rescrambling the descrambled RE using the descrambling sequence to generate a rescrambled RE and modifying the descrambling sequence to generate a modified descrambling sequence. The method also includes descrambling the rescrambled RE with the modified descrambling sequence to generate a modified descrambled RE and accumulating the modified descrambled RE to form a combined CSI2 value.
The present invention is directed to data communication systems and techniques thereof. In a specific embodiment, the present invention provides a network connector that includes an interface for connecting to a host. The interface includes a circuit for utilizing two data paths for the host. The circuit is configured to transform the host address to different addresses based on the data path being used. There are other embodiments as well.
A communication device generates a first packet and a second packet. The first packet includes a first physical layer (PHY) preamble having: a first legacy signal field (L-SIG) having first duration information that indicates a first duration of the first packet; and first non-legacy signal field information having first modulation information that indicates a first modulation used in the first packet. The second packet includes a second PHY preamble having: a second L-SIG having second duration information that indicates a second duration of the second packet, wherein the second duration is different than the first duration; and second non-legacy signal field information having second modulation information that indicates a second modulation used in the second packet, wherein the second modulation is different than the first modulation. The communication device simultaneously transmits the first packet in a first frequency segment and the second packet in a second frequency segment.
A system and corresponding method queue work within a virtualized scheduler based on in-unit accounting (IUA) of in-unit entries (IUEs). The system comprises an IUA resource and arbiter. The IUA resource stores, in association with an IUA identifier, an IUA count and threshold. The IUA count represents a global count of work-queue entries (WQEs) that are associated with the IUA identifier and occupy respective IUEs of an IUE resource. The IUA threshold limits the global count. The arbiter retrieves the IUA count and threshold from the IUA resource based on the IUA identifier and controls, as a function of the IUA count and threshold, whether a given WQE from a given scheduling group, assigned to the IUA identifier, is moved into the IUE resource to be queued for scheduling. The IUA count and threshold prevent group(s) assigned to the IUA identifier from using more than an allocated amount of IUEs.
A circuit and corresponding method control cycle time of an output clock used to clock at least one other circuit. The circuit comprises an agile ring oscillator (ARO) and ARO controller. The ARO includes at least one instance of a first ring oscillator (RO) and second RO that generate high and low phases, respectively, of cycles of the output clock. The ARO controller controls durations of the high and low phases, independently, via first and second control words output to the ARO, respectively. In a present cycle of the output clock, the ARO controller effects a change to the high or low phase, or a combination thereof, in a next cycle of the output clock by updating the first or second control word, or a combination thereof, based on an indication of expected usage of the at least one other circuit in the next cycle. The change improves a performance-to-power ratio of the at least one other circuit.
H03L 7/16 - Indirect frequency synthesis, i.e. generating a desired one of a number of predetermined frequencies using a frequency- or phase-locked loop
H03K 5/13 - Arrangements having a single output and transforming input signals into pulses delivered at desired time intervals
H03L 5/00 - Automatic control of voltage, current, or power
H03L 7/099 - Automatic control of frequency or phase; Synchronisation using a reference signal applied to a frequency- or phase-locked loop - Details of the phase-locked loop concerning mainly the controlled oscillator of the loop
57.
Method and apparatus for establishing timing to perform link training in ethernet communication based on link quality and/or channel conditions
Systems and methods are described for dynamically updating a duration of link training time for a first stage of link training implemented to set up a first characteristic of a link connection between a physical layer transceiver (PHY) and a link partner. A first stage of link training preconfigured to last for a first duration of time is initiated and a metric of link quality that measures a link connection quality is initiated. Based on the determined metric of link quality, updating the first duration of time for the first stage of link training.
A method includes receiving a first set of data. The method also includes receiving an instruction to determine a largest value within the first set of data. The first set of data is divided into a first plurality of data portions based on a hardware architecture of a first plurality of processing elements. The first plurality of data portions is mapped to the first plurality of processing elements. Each data portion of the first plurality of data portions is mapped exclusively to a processing element of the first plurality of processing elements. Each data portion of the first plurality of data portions is processed by its respective processing element to identify a largest value from each data portion of the first plurality of data portions, wherein the processing forms a first output data comprising the largest value from the each data portion of the first plurality of data portions.
G06N 20/10 - Machine learning using kernel methods, e.g. support vector machines [SVM]
G06F 15/80 - Architectures of general purpose stored program computers comprising an array of processing units with common control, e.g. single instruction multiple data processors
An optical transmitter includes a first encoder, a first interleaver, a second encoder, a mapper, a second interleaver, and a frame generator. The first encoder is configured to encode data using a staircase code to generate first codewords. The first interleaver is configured to interleave the first codewords using convolutional interleaving to spread a transmission order of the first codewords. The second encoder is configured to encode the interleaved first codewords using a second code to generate second codewords. The mapper is configured to map the second codewords to transmit symbols. The second interleaver is configured to interleave the transmit symbols to distribute the transmit symbols between pilot symbols. The frame generator is configured to generate a transmit frame including the interleaved transmit symbols and the pilot symbols.
H04L 1/00 - Arrangements for detecting or preventing errors in the information received
H03M 13/19 - Single error correction without using particular properties of the cyclic codes, e.g. Hamming codes, extended or generalised Hamming codes
H03M 13/25 - Error detection or forward error correction by signal space coding, i.e. adding redundancy in the signal constellation, e.g. Trellis Coded Modulation [TCM]
H03M 13/29 - Coding, decoding or code conversion, for error detection or error correction; Coding theory basic assumptions; Coding bounds; Error probability evaluation methods; Channel models; Simulation or testing of codes combining two or more codes or code structures, e.g. product codes, generalised product codes, concatenated codes, inner and outer codes
60.
METHOD AND APPARATUS FOR COMMUNICATING INFORMATION VIA PILOT SIGNALS
A first communication device receives control data that are to be communicated to a transceiver of a second communication device, the control data for use by the transceiver to adjust one or more operating parameters of the transceiver. The first communication device encodes the control data on multiple pilot symbols so that each pilot symbol of the multiple pilot symbols encodes less than all of the multiple bits of control data. The first communication device receives information bits that are to be communicated to the second communication device via data symbols, and generates a plurality of data symbols using the information bits. The first communication device transmits the plurality of data symbols and the multiple pilot symbols to the second communication device via a communication medium. When transmitted, the multiple pilot symbols and encoded portions of the multiple bits of control data are interspersed among the plurality of data symbols.
Transceiver circuitry in an integrated circuit device includes a receive path including an analog front end for receiving analog signals from an analog transmission path and conditioning the analog signals, and an analog-to-digital converter configured to convert the conditioned analog signals into received digital signals for delivery to functional circuitry, and a transmit path including a digital front end configured to accept digital signals from the functional circuitry and to condition the accepted digital signals, and a digital-to-analog converter configured to convert the conditioned digital signals into analog signals for transmission onto the analog transmission path. At least one of the analog front end and the digital front end introduces distortion and outputs a distorted conditioned signal. The transceiver circuitry further includes distortion correction circuitry at the one of the analog front end and the digital front end, to determine and apply a distortion cancellation function to the distorted signal.
A first communication device receives control data that are to be communicated to a transceiver of a second communication device, the control data for use by the transceiver to adjust one or more operating parameters of the transceiver. The first communication device encodes the control data on multiple pilot symbols so that each pilot symbol of the multiple pilot symbols encodes less than all of the multiple bits of control data. The first communication device receives information bits that are to be communicated to the second communication device via data symbols, and generates a plurality of data symbols using the information bits. The first communication device transmits the plurality of data symbols and the multiple pilot symbols to the second communication device via a communication medium. When transmitted, the multiple pilot symbols and encoded portions of the multiple bits of control data are interspersed among the plurality of data symbols.
The present disclosure describes apparatuses and methods for implementing a reinforcement learning-enabled low-density parity check (LDPC) decoder. In aspects, an RL-enabled LDPC decoder processes, as part of a first decoding iteration, data of a channel to generate LDPC state information and provides the LDPC state information to a machine learning (ML) algorithm of an RL agent. The RL-enabled LDPC decoder is then configured with LDPC decoding parameters obtained from the ML algorithm and processes, as part of a second decoding operation, the data using the decoding parameters to generate subsequent LDPC state information. The RL-enabled LDPC decoder provides decoded data of the channel based on the subsequent LDPC state information. By using the LDPC decoding parameters provided by the ML algorithm of the RL agent, the RL-enabled LDPC decoder may decode channel data in fewer decoding iterations or with a higher success rate, thereby improving LDPC decoding performance.
H03M 13/11 - Error detection or forward error correction by redundancy in data representation, i.e. code words containing more digits than the source words using block codes, i.e. a predetermined number of check bits joined to a predetermined number of information bits using multiple parity bits
G06N 3/04 - Architecture, e.g. interconnection topology
An optical transceiver includes a silicon photonics substrate, transmitter circuitry, and receiver circuitry that are heterogeneously integrated. The transmitter circuitry includes a plurality of laser devices formed on the silicon photonics substrate, each of the plurality of laser devices configured to generate a respective laser light, a plurality of modulators formed on the silicon photonics substrate, each of the plurality of modulators configured to modulate the laser lights based on driver signals and output, from the silicon photonics substrate, the modulated laser lights, and a driver formed on the silicon photonics substrate and configured to generate the driver signals. The receiver circuitry includes a photodetector configured to receive a plurality of optical signals and convert the plurality of optical signals to respective electrical signals and a transimpedance amplifier device configured to receive the electrical signals and output the electrical signals from the silicon photonics substrate as electrical outputs.
B60G 21/05 - Interconnection systems for two or more resiliently-suspended wheels, e.g. for stabilising a vehicle body with respect to acceleration, deceleration or centrifugal forces permanently interconnected mechanically between wheels on the same axle but on different sides of the vehicle, i.e. the left and right wheel suspensions being interconnected
B60G 15/02 - Resilient suspensions characterised by arrangement, location, or type of combined spring and vibration- damper, e.g. telescopic type having mechanical spring
An Ethernet Physical layer (PHY) device includes a PHY interface and PHY circuitry. The PHY interface is configured to connect to a physical link. The PHY circuitry is configured to generate layer-1 frames that carry data for transmission to a peer Ethernet PHY device, to insert among the layer-1 frames one or more management frames that are separate from the layer-1 frames and that are configured to control a General-Purpose Input-Output (GPIO) port associated with the peer Ethernet PHY device, to transmit the layer-1 frames and the inserted management frames, via the PHY interface, to the peer Ethernet PHY device over the physical link, for controlling one or more operations of the GPIO port associated with the peer Ethernet PHY device, and to receive, via the PHY interface, one or more verifications acknowledging that the one or more management frames were received successfully at the peer Ethernet PHY device.
Passage of data packets on a data pipeline is arbitrated in a distributed manner along the pipeline. Multiple data arbiters each operate to merge data from a respective data source to the data pipeline at a distinct point in the pipeline. At each stage, a multiplexer selectively passes, to the data pipeline, an upstream data packet or a local data packet from the respective data source. A register stores an indication of data packets passed by the multiplexer based on the respective data source originating the data packet. A controller controls the multiplexer to select the upstream data packet or the local data packet based on the indication of data packets passed by the multiplexer.
A system to support validation and debugging of compiled low-level instructions for a machine learning (ML) network model on an ML-specific hardware. A compiler identifies well-defined boundaries in the ML network model based on primitives used to generate low-level instructions for the hardware. The ML network model is partitioned into units/layers/sub-graphs based on the plurality of well-defined boundaries. The compiler then generates an internal representation for each of the units wherein the internal representation is mapped to components in the hardware. Each of the units is compiled into a first set to be executed on the ML-specific hardware and a second set to be executed on a second computing device. The output results from executing the two sets of low-level instructions are compared to validate the first set of low-level instructions. If the outputs do not match fully, the first set of low-level instructions is debugged and recompiled.
A circuit and corresponding method enable mining for digital currency in a blockchain network. The circuit comprises a controller and at least one partial hash engine that (i) implements a hash function, partially, to compute a partial hash digest of a final hash digest for a block header of a block candidate and (ii) generates a notification based on determining that the partial hash digest satisfies a criterion. The controller includes a complete hash engine that implements the hash function, completely. In response to the notification generated, the controller activates the complete hash engine to compute, in its entirety, the final hash digest for the block header, effectuating a decision for submission of the block candidate with the block header to the blockchain network for mining the digital currency. Power savings and reduction in area are achieved relative to multiple hash engines that compute the entire final hash digest.
G06Q 20/40 - Authorisation, e.g. identification of payer or payee, verification of customer or shop credentials; Review and approval of payers, e.g. check of credit lines or negative lists
H04L 9/06 - Arrangements for secret or secure communications; Network security protocols the encryption apparatus using shift registers or memories for blockwise coding, e.g. D.E.S. systems
H04L 9/00 - Arrangements for secret or secure communications; Network security protocols
A first communication device generates and transmits a frame that is configured to cause one or more second communication devices in a wireless local area network (WLAN) to refrain from transmitting during a set of repeating time segments, and the frame is generated to include an indication of a time period of the time segments in the set of repeating time segments, the time period being less than a duration of a beacon interval of the WLAN such that multiple ones of the time segments occur within one beacon interval. Alternatively, the frame is configured to cause one or more second communication devices in the WLAN to refrain from transmitting during a time segment that begins in conjunction with an end of transmission of i) the frame or ii) a packet that includes the frame, and the frame is generated to include an indication of a time duration of the time segment.
A communication device selects a frequency bandwidth via which a physical layer (PHY) protocol data unit (PPDU) will be transmitted in a vehicular communication network, and generates, the PPDU i) according to a downclocking ratio of 1/2, and ii) based on an orthogonal frequency division multiplexing (OFDM) numerology defined by an IEEE 802.11ac Standard. In response to the selected frequency bandwidth being 10 MHz, the PPDU is generated according to the downclocking ratio of 1/2 and based on the OFDM numerology defined by the IEEE 802.11ac Standard for 20 MHz PPDUs. In response to the selected frequency bandwidth being 20 MHz, the PPDU is generated according to the downclocking ratio of 1/2 and based on the OFDM numerology defined by the IEEE 802.11ac Standard for 40 MHz PPDUs.
A first communication device receives an analog receive signal via a communication medium. An ADC of the first communication device converts the analog receive signal to a digital receive signal. Logic circuitry of the first communication device detects a plurality of timing signals from a second communication device based on analyzing the digital receive signal. The logic circuitry adjusts a sampling phase of the ADC in connection with at least some of the timing signals so that the ADC is using different sampling phases when different ones of the timing signals are detected. The logic circuitry determines timing information based on the detection of the plurality of timing signals when the ADC is using different sampling phases when different ones of the timing signals are detected. The first communication device determines a time of flight between the first communication device and the second communication device based on the timing information.
G01S 7/00 - RADIO DIRECTION-FINDING; RADIO NAVIGATION; DETERMINING DISTANCE OR VELOCITY BY USE OF RADIO WAVES; LOCATING OR PRESENCE-DETECTING BY USE OF THE REFLECTION OR RERADIATION OF RADIO WAVES; ANALOGOUS ARRANGEMENTS USING OTHER WAVES - Details of systems according to groups , ,
G01S 13/34 - Systems for measuring distance only using transmission of continuous waves, whether amplitude-, frequency-, or phase-modulated, or unmodulated using transmission of continuous, frequency-modulated waves while heterodyning the received signal, or a signal derived therefrom, with a locally-generated signal related to the contemporaneously transmitted signal
H04L 7/033 - Speed or phase control by the received code signals, the signals containing no special synchronisation information using the transitions of the received signal to control the phase of the synchronising-signal- generating means, e.g. using a phase-locked loop
72.
CIRCUIT FOR MULTI-PATH INTERFERENCE MITIGATION IN AN OPTICAL COMMUNICATION SYSTEM
An optical receiver includes an error generator, a multipath interference estimator, and a combiner. The error generator is configured to receive an input comprising a received optical signal, to estimate a modulation level of samples of the received optical signal, and to generate an error signal based on the estimated modulation level of the samples, the error signal representing a difference between an actual level of the received optical signal and the estimated modulation level. The multipath interference estimator is configured to generate estimates of multipath interference (MPI) associated with the samples of the received optical signal based on the error signal. The combiner is configured to generate an MPI-mitigated signal based on a combination of the samples and the estimates of MPI.
H04B 10/58 - Compensation for non-linear transmitter output
H04B 10/00 - Transmission systems employing electromagnetic waves other than radio-waves, e.g. infrared, visible or ultraviolet light, or employing corpuscular radiation, e.g. quantum communication
H04B 10/2507 - Arrangements specific to fibre transmission for the reduction or elimination of distortion or dispersion
H04B 10/516 - Transmitters - Details of coding or modulation
Methods and apparatus for receiving a user message in a communication network are disclosed. In an exemplary embodiment, a method includes receiving data samples in an uplink transmission from user equipment, performing preamble detection on the data samples, generating a trigger signal that indicates when a preamble is detected, and decoding a user message in response to the trigger signal, wherein the user message follows the detected preamble.
A method for cancelling, from servo signals read in a read channel while a write channel is active, interference caused by write signals in the write channel, includes generating a predicted channel response signal from the write signals in a data clock domain, resampling the generated predicted channel response signal using a clock in the data clock domain having a rate corresponding to a servo clock from a servo clock domain, transferring the resampled predicted channel response signal from the data clock domain to the servo clock domain and aligning phase of the transferred resampled predicted channel response signal with phase of the servo clock, determining a domain-boundary-crossing delay incurred in the transferring, based on the domain-boundary-crossing delay, synchronizing the phase-aligned transferred resampled predicted channel response signal with the servo signals, and subtracting the synchronized phase-aligned transferred resampled predicted channel response signal from the servo signals.
A first communication device generates a first physical layer (PHY) data unit that includes information indicating a capability to use a channel bandwidth greater than a maximum channel bandwidth of the first communication device, and transmits the first PHY data unit to a second communication device during an association process with the second communication device. The first communication device generates a second PHY data unit that includes information indicating a capability to use at most the maximum channel bandwidth of the first communication device, and transmits the second PHY data unit to the second communication device when the first communication device is associated with the second communication device.
A first communication device generates an Operation, Administration, and Maintenance (OAM) frame that includes i) OAM message content and ii) an OAM frame header outside of the OAM message content, wherein generating the OAM frame comprises generating the OAM frame header to include information that signals one of i) a low power sleep (LPS) request, and ii) a wake-up request (WUR). The first communication device transmits the OAM frame to a second communication device via a communication medium to signal to the second communication device the one of i) the LPS request, and ii) the WUR.
A system and corresponding method perform large memory transaction (LMT) stores. The system comprises a processor associated with a data-processing width and a processor accelerator. The processor accelerator performs a LMT store of a data set to a coprocessor in response to an instruction from the processor targeting the coprocessor. The data set corresponds to the instruction. The LMT store includes storing data from the data set, atomically, to the coprocessor based on a LMT line (LMTLINE). The LMTLINE is wider than the data-processing width. The processor accelerator sends, to the processor, a response to the instruction. The response is based on completion of the LMT store of the data set in its entirety. The processor accelerator enables the processor to perform useful work in parallel with the LMT store, thereby improving processing performance of the processor.
G06F 3/06 - Digital input from, or digital output to, record carriers
G06F 12/1045 - Address translation using associative or pseudo-associative address translation means, e.g. translation look-aside buffer [TLB] associated with a data cache
78.
Structures and methods for deriving stable physical unclonable functions from semiconductor devices
A semiconductor device includes circuitry configured to derive a physical unclonable function. The circuitry includes a plurality of bitcells, each bitcell being readable as one of a ‘0’ value and a ‘1’ value, and sense amplifier circuitry configurable to read values from the plurality of bitcells. The sense amplifier circuitry includes margin circuitry configurable (i) to selectably bias reading of the plurality of bitcells toward one of ‘0’ values and ‘1’ values, (ii) to identify addresses of bitcells having a stable ‘1’ value when the margin circuitry is configured to bias reading of the plurality of bitcells toward ‘0’ values, and (iii) to identify addresses of bitcells having a stable ‘0’ value when the margin circuitry is configured to bias reading of the plurality of bitcells toward ‘1’ values. Each bitcell in the plurality of bitcells may include a differential transistor pair.
H04L 9/32 - Arrangements for secret or secure communications; Network security protocols including means for verifying the identity or authority of a user of the system
A first communication device is configured to process packets that conform to a first physical layer (PHY) protocol for wireless vehicular communications and packets that conform to a second PHY protocol for wireless vehicular communications. The first communication device determines that one or more second communication devices neighboring the first communication device are not capable of processing packets that conform to the second PHY protocol. The first communication device transmits a first packet to a third communication device that is configured to process packets that conform to the first PHY protocol and packets that conform to the second PHY protocol. The first packet indicates that the one or more second communication devices neighboring the first communication device are not capable of processing packets that conform to the second PHY protocol to inform the third communication device of the one or more second communication devices.
Memory blocks are allocated for a microcontroller having one memory subsystem storing instruction information, and a separate memory subsystem storing data information. At design time, an address map is created implementing configurations of different ways of allocating instruction information and data information between memory blocks. At runtime, a configuration signal is received, and a particular memory block configuration for storing instruction information and data information is determined. An incoming instruction signal received from a dedicated microcontroller port, is communicated according to the configuration signal and the address map to a connection point (e.g., pin, fuse, register). Via that connection point, the instruction signal is routed to a memory block designated exclusively for instructions. Similarly, based upon the configuration signal and the address map, an incoming data signal (received from another dedicated microcontroller port), is routed via a connection point to a different memory block designated to store exclusively data information.
A decoder for a receiver in a communication system includes an interface configured to receive encoded input data via a communication channel. The encoded input data includes forward error correction (FEC) codewords. A processor is configured to decode the FEC codewords using low density parity check (LDPC) codes defined by a parity check matrix. The parity check matrix is defined by both regular column partition (RCP) constraints and quasi-cyclic (QC) constraints. An output circuit is configured to output a decoded codeword based on the FEC codewords decoded by the processor.
H03M 13/00 - Coding, decoding or code conversion, for error detection or error correction; Coding theory basic assumptions; Coding bounds; Error probability evaluation methods; Channel models; Simulation or testing of codes
H03M 13/11 - Error detection or forward error correction by redundancy in data representation, i.e. code words containing more digits than the source words using block codes, i.e. a predetermined number of check bits joined to a predetermined number of information bits using multiple parity bits
82.
System and Method for Neural Network-Based Autonomous Driving
A system and corresponding method for autonomous driving of a vehicle are provided. The system comprises at least one neural network (NN) that generates at least one output for controlling the autonomous driving. The system further comprises a main data path that routes bulk sensor data to the at least one NN and a low-latency data path with reduced latency relative to the main data path. The low-latency data path routes limited sensor data to the at least one NN which, in turn, employs the limited sensor data to improve performance of the at least one NN's processing of the bulk sensor data for generating the at least one output. Improving performance of the at least one NN's processing of the bulk sensor data enables the system to, for example, identify a safety hazard sooner, enabling the autonomous driving to divert the vehicle and avoid contact with the safety hazard.
The present disclosure describes apparatuses and methods for contextual search of a storage system. In some aspects, a metadata manager of a storage system receives a query to search the data stored on the storage media of the apparatus. The metadata manager identifies an entry in a relational database of the metadata manager that includes a label that is relevant to the query and determines, based on the entry in the relational database, a reference address of a target node in a navigational database of the metadata manager that corresponds to the label. As results for the query to search, the metadata manager returns an object of the target node at the reference address in the navigational database and corresponding objects of relative nodes connected to the target node via respective links. By so doing, the metadata database may enable contextual or implicit search of data in the storage system.
Methods, PHYs, and computer-readable media are provided for reliably receiving data at a physical layer transceiver of an automobile in the presence of noise or interference. A non-equalized signal is received at a physical layer transceiver via a communication channel in a high noise or interference automotive environment. The non-equalized signal is prepared for extraction of data by performing one or more of the following: improving a signal-to-noise ratio of the non-equalized signal by using two or more parallel matching filters to correlate the non-equalized signal with two or more signal templates to detect the presence of logic low signal patterns and logic high signal patterns in the non-equalized signal; reducing jitter in the non-equalized signal by tracking a phase of the non-equalized signal using a digital timing loop; compensating for noise or interference distortion in the non-equalized signal by selecting a decision sample defined by a plurality of peaks, the selecting performed based on tracking peaks in the non-equalized signal; searching the non-equalized signal for a preamble before initiating a process of receiving payload data, to reduce false data reception caused by noise or interference; and extracting data from the prepared non-equalized signal.
H04L 25/497 - Transmitting circuits; Receiving circuits using three or more amplitude levels by correlative coding, e.g. partial response coding or echo modulation coding
H04L 25/49 - Transmitting circuits; Receiving circuits using three or more amplitude levels
An apparatus for performing cryptographic primitives includes a processor that is configured to receive an instruction to perform a cryptographic primitive, where the instruction includes one or more operands, at least one of the operands indicates one or more data structures that include values for the cryptographic primitive, and where the values include a first value indicating a mode of encryption that indicates an order of performing an encryption operation and an authentication operation and a second value indicating a cipher type; and perform the cryptographic primitive and store an output of the cryptographic primitive in an output data structure.
H04L 29/06 - Communication control; Communication processing characterised by a protocol
H04L 9/06 - Arrangements for secret or secure communications; Network security protocols the encryption apparatus using shift registers or memories for blockwise coding, e.g. D.E.S. systems
H04L 9/32 - Arrangements for secret or secure communications; Network security protocols including means for verifying the identity or authority of a user of the system
86.
EXPLICIT BEAMFORMING IN A HIGH EFFICIENCY WIRELESS LOCAL AREA NETWORK
A first communication device receives a sounding packet from a second communication device and develops beamforming information based on the sounding packet. The first communication device transmits beamforming feedback to the second communication device, the beamforming feedback including beamforming information for use by the second communication device to beamsteer a data packet to the first communication device, the data packet having a data portion that includes a second number of OFDM tones greater than a first number of OFDM tones in the sounding packet. After transmitting the beamforming feedback, the first communication device receives the data packet from the second communication device, the data packet including one or more data OFDM symbols, each of the one or more data OFDM symbols having the second number of OFDM tones.
H04B 7/0456 - Selection of precoding matrices or codebooks, e.g. using matrices for antenna weighting
H04B 7/06 - Diversity systems; Multi-antenna systems, i.e. transmission or reception using multiple antennas using two or more spaced independent antennas at the transmitting station
H04L 5/00 - Arrangements affording multiple use of the transmission path
In an embodiment, a method includes programming a control signal that specifies a target resistance and a target voltage in a circuit. The method further includes sending the control signal to at least one transistor configured to control a current flow in the circuit. The method further includes providing, as an output, a signal with the target voltage and target resistance.
H03K 19/00 - Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits
H03K 19/20 - Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits characterised by logic function, e.g. AND, OR, NOR, NOT circuits
88.
WIRELINE TRANSCEIVER WITH INTERNAL AND EXTERNAL CLOCK GENERATION
An integrated circuit device having functional circuitry driven by a clock signal includes onboard clock generation circuitry. The clock generation circuitry includes an input configured to accept a frequency reference signal, at least one variable loading capacitor coupled to the input for converting the crystal resonator signal into a calibrated clock signal, and calibration circuitry configured to calibrate the at least one variable loading capacitor based on a reference voltage. The input configured to accept a frequency reference signal may be configured to accept a crystal resonator signal.
A network device accesses, from a queue corresponding to a port of the device, a packet for processing. The device identifies a present operating region (ORE) of one or more OREs specified for the device, an ORE being associated with at least one of (i) one or more device attributes, or (ii) one or more environmental factors associated with an environment in which the device is operational. The device determines a number of power credits available for processing one or more packets. In response to determining that the number of power credits available is non-negative, the device completes processing of the packet. The device computes, based at least on the present ORE, a power credit reduction for the packet, which corresponds to an amount of power for processing the packet, and reduces the number of power credits available by the power credit reduction for the packet.
A method of reading servo wedge data from a rotating constant-density magnetic storage medium having a plurality of tracks, where each track is written at a track pattern frequency, the respective track pattern frequencies varying from a lowest frequency at an innermost one of the tracks to a highest frequency at an outermost one of the tracks, includes, for each respective track, determining, based on the pattern frequency of the respective track, a desired sampling position, sampling actual samples of servo wedge data based on a sampling clock used for all tracks, having a sampling frequency at least equal to the track pattern frequency of the outermost track, determining a phase relationship of the desired sampling position to the sampling clock, and, depending on the phase relationship between the sampling position and the sampling clock, interpolating a sample, or omitting interpolation of a sample and squelching the interpolation clock.
A method for writing repeatable run-out (RRO) data, to surfaces of a rotating magnetic storage medium in a storage device having two read channels, includes detecting, with a first head, using a first read channel, a servo sync mark (SSM) on a first track on a first surface, establishing a recurring servo-gating signal at a successive fixed interval from the SSM, detecting, with the first head, servo signals from the first track on occurrence of the recurring servo-gating signal, processing the servo signals from the first track, to generate first positioning signals for positioning the first head relative to the first track, following a similar procedure with a second read channel having a second head to generate second positioning signals for the second read head, and writing first and second RRO data to servo wedges of the first and second tracks according to the respective positioning signals.
G11B 5/596 - Disposition or mounting of heads relative to record carriers with provision for moving the head for the purpose of maintaining alignment of the head relative to the record carrier during transducing operation, e.g. to compensate for surface irregularities of the latter or for track following for track following on disks
92.
Reduction of four-wave mixing crosstalk in optical links
A transmitter includes at least three tunable laser sources, an optical multiplexer, and a processor. The at least three tunable laser sources are configured to receive respective data streams, and to output respective Tx light beams at different respective carrier frequencies, modulated with the respective data streams. The optical multiplexer is configured to combine the multiple Tx light beams to produce a combined beam formed of the modulated Tx light beams at the different carrier frequencies, and to transmit the combined beam over an optical fiber. The processor is configured to receive a notification indicative of an interference occurring due to Four-Wave Mixing (FWM) in the optical fiber, and to modify at least one of the carrier frequencies responsively to the notification in order to mitigate the interference due to FWM.
G02B 6/293 - Optical coupling means having data bus means, i.e. plural waveguides interconnected and providing an inherently bidirectional system by mixing and splitting signals with wavelength selective means
An integrated circuit includes a silicon photonics substrate having a silicon-based material, silicon photonics components formed in the silicon photonics substrate to receive and transmit optical signals, and electrical connections; a transimpedance amplifier chip arranged on the silicon photonics substrate, having a silicon-germanium material that is different than the silicon-based material, connected via the electrical connections to at least one of the silicon photonics components configured to receive an optical signal, and configured to process a received optical signal and output a processed signal to a digital signal processor; and a driver chip arranged on the silicon photonics substrate, having CMOS material that is different than the silicon-germanium material and the silicon-based material, connected via the electrical connections to drive at least one of the silicon photonics components configured to generate an optical signal for transmission.
G02B 6/12 - Light guides; Structural details of arrangements comprising light guides and other optical elements, e.g. couplings of the optical waveguide type of the integrated circuit kind
G02B 6/126 - Light guides; Structural details of arrangements comprising light guides and other optical elements, e.g. couplings of the optical waveguide type of the integrated circuit kind using polarisation effects
G02B 6/42 - Coupling light guides with opto-electronic elements
H01S 3/13 - Stabilisation of laser output parameters, e.g. frequency or amplitude
A multi-chip package includes first and second groups of integrated circuit (IC) chips and a transfer IC chip disposed in the multi-chip package. The transfer IC chip is communicatively interposed between the first and second groups of IC chips and is configured to transfer signals from at least a first IC chip of the first group of IC chips to at least a second IC chip of the second group of IC chips or an output interface. The output interface is configured to output first data from the multi-chip package. A first set of ultra-short reach (USR) signaling links connects the first group of IC chips to the transfer IC chip. A second set of USR signaling links connects the second group of IC chips to the transfer IC chip. Each of the USR signaling links comprises a trace length of less than one inch.
Forming a metal gate transistor includes forming a semiconductor channel in a substrate, and depositing a source electrode and a drain electrode on the semiconductor channel. The source and drain electrodes are spaced apart. Dielectric spacers are provided above the source and drain electrodes to define a gate void spanning the source and drain electrodes. A dielectric layer is deposited on a bottom wall and sidewalls of the gate void. A work-function metal layer is deposited on the dielectric layer. The work-function metal layer is etched away from the sidewalls leaving the work-function metal layer on the bottom wall to control work function between the semiconductor channel and a conductive metal gate material to be deposited. The gate void above the work-function metal layer on the bottom wall, and between the dielectric layers on the sidewalls, is filled with the conductive metal gate material.
A semiconductor device is configured to implement a security protocol. The semiconductor device includes an entropy source that includes a plurality of bitcells. The entropy source is configured to output a sequence of physical unclonable function bit values based on intrinsic properties of the plurality of bitcells to generate a unique device secret for the security protocol, and selectively damage at least a portion of the plurality of bitcells to prevent reverse engineering the sequence of physical unclonable function bit values.
G06F 21/71 - Protecting specific internal or peripheral components, in which the protection of a component leads to protection of the entire computer to assure secure computing or processing of information
G06F 21/14 - Protecting executable software against software analysis or reverse engineering, e.g. by obfuscation
A circuit and corresponding method perform resource arbitration. The circuit comprises a pending arbiter (PA) that outputs a PA selection for accessing a resource. The PA is selection based on PA input. The PA input represents respective pending-state of requesters of the resource. The circuit further comprises a valid arbiter (VA) that outputs a VA selection for accessing the resource. The VA selection is based on VA input. The VA input represents respective valid-state of the requesters. The circuit performs a validity check on the PA selection output. The circuit outputs a final selection for accessing the resource by selecting, based on the validity check performed, the PA selection output or VA selection output. The circuit addresses arbitration fairness issues that may result when multiple requesters are arbitrating to be selected for access to a shared resource and such requesters require a credit (token) to be eligible for arbitration.
A circuit detects a voltage droop exhibited by a power supply. A first signal delay line outputs a first delayed signal, and is comprised of delay elements having a first threshold voltage. A second delay line outputs a second delayed signal, and is comprised of delay elements having a second threshold voltage that is higher than the first threshold voltage. A phase detector compares the first and second delayed signals and outputs a comparison signal indicating which of the first and second signal delay lines exhibits a shorter delay. A reset circuit resets the first and second signal delay lines in response to the comparison signal, and a clock controller outputs a command to adjust a clock frequency or engage in other mitigation measures based on the comparison signal.
G01R 25/00 - Arrangements for measuring phase angle between a voltage and a current or between voltages or currents
H03K 5/14 - Arrangements having a single output and transforming input signals into pulses delivered at desired time intervals by the use of delay lines
H03L 7/00 - Automatic control of frequency or phase; Synchronisation
99.
System and method for schedule-based I/O multiplexing for integrated circuit (IC) scan test
An approach is proposed to support schedule-based I/O multiplexing for scan testing of an IC. A plurality of I/Os are assigned to a plurality of blocks in the IC for scan testing based on a set of slots under a set of schedules. Each of the set of slots includes a fixed number of scan input pins/pads and scan output pins/pads of the IC. Each slot is then assigned to a specific block on the IC for the scan test until all of the slots available are utilized. The group of assigned blocks is referred to as a schedule, and all of these blocks belonging to this schedule are scan tested in parallel at the same time. The remaining blocks on the IC are also assigned to the slots until all blocks on the IC are assigned to a schedule to be scan tested.
A first optical module includes an optical transceiver and a chip. The optical transceiver, subsequent to completion of link training of an in-band transmission link between the first optical module and a host device, waits for a second optical module to come up including transmitting a first awake signal from the first optical module to the second optical module, and receives a second awake signal from the second optical module when the second optical module is up. The chip i) based on a first out-of-band signal transmitted via an out-of-band link, performs the link training of the in-band transmission link independently of an in-band reception link between the first optical module and the host device, and ii) based on the second awake signal and a second out-of-band signal transmitted via the out-of-band link, performs link training of the in-band reception link independent of the in-band transmission link.
H04B 10/079 - Arrangements for monitoring or testing transmission systems; Arrangements for fault measurement of transmission systems using an in-service signal using measurements of the data signal
H04B 10/077 - Arrangements for monitoring or testing transmission systems; Arrangements for fault measurement of transmission systems using an in-service signal using a supervisory or additional signal
H04B 10/80 - Optical aspects relating to the use of optical transmission for specific applications, not provided for in groups , e.g. optical power feeding or optical transmission through water
