A method is claimed. The method includes receiving information associated with a software application's workflow. The method includes receiving information that describes a platform's current power consumption state and current thermal state. The method includes selecting platform components to support execution of the workflow. The method includes prior to execution of the workflow upon the selected platform components, estimating a thermal impact to the platform's current thermal state as a consequence of the workflow's execution upon the selected platform components. The method includes determining a change to be made to a thermal cooling system of the platform in response to the estimating and causing the change to be made to the thermal cooling system prior to execution of at least a portion of the workflow on the platform.
Techniques are described related to digital radio control and operation. The various techniques described herein enable high-frequency local oscillator (LO) signal generation using injection locked cock multipliers (ILCMs). The techniques also include the use of LO signals for carrier aggregation applications for phased array front ends. Furthermore, the disclosed techniques include the use of array element-level control using per-chain DC-DC converters. Still further, the disclosed techniques include the use of adaptive spatial filtering and optimal combining of analog-to-digital converters (ADCs) to maximize dynamic range in digital beamforming systems.
G01R 27/06 - Measuring reflection coefficients; Measuring standing-wave ratio
H01Q 3/40 - Arrangements for changing or varying the orientation or the shape of the directional pattern of the waves radiated from an antenna or antenna system varying the distribution of energy across a radiating aperture varying the phase by electrical means with phasing matrix
H03L 7/081 - Automatic control of frequency or phase; Synchronisation using a reference signal applied to a frequency- or phase-locked loop - Details of the phase-locked loop provided with an additional controlled phase shifter
H03L 7/24 - Automatic control of frequency or phase; Synchronisation using a reference signal directly applied to the generator
A system for privacy-enhanced sensor data exchange, including: a communication interface operable to receive sensor data related to surroundings of a sensor associated with an ego device; processor circuitry operable to: evaluate the sensor data for a privacy-sensitive attribute of the sensor data, wherein the sensor data is under privacy control of the ego device; filter the sensor data by decreasing a precision of a portion of the sensor data related to the privacy-sensitive attribute; and generate data packets based on the sensor data, formatted to enable discovery by an interested entity device.
Described herein are integrated circuit devices that include semiconductor devices near the center of the device, rather than towards the top or bottom of the device. In this arrangement, heat can become trapped inside the device. Metal fill, such as copper, is formed within a portion of the device, e.g., over the semiconductor devices and any front side interconnect structures, to transfer heat away from the semiconductor devices and towards a heat spreader.
H01L 23/367 - Cooling facilitated by shape of device
H01L 23/42 - Fillings or auxiliary members in containers selected or arranged to facilitate heating or cooling
H01L 23/532 - Arrangements for conducting electric current within the device in operation from one component to another including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body characterised by the materials
5.
STRIPPED REDISTRUBUTION-LAYER FABRICATION FOR PACKAGE-TOP EMBEDDED MULTI-DIE INTERCONNECT BRIDGE
An embedded multi-die interconnect bridge (EMIB) is fabricated on a substrate using photolithographic techniques, and the EMIB is separated from the substrate and placed on the penultimate layer of an integrated-circuit package substrate, below the top solder-resist layer. A low Z-height of the EMIB, allows for useful trace and via real estate below the EMIB, to be employed in the package substrate.
H01L 23/522 - Arrangements for conducting electric current within the device in operation from one component to another including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
H01L 23/00 - SEMICONDUCTOR DEVICES NOT COVERED BY CLASS - Details of semiconductor or other solid state devices
6.
SYSTEM AND METHODS FOR CLOSED LOOP DOPPLER TRACKING IN INTER-SATELLITE LINKS
An apparatus can include transceiver circuitry to receive an input signal from a target apparatus. The apparatus can further include a processing circuitry to determine position information of a source object and a target object. Based on the position information, the processing circuitry can calculate a relative velocity and determine a Doppler shift or carrier frequency offset in the input signal based on the relative velocity. The processing circuitry can adjust a local oscillator frequency based on a Doppler measured using the position information in an initial link acquisition phase. The processing circuitry can track the Doppler continuously over a range of tens of gigahertz accounting for Doppler phase ambiguities, and correct for a tracked Doppler shift by partially adjusting a local oscillator frequency and by correcting a residual Doppler shift digitally.
Described herein are integrated circuit devices that include semiconductor devices near the center of the device, rather than towards the top or bottom of the device, and integrated inductors formed over the semiconductor devices. Power delivery to the device is on the opposite side of the semiconductor devices. The integrated inductors may be used for power step-down to reduce device thickness and/or a number of power rails.
H01L 23/522 - Arrangements for conducting electric current within the device in operation from one component to another including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
Systems, apparatuses and methods may provide for controlling one or more end effectors by generating a semantic labelled image based on image data, wherein the semantic labelled image is to identify a shape of an object and a semantic label of the object, associating a first set of actions with the object, and generating a plan based on an intersection of the first set of actions and a second set of actions to satisfy a command from a user through actuation of one or more end effectors, wherein the second set of actions are to be associated with the command
Embodiments described herein provide a technique to facilitate the broadcast or multicast of asynchronous loads to shared local memory of a plurality of graphics cores within a graphics core cluster. One embodiment provides a graphics processor including a cache memory a graphics core cluster coupled with the cache memory. The graphics core cluster includes a plurality of graphics cores. The plurality of graphics cores includes a graphics core configured to receive a designation as a producer graphics core for a multicast load, read data from the cache memory; and transmit the data read from the cache memory to a consumer graphics core of the plurality of graphics cores.
Embodiments described herein provide a technique to enable access to entries in a surface state or sampler state using 64-bit virtual addresses. One embodiment provides a graphics core that includes memory access circuitry configured to facilitate access to the memory by functional units of the graphics core. The memory access circuitry is configured to receive a message to access an entry in a surface state or a sampler state associated with a parallel processing operation. The message specifies a base address for a surface state entry or sampler state entry. The circuitry can add the base address and the offset to determine a 64-bit virtual address for the entry in the surface state entry or the sampler state and submit a memory access request to the memory to access the entry of the surface state or sampler state.
When the speed of head movement exceeds the processing capability of the system, a reduced depiction is displayed. As one example, the resolution may be reduced using coarse pixel shading in order to create a new depiction at the speed of head movement. In accordance with another embodiment, only the region the user is looking at is processed in full resolution and the remainder of the depiction is processed at lower resolution. In still another embodiment, the background depictions may be blurred or grayed out to reduce processing time.
Embodiments include semiconductor packages and a method to form such semiconductor packages. A semiconductor package includes a plurality of dies on a substrate, and an encapsulation layer over the substrate. The encapsulation layer surrounds the dies. The semiconductor package also includes a plurality of dummy silicon regions on the substrate. The dummy silicon regions surround the dies and encapsulation layer. The plurality of dummy silicon regions are positioned on two or more edges of the substrate. The dummy silicon regions have a top surface substantially coplanar to a top surface of the dies. The dummy silicon regions include materials that include silicon, metals, or highly-thermal conductive materials. The materials have a thermal conductivity of approximately 120 W/mK or greater, or is equal to or greater than the thermal conductivity of silicon. An underfill layer surrounds the substrate and the dies, where the encapsulation layer surrounds portions of the underfill layer.
H01L 25/065 - Assemblies consisting of a plurality of individual semiconductor or other solid state devices all the devices being of a type provided for in the same subgroup of groups , or in a single subclass of , , e.g. assemblies of rectifier diodes the devices not having separate containers the devices being of a type provided for in group
H01L 21/48 - Manufacture or treatment of parts, e.g. containers, prior to assembly of the devices, using processes not provided for in a single one of the groups
H01L 21/56 - Encapsulations, e.g. encapsulating layers, coatings
H01L 21/78 - Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
H01L 23/00 - SEMICONDUCTOR DEVICES NOT COVERED BY CLASS - Details of semiconductor or other solid state devices
H01L 23/31 - Encapsulation, e.g. encapsulating layers, coatings characterised by the arrangement
An apparatus can include at least one audio device configured to detect sound. The apparatus can further include processing circuitry to determine presence of a relevant sound relevant to a user of the apparatus based on a user preference or an audio device parameter. The processing circuitry can further, responsive to detecting presence of the relevant sound, provide a control command to a user listening device to command the user listening device to provide the relevant sound to a microphone of the user listening device.
A data-centric network and non-Real-Time (RT) RAN Intelligence Controller (RIC) architecture are described. The data-centric network architecture provides data plane functions (DPFs) that serve as a shared database for control functions, user functions and management functions for data plane resources in a network. The DPFs interact with control plane functions, user plane functions, management plane functions, compute plane functions, network exposure functions, and application functions of the NR network via a service interface. The non-RT RIC provides functions via rApps, manages the rApps, performs conflict mitigation and security functions, monitors machine learning (ML) performance, provides a ML model catalog that contains ML model information, provides interface terminations and stores ML data and Near-RT RIC related information in a database. An ML training host trains and evaluates ML models in the catalog, obtains training and testing data from the database, and retrains and updates the ML models.
H04L 41/16 - Arrangements for maintenance, administration or management of data switching networks, e.g. of packet switching networks using machine learning or artificial intelligence
G06F 18/214 - Generating training patterns; Bootstrap methods, e.g. bagging or boosting
H04L 47/762 - Admission control; Resource allocation using dynamic resource allocation, e.g. in-call renegotiation requested by the user or requested by the network in response to changing network conditions triggered by the network
H04L 47/783 - Distributed allocation of resources, e.g. bandwidth brokers
15.
ADJUSTING WORKLOAD EXECUTION BASED ON WORKLOAD SIMILARITY
Adjusting workload execution based on workload similarity. A processor may determine a similarity of a first workload to a second workload. The processor may adjust execution of the first workload based on execution parameters of the second workload and the similarity of the first workload to the second workload.
An apparatus comprising translator circuitry to receive a plurality of physical addresses of memory data, determine an offset associated with each of the physical page addresses and apply a tweak seed to each offset to generate a plurality of tweaks.
Methods, apparatus, systems and articles of manufacture are disclosed for sparse tensor storage for neural network accelerators. An example apparatus includes sparsity map generating circuitry to generate a sparsity map corresponding to a tensor, the sparsity map to indicate whether a data point of the tensor is zero, static storage controlling circuitry to divide the tensor into one or more storage elements, and a compressor to perform a first compression of the one or more storage elements to generate one or more compressed storage elements, the first compression to remove zero points of the one or more storage elements based on the sparsity map and perform a second compression of the one or more compressed storage elements, the second compression to store the one or more compressed storage elements contiguously in memory.
An embodiment of an integrated circuit may comprise an array of hardware counters, and circuitry communicatively coupled to the array of hardware counters, the circuitry to count accesses to one or more selected pages of a memory with the array of hardware counters. Other embodiments are disclosed and claimed.
Thermal heat spreaders and/or an IC die with solderable thermal structures may be assembled together with a solder array thermal interconnects. A thermal heat spreader may include a non-metallic material and one or more metallized surfaces suitable for bonding to a solder alloy employed as thermal interface material between the heat spreader and an IC die. An IC die may include a metallized back-side surface similarly suitable for bonding to a thermal interconnect comprising a solder alloy. Metallization on the IC die and/or heat spreader may comprise a plurality of solderable structures. A multi-chip package may include multiple IC die having different die thickness that are accommodated by a z-height thickness variation in the thermal interconnects and/or the solderable structures of the IC die or heat spreader.
Microelectronic assemblies, and related devices and methods, are disclosed herein. For example, in some embodiments, a microelectronic assembly may include a package substrate having a first surface and an opposing second surface, and a die secured to the package substrate, wherein the die has a first surface and an opposing second surface, the die has first conductive contacts at the first surface and second conductive contacts at the second surface, and the first conductive contacts are coupled to conductive pathways in the package substrate by first non-solder interconnects.
H01L 23/00 - SEMICONDUCTOR DEVICES NOT COVERED BY CLASS - Details of semiconductor or other solid state devices
H01L 25/00 - Assemblies consisting of a plurality of individual semiconductor or other solid state devices
H01L 25/18 - Assemblies consisting of a plurality of individual semiconductor or other solid state devices the devices being of types provided for in two or more different subgroups of the same main group of groups , or in a single subclass of ,
21.
TOP GATE RECESSED CHANNEL CMOS THIN FILM TRANSISTOR AND METHODS OF FABRICATION
A device includes a device level having a metallization structure coupled to a semiconductor device and a transistor above the device level. The transistor has a body including a single crystal group III-V or group IV semiconductor material, a source structure on a first portion of the body and a drain structure on a second portion of the body, where the source structure is separate from the drain structure. The transistor further includes a gate structure including a first gate structure portion in a recess in the body and a second gate structure portion between the source structure and the drain structure. A source contact is coupled with the source structure and a drain contact is coupled with the drain structure. The source contact is in contact with the metallization structure in the device level.
H01L 23/522 - Arrangements for conducting electric current within the device in operation from one component to another including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
H01L 21/768 - Applying interconnections to be used for carrying current between separate components within a device
H01L 27/12 - Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being other than a semiconductor body, e.g. an insulating body
22.
TRIGGER-BASED PPDU RESOURCE INDICATION FOR EHT NETWORKS
An extremely high throughput (EHT) station (STA) configured for trigger based (TB) transmission may decode an trigger frame (TF) received from an access point (AP). The TF may include an assignment of resources comprising one or more 20 MHz channels. The EHT STA may determine which of the one or more assigned channels are available for transmission and which of the allocated channels are unavailable when the EHT STA is assigned more than one 20 MHz channel. The EHT STA may encode a EHT TB PPDU in response to the trigger frame. The EHT TB PPDU may be encoded to include an EHT preamble followed by a data field. The EHT preamble may be encoded to indicate channel availability. The EHT STA may generate signalling to cause the EHT STA to transmit the encoded EHT TB PPDU only on the assigned channels that have been determined to be available.
This disclosure describes systems, methods, and devices related to aligned channel access. A device may perform a first backoff countdown on a first link associated with a first station device (STA) of the device, wherein the device is a multi-link device (MLD). The device may detect a second backoff countdown associated with a second STA of the MLD after the first backoff countdown reaches zero. The device may determine to hold the first backoff countdown at zero based on the value of the second backoff countdown. The device may transmit in synchronization on the first link and on the second link from the first STA and the second STA respectively based on holding the first backoff countdown at zero.
Described herein is a generalized optimal reduction scheme for reducing an array modulo a constant. The constant modulo operation calculates a result for array of bits xi, width n modulo an odd positive integer constant d, (e.g., x[n:0] mod d). Circuitry to perform such operation can be configured to compress the array of bits xi, width n into an array of bits yi width m. The techniques described herein enable the design of optimal circuitry via iterative exploration of all potential reduction strategies that are available given the input constraints.
The techniques described in the detailed description above enable the manufacturing of circuits with increased performance and efficiency when performing division by a constant number. One embodiment provides circuitry including an input circuit to receive an input value including a plurality of bits, a logarithmic tree coupled with the input circuit, the logarithmic tree configured to compute an array of values based on a plurality of multi-bit groups of the plurality of bits of the input value, each value in the array of values includes a modulus of a corresponding multi-bit group with respect to the constant, a binary array adder to compute a quotient of the division operation based on the array of values, the input value, and the constant, and an output circuit to output the quotient.
A method is described. The method includes invoking one of more functions from a set of API functions that expose the current respective cooling states of different, respective cooling devices for different components of a hardware platform. The method includes orchestrating concurrent execution of multiple applications on the hardware platform in view of the current respective cooling states. The method includes, in order to prepare the hardware platform for the concurrent execution of the multiple applications, prior to the concurrent execution of the multiple applications, sending one or more commands to the hardware platform to change a cooling state of at least one of the cooling devices.
Embodiments detailed herein relate to matrix operations. In particular, support for matrix (tile) addition, subtraction, and multiplication is described. For example, circuitry to support instructions for element-by-element matrix (tile) addition, subtraction, and multiplication are detailed. In some embodiments, for matrix (tile) addition, decode circuitry is to decode an instruction having fields for an opcode, a first source matrix operand identifier, a second source matrix operand identifier, and a destination matrix operand identifier; and execution circuitry is to execute the decoded instruction to, for each data element position of the identified first source matrix operand: add a first data value at that data element position to a second data value at a corresponding data element position of the identified second source matrix operand, and store a result of the addition into a corresponding data element position of the identified destination matrix operand.
A device is provided, including a package substrate including at least one opening extending through the package substrate, and an interconnect structure including a first segment and a second segment. The first segment may extend under a bottom surface of the package substrate and may further extend beyond a footprint of the package substrate. The second segment may extend vertically from the first segment and may extend at least partially through the at least one opening of the package substrate.
H01L 21/48 - Manufacture or treatment of parts, e.g. containers, prior to assembly of the devices, using processes not provided for in a single one of the groups
H01L 25/00 - Assemblies consisting of a plurality of individual semiconductor or other solid state devices
H01L 25/065 - Assemblies consisting of a plurality of individual semiconductor or other solid state devices all the devices being of a type provided for in the same subgroup of groups , or in a single subclass of , , e.g. assemblies of rectifier diodes the devices not having separate containers the devices being of a type provided for in group
H01L 25/16 - Assemblies consisting of a plurality of individual semiconductor or other solid state devices the devices being of types provided for in two or more different main groups of groups , or in a single subclass of , , e.g. forming hybrid circuits
H01L 25/18 - Assemblies consisting of a plurality of individual semiconductor or other solid state devices the devices being of types provided for in two or more different subgroups of the same main group of groups , or in a single subclass of ,
29.
USER EQUIPMENT CAPABILITY FOR INTERRUPTIONS WITHOUT MEASUREMENT GAPS
Embodiments attempt to solve challenges in a wireless communications system. Embodiments describe various techniques, systems, and devices to support various measurement criteria for user equipment in a 3GPP 5G NR or 6G system, among other wireless communications systems. Other embodiments are described and claimed.
Examples described herein relate to circuitry to perform load balancing; at least one memory; and at least one processor. In some examples, at least one processor is to execute instructions stored in the at least one memory that cause the at least one processor to: execute a communication proxy that is to allocate packet data to the circuitry to perform load balancing to allocate workloads among cores and allocate received and transmitted remote procedure calls to at least one queue in circuitry to queue one or more packets.
Disclosed herein are microelectronic structures including bridges, as well as related assemblies and methods. In some embodiments, a microelectronic structure may include a substrate and a bridge.
H01L 23/538 - Arrangements for conducting electric current within the device in operation from one component to another the interconnection structure between a plurality of semiconductor chips being formed on, or in, insulating substrates
H01L 21/48 - Manufacture or treatment of parts, e.g. containers, prior to assembly of the devices, using processes not provided for in a single one of the groups
H01L 21/56 - Encapsulations, e.g. encapsulating layers, coatings
H01L 23/00 - SEMICONDUCTOR DEVICES NOT COVERED BY CLASS - Details of semiconductor or other solid state devices
H01L 23/31 - Encapsulation, e.g. encapsulating layers, coatings characterised by the arrangement
32.
ADAPTIVE CLOCK GATING FOR IMPROVING WEAR OUT-INDUCED DUTY CYCLE SHIFT IN COMPUTER CLOCK NETWORK
This disclosure describes systems, methods, and devices related to clock gating. A device may detect that gating of a local clock of a computer core is enabled; detect, based on the detection that the gating is enabled, that a clock gating condition for the local clock is satisfied; and set a clock gating polarity of the local clock based on the detection that the clock gating condition for the local clock is satisfied.
Embodiments herein relate to a technique to be performed by a power control unit (PCU) of an electronic device. Specifically, the PCU may identify, based on a metric related to an activity level of a processor core of a multi-core processor of the electronic device, first, second, and third weights that are respectively related to first, second, and third cores of the multi-core processor. Based on these weights, the PCU may identify a number of active processor cores of the multi-core processor, and alter a frequency limit of the multi-core processor accordingly. Other embodiments may be described and claimed.
Described herein is a technique for automatic program code optimization for high-level synthesis. One embodiment provides a method comprising receiving input including first program code in a high-level language; translating the first program code into an intermediate language; constructing an equality graph (e-graph) from the intermediate language; interleaving control-flow, data path, and gate-level transformations to explore equivalent hardware designs represented by the e-graph; selecting a hardware design based on a cost function; extracting a representation of a selected hardware design in the intermediate language; generating second program code in the high-level language; and performing high-level synthesis using the second program code.
Examples include techniques for a memory module per row activate counter. The techniques include detecting a row hammer or row disturb condition for a row address at a volatile memory device if an activate count to the row address matches a threshold count. The activate count is maintained by a controller for the memory module. Detection of the row hammer or row disturb condition can cause refresh management actions to mitigate the row hammer or row disturb condition.
This disclosure describes systems, methods, and devices related to adding or removing communication access points (APs) affiliated with an associated AP multi-link device (AP-MLD). A non-AP-MLD may identify a communication link between the non-AP-MLD and an AP-MLD, the communication link previously used by the non-AP-MLD; encode a request frame comprising a multi-link reconfiguration element indicative of a request to add or remove the communication link; cause the non-AP-MLD to transmit the request frame to the AP-MLD; and identify a response frame received from the AP-MLD, the response frame comprising the multi-link reconfiguration element and indicating whether the communication link was accepted or rejected to be added or removed.
Technologies for scheduling time-sensitive cyclical network traffic in real-time include an internet-of-things (IoT) device that includes at least one sensor for collecting sensor data. The IoT device is configured to store the collected sensor data in a data buffer, allocate a packet descriptor for the sensor data, and populate the allocated packet descriptor with a cyclic data port pointer indicative of a location of the data buffer. The IoT device is additionally configured to queue the packet descriptor into a media access control (MAC) unit transmit direct memory access (DMA) of the IoT device, fetch the sensor data, and packetize the fetched data to form a network packet. Further, the IoT device is configured to transmit the network packet to a target computing device based on a launch time, update the launch time, and requeue the packet descriptor into the MAC unit transmit DMA. Other embodiments are described herein.
This disclosure describes systems, methods, and devices related to WLAN sensing sounding. A device may identify a sensing null data packet (NDP) request frame received from a second device, the sensing NDP request frame associated with performing a wireless local area network channel sounding procedure; identify transmit parameters included in a transmit control field of the sensing NDP request frame; generate an NDP frame using the transmit parameters; and send, in response to the sensing NDP request frame, the NDP frame to the second device.
Embodiments herein relate to a circuit for evaluating the ground voltage of each circuit partition of a number of circuit partitions, one partition at a time. Once the ground voltage is determined, a corresponding code is stored to control a leakage circuit coupled to the ground node. The leakage circuit provides a leakage current based on the code to offset the ground voltage to a target voltage, which may be common for each of the partitions. The circuit can include a voltage source which supplies a stair step increasing voltage to a comparator. The comparator compares the voltage of the voltage source to the ground node voltage and provides an output which changes when the two input voltages are approximately equal, within a tolerance. The circuit may include a finite state machine for managing the process.
The disclosure relates to tuning configuration parameters for graphics pipeline for better user experience. A device for graphics processing, comprising: hardware engines; a graphics pipeline at least partly implemented by the hardware engines; and a tuner, coupled to the hardware engines and the graphics pipeline, the tuner to: collect statuses of the device during runtime for a previous frame; determine configuration parameters based on the collected statuses, the configuration parameters associated with three-dimensional 3D rendering, pre-processing and video encoding of the graphics pipeline; and tune the graphics pipeline with the determined configuration parameters for processing a next frame.
The disclosure is directed to apparatus and methods for detection of out of position (OOP) components in a carrier tape forming machine. An apparatus includes cross track sensors coupled to the bus interface circuitry, the cross track sensors configured to detect OOP components prior to overlaying the components on the carrier tape with cover tape, optical sensors to detect the OOP components on the carrier tape after overlaying with cover tape and prior to sealing and to detect reflections from OOP components seated on the carrier tape, an amplifier coupled to the optical sensors to amplify signals generated by the optical sensors and set a range for determining whether the components are OOP, and relays to receive indications of detected OOP components, and a controller coupled to the relays to stop the carrier tape forming machine as a function of signals received by the relays.
G01D 5/353 - Mechanical means for transferring the output of a sensing member; Means for converting the output of a sensing member to another variable where the form or nature of the sensing member does not constrain the means for converting; Transducers not specially adapted for a specific variable using optical means, i.e. using infrared, visible or ultraviolet light with attenuation or whole or partial obturation of beams of light the beams of light being detected by photocells influencing the transmission properties of an optical fibre
B65B 11/52 - Enclosing articles, or quantities of material, by disposing contents between two sheets, e.g. pocketed sheets, and securing their opposed free margins one sheet being rendered plastic, e.g. by heating, and forced by fluid pressure, e.g. vacuum, into engagement with the other sheet and contents, e.g. skin-packaging
B65B 57/02 - Automatic control, checking, warning or safety devices responsive to absence, presence, abnormal feed, or misplacement of binding or wrapping material, containers, or packages
Embodiments described herein provide a technique to facilitate the synchronization of workgroups executed on multiple graphics cores of a graphics core cluster. One embodiment provides a graphics core including a cache memory and a graphics core coupled with the cache memory. The graphics core includes execution resources to execute an instruction via a plurality of hardware threads and barrier circuitry to synchronize execution of the plurality of hardware threads, wherein the barrier circuitry is configured to provide a plurality of re-usable named barriers.
Examples described herein relate to a network interface device. In some examples, the network interface device includes a device interface; a direct memory access (DMA) circuitry; a network interface; a processor; and circuitry to boot from a network source, obtain one or more boot images from said network source, and subsequently operate as a network boot server for at least one other device.
A system, including: a communication interface operable to receive sensor data related to a state of an object; object state estimation processor circuitry operable to estimate, based on the sensor data, a prospective probability of a degradation of the state of the object; and cobot fleet control processor circuitry operable to generate a command for either a transport cobot operable to transport the object, or another actor, to take proactive action to mitigate the prospective probability of the degradation of the state of the object.
G05B 19/418 - Total factory control, i.e. centrally controlling a plurality of machines, e.g. direct or distributed numerical control (DNC), flexible manufacturing systems (FMS), integrated manufacturing systems (IMS), computer integrated manufacturing (CIM)
Embodiments include apparatuses, methods, and systems including a power control unit to control different power consumptions by one or more processors to operate different applications. The power control unit may receive power information that may include a priority information for each application to be operated on the one or more processors, determine to control, based on the power information for different applications, different power consumptions by the one or more processors to operate the different applications. Other embodiments may also be described and claimed.
A first computing system includes a data store with a sensitive dataset. The first computing system uses a feature extraction tool to perform a statistical analysis of the dataset to generate feature description data to describe a set of features within the dataset. A second computing system is coupled to the first computing system and does not have access to the dataset. The second computing system uses a data synthesizer to receive the feature description data and generate a synthetic dataset that models the dataset and includes the set of features. The second computing system trains a machine learning model with the synthetic data set and provides the trained machine learning model to the first computing system for use with data from the data store as an input.
Various embodiments herein provide techniques related to hybrid automatic repeat request acknowledgement (HARQ-ACK) transmission in cellular networks. Some embodiments may relate to HARQ-ACK transmission in networks that use a relatively high carrier frequency (e.g., a carrier frequency above approximately 52.6 gigahertz (GHz)). Some embodiments may relate to HARQ-ACK codebook size determination for multi-physical downlink shared channel (PDSCH) scheduling. Some embodiments may relate to downlink control and HARQ-ACK transmission for multi-PDSCH scheduling. Other embodiments may be described and/or claimed.
H04W 72/232 - Control channels or signalling for resource management in the downlink direction of a wireless link, i.e. towards a terminal the control data signalling from the physical layer, e.g. DCI signalling
An apparatus and system are described to provide functions and procedures in a data-centric infrastructure (DCI). The logical architecture includes an infrastructure orchestration function and controller. Interactions between the infrastructure orchestration function and controller include a function request to form or release a logical computing node, or modify the logical computing node through addition or removal of at least one of a function-dedicated computing (FDC) function, a data plane (DP) function, or a function-dedicated network (FDN) function to the logical computing node. The controller configures the FDC/DP/FDN functions and sends a response indicating completion of operations performed by the controller that are related to the function request.
H04W 8/22 - Processing or transfer of terminal data, e.g. status or physical capabilities
H04L 41/342 - Signalling channels for network management communication between virtual entities, e.g. orchestrators, SDN or NFV entities
H04W 8/18 - Processing of user or subscriber data, e.g. subscribed services, user preferences or user profiles; Transfer of user or subscriber data
H04W 72/232 - Control channels or signalling for resource management in the downlink direction of a wireless link, i.e. towards a terminal the control data signalling from the physical layer, e.g. DCI signalling
49.
ENHANCED ARTIFICIAL INTELLIGENCE FOR PERFORMANCE VALIDATION OF CORE INTEGRAETED CIRCUIT FEATURES
This disclosure describes systems, methods, and devices related to using artificial intelligence to validate performance of integrated circuit features. A device may extract, from instruction files, microinstructions source and destination registers; generate a dependency graph including macroinstructions as nodes and dependencies between macroinstructions as edges between the nodes; generate, based on the dependency graph, a frequency distribution of instructions from trace files, performance univariate autoregressive conditionally heteroscedastic (Perf uarch) stat files, and register transfer language (RTL) stat files, predictors for a machine learning model; generate, based on the Perf uarch stat files and the RTL stat files, ratios of Perf uarch stats to RTL stats as target stat ratios; generate, using the predictors and the machine learning model, predicted ratios of Perf uarch stats to RTL stats; and generate, using greedy constrained optimization, based on the target stat ratios and the predicted ratios, recommended traces for debugging.
G06F 30/398 - Design verification or optimisation, e.g. using design rule check [DRC], layout versus schematics [LVS] or finite element methods [FEM]
G06F 30/27 - Design optimisation, verification or simulation using machine learning, e.g. artificial intelligence, neural networks, support vector machines [SVM] or training a model
50.
QUICK USER DATAGRAM PROTOCOL (UDP) INTERNET CONNECTIONS (QUIC) PACKET OFFLOADING
Embodiments include a method of opening a Quick User Datagram Protocol (UDP) Internet Connections (QUIC) socket on a computing platform, initializing QUIC packet processing of a hardware-based offloader, opening a QUIC connection to the offloader, and transmitting a first QUIC packet to the offloader over the QUIC connection. The hardware-based offloader encrypts and transmits the QUIC packet.
H04L 69/164 - Adaptation or special uses of UDP protocol
H04L 69/324 - Intralayer communication protocols among peer entities or protocol data unit [PDU] definitions in the data link layer [OSI layer 2], e.g. HDLC
H04L 69/326 - Intralayer communication protocols among peer entities or protocol data unit [PDU] definitions in the transport layer [OSI layer 4]
51.
METHODS AND APPARATUS FOR GRADIENT IMAGE DETECTION TO IMPROVE DISPLAY POWER SAVINGS
Systems, apparatus, articles of manufacture, and methods are disclosed for gradient image detection to improve power savings. An example disclosed apparatus includes programmable circuitry to at least one of instantiate or execute the machine readable instructions to identify a region in an image that satisfies a brightness threshold, define a plurality of lines in the image that extend away from the region, and determine the region corresponds to a gradient based on an analysis of pixels along different ones of the plurality of lines.
This disclosure describes systems, methods, and devices related to optical proximity corrections to an integrated circuit photomask. A method may include identifying a first contour of a first adjacent polygon of a photomask predicted for a first polygon of an integrated circuit, the first contour excluding a first corner formed by a first edge and a second edge of the first polygon; identifying a second contour of a second adjacent polygon of a photomask predicted for a second polygon of the integrated circuit, the second contour excluding a second corner formed by a third edge and a fourth edge of the second polygon; generating a fast contour prediction based on corner rounding associated with the first contour and the second contour; and generating, based on the fast contour prediction, a minimum distance between the first contour and the second contour, the minimum distance associated with the optical proximity corrections.
This disclosure describes systems, methods, and devices related to enhanced access category (AC) traffic management. A device may receive one or more frames via a network interface, wherein each of the one or more frames comprises a header. The device may analyze the header of a first frame of the one or more frames to determine prioritization based on predefined criteria. The device may assign and route the first frame to appropriate Access Categories (AC) and Traffic Identifications (TID) based on the prioritization. The device may utilize established dual queuing for each AC, comprising a deep buffer queue and a shallow buffer queue. The device may direct prioritized, low latency frames to the shallow buffer queue. The device may control traffic flow via the deep buffer queue or the shallow buffer queue based on the assigned TID for each AC.
This disclosure describes systems, methods, and devices related to traffic indications for multi-link devices (MLDs). A device may generate a first traffic indication map (TIM) with a first bitmap including a first indication that traffic is to be sent by a first access point (AP) device of the MLD to a first non-AP device of a second MLD using a first communication link The device may generate a second TIM with a second bitmap including a second indication that no traffic is to be sent by a second AP device of the MLD to a second non-AP device of the second MLD using a second communication link The device may send, using the first communication link, the beacon, the beacon including the first TIM and the second TIM. The device may send, using the first communication link, a data frame to the first non-AP device of the second MLD.
Apparatus, articles of manufacture, and methods for managing processing units are disclosed. An example apparatus includes first processor circuitry to implement a central processing unit and second processor circuitry to perform at least one of first operations, second operations or third operations to obtain a resource request associated with a first workload; determine if a processing resource of a programmable network device is available to perform processing for the workload; determine if a second workload can be migrated from execution on the programmable network device; based on the determination that the second workload can be migrated, cause the second workload to be migrated; and cause the first workload to execute on the processing resource of the programmable network device.
Embodiments herein relate to a sampling phase-locked loop (PLL) with a compensation circuit for reducing ripples due to the use of a fractional N divider. The compensation circuit includes a ripple amplifier and a ripple divider. The ripple amplifier receives an output voltage, Vmain, of a main sampling circuit of the PLL and amplifies its alternating current (AC) components. The amplified output voltage is provided to a ripple integrator which samples the minimum and maximum values to provide inputs to an operational amplifier (op amp). An output of the op amp is fed back to a digital-to-analog converter (DAC), which provides a corresponding compensation voltage, Vcomp. Vcomp is added to Vmain to provide a final output control voltage, Vctrl, to control a voltage-controlled oscillator (VCO) of the PLL.
H03L 7/099 - Automatic control of frequency or phase; Synchronisation using a reference signal applied to a frequency- or phase-locked loop - Details of the phase-locked loop concerning mainly the controlled oscillator of the loop
H03L 7/093 - Automatic control of frequency or phase; Synchronisation using a reference signal applied to a frequency- or phase-locked loop - Details of the phase-locked loop concerning mainly the frequency- or phase-detection arrangement including the filtering or amplification of its output signal using special filtering or amplification characteristics in the loop
This disclosure describes systems, methods, and devices related to bond strength measurement. A device may comprise a first portion of a plate connected to a movement mechanism, a second portion of the plate comprising a sticky probe and a third portion of the plate comprising a mirror with a reflective side pointing outwards. The device may further comprise an optical fiber sensor assembly comprising an optical fiber bundle for sending light through a first optical fiber and receiving light reflected from the mirror through a second optical fiber.
An initializer for circle distribution on a 2D surface using a polar coordinate system for image compression, video compression, motion detection, and posture detection. The initializer can also be used for sphere distribution in a 3D shape. The initializer uses a mixed deterministic and iterative/stochastic approach. Using the polar coordinate system for initialization enables coverage of the user space, and after parameters are initialized, the method transitions to a cartesian coordinate system. Methods for using the polar system in CPU units by applying an XNOR/AND architecture for neural network model compression are also described. The neural network includes a perceptron for supervised learning of binary classifiers. The unit responsible for multiplication in a MAC architecture can be replaced with a non-linear expressive function. Thus, a neural network having a non-linear expressive perceptron (quadtron) is described for solving circle distribution and other problems.
Described herein is a graphics processor comprising a system interconnect and a graphics processor cluster coupled with the system interconnect. The graphics processor cluster includes circuitry configurable to generate per-frame neural representations of a multi-view video via incremental training and transferal of weights.
Systems, apparatus, articles of manufacture, and methods are disclosed to preserve privacy in a user dataset including interface circuitry, machine readable instructions, and programmable circuitry to determine a data usage type for each one of a plurality of user data features in a first dataset, classify the data usage type associated with each user data feature of the plurality of user data feature into a feature category, apply at least one feature engineering mechanism to feature categories of the data usage types of the plurality of user data features, select, based on application of feature engineering, a subset of the plurality of user data features for a feature selection training model, and output a second dataset based on the subset of the plurality of user data for the feature selection training model, the second dataset to include fewer user data features than the first dataset.
The disclosure is directed to apparatus and methods for manufacturing including a collaborative robot, a camera operatively coupled to the collaborative robot, a memory coupled to the collaborative robot, and processing circuitry coupled to the memory, the processing circuitry configured to receive image data of at least one component intended for a printed circuit board (PCB), the image data collected by the camera operatively coupled to the collaborative robot, determine, based on the image data, a coordinate location for the component, and secure the component to the PCB using an end effector of the collaborative robot based on the received image data. In one embodiment, the collaborative robot is configured to operate alongside a human, the collaborative robot in combination with the camera configured to manufacture a computer system with the PCB.
Techniques are disclosed for a programmable processor architecture that enables data interpolation using an architecture that iteratively processes portions of a look-up table (LUT) in accordance with a fused single instruction stream, multiple data streams (SIMD) instruction. The LUT may contain segment entries that correspond to a result of evaluating a function using a corresponding index values, which represent an independent variable of the function. The index values are used to map data sample values in a data array that is to be interpolated to the segment entries. By using an iterative process of mapping data samples to valid segment entries contained in each LUT portion, the architecture advantageously facilitates scaling to support larger LUTs and thus may be expanded to enable linear interpolation on multiple dimensions.
G06F 15/80 - Architectures of general purpose stored program computers comprising an array of processing units with common control, e.g. single instruction multiple data processors
G06F 1/03 - Digital function generators working, at least partly, by table look-up
63.
ALLOCATION OF POST PACKAGE REPAIR (PPR) RESOURCES BASED ON MEMORY ROW ERROR TYPE CLASSIFICATION
Allocation of post package repair (PPR) resources based on memory row error type classification. The method executes various system memory tests for dynamic random access memory devices and modules in operable communication with a processor. The methodology performed quickly classifies an error detected at boot-time as either a correctable error (CE) type or an uncorrectable error (UCE) type. A preprogrammed CE threshold (a maximum number of CEs per row) is also employed. The method advantageously only resorts to PPR in the following scenarios: If there is a UCE in the row, then perform PPR to repair the row immediately; and, If there are only CEs in the row, but the number of CE is above a pre-defined threshold, then perform PPR to repair the row immediately.
Disclosed herein are integrated circuit (IC) contact structures, and related devices and methods. For example, in some embodiments, an IC contact structure may include an electrical element, a metal on the electrical element, and a semiconductor material on the metal. The metal may conductively couple the semiconductor material and the electrical element.
Techniques are disclosed for dynamically selecting out of band emission protection mechanisms to protect the usage of other frequency bands, as well as techniques for managing the scheduling and transmission of safety related messages having different communication latency requirements.
For example, a wireless communication device may be configured to determine an expected interference-based value corresponding to an Uplink (UL) transmission from a wireless communication station (STA) in a Trigger-Based (TB) Multi-User (MU) UL transmission to be communicated from a plurality of STAs to the wireless communication device; to determine one or more transmit (Tx) configuration parameters for the STA based on the expected interference-based value corresponding to the UL transmission from the STA; and to transmit a trigger frame to trigger the TB MU UL transmission, the trigger frame including the one or more Tx configuration parameters to configure the UL transmission from the STA.
Disclosed embodiments relate to executing a vector-complex fused multiply-add instruction. In one example, a method includes fetching an instruction, a format of the instruction including an opcode, a first source operand identifier, a second source operand identifier, and a destination operand identifier, wherein each of the identifiers identifies a location storing a packed data comprising at least one complex number, decoding the instruction, retrieving data associated with the first and second source operand identifiers, and executing the decoded instruction to, for each packed data element position of the identified first and second source operands, cross-multiply the real and imaginary components to generate four products: a product of real components, a product of imaginary components, and two mixed products, generate a complex result by using the four products according to the instruction, and store a result to the corresponding position of the identified destination operand.
For example, an Access Point (AP) may be configured to process network slicing information including slice identification information and Service Level Agreement (SLA) information, wherein the slice identification information is to identify one or more Quality of Service (QoS) network slices. For example, the AP may be configured to determine a configuration of one or more radio resource allocations to be assigned to the one or more QoS network slices, and to transmit a network slicing advertisement including network slicing assignment information to indicate an assignment of the one or more radio resource allocations to the one or more QoS network slices.
Various examples relate to a method, apparatus, device and computer program for a first entity, to a method, apparatus, device and computer program for a second entity, to the first and second entity, and to a system comprising the first and second entity. Some aspects of the present disclosure relate to a method for a first entity for data buffering of write operations performed by a second entity comprises providing a limited-space data buffer comprising a plurality of slots for storing data provided by the second entity, processing the data stored in the slots of the limited-space data buffer, updating a read indicator based on the processing of the data, and providing a copy of the read indicator to the second entity according to a pre-defined criterion.
Various embodiments herein provide techniques for cancelation of one or more uplink (UL) transmissions from a user equipment (UE). The UE may receive an indication of a parameter d to use for determining a start of a reference UL resource (RUR). The parameter d may be UE-specific. The UE may further receive a physical downlink control channel (PDCCH) that includes a downlink control information (DCI) to indicate that a UL transmission is to be canceled in a RUR. The UE may determine a starting symbol of the RUR based on the parameter d. In embodiments, the UE may scale the parameter d based on a first subcarrier spacing (SCS) associated with the parameter d and a second SCS associated with the uplink transmission to obtain a scaled parameter d′ that is used to determine the starting symbol of the RUR. Other embodiments may be described and claimed.
This disclosure describes systems, methods, and devices related to enhanced plate polishing. A device may place a liquid between a plate and a wafer. The device may utilize a controller to vary a current flowing through an array of coils. The device may apply pressure on the plate to press against the liquid and the wafer.
B24B 1/00 - Processes of grinding or polishing; Use of auxiliary equipment in connection with such processes
B24B 37/04 - Lapping machines or devices; Accessories designed for working plane surfaces
B24B 57/02 - Devices for feeding, applying, grading or recovering grinding, polishing or lapping agents for feeding of fluid, sprayed, pulverised, or liquefied grinding, polishing or lapping agents
Technologies for cryptographic separation of MMIO operations with an accelerator device include a computing device having a processor and an accelerator. The processor establishes a trusted execution environment. The accelerator determines, based on a target memory address, a first memory address range associated with the memory-mapped I/O transaction, generates a second authentication tag using a first cryptographic key from a set of cryptographic keys, wherein the first key is uniquely associated with the first memory address range. An accelerator validator determines whether the first authentication tag matches the second authentication tag, and a memory mapper commits the memory-mapped I/O transaction in response to a determination that the first authentication tag matches the second authentication tag. Other embodiments are described and claimed.
G06F 12/06 - Addressing a physical block of locations, e.g. base addressing, module addressing, address space extension, memory dedication
G06F 9/48 - Program initiating; Program switching, e.g. by interrupt
G06F 12/0895 - Caches characterised by their organisation or structure of parts of caches, e.g. directory or tag array
G06F 12/14 - Protection against unauthorised use of memory
G06F 21/76 - Protecting specific internal or peripheral components, in which the protection of a component leads to protection of the entire computer to assure secure computing or processing of information in application-specific integrated circuits [ASIC] or field-programmable devices, e.g. field-programmable gate arrays [FPGA] or programmable logic devices [PLD]
74.
METHOD TO IMPLEMENT WAFER-LEVEL CHIP-SCALE PACKAGES WITH GROUNDED CONFORMAL SHIELD
Embodiments disclosed herein include electronic packages with conformal shields and methods of forming such packages. In an embodiment, the electronic package comprises a die having a first surface, a second surface opposite the first surface, and sidewall surfaces. A redistribution layer is over the first surface of the die, and the redistribution layer comprises a first conductive layer. In an embodiment, an under ball metallization (UBM) layer is over the redistribution layer, and a conductive shield is over the sidewall surfaces of the die and the second surface of the die. In an embodiment, the conductive shield is electrically coupled to the UBM layer.
H01L 23/552 - Protection against radiation, e.g. light
H01L 21/48 - Manufacture or treatment of parts, e.g. containers, prior to assembly of the devices, using processes not provided for in a single one of the groups
H01L 21/78 - Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
H01L 23/31 - Encapsulation, e.g. encapsulating layers, coatings characterised by the arrangement
An electronic device may include a first die that may include a first set of die contacts. The electronic device may include a second die that may include a second set of die contacts. The electronic device may include a bridge interconnect that may include a first set of bridge contacts and may include a second set of bridge contacts. The first set of bridge contacts may be directly coupled to the first set of die contacts (e.g., with an interconnecting material, such as solder). The second set of bridge contacts may be directly coupled to the second set of die contacts (e.g., with solder). The bridge interconnect may help facilitate electrical communication between the first die and the second die.
H01L 25/00 - Assemblies consisting of a plurality of individual semiconductor or other solid state devices
H01L 21/56 - Encapsulations, e.g. encapsulating layers, coatings
H01L 23/00 - SEMICONDUCTOR DEVICES NOT COVERED BY CLASS - Details of semiconductor or other solid state devices
H01L 23/538 - Arrangements for conducting electric current within the device in operation from one component to another the interconnection structure between a plurality of semiconductor chips being formed on, or in, insulating substrates
H01L 25/18 - Assemblies consisting of a plurality of individual semiconductor or other solid state devices the devices being of types provided for in two or more different subgroups of the same main group of groups , or in a single subclass of ,
76.
HARDWARE ACCELERATION OF DATA REDUCTION OPERATIONS
A hardware accelerator device is provided with circuitry to perform one or more reversible data transforms on data based on a request and compress the transformed data to generate compressed transformed data. The hardware accelerator device generates an output including the compressed transformed data and transform metadata indicating the set of reversible data transforms applied to the compressed transformed data.
An example apparatus disclosed herein is to receive network data communicated via a first channel associated with the online collaboration session, the network data including received media data packets. The disclosed example apparatus is also to analyze the network data to determine first loopback data, the first loopback data including at least one of a first quality score based on a first analysis of the received media data packets or a second quality score based on a second analysis of media decoded from the received media data packets. The disclosed example apparatus is also to analyze local data obtained by a local client during the online collaboration session to determine second loopback data. The disclosed example apparatus is further to cause transmission of a loopback message to a moderator client via the second channel, the loopback message based on the first loopback data and the second loopback data.
H04L 12/18 - Arrangements for providing special services to substations for broadcast or conference
G06F 3/04817 - Interaction techniques based on graphical user interfaces [GUI] based on specific properties of the displayed interaction object or a metaphor-based environment, e.g. interaction with desktop elements like windows or icons, or assisted by a cursor's changing behaviour or appearance using icons
H04L 51/04 - Real-time or near real-time messaging, e.g. instant messaging [IM]
H04L 65/1069 - Session establishment or de-establishment
An apparatus of an access point (AP) includes memory and processing circuitry configured to encode a trigger frame for transmission to a plurality of station devices (STAs) in a wireless network. A first request frame received from a STA of the plurality of STAs is decoded. The first request frame requests the AP to create a protected period for the STA when the STA is in an exposed node situation. A second request frame is encoded for transition to at least a second AP. The second request frame requests the at least second AP to establish a restricted target wake time (rTWT) for the STA. A first response frame from the at least second AP is decoded. The first response frame includes an indication of whether the rTWT is established. A second response frame is encoded for transmission to the STA. The second response frame includes the indication.
Disclosed embodiments relate to computing dot products of nibbles in tile operands. In one example, a processor includes decode circuitry to decode a tile dot product instruction having fields for an opcode, a destination identifier to identify a M by N destination matrix, a first source identifier to identify a M by K first source matrix, and a second source identifier to identify a K by N second source matrix, each of the matrices containing doubleword elements, and execution circuitry to execute the decoded instruction to perform a flow K times for each element (m, n) of the specified destination matrix to generate eight products by multiplying each nibble of a doubleword element (M,K) of the specified first source matrix by a corresponding nibble of a doubleword element (K,N) of the specified second source matrix, and to accumulate and saturate the eight products with previous contents of the doubleword element.
Embodiments for orchestrating execution of workloads on a distributed computing infrastructure are disclosed herein. In one example, environment data is received for compute devices in a distributed computing infrastructure. The environment data is indicative of an operating environment of the respective compute devices and a physical environment of the respective locations of the compute devices. Future operating conditions of the compute devices are predicted based on the environment data, and workloads are orchestrated for execution on the distributed computing infrastructure based on the predicted future operating conditions.
The present disclosure is generally related to reconfigurable radio equipment (RREs), and in particular to information models and protocols for the multiradio interface for RREs and radio application packages (RAPs) used for reconfiguring RREs. Various extensions to the information models of the multiradio interface for RREs are provided such that internal state information is included in the information models and protocols of the multiradio interface. Various aspects of RAP container formats and structure are also provided.
H04L 41/0895 - Configuration of virtualised networks or elements, e.g. virtualised network function or OpenFlow elements
G06F 8/71 - Version control ; Configuration management
H04L 41/0806 - Configuration setting for initial configuration or provisioning, e.g. plug-and-play
H04L 67/60 - Scheduling or organising the servicing of application requests, e.g. requests for application data transmissions using the analysis and optimisation of the required network resources
Apparatus, systems, articles of manufacture, and methods for robot movement are disclosed. An example robot movement apparatus includes a sequence generator to generate a sequence of context variable vectors and policy variable vectors. The context variable vectors are related to a movement target, and the policy variable vectors are related to a movement trajectory. The example apparatus includes a calculator to calculate an upper policy and a loss function based on the sequence. The upper policy is indicative of a robot movement, and the loss function is indicative of a degree to which a movement target is met. The example apparatus also includes a comparator to determine if the loss function satisfies a threshold and an actuator to cause the robot to perform the robot movement of the upper policy when the loss function satisfies the threshold.
Described herein is a technique for automated detection of case-splitting opportunities in RTL. The techniques described herein facilitate the integration of case-splitting into a hardware design tool flow, allowing the generation of hardware designs that do not suffer from timing violations. One embodiment provides a method comprising analyzing a first hardware description in a hardware description language to identify a critical path in a circuit represented by the hardware description, automatically detecting a case-splitting opportunity within the critical path, generating hardware description language for a case split having determined operator domain restrictions, and outputting a second hardware description including the hardware description language for the case split, wherein the second hardware description has a reduced operator hardware cost for the critical path relative to the first hardware description.
The present disclosure provides techniques for physical uplink shared channel (PUSCH) only based small data transmission, including: configuration of pre-allocated UL resource (PUR) set; association of synchronization signal block (SSB) and PUSCH transmission; scrambling sequence generation of the PUSCH transmission; and a procedure for PUSCH only transmission carrying small data. Other embodiments may be described and claimed.
H04L 1/1867 - Arrangements specially adapted for the transmitter end
H04L 5/00 - Arrangements affording multiple use of the transmission path
H04L 5/10 - Channels characterised by the type of signal the signals being represented by different frequencies with mechanical filters or demodulators
H04L 5/14 - Two-way operation using the same type of signal, i.e. duplex
Methods, apparatus, systems, and articles of manufacture are disclosed to improve webservers using dynamic load balancers. An example method includes identifying a first and second data object type associated with media and with first and second data objects of the media. The example method also includes enqueuing first and second event data associated with the first and second data object in a first and second queue in first circuitry in a die of programmable circuitry. The example method further includes dequeuing the first and second event data into a third and fourth queue associated with a first and second core of the programmable circuitry, the first circuitry separate from the first core and the second core. The example method additionally includes causing the first and second core to execute a first and second computing operation based on the first and second event data in the third and fourth queues.
H04L 65/612 - Network streaming of media packets for supporting one-way streaming services, e.g. Internet radio for unicast
H04L 67/02 - Protocols based on web technology, e.g. hypertext transfer protocol [HTTP]
H04L 67/60 - Scheduling or organising the servicing of application requests, e.g. requests for application data transmissions using the analysis and optimisation of the required network resources
Systems or methods of the present disclosure may provide for implementing design software that is used to design a configuration for a programmable fabric of a programmable logic device. Implementing the design software includes receiving, at a processor, design configuration details for the configuration. Implementing the design software also includes receiving, at the processor, a plurality of constraints including a thermal constraint for the configuration. Moreover, implementing the design software comprises performing thermal aware resource selection based at least in part on the thermal constraint. Furthermore, implementing the design software includes causing the programmable logic device to be operated to stay within the thermal constraint.
Microelectronic assemblies, and related devices and methods, are disclosed herein. For example, in some embodiments, a microelectronic assembly may include a package substrate having a first surface and an opposing second surface, and a die secured to the package substrate, wherein the die has a first surface and an opposing second surface, the die has first conductive contacts at the first surface and second conductive contacts at the second surface, and the first conductive contacts are coupled to conductive pathways in the package substrate by first non-solder interconnects.
H01L 23/538 - Arrangements for conducting electric current within the device in operation from one component to another the interconnection structure between a plurality of semiconductor chips being formed on, or in, insulating substrates
H01L 25/065 - Assemblies consisting of a plurality of individual semiconductor or other solid state devices all the devices being of a type provided for in the same subgroup of groups , or in a single subclass of , , e.g. assemblies of rectifier diodes the devices not having separate containers the devices being of a type provided for in group
H01L 25/18 - Assemblies consisting of a plurality of individual semiconductor or other solid state devices the devices being of types provided for in two or more different subgroups of the same main group of groups , or in a single subclass of ,
88.
METHOD AND SYSTEM OF VIDEO CODING WITH HANDLING OF ILLEGAL BLOCK PARTITIONS
Methods, systems, and articles are described herein related to video coding. The method comprises receiving compressed image data of video frames including a block of image data of at least one of the frames. The method also comprises receiving first partition data to be used to decode the compressed image data and indicating a partition in the block. This method comprises detecting whether or not the block has an illegal block partition. Also, the method comprises generating second partition data to indicate the illegal block partition of the block is to be ignored. Further, the method includes decoding the block at least according to the second partition data.
H04N 19/176 - Methods or arrangements for coding, decoding, compressing or decompressing digital video signals using adaptive coding characterised by the coding unit, i.e. the structural portion or semantic portion of the video signal being the object or the subject of the adaptive coding the unit being an image region, e.g. an object the region being a block, e.g. a macroblock
H04N 19/119 - Adaptive subdivision aspects e.g. subdivision of a picture into rectangular or non-rectangular coding blocks
H04N 19/186 - Methods or arrangements for coding, decoding, compressing or decompressing digital video signals using adaptive coding characterised by the coding unit, i.e. the structural portion or semantic portion of the video signal being the object or the subject of the adaptive coding the unit being a colour or a chrominance component
H04N 19/59 - Methods or arrangements for coding, decoding, compressing or decompressing digital video signals using predictive coding involving spatial sub-sampling or interpolation, e.g. alteration of picture size or resolution
H04N 19/70 - Methods or arrangements for coding, decoding, compressing or decompressing digital video signals characterised by syntax aspects related to video coding, e.g. related to compression standards
89.
LASER ABLATION-BASED SURFACE PROPERTY MODIFICATION AND CONTAMINATION REMOVAL
Embodiments disclosed herein include electronic packages. In an embodiment, the electronic package comprises a mold layer and a die embedded in the mold layer. In an embodiment the electronic package further comprises a solder resist with a first surface over the mold layer and a second surface opposite from the first surface. In an embodiment, the second surface comprises a first cavity into the solder resist.
H01L 25/18 - Assemblies consisting of a plurality of individual semiconductor or other solid state devices the devices being of types provided for in two or more different subgroups of the same main group of groups , or in a single subclass of ,
H01L 23/31 - Encapsulation, e.g. encapsulating layers, coatings characterised by the arrangement
H01L 25/065 - Assemblies consisting of a plurality of individual semiconductor or other solid state devices all the devices being of a type provided for in the same subgroup of groups , or in a single subclass of , , e.g. assemblies of rectifier diodes the devices not having separate containers the devices being of a type provided for in group
Example apparatus disclosed herein are to process a first image of a first video segment from the image capture sensor with a machine learning algorithm to determine a first score for the first image, the machine learning algorithm to detect actions associated with images, the actions associated with labels. Disclosed example apparatus are also to determine a second score for the first video segment based on respective first scores for corresponding images in the first video segment. Disclosed example apparatus are further to determine, based on the second score, whether to retain the first video segment in the memory.
G06V 10/40 - Extraction of image or video features
G06V 10/764 - Arrangements for image or video recognition or understanding using pattern recognition or machine learning using classification, e.g. of video objects
G06V 10/82 - Arrangements for image or video recognition or understanding using pattern recognition or machine learning using neural networks
G06V 20/40 - Scenes; Scene-specific elements in video content
91.
DYNAMIC PARALLEL PROCESSING IN AN EDGE COMPUTING SYSTEM
Data that is to be processed by a particular service executed by a first edge computing device in an application, is analyzed to determine characteristics of the data. An opportunity to replicate the particular service on a plurality of edge computing devices is determined based on characteristics of the data. A second edge computing device is determined to be available to execute a replicated instance of the particular service. Replication of the particular service is initiated on a plurality of edge computing devices including the second edge computing device. An output of an instance of the particular service executed on the first edge computing device and an output of the replicated instance of the particular service executed on the second edge computing device are combined to form a single output for the particular service.
Technologies for a flexible three-dimensional power plane in a chassis are disclosed. In one embodiment, a flexible ribbon cable is laid along a circuit board tray. The flexible ribbon cable is secured to the tray using power bosses. The power bosses connect to one or more conductors on the ribbon cable. When the circuit board is mounted on the circuit board tray, the power bosses extend through holes in the circuit board and mate with power clips on the surface of the circuit board tray. The ribbon cable, power bosses, and power clips can distribute power to various locations on the circuit board, without requiring large traces that take up space on the circuit board.
H05K 7/14 - Mounting supporting structure in casing or on frame or rack
H01R 12/79 - Coupling devices for flexible printed circuits, flat or ribbon cables or like structures connecting to rigid printed circuits or like structures
A system that includes at least one memory device and at least one graphics processing unit (GPU) comprising at least one processor and at least one register accessible to the at least one processor. In some examples, the at least one processor is configured to: retrieve, from the at least one memory device, pixel data of a kernel grid into the at least one register to load pixel data neighboring a target pixel region once into the one or more registers and process the neighboring pixel data based on the retrieved pixel data of the kernel grid from the at least one register.
Described herein is a data processing system having a multisample antialiasing compressor coupled to a texture unit and shader execution array. In one embodiment, the data processing system includes a memory device to store a multisample render target, the multisample render target to store color data for a set of sample locations of each pixel in a set of pixels; and general-purpose graphics processor comprising a multisample antialiasing compressor to apply multisample antialiasing compression to color data generated for the set of sample locations of a first pixel in the set of pixels and a multisample render cache to store color data generated for the set of sample locations of the first pixel in the set of pixels, wherein color data evicted from the multisample render cache is to be stored to the multisample render target.
H04N 19/436 - Methods or arrangements for coding, decoding, compressing or decompressing digital video signals - characterised by implementation details or hardware specially adapted for video compression or decompression, e.g. dedicated software implementation using parallelised computational arrangements
G06T 1/20 - Processor architectures; Processor configuration, e.g. pipelining
G06T 5/20 - Image enhancement or restoration by the use of local operators
H04N 19/85 - Methods or arrangements for coding, decoding, compressing or decompressing digital video signals using pre-processing or post-processing specially adapted for video compression
95.
HARDWARE PROCESSOR CORE HAVING A MEMORY SLICED BY LINEAR ADDRESS
Techniques for slicing memory of a hardware processor core by linear address are described. In certain examples, a hardware processor core includes memory circuitry having: a cache comprising a plurality of slices of memory, wherein each of a plurality of cache lines of memory are only stored in a single slice, and each slice stores a different range of address values compared to any other slice, wherein each of the plurality of slices of memory comprises: an incomplete load buffer to store a load address from the address generation circuit for a load request operation, broadcast to the plurality of slices of memory by the memory circuit from the execution circuit, in response to the load address being within a range of address values of that memory slice, a store address buffer to store a store address from the address generation circuit for a store request operation, broadcast to the plurality of slices of memory by the memory circuit from the execution circuit, in response to the store address being within a range of address values of that memory slice, a store data buffer to store data, including the data for the store request operation that is to be stored at the store address, for each store request operation broadcast to the plurality of slices of memory by the memory circuit from the execution circuit, and a store completion buffer to store the data for the store request operation in response to the store address being stored in the store address buffer of that memory slice, and, in response, clear the store address for the store request operation from the store address buffer and clear the data for the store request operation from the store data buffer.
Technologies for performing sensor fusion include a compute device. The compute device includes circuitry configured to obtain detection data indicative of objects detected by each of multiple sensors of a host system. The detection data includes camera detection data indicative of a two or three dimensional image of detected objects and lidar detection data indicative of depths of detected objects. The circuitry is also configured to merge the detection data from the multiple sensors to define final bounding shapes for the objects.
Systems and methods are disclosed for providing non-lexical cues in synthesized speech. An example system includes processor circuitry to generate a breathing cue to enhance speech to be synthesized from text; determine a first insertion point of the breathing cue in the text, wherein the breathing cue is identified by a first tag of a markup language; generate a prosody cue to enhance speech to be synthesized from the text; determine a second insertion point of the prosody cue in the text, wherein the prosody cue is identified by a second tag of the markup language; insert the breathing cue at the first insertion point based on the first tag and the prosody cue at the second insertion point based on the second tag; and trigger a synthesis of the speech from the text, the breathing cue, and the prosody cue.
G06F 40/40 - Processing or translation of natural language
G10L 13/08 - Text analysis or generation of parameters for speech synthesis out of text, e.g. grapheme to phoneme translation, prosody generation or stress or intonation determination
98.
METHODS AND APPARATUS FOR TELEMETRY GRANULARITY MANAGEMENT
An example first device disclosed includes interface circuitry, machine readable instructions, and programmable circuitry to operate based on the machine readable instructions to update configuration data based on a telemetry pattern from a second device, the second device to satisfy a neighbor condition, generate telemetry data based on the configuration data, and update the first set of data based on feedback from a recipient of the telemetry data.
A method and apparatus for detecting data lane mapping between a first circuitry and a second circuitry in a system. The first and second circuitry include a plurality of first and second data lanes, respectively that are mapped each other. The external device and the first circuitry are configured with a specific data pattern. A data transfer test is performed such that the specific data pattern is transferred from the external device to the first circuitry via the second data lanes. The data transfer test is performed iteratively by adjusting timing parameters for the second data lanes in the second circuitry in a pre-configured range while setting a timing parameter for a target second data lane in the second circuitry to an invalid value. Data lane mapping for the target second data lane between the first circuitry and the second circuitry is determined based on the data transfer test result.
An apparatus including a memory and a processor configured to: identify an item located within the environment based on sensor data, wherein the sensor data represents one or more sensor detections of the environment; determine a metric representative of a likelihood of the item becoming lost the within the environment based on information about the item; and select, based on the metric, at least one monitoring method to monitor the item within the environment from a plurality of monitoring methods.
